Readout circuit and data readout method

Abstract

The embodiment of the present application relates to the field of semiconductor circuit design, and particularly relates to a readout circuit and a data readout method, which comprises: a first isolation unit is configured to connect a bit line to a readout bit line based on an isolation signal; a second isolation unit is configured to connect a complementary bit line to a complementary readout bit line based on the isolation signal; a first PMOS tube is connected between a first signal end and the readout bit line, and has a control terminal connected to the complementary readout bit line; a second PMOS tube is connected between the first signal end and the complementary readout bit line, and has a control terminal connected to the readout bit line; a first NMOS tube is connected between a second signal end and the bit line, and has a control terminal connected to the complementary readout bit line; and a second NMOS tube is connected between the second signal end and the complementary bit line, and has a control terminal connected to the readout bit line, so that the offset noise in the readout circuit is eliminated without introducing more offset cancellation MOS tubes, and the DRAM integration is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to a readout circuit and a data readout method. Background Art

[0002] Dynamic Random Access Memory (DRAM) writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line. In DRAM, when a read operation or refresh operation is performed, the read amplifier reads and amplifies the voltage difference between the bit line and the complementary bit line.

[0003] The semiconductor devices that make up the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. These different device characteristics can cause offset noise in the sense amplifier, which can reduce the effective read margin of the sense amplifier and degrade DRAM performance.

[0004] The applicant has found that in the current process of eliminating DRAM offset noise, a MOS transistor specially designed for offset elimination is required, thereby increasing the layout area required for the sensing amplifier circuit, which is not conducive to improving the integration of DRAM.

[0005] Therefore, how to eliminate the offset noise in the readout circuit without introducing too many offset cancellation MOS transistors is an urgent problem to be solved. Summary of the Invention

[0006] The embodiments of the present application provide a readout circuit and a data readout method, which eliminate offset noise in the readout circuit without introducing too many offset cancellation MOS tubes, thereby facilitating improvement of DRAM integration.

[0007] An embodiment of the present application provides a readout circuit, comprising: a first isolation unit, configured to connect a bit line to a readout bit line based on an isolation signal; a second isolation unit, configured to connect a complementary bit line to a complementary readout bit line based on an isolation signal; a first PMOS transistor, connected between a first signal terminal and the readout bit line, and having a control terminal connected to the complementary readout bit line; a second PMOS transistor, connected between a first signal terminal and the complementary readout bit line, and having a control terminal connected to the readout bit line; a first NMOS transistor, connected between a second signal terminal and the bit line, and having a control terminal connected to the complementary readout bit line; a second NMOS transistor, connected between a second signal terminal and the complementary bit line, and having a control terminal connected to the readout bit line; wherein the first signal terminal is used to receive a first-level signal, and the second signal terminal is used to receive a first-level signal or a second-level signal, and the voltage of the first-level signal is greater than the voltage of the second-level signal.

[0008] An embodiment of the present application also provides a data reading method, including a first reading phase, a data sharing phase, and a second reading phase, which are performed sequentially. In the first reading phase, a first level signal is provided to a first signal terminal connected to a first PMOS transistor and a second PMOS transistor, and a first level signal is provided to a second signal terminal connected to a first NMOS transistor and a second NMOS transistor; in the data sharing phase, a word line connected to a target storage unit is turned on; in the second reading phase, an isolation signal is provided, and a first level signal is provided to the first signal terminal, and a second level signal is provided to the second signal terminal, wherein the voltage of the first level signal is greater than the voltage of the second level signal.

[0009] An embodiment of the present application also provides a memory, including a memory cell and a complementary memory cell, and applies the above-mentioned readout circuit, wherein the memory cell is connected to the readout circuit through a bit line, and the complementary memory cell is connected to the readout circuit through a complementary bit line.

[0010] During the offset cancellation process, the gate of the first PMOS transistor is connected to the complementary read bit line, and the drain is connected to the read bit line. When the first PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive a high level corresponding to a logic "1", that is, the first signal terminal receives the chip's internal power supply voltage. At this time, the turned-on first PMOS transistor affects the level of the read bit line based on the level and threshold voltage of the complementary read bit line. The gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line. When the second PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive a high level corresponding to a logic "1", that is, the chip's internal power supply voltage. At this time, the turned-on second PMOS transistor affects the level of the complementary read bit line based on the level and threshold voltage of the read bit line. The difference in threshold voltages between the first and second PMOS transistors will cause a difference in the levels of the read bit line and the complementary read bit line. That is, the offset noise of the first and second PMOS transistors is reflected through the levels of the read bit line and the complementary read bit line. The gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line; the gate of the second NMOS transistor is connected to the read bit line, and the drain is complementary to the bit line. Due to the connection method of the first isolation unit and the second isolation unit, when offset cancellation is performed, the first isolation unit and the second isolation unit are not conductive, and the second signal terminal is also used to receive a high level corresponding to logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip. Therefore, the difference in conduction between the first NMOS transistor and the second NMOS transistor does not affect the read bit line and the complementary read bit line, but directly adjusts the bit line voltage and the complementary bit line voltage. In addition, since the voltage levels of the read bit line and the complementary read bit line already reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and the conduction level of the first NMOS transistor is determined based on the voltage level of the complementary read bit line and the threshold voltage of the first NMOS transistor, and the conduction level of the second NMOS transistor is determined based on the voltage level of the read bit line and the threshold voltage of the second NMOS transistor, in this case, after the first NMOS transistor and the second NMOS transistor are turned on based on the complementary read bit line and the read bit line, respectively, the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and simultaneously reflect the offset noise of the first NMOS transistor and the second NMOS transistor, thus completing the offset cancellation operation of the read circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a circuit structure of a readout circuit provided in one embodiment of the present application;

[0012] Figure 2 A schematic diagram of another circuit structure of a readout circuit provided in one embodiment of the present application;

[0013] Figure 3 A timing diagram of a data readout method provided in another embodiment of the present application;

[0014] Figures 4 to 7 This is a structural schematic diagram of the readout circuit corresponding to each step in the data readout method provided in another embodiment of the present application. DETAILED DESCRIPTION

[0015] The semiconductor devices that make up the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. These different device characteristics can cause offset noise in the sense amplifier, which can reduce the effective read margin of the sense amplifier and degrade DRAM performance.

[0016] Currently, in the process of eliminating DRAM offset noise, a MOS transistor specially designed for offset elimination is required, which increases the layout area required for the sensing amplifier circuit and is not conducive to improving the integration of DRAM.

[0017] An embodiment of the present application provides a readout circuit, comprising: a first isolation unit, configured to connect a bit line to a readout bit line based on an isolation signal; a second isolation unit, configured to connect a complementary bit line to a complementary readout bit line based on the isolation signal; a first PMOS transistor, connected between a first signal terminal and the readout bit line, and having a control terminal connected to the complementary readout bit line; a second PMOS transistor, connected between the first signal terminal and the complementary readout bit line, and having a control terminal connected to the readout bit line; a first NMOS transistor, connected between a second signal terminal and the bit line, and having a control terminal connected to the complementary readout bit line; a second NMOS transistor, connected between the second signal terminal and the complementary bit line, and having a control terminal connected to the readout bit line; wherein the first signal terminal is used to receive a first-level signal, and the second signal terminal is used to receive a first-level signal or a second-level signal, and the voltage of the first-level signal is greater than the voltage of the second-level signal.

[0018] Those skilled in the art will appreciate that, in the various embodiments of this application, many technical details are provided to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0019] Figure 1 A schematic diagram of a circuit structure of a readout circuit provided in this embodiment, Figure 2 This is another circuit structure diagram of the readout circuit provided in this embodiment. The readout circuits provided in various embodiments of the present application are further described in detail below in conjunction with the accompanying drawings, as follows:

[0020] refer to Figure 1 , the readout circuit includes:

[0021] The first PMOS tube<p1>, connected between the first signal terminal and the read bit line SABL, and having a control terminal connected to the complementary read bit line SABLB. <p1>The source is connected to the first signal terminal, the drain is connected to the read bit line SABL, and the gate is connected to the complementary read bit line SABLB.

[0022] The second PMOS tube <p2>, connected between the first signal terminal and the complementary read bit line SABLB, and having a control terminal connected to the read bit line SABL. <p2>The source is connected to the first signal terminal, the drain is connected to the complementary read bit line SABLB, and the gate is connected to the read bit line SABL.

[0023] The first NMOS tube <n1>, connected between the second signal terminal and the bit line BL, and having a control terminal connected to the complementary readout bit line SABLB. <n1>The source is connected to the second signal terminal, the drain is connected to the bit line BL, and the gate is connected to the complementary readout bit line SABLB.

[0024] The second NMOS tube <n2>, connected between the second signal terminal and the complementary bit line BLB, and having a control terminal connected to the read bit line SABL. <n2>The source is connected to the second signal terminal, the drain is connected to the complementary bit line BLB, and the gate is connected to the read bit line SABL.

[0025] Regarding the bit line BL and the complementary bit line BLB, the bit line BL connects the memory cells of the memory array 400 in the adjacent memory array. <01> The complementary bit line BLB connects the memory cells of the complementary memory array 401 in the adjacent memory array. <02> .

[0026] In the offset elimination process, both the first signal terminal and the second signal terminal are used to receive a high level corresponding to a logic "1"; in the data readout process, the first signal terminal is used to receive a high level corresponding to a logic "1", and the second signal terminal is used to receive a low level corresponding to a logic "0". In this embodiment, the voltage of the first-level signal (Positive Cell Storing Signal, PCS) is greater than the voltage of the second-level signal (Negative Cell Storing Signal, NCS), that is, the first-level signal PCS is a high level corresponding to a logic "1", and the second-level signal NCS is a low level corresponding to a logic "0"; in other embodiments, it can also be set so that the voltage of the first-level signal is less than the voltage of the second-level signal, that is, the first-level signal is a low level corresponding to a logic "0", and the second-level signal is a high level corresponding to a logic "1".

[0027] In addition, the readout circuit also includes: a first isolation unit and a second isolation unit, wherein the first isolation unit is configured to connect the bit line BL to the readout bit line SABL based on the isolation signal, and the second isolation unit is configured to connect the complementary bit line BLB to the complementary readout bit line SABLB based on the isolation signal.

[0028] Specifically, the first isolation unit includes: a first isolation MOS transistor <11> The second isolation unit includes: a second isolation MOS tube <12> .

[0029] Among them, the first isolation MOS tube <11> The source is connected to the bit line BL, the drain is connected to the read bit line SABL, and the gate is used to receive the isolation signal (ISO). The first isolation MOS transistor <11> The second isolation MOS transistor is used to conduct according to the isolation signal, so that the bit line BL is electrically connected to the read bit line SABL. <12> The source is connected to the complementary bit line BLB, the drain is connected to the complementary readout bit line SABLB, the gate is used to receive the isolation signal, and the second isolation MOS transistor <12> It is used to be turned on according to the isolation signal to electrically connect the complementary bit line BLB to the complementary readout bit line SABLB.

[0030] For a memory, before data is read out, the memory precharges the bit line BL, the complementary bit line BLB, the read bit line SABL, and the complementary read bit line SABLB to a preset voltage.

[0031] For the readout circuit of this embodiment, in the first readout stage, that is, the offset elimination stage of the memory, a first level signal PCS is provided to the first signal terminal and the second signal terminal; the first PMOS transistor <p1>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, the source is connected to the first signal terminal, and the first PMOS transistor <p1>After the complementary read bit line SABLB is turned on based on the preset voltage, the first signal terminal is electrically connected to the read bit line SABL, and the read bit line SABL is pulled high under the action of the first level signal PCS; the second PMOS transistor <p2>The gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, the source is connected to the first signal terminal, and the second PMOS transistor <p2>After the preset voltage of the read bit line SABL is turned on, the first signal terminal is electrically connected to the complementary read bit line SABLB, and the complementary read bit line SABLB is pulled high under the action of the first level signal PCS.

[0032] After the level of the read bit line SABL and the complementary read bit line SABLB is pulled high, the first PMOS transistor <p1>and the second PMOS tube <p2>However, the semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variation and temperature, that is, due to external factors or the influence of the formation process, the first PMOS transistor may be turned off. <p1>and the second PMOS tube <p2>There are differences in the threshold voltage of the first PMOS tube <p1>and the second PMOS tube <p2>Based on the different conduction capabilities after the preset voltage is turned on, the first PMOS tube <p1>and the second PMOS tube <p2>After being turned on, there is a difference in the levels of the read bit line SABL and the complementary read bit line SABLB, that is, the first PMOS transistor <p1>and the second PMOS tube <p2>Due to the connection mode of the first isolation unit and the second isolation unit, the first isolation unit and the second isolation unit are not conductive during the offset cancellation process. At this time, the level of the read bit line SABL is not synchronized with the bit line BL, and the level of the complementary read bit line SABLB is not synchronized with the complementary bit line BLB.

[0033] After the level of the read bit line SABL and the complementary read bit line SABLB is pulled high, the first NMOS transistor <n1>The gate is connected to the complementary readout bit line SABLB, the drain is connected to the bit line BL, the source is connected to the second signal terminal, and the first NMOS transistor <n1>Based on the complementary read bit line SABLB being turned on after being pulled high, the first NMOS transistor <n1>After the bit line BL is turned on, it is electrically connected to the second signal terminal. The bit line BL is pulled high under the action of the first level signal PCS. <n2>The gate is connected to the read bit line SABL, the drain is the complementary bit line BLB, the source is connected to the second signal terminal, and the second NMOS transistor <n2>Based on the pulled-up read bit line SABL being turned on, the second NMOS transistor <n2>After being turned on, the complementary bit line BLB is electrically connected to the second signal terminal, and the complementary bit line BLB is pulled high under the action of the first level signal PCS.

[0034] Since the semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variation and temperature, that is, due to external factors or the influence of the formation process, the first NMOS transistor may have different device characteristics (e.g., threshold voltage). <n1>and the second NMOS tube <n2>There is a difference in the threshold voltage of the first NMOS tube <n1>and the second NMOS tube <n2>Based on the different conduction capabilities after the preset voltage is turned on, the first NMOS tube <n1>and the second NMOS tube <n2>After being turned on, the level of the bit line BL and the complementary bit line BLB are different, and the first NMOS transistor <n1>and the second NMOS tube <n2>The on-state voltage of the first PMOS tube <p1>and the second PMOS tube <p2>The offset noise of the bit line BL and the complementary bit line BLB includes the level difference of the first PMOS transistor <p1>and the second PMOS tube <p2>The offset noise and the first NMOS tube <n1>and the second NMOS tube <n2>Assume that the first PMOS tube <p1>and the first NMOS tube <n1>As standard, the second PMOS tube <p2>and the second NMOS tube <n2>The threshold voltage of the first PMOS tube is lower than <p1>and the first NMOS tube <n1>Based on the above discussion, it can be seen that after the offset is eliminated, the voltage of the bit line BL is lower than the voltage of the complementary bit line BLB.

[0035] In the data sharing phase, the word line WL is turned on to transfer the target memory cell to the target memory cell. <01> The voltage of the bit line BL is shared with the bit line BL. At this time, due to the execution of the offset cancellation process, the actual voltage of the bit line BL is smaller than the theoretical voltage, so that in the second readout stage, that is, the actual readout amplification stage, the first isolation unit and the second isolation unit are turned on, the bit line BL is electrically connected to the readout bit line SABL, and the complementary bit line BLB is electrically connected to the complementary readout bit line SABLB, so that the second PMOS transistor with a smaller threshold voltage is electrically connected to the complementary readout bit line SABLB. <p2>and the second NMOS tube <n2>The gate voltage received is too small, so the voltage difference between the read bit line SABL and the complementary read bit line SABLB is compensated for by the first PMOS transistor. <p1>and the second PMOS tube <p2>, and the first NMOS tube <n1>and the second NMOS tube <n2>offset noise.

[0036] In addition, in other embodiments, the complementary word line WLB can be turned on to connect the complementary target memory cell to the target memory cell. <02> The voltage of the target memory cell is shared to the complementary bit line BLB to realize data sharing. It should be noted that, in other embodiments, when the word line WL is turned on, the target memory cell <01> The voltage of the bit line BL is shared with the complementary word line WLB, and the complementary target memory cell is connected. <02> The voltage of the target memory cell is shared to the complementary bit line BLB, wherein the target memory cell <01> and complementary target memory cells <02> Used to store opposite data (i.e. target storage unit <01> Complementary target storage unit when storing high level <02> Store low level, target storage unit <01> Complementary target storage unit when storing low level <02> Store high level).

[0037] Due to the fine-tuning of the bit line BL and the complementary bit line BLB by the offset cancellation operation, the level of one of the bit line BL and the complementary bit line BLB is higher than the preset voltage, and the level of the other is lower than the preset voltage; after charge sharing, the bit line BL or the complementary bit line BLB below the preset voltage may be pulled high, or the bit line BL or the complementary bit line BLB above the preset voltage may be pulled low, resulting in the situation that the bit line BL and the complementary bit line BLB are both higher than the preset voltage or both lower than the preset voltage at the same time, by turning on the target memory cell at the same time. <01> and complementary target memory cells <02> This ensures that the bit line BL and the complementary bit line BLB are pulled up and pulled down at the same time, thereby ensuring the accuracy of subsequent data reading.

[0038] In one embodiment, reference Figure 2 The readout circuit further includes: a precharge module configured to precharge the bit line BL, the readout bit line SABL, the complementary bit line BLB and the complementary readout bit line SABLB to a preset voltage V based on a precharge signal (Precharge Signal, PRE). BLP In this embodiment, the preset voltage V BLP =1 / 2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the preset voltage V BLP It can be set according to the specific application scenario.

[0039] Specifically, the precharge module includes: a first precharge unit configured to precharge the bit line BL and the complementary bit line BLB to a preset voltage V based on a precharge signal PRE; BLP The second precharge unit is configured to precharge the read bit line SABL and the complementary read bit line SABLB to a preset voltage V based on the precharge signal PRE BLP The first precharge unit precharges the bit line BL and the complementary bit line BLB, and the second precharge unit precharges the read bit line SABL and the complementary read bit line SABLB. The two precharge units precharge simultaneously to increase the precharge speed of the read circuit.

[0040] The first pre-charging unit includes a first pre-charging MOS tube <21> And the second pre-charge MOS tube <22> ; The first pre-charge MOS tube <21> , one terminal is connected to the bit line BL, and the other terminal is used to receive the preset voltage V BLP , the control terminal is used to receive the pre-charge signal PRE, the first pre-charge MOS tube <21> is configured to be turned on based on the pre-charge signal PRE. Specifically, in this embodiment, the first pre-charge MOS transistor <21> The source is connected to the bit line BL, and the drain is used to receive the preset voltage V BLP , the gate is used to receive the pre-charge signal PRE; the second pre-charge MOS tube <22> , one terminal is connected to the complementary bit line BLB, and the other terminal is used to receive the preset voltage V BLP , the control terminal is used to receive the pre-charge signal PRE, the second pre-charge MOS tube <22> is configured to be turned on based on the pre-charge signal PRE. Specifically, in this embodiment, the second pre-charge MOS transistor <22> The source is connected to the complementary bit line BLB, and the drain is used to receive the preset voltage V BLP , the gate is used to receive a pre-charge signal PRE.

[0041] In a specific example, the first pre-charge MOS tube <21> Receive preset voltage V BLP terminals and the second pre-charge MOS tube <22> Receive preset voltage V BLP The first pre-charge MOS tube is connected to the terminal. <21> The drain and the second pre-charge MOS tube <22> is connected to the drain of the BLP .

[0042] In a specific example, the first pre-charge MOS tube <21> And the second pre-charge MOS tube <22> Set in the same active area.

[0043] In a specific example, the first pre-charge MOS tube <21> The control terminal and the second pre-charge MOS tube <22> The control terminal of the first pre-charge MOS tube is connected <21> The gate and the second pre-charge MOS tube <22> is connected to the gate of the device for receiving a pre-charge signal PRE.

[0044] The second pre-charging unit includes a third pre-charging MOS tube <23> ; The third pre-charge MOS tube <23> One terminal is connected to the read bit line SABL or the complementary read bit line SABLB, and the other terminal is used to receive the preset voltage V BLP , the control terminal is used to receive the pre-charge signal PRE, the third pre-charge MOS tube <23> is configured to be turned on based on the pre-charge signal PRE. Specifically, in this embodiment, the third pre-charge MOS transistor <23> The source is connected to the read bit line SABL or the complementary read bit line SABLB, and the drain is used to receive the preset voltage V BLP , the gate is used to receive a pre-charge signal PRE.

[0045] Furthermore, the readout circuit further includes: an equalizing unit configured to connect the readout bit line SABL to the complementary readout bit line SABLB based on an equalizing signal (EQ).

[0046] In one example, the balancing unit includes a balancing MOS tube <31> , balanced MOS tube <31> is connected between the read bit line SABL and the complementary read bit line SABLB and has a control terminal for receiving the equalization signal EQ. <31> The source is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, and the gate is used to receive the equalization signal EQ.

[0047] In a specific example, due to the connection mode of the readout circuit in this embodiment, during the offset cancellation process, the levels of the bit line BL and the readout bit line BLB are only affected by the first NMOS transistor. <n1>and the second NMOS tube <n2>That is, during the offset cancellation process, an equalization signal EQ can be provided to turn on the equalization unit, thereby electrically connecting the read bit line SABL to the complementary read bit line SABLB to ignore the first PMOS transistor. <p1>and the second PMOS tube <p2>The offset effect of the first NMOS tube is eliminated more accurately. <n1>and the second NMOS tube <n2>offset noise.

[0048] In one example, the precharge signal includes a first precharge signal and a second precharge signal, wherein the first precharge unit is configured to precharge the bit line BL and the complementary bit line BLB to a preset voltage V based on the first precharge signal. BLP The second precharge unit is configured to precharge the read bit line SABL or the complementary read bit line SABLB to a preset voltage V based on the second precharge signal BLP The first pre-charging unit is controlled by the first pre-charging signal, and the second pre-charging unit is controlled by the second pre-charging signal, thereby realizing separate control of the first pre-charging unit and the second pre-charging unit.

[0049] In one example, the preset voltage V BLP It includes a first preset voltage and a second preset voltage, wherein the first pre-charge unit is configured to pre-charge the bit line BL and the complementary bit line BLB to the first preset voltage based on the first pre-charge signal, and the second pre-charge unit is configured to pre-charge the read bit line SABL or the complementary read bit line SABLB to the second preset voltage based on the second pre-charge signal. By configuring the first pre-charge unit to pre-charge to the first preset voltage and the second pre-charge unit to pre-charge to the second preset voltage, different degrees of pre-charging of the bit line BL and the complementary bit line BLB, as well as the read bit line SABL and the complementary read bit line SABLB are achieved.

[0050] It should be noted that the specific connection methods of the "source" and "drain" defined in the above-mentioned transistors do not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be adopted.

[0051] During the offset cancellation process, the gate of the first PMOS transistor is connected to the complementary read bit line, and the drain is connected to the read bit line. When the first PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive a high level corresponding to a logic "1", that is, the first signal terminal receives the chip's internal power supply voltage. At this time, the turned-on first PMOS transistor affects the level of the read bit line based on the level and threshold voltage of the complementary read bit line. The gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line. When the second PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive a high level corresponding to a logic "1", that is, the chip's internal power supply voltage. At this time, the turned-on second PMOS transistor affects the level of the complementary read bit line based on the level and threshold voltage of the read bit line. The difference in threshold voltages between the first and second PMOS transistors will cause a difference in the levels of the read bit line and the complementary read bit line. That is, the offset noise of the first and second PMOS transistors is reflected through the levels of the read bit line and the complementary read bit line. The gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line. The gate of the second NMOS transistor is connected to the read bit line, and the drain is connected to the complementary bit line. Due to the connection method of the first isolation unit and the second isolation unit, when offset cancellation is performed, the first isolation unit and the second isolation unit are not conductive, and the second signal terminal is also used to receive a high level corresponding to logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip. Therefore, the difference in conduction between the first NMOS transistor and the second NMOS transistor does not affect the read bit line and the complementary read bit line, but directly adjusts the bit line voltage and the complementary bit line voltage. In addition, since the voltage levels of the read bit line and the complementary read bit line already reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and the conduction level of the first NMOS transistor is determined based on the voltage level of the complementary read bit line and the threshold voltage of the first NMOS transistor, and the conduction level of the second NMOS transistor is determined based on the voltage level of the read bit line and the threshold voltage of the second NMOS transistor, in this case, after the first NMOS transistor and the second NMOS transistor are turned on based on the complementary read bit line and the read bit line, respectively, the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and simultaneously reflect the offset noise of the first NMOS transistor and the second NMOS transistor, thus completing the offset cancellation operation of the read circuit.

[0052] It should be noted that, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems raised by this application, but this does not mean that there are no other units in this embodiment; ordinary technicians in this field can understand that the above-mentioned embodiments are specific embodiments for implementing this application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

[0053] Another embodiment of the present application also provides a data reading method, including a first reading phase, a data sharing phase, and a second reading phase performed sequentially, wherein in the first reading phase, a first level signal is provided to a first signal terminal connected to the first PMOS transistor and the second PMOS transistor, and a first level signal is provided to a second signal terminal connected to the first NMOS transistor and the second NMOS transistor; in the data sharing phase, a word line connected to a target memory cell is turned on, and a word line connected to a complementary memory cell of the target memory cell is turned on; in the second reading phase, an isolation signal is provided, and a first level signal is provided to the first signal terminal, and a second level signal is provided to the second signal terminal, and the voltage of the first level signal is greater than the voltage of the second level signal.

[0054] Figure 3 A timing diagram of the data reading method provided in this embodiment, Figures 4 to 7 The structural diagram of the readout circuit corresponding to each step in the data readout method provided in this embodiment is as follows:

[0055] It should be noted that, in this embodiment, the voltage of the first level signal (Positive Cell Storing Signal, PCS) is greater than the voltage of the second level signal (Negative Cell Storing Signal, NCS), that is, the first level signal PCS is a high level corresponding to logic "1", and the second level signal NCS is a low level corresponding to logic "0"; in other embodiments, it can also be set that the voltage of the first level signal is less than the voltage of the second level signal, that is, the first level signal is a low level corresponding to logic "0", and the second level signal is a high level corresponding to logic "1".

[0056] refer to Figure 3 The data read-out method includes a first read-out phase, a data sharing phase and a second read-out phase which are executed in sequence.

[0057] The first readout stage is Figure 3 The data sharing stage is the t1~t2 stage. Figure 3 The second readout stage is the t2~t3 stage. Figure 3 The t3 to t5 stage.

[0058] Specifically, before the first readout phase, it also includes: a pre-charge phase, i.e. Figure 3 The stage t0 to t1 is a precharge stage, which is used to provide a precharge signal PRE to precharge the bit line, the read bit line, the complementary bit line and the complementary read bit line to a preset voltage.

[0059] refer to Figure 2 、 Figure 4 as well as Figure 3 In the t0~t1 stage, for the pre-charge stage, it includes:

[0060] Provide an isolation signal ISO, connect the bit line BL to the read bit line SABL through the first isolation unit, and connect the complementary bit line BLB to the complementary read bit line SABLB through the second isolation unit. Specifically, provide the isolation signal ISO to turn on the first isolation MOS transistor <11> and the second isolation MOS tube <12> After the first isolation unit is turned on, the bit line BL is connected to the read bit line SABL, and after the second isolation unit is turned on, the complementary bit line BLB is connected to the complementary read bit line SABLB.

[0061] Provide an equalization signal EQ, and connect the read bit line SABL to the complementary read bit line SABLB through the equalization unit. Specifically, provide the equalization signal EQ to turn on the equalization MOS transistor <31> , balanced MOS tube <31> When turned on, the sense bit line SABL is connected to the complementary sense bit line SABLB.

[0062] A precharge signal PRE is provided to precharge the bit line BL, the read bit line SABL, the complementary bit line BLB and the complementary read bit line SABLB through the first precharge unit and / or the second precharge unit. Specifically, a precharge signal PRE is provided to turn on the first precharge MOS transistor. <21> , the second pre-charge MOS tube <22> And the third pre-charge MOS tube <23> , the first pre-charge MOS tube <21> After being turned on, the bit line BL is precharged to a preset voltage V BLP ; The second pre-charge MOS tube <22> After being turned on, the complementary bit line BLB is precharged to a preset voltage V BLP ; The third pre-charge MOS tube <23> After being turned on, the read bit line SABL and the complementary read bit line SABLB are precharged to a preset voltage V BLP .

[0063] In this embodiment, the preset voltage V BLP =1 / 2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the preset voltage V BLP It can be set according to the specific application scenario.

[0064] refer to Figure 2 、 Figure 5 as well as Figure 3 In the period t1 to t2, the first readout stage is the offset elimination stage of the readout circuit. In the first readout stage, the offset of the first NMOS transistor is eliminated. <n1>With the second NMOS tube <n2>The current conduction capability difference of the first PMOS tube is eliminated. <p1>With the second PMOS tube <p2>The current conducting capability difference.

[0065] Specifically, in the first readout phase, the first PMOS transistor <p1>and the second PMOS tube <p2>The connected first signal terminal provides a first level signal PCS, and provides the first level signal PCS to a second signal terminal connected to the first NMOS transistor and the second NMOS transistor.

[0066] In the first readout phase, a first level signal PCS is provided to the first signal terminal and the second signal terminal; the first PMOS transistor <p1>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, the source is connected to the first signal terminal, and the first PMOS transistor <p1>After the complementary read bit line SABLB is turned on based on the preset voltage, the first signal terminal is electrically connected to the read bit line SABL, and the read bit line SABL is pulled high under the action of the first level signal PCS; the second PMOS transistor <p2>The gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, the source is connected to the first signal terminal, and the second PMOS transistor <p2>After the preset voltage of the read bit line SABL is turned on, the first signal terminal is electrically connected to the complementary read bit line SABLB, and the complementary read bit line SABLB is pulled high under the action of the first level signal PCS.

[0067] After the level of the read bit line SABL and the complementary read bit line SABLB is pulled high, the first PMOS transistor <p1>and the second PMOS tube <p2>However, the semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variation and temperature, that is, due to external factors or the influence of the formation process, the first PMOS transistor may be turned off. <p1>and the second PMOS tube <p2>There are differences in the threshold voltage of the first PMOS tube <p1>and the second PMOS tube <p2>Based on the different conduction capabilities after the preset voltage is turned on, the first PMOS tube <p1>and the second PMOS tube <p2>After being turned on, there is a difference in the levels of the read bit line SABL and the complementary read bit line SABLB, that is, the first PMOS transistor <p1>and the second PMOS tube <p2>Due to the connection mode of the first isolation unit and the second isolation unit, the first isolation unit and the second isolation unit are not conductive during the offset cancellation process. At this time, the level of the read bit line SABL is not synchronized with the bit line BL, and the level of the complementary read bit line SABLB is not synchronized with the complementary bit line BLB.

[0068] After the level of the read bit line SABL and the complementary read bit line SABLB is pulled high, the first NMOS transistor <n1>The gate is connected to the complementary readout bit line SABLB, the drain is connected to the bit line BL, the source is connected to the second signal terminal, and the first NMOS transistor <n1>Based on the complementary read bit line SABLB being turned on after being pulled high, the first NMOS transistor <n1>After the bit line BL is turned on, it is electrically connected to the second signal terminal. The bit line BL is pulled high under the action of the first level signal PCS. <n2>The gate is connected to the read bit line SABL, the drain is the complementary bit line BLB, the source is connected to the second signal terminal, and the second NMOS transistor <n2>Based on the pulled-up read bit line SABL being turned on, the second NMOS transistor <n2>After being turned on, the complementary bit line BLB is electrically connected to the second signal terminal, and the complementary bit line BLB is pulled high under the action of the first level signal PCS.

[0069] Since the semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variation and temperature, that is, due to external factors or the influence of the formation process, the first NMOS transistor may have different device characteristics (e.g., threshold voltage). <n1>and the second NMOS tube <n2>There is a difference in the threshold voltage of the first NMOS tube <n1>and the second NMOS tube <n2>Based on the different conduction capabilities after the preset voltage is turned on, the first NMOS tube <n1>and the second NMOS tube <n2>After being turned on, the level of the bit line BL and the complementary bit line BLB are different, and the first NMOS transistor <n1>and the second NMOS tube <n2>The on-state voltage of the first PMOS tube <p1>and the second PMOS tube <p2>The offset noise of the bit line BL and the complementary bit line BLB includes the level difference of the first PMOS transistor <p1>and the second PMOS tube <p2>The offset noise and the first NMOS tube <n1>and the second NMOS tube <n2>offset noise.

[0070] Assume that the first PMOS tube <p1>and the first NMOS tube <n1>As standard, the second PMOS tube <p2>and the second NMOS tube <n2>The threshold voltage of the first PMOS tube is lower than <p1>and the first NMOS tube <n1>Based on the above discussion, it can be seen that after the offset is eliminated, the voltage of the bit line BL is lower than the voltage of the complementary bit line BLB.

[0071] In one example, the first readout stage further includes: providing an equalization signal to connect the readout bit line SABL to the complementary readout bit line SABLB. Since, during the offset cancellation process, the levels of the bit line BL and the readout bit line BLB are only affected by the first NMOS transistor. <n1>and the second NMOS tube <n2>That is, during the offset cancellation process, an equalization signal EQ can be provided to turn on the equalization unit, thereby electrically connecting the read bit line SABL to the complementary read bit line SABLB to ignore the first PMOS transistor. <p1>and the second PMOS tube <p2>The offset effect of the first NMOS tube is eliminated more accurately. <n1>and the second NMOS tube <n2>offset noise.

[0072] refer to Figure 2 、 Figure 6 as well as Figure 3 In the t2~t3 part, during the data sharing phase, the target storage unit is turned on. <01> connected word line WL to the target memory cell <01> The voltage of the target memory cell is read to the bit line BL. <01> The stored level is low level as an example for detailed description, as follows:

[0073] After the offset cancellation, the voltages of both bit line BL and complementary bit line BLB increase, but the voltage change on bit line BL is smaller than the voltage change on complementary bit line BLBL. During the data sharing phase, the voltage of the target memory cell is shared with bit line BL, and the voltage of bit line BL is pulled down. At this time, due to the execution of the offset cancellation process, the actual voltage of bit line BL is greater than the theoretical voltage.

[0074] Similarly, the above description also applies to the target storage unit <01> In addition, in other embodiments, the complementary word line WLB can be turned on to store the complementary target memory cell. <02> The voltage of the target memory cell is shared to the complementary bit line BLB to realize data sharing; it should also be noted that, in other embodiments, when the word line WL is turned on, the target memory cell <01> The voltage of the bit line BL is shared with the complementary word line WLB, and the complementary target memory cell is connected. <02> The voltage of the target memory cell is shared to the complementary bit line BLB, wherein the target memory cell <01> and complementary target memory cells <02> Used to store opposite data to ensure the accuracy of subsequent data reading.

[0075] refer to Figure 2 、 Figure 7 as well as Figure 3 In the portion t3 to t5, in the second readout phase, an isolation signal ISO is provided to connect the bit line BL to the readout bit line SABL, and the complementary bit line BLB to the complementary readout bit line SABLB, a first level signal PCS is provided to the first signal terminal, and a second level signal NCS is provided to the second signal terminal.

[0076] Specifically, an isolation signal ISO is provided to connect the bit line BL to the read bit line SABL, and the complementary bit line BLB to the complementary read bit line SABLB; in the process of providing the isolation signal ISO, a first level signal PCS is provided to the first signal terminal, and a second level signal NCS is provided to the second signal terminal.

[0077] Specifically, since the voltages of the bit line BL and the complementary bit line BLB both increase after the offset is eliminated, and the voltage increase of the complementary bit line BLB is greater than the voltage increase of the bit line BL, after the bit line BL is connected to the read bit line SABL and the complementary bit line BLB is connected to the complementary read bit line SABLB, the actual voltage of the complementary read bit line SABLB is greater than the voltage of the read bit line SABL, thereby compensating the voltage difference between the read bit line SABL and the complementary read bit line SABLB. <p1>and the second PMOS tube <p2>, and the first NMOS tube <n1>and the second NMOS tube <n2>offset noise to ensure that the first PMOS tube <p1>and the second PMOS tube <p2>The conduction state of the first NMOS tube is consistent. <n1>and the second NMOS tube <n2>The conduction state is consistent.

[0078] For the first PMOS tube <p1>and the first NMOS tube <n1>, since the first PMOS tube <p1>Gate and first NMOS tube <n1>The connection relationship of the gate is the same, that is, based on the different levels of the complementary read bit line SABLB, the first PMOS transistor <p1>Or the first NMOS tube <n1>When turned on, the first PMOS tube <p1>and the first NMOS tube <n1>There is only one MOS tube with strong conduction capability; for the second PMOS tube <p2>and the second NMOS tube <n2>, since the second PMOS tube <p2>Gate and second NMOS tube <n2>The connection relationship of the gate is the same, that is, based on the different levels of the read bit line SABL, the second PMOS transistor <p2>Or the second NMOS tube <n2>When turned on, the second PMOS tube <p2>and the second NMOS tube <n2>There is only one MOS tube with strong conduction capability.

[0079] Specifically, when the first PMOS tube <p1>The conduction capability is strong, and the first signal end is connected to the first read bit line SABL, thereby pulling the first read bit line SABL high to the first level signal PCS, and then pulling the initial bit line BL high to the first level signal PCS, so that the data read out of the memory through the initial bit line BL is the high level of the first level signal PCS corresponding to the logic "1"; when the first NMOS transistor <n1>The conduction capability is strong, and the second signal end is connected to the bit line BL, thereby pulling the bit line BL down to the second level signal NCS, so that the data read out of the memory through the initial bit line BL is the low level of the second level signal NCS corresponding to the logic "0"; when the second PMOS transistor <p2>The conduction capability is strong, and the first signal end is connected to the complementary read bit line SABLB, thereby pulling the complementary read bit line SABLB high to the first level signal PCS, and then pulling the initial complementary bit line BLB high to the first level signal PCS, so that the data read out of the memory through the initial complementary bit line BLB is the high level of the first level signal PCS corresponding to the logic "1"; when the second NMOS transistor <n2>The conduction capability is strong, and the second signal end complementary bit line BLB is connected, thereby pulling the complementary bit line BLB down to the second level signal NCS, so that the data read out of the memory through the initial complementary bit line BLB is the low level of the second level signal NCS corresponding to logic "0".

[0080] Based on the above discussion, it can be seen that in the second read phase, since the target storage unit <01> After the charge sharing, the pull-down makes the voltage of the bit line BL lower than the voltage of the complementary bit line BLB, that is, the voltage of the read bit line SABL is lower than the voltage of the complementary read bit line SABLB. At this time, the second NMOS transistor <n2>The conduction capability is smaller than that of the first NMOS tube <n1>The conduction capability of the first PMOS tube <p1>The conduction capability is greater than that of the second PMOS tube <p2>, thereby pulling down the voltage of the read bit line SABL to the same voltage as the second level signal NCS, and pulling up the voltage of the complementary read bit line SABLB to the same voltage as the first level signal PCS.

[0081] That is, the level of the bit line BL is pulled down to a low potential with the read bit line SABL, and the level of the complementary bit line BLB is pulled up to a high potential with the complementary read bit line SABLB, and at this time the word line WL is still turned on, and the target memory cell <01> The level stored in the same bit line BL is pulled down to a low potential, thereby completing the target memory cell <01> The charge of the bit line BL is restored, and the level of the bit line BL is turned on by the column selection unit to realize the data reading of the memory.

[0082] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects achieved in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0083] The above division of the readout stages is only for clarity of description. During implementation, they can be combined into one readout stage or some readout stages can be split and decomposed into multiple readout stages. As long as the timing change of the control signal is the same, they are all within the scope of protection of this patent; adding insignificant modifications or introducing insignificant designs to the readout stage without changing the core design of the readout stage are all within the scope of protection of this patent; ordinary technicians in this field can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

[0084] In addition, another embodiment of the present application further provides a memory, including a memory cell and a complementary memory cell, including the readout circuit provided by the above embodiment, wherein the memory cell is connected to the readout circuit through a bit line, and the complementary memory cell is connected to the readout circuit through a complementary bit line; thereby eliminating offset noise in the readout circuit without introducing too many offset elimination MOS tubes, which is beneficial to improving the integration of DRAM.

[0085] Since the above embodiments correspond to this embodiment, the relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment. In order to reduce repetition, they will not be repeated here.

[0086] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A readout circuit, characterized in that: include: a first isolation unit configured to connect the bit line to a read bit line based on an isolation signal; a second isolation unit configured to connect the complementary bit line to a complementary read bit line based on the isolation signal; a first PMOS transistor connected between the first signal terminal and the read bit line and having a control terminal connected to the complementary read bit line; a second PMOS transistor connected between the first signal terminal and the complementary read bit line and having a control terminal connected to the read bit line; a first NMOS transistor connected between the second signal terminal and the bit line and having a control terminal connected to the complementary readout bit line; a second NMOS transistor connected between the second signal terminal and the complementary bit line and having a control terminal connected to the readout bit line; The first signal end is used to receive a first level signal, and the second signal end is used to receive the first level signal or the second level signal. The voltage of the first level signal is greater than the voltage of the second level signal.

2. The readout circuit according to claim 1, wherein: Also includes: The precharge module is configured to precharge the bit line, the read bit line, the complementary bit line and the complementary read bit line to a preset voltage based on a precharge signal.

3. The readout circuit according to claim 2, wherein: The pre-charging module includes: a first precharge unit, configured to precharge the bit line and the complementary bit line to the preset voltage based on the precharge signal; The second precharge unit is configured to precharge the read bit line or the complementary read bit line to the preset voltage based on the precharge signal.

4. The readout circuit according to claim 3, wherein: Also includes: The equalization unit is configured to connect the read bit line to the complementary read bit line based on an equalization signal.

5. The readout circuit according to claim 3, wherein: The first pre-charging unit includes: a first pre-charging MOS transistor, one terminal of which is connected to the bit line, another terminal of which is used to receive the preset voltage, and a control terminal of which is used to receive the pre-charging signal, wherein the first pre-charging MOS transistor is configured to be turned on based on the pre-charging signal; A second pre-charging MOS transistor has one terminal connected to the complementary bit line, another terminal for receiving the preset voltage, and a control terminal for receiving the pre-charging signal. The second pre-charging MOS transistor is configured to be turned on based on the pre-charging signal.

6. The readout circuit according to claim 5, wherein: A terminal of the first pre-charging MOS transistor for receiving the preset voltage is connected to a terminal of the second pre-charging MOS transistor for receiving the preset voltage, and the first pre-charging MOS transistor and the second pre-charging MOS transistor are arranged in the same active area.

7. The readout circuit according to claim 5, wherein: The control terminal of the first pre-charging MOS transistor is connected to the control terminal of the second pre-charging MOS transistor.

8. The readout circuit according to claim 4, wherein: The second pre-charging unit includes a third pre-charging MOS tube, and the balancing unit includes a balancing MOS tube; The third pre-charging MOS transistor has one terminal connected to the read bit line or the complementary read bit line, another terminal for receiving the preset voltage, and a control terminal for receiving the pre-charging signal, and the third pre-charging MOS transistor is configured to be turned on based on the pre-charging signal; The equalizing MOS transistor is connected between the read bit line and the complementary read bit line and has a control terminal for receiving the equalizing signal.

9. The readout circuit according to claim 3, wherein: The precharge signal includes a first precharge signal and a second precharge signal, wherein: The first precharge unit is configured to precharge the bit line and the complementary bit line to the preset voltage based on the first precharge signal; The second precharge unit is configured to precharge the read bit line or the complementary read bit line to the preset voltage based on the second precharge signal.

10. The readout circuit according to claim 9, wherein: The preset voltage includes a first preset voltage and a second preset voltage, wherein: The first precharge unit is configured to precharge the bit line and the complementary bit line to the first preset voltage based on the first precharge signal; The second precharge unit is configured to precharge the read bit line or the complementary read bit line to the second preset voltage based on the second precharge signal.

11. A data reading method, applied to the reading circuit according to any one of claims 1 to 10, characterized in that: It includes a first readout phase, a data sharing phase, and a second readout phase that are performed sequentially, wherein: In the first readout phase, a first level signal is provided to a first signal terminal connected to the first PMOS transistor and the second PMOS transistor, and the first level signal is provided to a second signal terminal connected to the first PMOS transistor and the second PMOS transistor; During the data sharing phase, turning on the word line connected to the target memory cell; In the second readout phase, an isolation signal is provided, and the first level signal is provided to the first signal terminal, and a second level signal is provided to the second signal terminal, wherein the voltage of the first level signal is greater than the voltage of the second level signal.

12. The data reading method according to claim 11, wherein: Before the first readout stage, the method further includes: a precharge stage, wherein in the precharge stage, a precharge signal is provided to precharge the bit line, the readout bit line, the complementary bit line and the complementary readout bit line to a preset voltage.

13. The data reading method according to claim 12, wherein: The pre-charge stage includes: providing an isolation signal, connecting the bit line to the read bit line through a first isolation unit, and connecting the complementary bit line to the complementary read bit line through a second isolation unit; providing an equalization signal to connect the sense bit line to the complementary sense bit line via an equalization unit; A precharge signal is provided to precharge the bit line, the read bit line, the complementary bit line, and the complementary read bit line through the first precharge unit and / or the second precharge unit.

14. The data reading method according to claim 12, wherein: The first sensing stage further includes providing an equalization signal to connect the sensing bit line to the complementary sensing bit line.

15. A memory comprising a storage unit and a complementary storage unit, characterized in that: The readout circuit according to any one of claims 1 to 10 is applied, wherein the memory cell is connected to the readout circuit via a bit line, and the complementary memory cell is connected to the readout circuit via a complementary bit line.

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