A high-voltage gallium nitride MOSFET device, preparation method and chip

Abstract

The present application belongs to the field of semiconductor technology and provides a high-voltage gallium nitride MOSFET device, a preparation method, and a chip. Multiple dielectric field plate layers are sequentially stacked between a gallium nitride drift layer and a gate insulating layer. The distance between the dielectric field plate layer and the gate insulating layer is inversely proportional to the width of the dielectric field plate layer. Furthermore, an isolation metal layer is provided within each dielectric field plate layer. This allows the dielectric field plate layers and the isolation metal layers of varying lengths to form stepped corners at their interfaces with the gallium nitride drift layer, thereby forming multiple electric field spikes within the gallium nitride drift layer. These factors help to offset the electric field concentration caused by the sharp corners of the gate insulating layer, thereby achieving uniform electric field performance and reducing the electric field spikes borne by the gate insulating layer. This prevents electric field concentration on the gate insulating layer, thereby increasing the breakdown voltage of the high-voltage gallium nitride MOSFET device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a high-voltage gallium nitride MOSFET device, a preparation method, and a chip. Background Art

[0002] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, such as a high critical breakdown field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operation. Vertical GaN trench metal-oxide semiconductor field-effect transistors (TG-MOSFETs) are extremely popular in high-power applications. The simplicity of GaN epitaxial growth and device fabrication also offers potential advantages in structural improvements.

[0003] However, the biggest challenge of TG-MOSFET is that the peak electric field of its bottom trench exceeds the critical breakdown electric field strength of the GaN material, resulting in a low breakdown voltage, which greatly limits the application range of TG-MOSFET. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a high-voltage gallium nitride MOSFET device, a preparation method and a chip, aiming to solve the problem of low breakdown voltage of TG-MOSFET prepared based on GaN materials.

[0005] A first aspect of an embodiment of the present application provides a high-voltage gallium nitride MOSFET device, the high-voltage gallium nitride MOSFET device comprising:

[0006] GaN substrate;

[0007] A gallium nitride drift layer is provided on the front surface of the gallium nitride substrate;

[0008] A first N-type doping region, a second N-type doping region, and a gate insulating layer are provided on the gallium nitride drift layer; wherein the gate insulating layer is concave, and the first N-type doping region and the second N-type doping region are respectively provided on both sides of the gate insulating layer;

[0009] A gate material layer is provided on the inner wall of the groove of the gate insulating layer;

[0010] A first P-type base region and a first P-type doping layer are provided on the first N-type doping region;

[0011] A second P-type base region and a second P-type doping layer are provided on the second N-type doping region;

[0012] A first source doping region and a second source doping region are respectively provided on the first P-type base region and the second P-type base region;

[0013] a source metal layer, contacting the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region;

[0014] a dielectric layer disposed between the source metal layer and the gate material layer; wherein the dielectric layer has a convex structure, and a convex portion of the dielectric layer is located in a groove of the gate material layer;

[0015] A drain metal layer is provided on the back side of the gallium nitride substrate;

[0016] A plurality of dielectric field plate layers stacked in sequence are provided between the gate insulating layer and the gallium nitride drift layer; wherein the distance between the dielectric field plate layer and the gate insulating layer is inversely proportional to the width of the dielectric field plate layer, and an isolation metal layer is provided in each dielectric field plate layer.

[0017] In one embodiment, the plurality of dielectric field plate layers stacked sequentially form a trapezoidal structure.

[0018] In one embodiment, the width of the dielectric field plate layer is less than or equal to the width of the gate insulation layer.

[0019] In one embodiment, the distance between the isolation metal layer and the gate insulation layer is in inverse proportion to the width of the isolation metal layer.

[0020] In one embodiment, the dielectric field plate layer is a high dielectric material.

[0021] In one embodiment, the high dielectric constant of the high dielectric material is greater than 3.

[0022] In one embodiment, the thickness of each dielectric field plate layer is equal.

[0023] In one embodiment, the width differences between adjacent dielectric field plate layers are equal.

[0024] A second aspect of the embodiments of the present application further provides a method for preparing a high-voltage gallium nitride MOSFET device, comprising:

[0025] forming a gallium nitride drift layer on the front surface of the gallium nitride substrate, and etching a first deep trench on the front surface of the gallium nitride drift layer;

[0026] Repeating multiple times to form a dielectric field plate layer and an isolation metal layer on the inner wall of the first deep trench, and epitaxially growing the gallium nitride drift layer after each formation of the dielectric field plate layer and the isolation metal layer, so as to form a plurality of dielectric field plate layers stacked in sequence within the first deep trench; wherein the width of the dielectric field plate layers gradually increases, and the isolation metal layer is disposed within each dielectric field plate layer;

[0027] forming an N-type doping layer on the gallium nitride drift layer;

[0028] forming a P-type base region, a P-type doping layer and a source doping layer on the N-type doping layer; wherein the source doping layer is located on the P-type base region;

[0029] Etching the source doping layer to form a second deep trench extending into the gallium nitride drift layer, so as to divide the source doping layer into a first source doping region and a second source doping region, divide the P-type base region into a first P-type base region and a second P-type base region, and divide the N-type doping layer into a first N-type doping region and a second N-type doping region;

[0030] forming a gate insulating layer on the inner wall of the second deep trench, and forming a gate material layer on the inner wall of the gate insulating layer; wherein the gate insulating layer and the gate material layer both have a concave structure;

[0031] forming a dielectric layer on the gate material layer; wherein the dielectric layer has a convex structure, and a convex portion of the dielectric layer is located in a groove of the gate material layer;

[0032] forming a source metal layer in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; wherein the bottom of the dielectric layer is located in the groove of the source metal layer;

[0033] A drain metal layer is formed on the back side of the gallium nitride substrate.

[0034] A third aspect of the embodiments of the present application further provides a chip, wherein the chip integrates the high-voltage-resistant gallium nitride MOSFET device as described in any of the above embodiments; or includes a high-voltage-resistant gallium nitride MOSFET device prepared by the preparation method described in the above embodiments.

[0035] Compared with the prior art, the embodiments of the present application have the following advantages: by forming a plurality of dielectric field plate layers stacked in sequence between the gallium nitride drift layer and the gate insulating layer, the distance between the dielectric field plate layer and the gate insulating layer is inversely proportional to the width of the dielectric field plate layer, and an isolation metal layer is provided within each dielectric field plate layer, so that the dielectric field plate layers and the isolation metal layers of varying lengths can form stepped sharp corners at the interface with the gallium nitride drift layer, thereby forming multiple electric field spikes within the gallium nitride drift layer, thereby distributing the electric field concentration caused by the sharp corner structure of the gate insulating layer, achieving the purpose of homogenizing the electric field, reducing the electric field spikes borne by the gate insulating layer, avoiding electric field concentration on the gate insulating layer, and achieving the effect of improving the breakdown voltage of the high-voltage gallium nitride MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic diagram of a vertical cross-section structure of a gallium nitride-based high-voltage gallium nitride MOSFET device provided by one embodiment of the present application;

[0037] Figure 2 This is a schematic diagram of a vertical cross-section structure of a gallium nitride-based high-voltage gallium nitride MOSFET device provided by another embodiment of the present application;

[0038] Figure 3 This is a flow chart of a method for preparing a gallium nitride-based high-voltage gallium nitride MOSFET device provided by one embodiment of the present application;

[0039] Figure 4 1 is a schematic structural diagram of forming a gallium nitride drift layer 200 on a gallium nitride substrate 100 according to an embodiment of the present application;

[0040] Figure 5 3 is a schematic structural diagram of multiple dielectric field plate layers 310 provided in one embodiment of the present application;

[0041] Figure 6 This is a schematic structural diagram after forming an N-type doping layer 400 according to an embodiment of the present application;

[0042] Figure 7 1 is a schematic diagram of a structure for forming a first P-type doping layer 510, a second P-type doping layer 520, a P-base region 600, and a source doping layer 700, provided in one embodiment of the present application;

[0043] Figure 8 This is a schematic structural diagram of forming a second deep groove 202 according to an embodiment of the present application;

[0044] Figure 9 8 is a schematic structural diagram after forming a gate insulating layer 810, a gate material layer 820, and a dielectric layer 830, according to an embodiment of the present application;

[0045] Figure 10 This is a schematic structural diagram after forming a source metal layer 840 and a drain metal layer 850 according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0047] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0048] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0050] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0051] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, including a high critical breakdown field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operation capability. Third-generation GaN-based semiconductor devices, such as high electron mobility transistors (HEMTs) and heterojunction field-effect transistors (HFETs), have already been applied, particularly in fields requiring high power and high frequency, such as radio frequency and microwaves.

[0052] The biggest challenge of TG-MOSFET is that the peak electric field of its bottom trench exceeds the critical breakdown electric field strength of the GaN material, resulting in a low breakdown voltage, which greatly limits the application range of TG-MOSFET.

[0053] In order to solve the above technical problems, an embodiment of the present application provides a high-voltage gallium nitride MOSFET device, which aims to improve the breakdown voltage of a gallium nitride-based vertical trench MOSFET device.

[0054] In one embodiment, combined Figure 1 As shown, the high-voltage gallium nitride MOSFET device in this embodiment includes: a gallium nitride substrate 100, a gallium nitride drift layer 200, a first N-type doping region 410, a second N-type doping region 420, a gate insulating layer 810, a gate material layer 820, a first P-type base region 610, a first P-type doping layer 510, a second P-type base region 620, a second P-type doping layer 520, a first source doping region 710, a second source doping region 720, a source metal layer 840, a dielectric layer 830, a drain metal layer 850, and a plurality of dielectric field plate layers 310.

[0055] Specifically, the gallium nitride drift layer 200 is disposed on the front surface of the gallium nitride substrate 100, the drain metal layer 850 is disposed on the back surface of the gallium nitride substrate 100, the first N-type doping region 410, the second N-type doping region 420, and the gate insulation layer 810 are disposed on the gallium nitride drift layer 200, the gate insulation layer 810 is concave, and the first N-type doping region 410 and the second N-type doping region 420 are respectively disposed on both sides of the gate insulation layer 810; the gate material layer 820 is disposed on the inner wall of the groove of the gate insulation layer 810, so that the gate material layer 820 is also configured as a concave structure.

[0056] The first P-type base region 610 and the first P-type doping layer 510 are arranged on the first N-type doping region 410; the second P-type base region 620 and the second P-type doping layer 520 are arranged on the second N-type doping region 420; the first source doping region 710 and the second source doping region 720 are respectively arranged on the first P-type base region 610 and the second P-type base region 620; the source metal layer 840 is in contact with the first P-type doping layer 510, the second P-type doping layer 520, the first source doping region 710 and the second source doping region 720; the dielectric layer 830 is arranged between the source metal layer 840 and the gate material layer 820, and the dielectric layer 830 has a convex structure, the convex portion of the dielectric layer 830 is located in the groove of the gate material layer 820, and the source metal layer 840 has a concave structure, and the bottom of the dielectric layer 830 is located in the groove of the source metal layer 830.

[0057] In this embodiment, multiple dielectric field plate layers 310 are located between the gate insulating layer 810 and the gallium nitride drift layer 200. The width of the multiple dielectric field plate layers 310 gradually decreases according to the distance from the gate insulating layer 810. Specifically, the farther the distance between the dielectric field plate layer 310 and the bottom of the gate insulating layer 810 is, the smaller the width of the dielectric field plate layer 310 is. An isolation metal layer 311 is provided in each dielectric field plate layer 310.

[0058] In this embodiment, a plurality of dielectric field plate layers 310 are sequentially stacked between the GaN drift layer 200 and the gate insulating layer 810. The distance between the dielectric field plate layers 310 and the gate insulating layer 810 is inversely proportional to the width of the dielectric field plate layers 310. Furthermore, an isolation metal layer 311 is provided within each dielectric field plate layer 310. This allows the dielectric field plate layers 310 and the isolation metal layers 311 of varying lengths to form stepped corners at their interfaces with the GaN drift layer 200. This results in multiple electric field peaks within the GaN drift layer 200, thereby distributing the electric field concentration caused by the sharp corners of the gate insulating layer 810. This achieves the purpose of homogenizing the electric field and reducing the electric field peaks borne by the gate insulating layer 810. This prevents electric field concentration on the gate insulating layer 810, thereby improving the breakdown voltage of the high-voltage GaN MOSFET device.

[0059] In one embodiment, the first dielectric field plate layer 310 in the multi-layer dielectric field plate layer 310 contacts the bottom of the gate insulating layer 810 , and the gate insulating layer 810 has a concave structure formed at the bottom and two sides.

[0060] In one embodiment, the plurality of dielectric field plate layers 310 stacked sequentially form a trapezoidal structure.

[0061] In this embodiment, as the distance between the dielectric field plate layer 310 and the bottom of the gate insulation layer 810 gradually increases or decreases, the width of the dielectric field plate layer 310 also gradually decreases. Specifically, the width of each dielectric field plate layer 310 below the first dielectric field plate layer 310 is smaller than the width of the adjacent upper dielectric field plate layer 310, and both side edges of each dielectric field plate layer 310 below the first dielectric field plate layer 310 are located on the inner side of both side edges of the adjacent upper dielectric field plate layer 310, thereby forming a step structure between adjacent dielectric field plate layers 310.

[0062] In one embodiment, the width of the dielectric field plate layer 310 is less than or equal to the width of the gate insulation layer 810 .

[0063] In this embodiment, the first layer of the dielectric field plate layer 310 contacts the bottom of the gate insulating layer 810, and its width is the maximum width among the widths of the multiple dielectric field plate layers 310. The left side boundary of the first layer of the dielectric field plate layer 310 is aligned with the left side boundary of the bottom of the gate insulating layer 810, or is located on the inner side of the left side boundary of the bottom of the gate insulating layer 810. The right side boundary of the first layer of the dielectric field plate layer 310 is aligned with the right side boundary of the bottom of the gate insulating layer 810, or is located on the inner side of the right side boundary of the bottom of the gate insulating layer 810.

[0064] In one embodiment, the distance between the isolation metal layer 311 and the gate insulation layer 810 is inversely proportional to the width of the isolation metal layer 311 .

[0065] In this embodiment, the isolation metal layer 311 is located in the corresponding dielectric field plate layer 310, and the width of the multiple isolation metal layers 311 gradually decreases according to the distance from the gate insulation layer 810. Specifically, the farther the distance between the isolation metal layer 311 and the bottom of the gate insulation layer 810 is, the smaller the width of the isolation metal layer 311 is.

[0066] In this embodiment, multiple dielectric field plate layers 310 with a wide top and narrow bottom are formed between the gate insulating layer 810 and the gallium nitride drift layer 200. This allows multiple electric field peaks to be formed at the sharp corners of the dielectric field plate layers 310, thereby homogenizing the electric field of the gallium nitride drift layer 200 and improving the breakdown voltage of the device. Furthermore, this allows the Miller capacitance Cgd of the device to be shielded, reducing the switching loss of the device, while minimizing the increase in the parasitic capacitance Cds within the device.

[0067] In one embodiment, the dielectric field plate layer 310 is a high dielectric material.

[0068] In one embodiment, the high dielectric constant of the high dielectric material is greater than 3.

[0069] In this embodiment, by using a high-dielectric material to form the dielectric field plate layer 310, the dielectric field plate layer 310 can have a stronger attraction for holes in the gallium nitride drift layer 200, thereby improving the electric field spike capability of the dielectric field plate layer 310, thereby expanding the process window during the manufacturing process.

[0070] In one embodiment, the dielectric field plate layer 310 around the isolation metal layer 311 has the same thickness.

[0071] In one embodiment, the thickness of each dielectric field plate layer 310 is equal.

[0072] In one embodiment, the width differences between adjacent dielectric field plate layers 310 are equal.

[0073] In this embodiment, by controlling the size ratio of the isolation metal layer 311 and the dielectric field plate layer 310, the electric field peaks formed at the sharp corners of adjacent dielectric field plate layers 310 can be made equal to the electric field peaks at the sharp corners of the gate insulation layer 810, thereby homogenizing the electric field of the gallium nitride drift layer 200 and improving the breakdown voltage of the high-voltage gallium nitride MOSFET device.

[0074] In one embodiment, the dielectric layer 830 is disposed between the source metal layer 840 and the gate material layer 820 to isolate the source metal layer 840 from the gate material layer 820. Figure 1 As shown, the source metal layer 840 has a concave structure, and the dielectric layer 830 is located in the groove of the source metal layer 840 .

[0075] The dielectric layer 830 has a convex structure, the convex portion of the dielectric layer 830 is located in the groove of the gate material layer 820 , and the bottom of the dielectric layer 830 is located in the groove of the source metal layer 840 .

[0076] In one embodiment, dielectric layer 830 may be a silicon nitride material.

[0077] In one embodiment, the gate material layer 820 may be a polysilicon material.

[0078] In one embodiment, the gate insulating layer 810 may be made of silicon oxide.

[0079] In one embodiment, the dielectric layer 830 is further disposed between the gate insulation layer 810 and the source metal layer 840 .

[0080] In one embodiment, the width of the bottom of the dielectric layer 830 is greater than the width of the gate insulating layer 810 .

[0081] In one embodiment, the thickness of the gate insulating layer 810 is equal to the sum of the thicknesses of the first N-type doping region 410 , the first P-type base region 610 , and the first source doping region 710 .

[0082] In one embodiment, the first N-type doping region 410 and the second N-type doping region 420 are symmetrically arranged.

[0083] In one embodiment, the first P-type base region 610 and the second P-type base region 620 are symmetrically arranged.

[0084] In one embodiment, the first source doping region 710 and the second source doping region 720 are symmetrically arranged.

[0085] In one embodiment, the first side of the first source doping region 710 is flush with the first side of the first P-type base region 610 and contacts the first side of the gate insulating layer 810. The gate insulating layer 810 is formed into a concave structure by a bottom, a first side, and a second side.

[0086] In one embodiment, the width of the first source doping region 710 is greater than the width of the first P-type base region 610 .

[0087] In one embodiment, the GaN substrate 100 and the GaN drift layer 200 are both N-type doped GaN.

[0088] In one embodiment, the doping concentration of the GaN substrate 100 is greater than the doping concentration of the GaN drift layer 200 .

[0089] In one embodiment, combined Figure 2 As shown, a plurality of second P-type isolation regions 320 are further provided between the GaN drift layer 200 and the first N-type doping region 410 and the second N-type doping region 420 . The plurality of second P-type isolation regions 320 are respectively provided on both sides of the dielectric field plate layer 310 .

[0090] Combine Figure 1 As shown, the multiple second P-type isolation regions 320 do not contact each other, and the second P-type isolation regions 320 on the first side of the dielectric field plate layer 310 contact the first N-type doping region 410, and the second P-type isolation regions 320 on the second side of the dielectric field plate layer 310 contact the second N-type doping region 420.

[0091] In one embodiment, the doping concentration of the second P-type isolation region 320 is negatively correlated with the first spacing distance; wherein the first spacing distance is the distance between the second P-type isolation region 320 and the dielectric field plate layer 310 .

[0092] In this embodiment, the doping concentration of the second P-type isolation region 320 that is farther away from the dielectric field plate layer 310 is lower, and the doping concentration of the second P-type isolation region 320 that is closer to the dielectric field plate layer 310 is higher.

[0093] In one embodiment, the intervals between the plurality of second P-type isolation regions 320 on the first side of the dielectric field plate layer 310 are equal in width; the intervals between the plurality of second P-type isolation regions 320 on the second side of the dielectric field plate layer 310 are equal in width.

[0094] In one embodiment, the spacing width between the plurality of second P-type isolation regions 320 is negatively correlated with the second spacing distance; wherein the second spacing distance is the distance between the second P-type isolation region 320 and the dielectric field plate layer 310 .

[0095] In this embodiment, the farther the second P-type isolation region 320 is from the dielectric field plate layer 310 , the smaller the spacing between adjacent second P-type isolation regions 320 , and the closer the second P-type isolation region 320 is to the dielectric field plate layer 310 , the larger the spacing between adjacent second P-type isolation regions 320 .

[0096] In one embodiment, the width of the dielectric field plate layer 310 is greater than the width of the second P-type isolation region 320 .

[0097] In this embodiment, the width of the dielectric field plate layer 310 is greater than the width of the polysilicon material layer 820. At this time, a depletion region is formed between the dielectric field plate layer 310 and the gallium nitride drift layer 200. The dielectric field plate layer 310 can protect the sharp corners on both sides of the bottom of the gate insulation layer 810. At the same time, the multiple second P-type isolation regions 320 uniformize the electric field between the drain metal layer 850 and the source metal layer 840, avoiding the electric field concentration on the gate insulation layer 810, thereby achieving the purpose of improving the breakdown voltage of the device.

[0098] In one embodiment, the thicknesses of the plurality of second P-type isolation regions 320 are equal.

[0099] In one embodiment, the width of the second P-type isolation region 320 is negatively correlated with the second spacing distance; wherein the second spacing distance is the distance between the second P-type isolation region 320 and the dielectric field plate layer 310 .

[0100] In this embodiment, the farther the second P-type isolation region 320 is from the dielectric field plate layer 310 , the smaller the width of the second P-type isolation region 320 ; and the closer the second P-type isolation region 320 is to the dielectric field plate layer 310 , the larger the width of the second P-type isolation region 320 .

[0101] In one embodiment, the number of the second P-type isolation regions 320 on the first side of the dielectric field plate layer 310 is equal to the number of the second P-type isolation regions 320 on the second side of the dielectric field plate layer 310 .

[0102] In this embodiment, the dielectric field plate layer 310 and the second P-type isolation region 320 are provided to make the electric field between the source and drain of the device more uniform. At this time, when the device is working, the current flowing from the drain to the source is dispersed, thereby dispersing the potential borne by the gate insulation layer 810, thereby achieving the purpose of increasing the breakdown voltage of the device.

[0103] The present application also provides a method for preparing a high voltage gallium nitride MOSFET device of HEMT, see Figure 3 As shown, the preparation method in this embodiment includes steps S10 to S90.

[0104] In step S10 , a gallium nitride drift layer 200 is formed on the front surface of the gallium nitride substrate 100 , and a first deep trench 201 is formed on the front surface of the gallium nitride drift layer 200 by etching.

[0105] Combine Figure 3 As shown, the GaN drift layer 200 is formed on the front surface of the GaN substrate 100. Specifically, the GaN drift layer 200 can be formed on the front surface of the GaN substrate 100 by epitaxial growth. Then, a first photomask is used to cover the surface of the GaN drift layer 200 to form a first deep trench 201 on the surface of the GaN drift layer 200.

[0106] In one embodiment, the first deep trench 201 may be located in a central region of the surface of the GaN drift layer 200 .

[0107] In one embodiment, the thickness of the GaN drift layer 200 is greater than the thickness of the GaN substrate 100 .

[0108] In one embodiment, the GaN drift layer 200 and the GaN substrate 100 are both N-type GaN, wherein the doping concentration of the N-type doping element in the GaN drift layer 200 is lower than the doping concentration of the N-type doping element in the GaN substrate 100 .

[0109] In one embodiment, the N-type doping element in the GaN drift layer 200 and the GaN substrate 100 may be silicon.

[0110] In step S20 , a dielectric field plate layer 310 and an isolation metal layer 311 are repeatedly formed on the inner wall of the first deep trench 201 . After each formation of the dielectric field plate layer 310 and the isolation metal layer 311 , the gallium nitride drift layer 200 is epitaxially grown, thereby forming a plurality of dielectric field plate layers 310 stacked in sequence within the first deep trench 201 .

[0111] In this embodiment, combined with Figure 5As shown, the width of each dielectric field plate layer 310 gradually increases, and the dielectric field plate layers 310 and the isolation metal layers 311 are formed in sequence. Since the isolation metal layers 311 are formed on the inner walls of the dielectric field plate layers 310, the width of the isolation metal layer 311 corresponding to each dielectric field plate layer 310 is smaller than the width of the dielectric field plate layer 310 of that layer. Then, the sidewall portions of the dielectric field plate layers 310 and the isolation metal layers 311 are removed by etching, leaving only the dielectric field plate layer 310 and the isolation metal layer 311 at the bottom.

[0112] Multiple layers of dielectric field plate layers 310 are repeatedly formed in sequence, and then an isolation metal layer 311 is formed on the inner wall of each dielectric field plate layer 310 after it is formed. Finally, the sidewall portions of the dielectric field plate layer 310 and the isolation metal layer 311 are etched away, so that an isolation metal layer 311 is provided in each dielectric field plate layer 310.

[0113] In one embodiment, a photomask may be formed on the surface of the gallium nitride drift layer 200, and then P-type dopant ions may be implanted into the surface of the gallium nitride drift layer 200 under the cover of the photomask, thereby forming a plurality of second P-type isolation regions 320 on the surface of the gallium nitride drift layer 200. The positions and structures of the plurality of second P-type isolation regions 320 are as follows: Figure 2 shown.

[0114] A plurality of second P-type isolation regions 320 are respectively disposed on both sides of the dielectric field plate layer 310 .

[0115] In one embodiment, the P-type dopant ions may be magnesium ions.

[0116] In step S30, combining Figure 6 As shown, an N-type doping layer 400 is formed on the GaN drift layer 200, and Figure 7 As shown, a P-type base region 600 , a P-type doping layer and a source doping layer 700 are formed on the N-type doping layer 400 ; wherein the source doping layer 700 is located on the P-type base region 600 .

[0117] Combine Figure 6 As shown, the N-type doped layer 400 can be formed on the GaN drift layer 200 by implanting N-type dopant ions into the front surface of the GaN drift layer 200 , or the N-type doped layer 400 can be directly formed on the GaN drift layer 200 by epitaxial growth.

[0118] Combine Figure 7As shown, P-type doping ions are injected into the front side of the N-type doping layer 400 or a P-type doping layer is formed through an epitaxial growth process, and then a P-base region 600 and a source doping layer 700 are formed at the center of the P-type doping layer at one time. At this time, the P-type doping layer is divided into a first P-type doping layer 510 and a second P-type doping layer 520. The first P-type doping layer 510 and the second P-type doping layer 520 are respectively located on both sides of the P-base region 600 and the source doping layer 700.

[0119] Combine Figure 7 As shown, the width of the source doping layer 700 is greater than the width of the P base region 600, the first P-type doping layer 510 and the second P-type doping layer 520 are L-shaped structures, and the source doping layer 70 is also located on the horizontal parts of the first P-type doping layer 510 and the second P-type doping layer 520.

[0120] In one embodiment, combined Figure 7 As shown, the heights of the vertical portions of the first P-type doping layer 510 and the second P-type doping layer 520 are equal to the thickness of the source doping layer 700 .

[0121] In one embodiment, the width of the source doping layer 700 is greater than the width of the P-type base region 600 , and both side boundaries of the source doping layer 700 are located outside the both side boundaries of the P-type base region 600 .

[0122] In one embodiment, the first P-type doping layer 510 , the second P-type doping layer 520 , and the P-type base region 600 may be P-type gallium nitride, and the source doping layer 700 may be N-type gallium nitride.

[0123] Specifically, N-type gallium nitride can be formed by doping silicon into a gallium nitride material, and P-type gallium nitride can be formed by doping magnesium into a gallium nitride material.

[0124] In one embodiment, the doping concentration of the P-type element in the first P-type doping layer 510 and the second P-type doping layer 520 is greater than the doping concentration of the P-type element in the P-type base region 600 .

[0125] In step S40, etching is performed on the source doping layer 700 to form a second deep trench 202 that penetrates into the gallium nitride drift layer 200, so as to divide the source doping layer 700 into a first source doping region 710 and a second source doping region 720, divide the P-type base region 600 into a first P-type base region 610 and a second P-type base region 620, and divide the N-type doping layer 400 into a first N-type doping region 410 and a second N-type doping region 420.

[0126] In this embodiment, combined with Figure 8As shown, a second deep trench 202 is etched on the source doping layer 700, and the second deep trench 202 penetrates into the dielectric field plate layer 310 in the gallium nitride drift layer 200. At this time, the source doping layer 700 is divided into a first source doping region 710 and a second source doping region 720 by the second deep trench 202, and the P-type base region 600 is divided into a first P-type base region 610 and a second P-type base region 620 by the second deep trench 202. The N-type doping layer 400 is divided into a first N-type doping region 410 and a second N-type doping region 420 by the second deep trench 202.

[0127] In one embodiment, the widths of the first source doping region 710 and the second source doping region 720 on both sides of the second deep trench 202 are equal.

[0128] In one embodiment, the widths of the first P-type base region 610 and the second P-type base region 620 on both sides of the second deep trench 202 are equal.

[0129] In one embodiment, the widths of the first N-type doping region 410 and the second N-type doping region 420 on both sides of the second deep trench 202 are equal.

[0130] In step S50 , a gate insulating layer 810 is formed on the inner wall of the second deep trench 202 , and a gate material layer 820 is formed on the inner wall of the gate insulating layer 810 ; wherein both the gate insulating layer 810 and the gate material layer 820 have a concave structure.

[0131] In this embodiment, combined with Figure 9 As shown, a gate insulating layer 810 is formed on the inner wall of the second deep trench 202 , and a gate material layer 820 can be formed on the inner wall of the groove formed by the gate insulating layer 810 by depositing gate material on the inner wall of the gate insulating layer 810 using the same deposition process.

[0132] In step S60 , a dielectric layer 830 is formed on the gate material layer 820 .

[0133] In this embodiment, combined with Figure 9 As shown, the dielectric layer 830 is arranged between the source metal layer 840 and the gate material layer 820. Specifically, the dielectric layer 830 has a convex structure, and the protruding portion of the dielectric layer 830 is located in the groove of the gate material layer 820. The gate material layer 820 is isolated by the dielectric layer 830 and the gate insulation layer 810.

[0134] In one embodiment, the width of the dielectric layer 830 is greater than the width of the gate insulating layer 810 .

[0135] In one embodiment, the thickness of the gate insulating layer 810 is equal to the sum of the thicknesses of the first N-type doping region 410 , the first P-type base region 610 , and the first source doping region 710 .

[0136] In step S70 , a source metal layer 840 is formed to contact the first and second P-type doping layers 510 and 520 , the first and second source doping regions 710 and 720 .

[0137] In this embodiment, combined with Figure 10 As shown, the source metal layer 840 has a concave structure, and the bottom of the dielectric layer 830 is located in the groove of the source metal layer 840 .

[0138] In step S80 , a drain metal layer 850 is formed on the back surface of the gallium nitride substrate 100 .

[0139] In this embodiment, combined with Figure 10 As shown, a drain metal layer 850 may be formed on the back side of the gallium nitride substrate 100 by metal deposition.

[0140] An embodiment of the present application further provides a chip, in which the high-voltage gallium nitride MOSFET device as described in any of the above embodiments is integrated.

[0141] In one embodiment, the chip integrates a high-voltage gallium nitride MOSFET device manufactured by the manufacturing method described in the above embodiment.

[0142] In this embodiment, the chip includes a chip substrate, on which one or more gallium nitride vertical trench MOSFET devices are arranged. The gallium nitride vertical trench MOSFET device can be prepared by the preparation method in any of the above embodiments, or the gallium nitride vertical trench MOSFET device in any of the above embodiments can be arranged on the chip substrate.

[0143] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit together with the gallium nitride vertical trench MOSFET device.

[0144] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0145] Compared with the prior art, the embodiments of the present application have the following advantages: by forming a plurality of dielectric field plate layers stacked in sequence between the gallium nitride drift layer and the gate insulating layer, the distance between the dielectric field plate layer and the gate insulating layer is inversely proportional to the width of the dielectric field plate layer, and an isolation metal layer is provided within each dielectric field plate layer, so that the dielectric field plate layers and the isolation metal layers of varying lengths can form stepped sharp corners at the interface with the gallium nitride drift layer, thereby forming multiple electric field spikes within the gallium nitride drift layer, thereby distributing the electric field concentration caused by the sharp corner structure of the gate insulating layer, achieving the purpose of homogenizing the electric field, reducing the electric field spikes borne by the gate insulating layer, avoiding electric field concentration on the gate insulating layer, and achieving the effect of improving the breakdown voltage of the high-voltage gallium nitride MOSFET device.

[0146] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0147] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0148] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A high-voltage gallium nitride MOSFET device, characterized in that: The high-voltage gallium nitride MOSFET device comprises: GaN substrate; A gallium nitride drift layer is provided on the front surface of the gallium nitride substrate; A first N-type doping region, a second N-type doping region, and a gate insulating layer are provided on the gallium nitride drift layer; wherein the gate insulating layer is concave, and the first N-type doping region and the second N-type doping region are respectively provided on both sides of the gate insulating layer; A gate material layer is provided on the inner wall of the groove of the gate insulating layer; A first P-type base region and a first P-type doping layer are provided on the first N-type doping region; A second P-type base region and a second P-type doping layer are provided on the second N-type doping region; A first source doping region and a second source doping region are respectively provided on the first P-type base region and the second P-type base region; a source metal layer, contacting the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; a dielectric layer disposed between the source metal layer and the gate material layer; wherein the dielectric layer has a convex structure, and a convex portion of the dielectric layer is located in a groove of the gate material layer; A drain metal layer is provided on the back side of the gallium nitride substrate; A plurality of dielectric field plate layers stacked in sequence are provided between the gate insulating layer and the gallium nitride drift layer; wherein the distance between the dielectric field plate layer and the gate insulating layer is inversely proportional to the width of the dielectric field plate layer, and an isolation metal layer is provided in each dielectric field plate layer.

2. The high-voltage gallium nitride MOSFET device according to claim 1, wherein: The plurality of dielectric field plate layers stacked in sequence form a trapezoidal structure.

3. The high-voltage gallium nitride MOSFET device according to claim 1, wherein: The width of the dielectric field plate layer is less than or equal to the width of the gate insulating layer.

4. The high-voltage gallium nitride MOSFET device according to claim 1, wherein: The distance between the isolation metal layer and the gate insulation layer is in inverse proportion to the width of the isolation metal layer.

5. The high-voltage gallium nitride MOSFET device according to claim 1, wherein: The dielectric field plate layer is made of high dielectric material.

6. The high-voltage gallium nitride MOSFET device according to claim 5, wherein: The dielectric constant of the high dielectric material is greater than 3.

7. The high-voltage gallium nitride MOSFET device according to any one of claims 1 to 6, wherein: The thickness of each dielectric field plate layer is equal.

8. The high-voltage gallium nitride MOSFET device according to any one of claims 1 to 6, wherein: The width differences between adjacent dielectric field plate layers are equal.

9. A method for preparing a high-voltage gallium nitride MOSFET device, characterized in that: include: forming a gallium nitride drift layer on the front surface of the gallium nitride substrate, and etching a first deep trench on the front surface of the gallium nitride drift layer; Repeating multiple times to form a dielectric field plate layer and an isolation metal layer on the inner wall of the first deep trench, and epitaxially growing the gallium nitride drift layer after each formation of the dielectric field plate layer and the isolation metal layer, so as to form a plurality of dielectric field plate layers stacked in sequence within the first deep trench; wherein the width of the dielectric field plate layers gradually increases, and the isolation metal layer is disposed within each dielectric field plate layer; An N-type doped layer is formed on the gallium nitride drift layer, and a P-type base region, a P-type doped layer, and a source doped layer are formed on the N-type doped layer; wherein the source doped layer is located on the P-type base region, and the P-type base region and the source doped layer divide the P-type doped layer into a first P-type doped layer and a second P-type doped layer, and the first P-type doped layer and the second P-type doped layer are respectively located on either side of the P-base region and the source doped layer; Etching the source doping layer to form a second deep trench extending into the gallium nitride drift layer, so as to divide the source doping layer into a first source doping region and a second source doping region, divide the P-type base region into a first P-type base region and a second P-type base region, and divide the N-type doping layer into a first N-type doping region and a second N-type doping region; forming a gate insulating layer on the inner wall of the second deep trench, and forming a gate material layer on the inner wall of the gate insulating layer; wherein the gate insulating layer and the gate material layer both have a concave structure; forming a dielectric layer on the gate material layer; wherein the dielectric layer has a convex structure, and a convex portion of the dielectric layer is located in a groove of the gate material layer; forming a source metal layer in contact with the first P-type doped layer, the second P-type doped layer, the first source doped region, and the second source doped region; wherein the bottom of the dielectric layer is located in the groove of the source metal layer; A drain metal layer is formed on the back side of the gallium nitride substrate.

10. A chip, characterized in that: The chip integrates the high-voltage-withstand-type gallium nitride MOSFET device according to any one of claims 1 to 8; or includes the high-voltage-withstand-type gallium nitride MOSFET device prepared by the preparation method according to claim 9.

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