A dual tube driver circuit suitable for high frequency applications

Abstract

This invention relates to the field of switching power supply conversion, and more specifically, to a dual-transistor drive circuit suitable for high-frequency applications. It employs a separate dual NPN power transistor operating mode. Relying on a first drive unit, a second drive unit, a third drive unit, and the first power transistor NPN1, the second power transistor NPN2 is forcibly clamped in the critical state between the saturation and amplification regions. The third drive unit achieves rapid turn-off of over 1A, thus achieving the fastest turn-off speed for the second power transistor NPN2. This raises the operating frequency of NPN transistors from the current 65kHz to 120kHz, achieving a frequency range currently only achievable by expensive Cool MOSFETs. Furthermore, the drive current of the second power transistor NPN2 is introduced into the primary inductance Lp of the external transformer through the first power transistor NPN1, significantly reducing drive losses.

Description

Technical Field

[0001] This invention relates to the field of switching power supply conversion, and more specifically, to a dual-transistor drive circuit suitable for high-frequency applications. Background Technology

[0002] With the development of modern fast charging technology, charging voltage and current have gradually increased, expanding from a single 5V output to 3-48V output, and the output power has become common up to 65W. A few mobile phone manufacturers have increased it to 120W, and chargers with a power of 65W or less are the absolute mainstream at present. In the 15W to 65W range, the power transistors driven are all NMOS, which are at least twice as expensive as power transistors.

[0003] However, the use of power transistor drivers has always been limited in the high-power field due to the driving current loss and turn-off loss. Currently, the application of all transistor drivers is limited to within 15W, especially in the 5W power range. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a dual-transistor drive circuit suitable for high-frequency applications.

[0005] To achieve the above objectives, the first technical solution adopted by the present invention is as follows:

[0006] A dual-transistor drive circuit suitable for high-frequency applications includes a logic control unit, a first drive unit, a second drive unit, a third drive unit, a first power transistor NPN1, a second power transistor NPN2, a current peak sampling unit, and a drive current generation unit.

[0007] The logic control unit is electrically connected to the first driving unit, the second driving unit, the third driving unit, the current peak sampling unit, and the driving current generating unit, respectively.

[0008] The second driving unit is electrically connected to the base of the first power transistor NPN1; the first driving unit is electrically connected to the base of the second power transistor NPN2; the third driving unit is electrically connected to the base of the second power transistor NPN2.

[0009] The collector of the first power transistor NPN1 and the collector of the second power transistor NPN2 are electrically connected to the Lp of the external transformer, respectively. The emitter of the first power transistor NPN1 is electrically connected to the base of the second power transistor NPN2. The emitter of the second power transistor NPN2 is electrically connected to the external sampling resistor Rcs, the current peak sampling unit, the logic control unit, and the drive current generation unit, respectively.

[0010] The peak current sampling unit is electrically connected to the drive current generating unit, and the drive current generating unit is electrically connected to the second drive unit.

[0011] Furthermore, the first driving unit includes a current source Iref1, a current source Iref2, a field-effect transistor N8, and a field-effect transistor N9;

[0012] The current source Iref1 is electrically connected to the drain of the field-effect transistor N8, and the current source Iref2 is electrically connected to the drain of the field-effect transistor N9; the gates of the field-effect transistor N8 and the field-effect transistor N9 are respectively electrically connected to the logic control unit.

[0013] The source of the field-effect transistor N8 is electrically connected to the base of the first power transistor NPN1; the source of the field-effect transistor N9 is electrically connected to the base of the first power transistor NPN2.

[0014] Furthermore, the first driving unit also includes an inverter INV1, a field-effect transistor P5, a resistor R4, a field-effect transistor N7, a capacitor C2, and an AND gate circuit And1;

[0015] The input terminal of the inverter INV1 and one input terminal of the AND gate And1 are electrically connected to the logic control unit, respectively; the output terminal of the inverter INV1 is electrically connected to the gate of the field-effect transistor N7 and the gate of the field-effect transistor P5, respectively; the drain of the field-effect transistor P5 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to one end of the capacitor C2, the drain of the field-effect transistor N7, and the other input terminal of the AND gate And1, respectively; the source of the field-effect transistor N7 and the other end of the capacitor C2 are both grounded; the output terminal of the AND gate And1 is electrically connected to the gate of the field-effect transistor N8 and the gate of the field-effect transistor N9, respectively.

[0016] Furthermore, the second driving unit includes an inverter INV2, a field-effect transistor N5, a field-effect transistor N6, and a resistor R3;

[0017] The input terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N5 and the logic control unit, respectively. The output terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N6. The source of the field-effect transistor N5 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the drain of the field-effect transistor N6 and the base of the first power transistor NPN1, respectively.

[0018] Furthermore, the second driving unit also includes field-effect transistor N3, field-effect transistor N4, field-effect transistor P3, and field-effect transistor P4;

[0019] The gate and drain of the field-effect transistor N3 are short-circuited and electrically connected to the drive current generating unit. The gate of the field-effect transistor N3 is electrically connected to the gate of the field-effect transistor N4. The source of the field-effect transistor N3 is electrically connected to the source of the field-effect transistor N4 and the source of the field-effect transistor N6, respectively. The drain of the field-effect transistor N4 is electrically connected to the drain of the field-effect transistor P3. The drain and gate of the field-effect transistor P3 are short-circuited and electrically connected to the gate of the field-effect transistor P4. The drain of the field-effect transistor P4 is electrically connected to the drain of the field-effect transistor N5. The source of the field-effect transistor P3 is electrically connected to the source of the field-effect transistor P4.

[0020] Furthermore, the third driving unit includes inverters INV3, INV4, INV5, and INV6, a field-effect transistor N10, and a field-effect transistor N11;

[0021] The input terminal of inverter INV3 is electrically connected to the logic control unit. The output terminal of inverter INV3 is electrically connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is electrically connected to the input terminal of inverter INV5 and the gate of field-effect transistor N10. The output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is electrically connected to the gate of field-effect transistor N11. The drains of field-effect transistors N10 and N11 are electrically connected to the base of the second power transistor NPN2. The sources of field-effect transistors N10 and N11 are both grounded.

[0022] Furthermore, the current peak sampling unit includes a field-effect transistor N1 and a comparator CMP1;

[0023] The gate of the field-effect transistor N1 is electrically connected to the logic control unit, the drain of the field-effect transistor N1 is electrically connected to the emitter of the second power transistor NPN2, the source of the field-effect transistor N1 is electrically connected to the inverting input of the comparator CMP1, the non-inverting input of the comparator CMP1 is connected to the reference voltage V1, and the output of the comparator CMP1 is electrically connected to the drive current generating unit.

[0024] Furthermore, the drive current generating unit includes a transconductance amplifier Gm1, a field-effect transistor N2, a resistor R1, a resistor R2, a switch N3, a field-effect transistor P1, and a field-effect transistor P2;

[0025] The positive input terminal of the transconductance amplifier Gm1 is electrically connected to the emitter of the second power transistor NPN2. The negative input terminal of the transconductance amplifier Gm1 is electrically connected to the source of the field-effect transistor N2 and one end of the resistor R1. The output terminal of the transconductance amplifier Gm1 is electrically connected to the gate of the field-effect transistor N2. The drain of the field-effect transistor N2 is electrically connected to the drain of the field-effect transistor P1. The drain of the field-effect transistor P1 is shorted to the gate of the field-effect transistor P2. The source of the field-effect transistor P1 is electrically connected to the source of the field-effect transistor P2. The drain of the field-effect transistor P2 is electrically connected to the drain of the field-effect transistor N3.

[0026] The other end of resistor R1 is electrically connected to one end of resistor R2 and the drain of switch N3, the other end of resistor R2 is electrically connected to the source of switch N3 and then grounded, and the gate of switch N3 is electrically connected to the output of comparator CMP1.

[0027] Furthermore, the emitter of the second power transistor NPN2 is electrically connected to one end of the sampling resistor Rcs, and the other end of the sampling resistor Rcs is grounded.

[0028] Furthermore, it also includes diode D1 and capacitor C0;

[0029] One end of the external transformer Ls is electrically connected to the positive terminal of diode D1, the negative terminal of diode D1 is electrically connected to one end of capacitor C0, and the other end of capacitor C0 is electrically connected to the other end of the external transformer Ls.

[0030] The beneficial effects of the above technical solution are:

[0031] This invention employs a separate dual NPN power transistor operating mode. Relying on a first drive unit, a second drive unit, a third drive unit, and the first power transistor NPN1, the second power transistor NPN2 is forcibly clamped to the critical state between the saturation and amplification regions. The third drive unit achieves rapid turn-off of over 1A, thus achieving the fastest turn-off speed for the second power transistor NPN2. This increases the operating frequency of NPN transistors from the current 65kHz to 120kHz, reaching a frequency range currently achievable only by expensive Cool MOS transistors. Furthermore, the drive current of the second power transistor NPN2 is introduced into the primary inductance Lp of the external transformer through the first power transistor NPN1, significantly reducing drive losses. Specifically, the drive loss of the second power transistor NPN2 under full load at low line voltage (90-110V) is reduced to 50mW, achieving the drive losses of expensive MOS power transistors. This technical solution can perfectly replace current systems using MOS power transistors. Systems using this invention increase the power range from 15W to 65W, significantly saving system costs and enhancing product competitiveness. Attached Figure Description

[0032] Figure 1 The diagram shown is a schematic block diagram of a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0033] Figure 2 The diagram shown is a circuit connection diagram of the first driving unit of a dual-transistor driving circuit suitable for high-frequency applications according to the present invention.

[0034] Figure 3 The diagram shown is a circuit connection diagram of the second driving unit of a dual-transistor driving circuit suitable for high-frequency applications according to the present invention.

[0035] Figure 4 The diagram shown is a circuit connection diagram of the third driving unit of a dual-transistor driving circuit suitable for high-frequency applications according to the present invention.

[0036] Figure 5 The diagram shown is a circuit connection diagram of the current peak sampling unit of a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0037] Figure 6 The diagram shown is a circuit connection diagram of the drive current generation unit of a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0038] Figure 7 The diagram shown is a circuit connection diagram of inverter INV1 in a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0039] Figure 8 The diagram shown is an AND gate circuit And1 of a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0040] Figure 9 The diagram shown is a circuit connection diagram of inverter INV2 in a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0041] Figure 10 The diagram shown is a circuit connection diagram of a comparator CMP1 in a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0042] Figure 11 The diagram shown is a circuit connection diagram of a transconductance amplifier Gm1 in a dual-transistor drive circuit suitable for high-frequency applications according to the present invention.

[0043] Figure 12 The diagram shown is a classic Darlington transistor circuit connection diagram. Detailed Implementation

[0044] Most mainstream NPN drive circuits currently operate at low frequencies, primarily below 65kHz, and require very large base drive currents. For example, when IC = 800mA, and the high-voltage NPN amplification factor β = 20, then Ib = 800 / 20 = 40mA is needed. This is just the most basic drive current. To utilize the low saturation voltage drop of NPN, the drive current increases to 80mA, and the average drive current increases to 30mA. Furthermore, the NPN drive current needs to be continuously present. If the system operates at 40V VCC and the input line voltage is 90V, the drive loss reaches 40*30 = 1.2W. Such high power consumption severely restricts the use of NPN in the high-power range.

[0045] Therefore, this invention adopts a high-low voltage composite driving method. Under medium and light load conditions, chip power supply is used, and under high current conditions, the power supply is switched to the first power transistor NPN1, which greatly reduces the driving loss and reduces the original 1.2W to 1.2W / 15 = 80mW, achieving the driving current required by the power MOS.

[0046] The classic Darlington transistor achieves a small drive mode, where the drive current of B is only 0.05 times that required by the NPN base. However, this classic structure has the following problems: Figure 12 As shown, the discharge speed of R4 is limited, which greatly reduces the switching speed of NPN2. In the low-to-medium current operating range, due to the small current, the VCE voltage drop of NPN2 is too small, which makes it impossible for NPN1 current to be obtained from the C terminal, resulting in the NPN2 not being able to achieve its full efficiency in the low-to-medium current operating range.

[0047] To address the above problems, the present invention will be further described below with reference to the accompanying drawings and specific embodiments:

[0048] like Figure 1 As shown, the present invention provides a dual-transistor drive circuit suitable for high-frequency applications, including a logic control unit, a first drive unit, a second drive unit, a third drive unit, a first power transistor NPN1, a second power transistor NPN2, a current peak sampling unit, and a drive current generation unit.

[0049] The logic control unit is electrically connected to the first driving unit, the second driving unit, the third driving unit, the current peak sampling unit, and the driving current generating unit, respectively.

[0050] The second driving unit is electrically connected to the base of the first power transistor NPN1; the first driving unit is electrically connected to the base of the second power transistor NPN2; the third driving unit is electrically connected to the base of the second power transistor NPN2.

[0051] The collector of the first power transistor NPN1 and the collector of the second power transistor NPN2 are electrically connected to the Lp of the external transformer, respectively. The emitter of the first power transistor NPN1 is electrically connected to the base of the second power transistor NPN2. The emitter of the second power transistor NPN2 is electrically connected to the external sampling resistor Rcs, the current peak sampling unit, the logic control unit, and the drive current generation unit, respectively.

[0052] The emitter of the second power transistor NPN2 is electrically connected to one end of the sampling resistor Rcs, and the other end of the sampling resistor Rcs is grounded. It also includes a diode D1 and a capacitor C0; one end of the external transformer Ls is electrically connected to the anode of diode D1, the cathode of diode D1 is electrically connected to one end of capacitor C0, and the other end of capacitor C0 is electrically connected to the other end of the external transformer Ls.

[0053] The peak current sampling unit is electrically connected to the drive current generating unit, and the drive current generating unit is electrically connected to the second drive unit.

[0054] The beneficial effects of the above technical solution are:

[0055] This invention employs a separate dual NPN power transistor operating mode, forcibly clamping the second power transistor NPN2 to the critical state between the saturation and amplification regions. The third drive unit achieves rapid turn-off of over 1A, thus realizing the fastest turn-off speed for the second power transistor NPN2. This increases the operating frequency of NPN transistors from the current 65kHz to 120kHz, achieving a frequency range currently only achievable by expensive Cool MOS transistors. The first power transistor NPN1 introduces the base drive current of the second power transistor NPN2 into the primary inductance Lp of the external transformer, reducing the drive loss of the second power transistor NPN2 under full load at low line voltage (90-110V) to 50mW, achieving the drive loss of expensive MOS power transistors. This technical solution can perfectly replace the current system solution using MOS power transistors. The system power range using this invention is increased from 15W to 65W, greatly saving system costs and enhancing product competitiveness.

[0056] like Figure 2 As shown, the first driving unit includes a current source Iref1, a current source Iref2, a field-effect transistor N8, a field-effect transistor N9, an inverter INV1, a field-effect transistor P5, a resistor R4, a field-effect transistor N7, a capacitor C2, and an AND gate circuit And1;

[0057] The current source Iref1 is electrically connected to the drain of the field-effect transistor N8, and the current source Iref2 is electrically connected to the drain of the field-effect transistor N9; the gates of the field-effect transistor N8 and the field-effect transistor N9 are respectively electrically connected to the logic control unit.

[0058] The source of the field-effect transistor N8 is electrically connected to the base of the first power transistor NPN1; the source of the field-effect transistor N9 is electrically connected to the base of the first power transistor NPN2.

[0059] The input terminal of the inverter INV1 and one input terminal of the AND gate And1 are electrically connected to the logic control unit, respectively; the output terminal of the inverter INV1 is electrically connected to the gate of the field-effect transistor N7 and the gate of the field-effect transistor P5, respectively; the drain of the field-effect transistor P5 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to one end of the capacitor C2, the drain of the field-effect transistor N7, and the other input terminal of the AND gate And1, respectively; the source of the field-effect transistor N7 and the other end of the capacitor C2 are both grounded; the output terminal of the AND gate And1 is electrically connected to the gate of the field-effect transistor N8 and the gate of the field-effect transistor N9, respectively.

[0060] The working principle of the first driving unit mentioned above is as follows:

[0061] When the SW1 control signal of the logic control unit sends an enable signal, two pulse drive signals are generated. The drive pulse output by the current source Iref1 and the field-effect transistor N8 drives the base of the first power transistor NPN1; the drive pulse output by the current source Iref2 and the field-effect transistor N9 drives the base of the second power transistor NPN2. The width of the drive pulses is controlled by the resistor R4, the capacitor C2, and the inverting voltage of the AND gate circuit And1. The drive currents generated by the two pulse drives are different, with Iref2 being greater than 10 * Iref1. The two generated pulse drives instantaneously charge the BE capacitors of the first power transistor NPN1 and the second power transistor NPN2 to reach the voltage at which BE is just turned on, minimizing the system's turn-on delay.

[0062] The specific structure and circuit connection of inverter INV1 are as follows: Figure 7 As shown, the specific structure and circuit connection of the AND gate circuit And1 are as follows: Figure 8 As shown.

[0063] like Figure 3 As shown, the second driving unit includes an inverter INV2, a field-effect transistor N5, a field-effect transistor N6, a resistor R3, a field-effect transistor N3, a field-effect transistor N4, a field-effect transistor P3, and a field-effect transistor P4;

[0064] The input terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N5 and the logic control unit, respectively. The output terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N6. The source of the field-effect transistor N5 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the drain of the field-effect transistor N6 and the base of the first power transistor NPN1, respectively.

[0065] The gate and drain of the field-effect transistor N3 are short-circuited and electrically connected to the drive current generating unit. The gate of the field-effect transistor N3 is electrically connected to the gate of the field-effect transistor N4. The source of the field-effect transistor N3 is electrically connected to the source of the field-effect transistor N4 and the source of the field-effect transistor N6, respectively. The drain of the field-effect transistor N4 is electrically connected to the drain of the field-effect transistor P3. The drain and gate of the field-effect transistor P3 are short-circuited and electrically connected to the gate of the field-effect transistor P4. The drain of the field-effect transistor P4 is electrically connected to the drain of the field-effect transistor N5. The source of the field-effect transistor P3 is electrically connected to the source of the field-effect transistor P4.

[0066] The working principle of the second drive unit mentioned above is as follows:

[0067] The Iout1 current output from the drive current generation unit is connected to the gate and drain of MOSFET N3. The gate and drain of MOSFET N3 are short-circuited. The gate of MOSFET N4 is connected to the gate of MOSFET N3. MOSFETs N3 and N4 establish a proportional current source. The ratio of the current of MOSFET N4 to the current of MOSFET N3 is n. The drain of MOSFET N4 is connected to the gate and drain of MOSFET P3. The gate and drain of MOSFET P3 are short-circuited. The gate of MOSFET P4 is connected to the gate of MOSFET P3. MOSFETs P3 and P4 establish a proportional current source. The ratio of the current of MOSFET P4 to the current of MOSFET P3 is p. The proportionality coefficient satisfies the following relationship; the total gain is g.

[0068] n×p=g, and the value of g is different for different power ranges;

[0069] The current output from MOSFET P4 is connected to MOSFET N5. When the logic control unit sends an enable signal via SW1, MOSFET N5 is enabled. MOSFET N5 is connected to resistor R3, which is an anti-saturation resistor used to prevent deep saturation of the first power transistor NPN1. Resistor R3 is connected to the base of the first power transistor NPN1. The current output from MOSFET P4 is output to the first power transistor NPN1 via MOSFET N5 and resistor R3, providing drive current for the first power transistor NPN1. The drain of MOSFET N6 is connected to the base of the first power transistor NPN1, the source of MOSFET N6 is connected to ground, and the gate is connected to the output of inverter INV2. The input of inverter INV2 is connected to the SW1 control signal of the logic control unit.

[0070] When the SW1 control signal of the logic control unit sends a shutdown signal, the inverter INV2 outputs a high-level drive signal to control the field-effect transistor N6 to turn on, quickly pulling the base of the first power transistor NPN1 to ground. Due to the anti-saturation resistor R3, the first power transistor NPN1 operates in the critical saturation state, and the turn-off recovery speed of the first power transistor NPN1 is greatly improved, which is 200ns faster than the turn-off speed in the deep saturation state.

[0071] The specific structure and circuit connection of inverter INV2 are as follows: Figure 9 As shown.

[0072] Inverter INV2 includes P10, P11, P12, N16, N17, and N18. The gates and drains of P10 and N16 are connected to form the first stage of INV2 driving. The gates and drains of P11 and N17 are connected to form the second stage of INV2 driving, with a driving capability greater than 10 times that of the first stage of INV2 driving. The gates and drains of P12 and N18 are connected to form the third stage of INV2 driving, with a driving capability greater than 10 times that of the second stage of INV2 driving, accelerating the turn-off of the first power transistor NPN1.

[0073] like Figure 4 As shown, the third driving unit includes inverters INV3, INV4, INV5, and INV6, as well as field-effect transistors N10 and N11.

[0074] The input terminal of inverter INV3 is electrically connected to the logic control unit. The output terminal of inverter INV3 is electrically connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is electrically connected to the input terminal of inverter INV5 and the gate of field-effect transistor N10. The output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is electrically connected to the gate of field-effect transistor N11. The drains of field-effect transistors N10 and N11 are electrically connected to the base of the second power transistor NPN2. The sources of field-effect transistors N10 and N11 are both grounded.

[0075] The working principle of the third drive unit mentioned above is as follows:

[0076] The SW1 control signal of the logic control unit is connected to the input terminal of the inverter INV3. Inverters INV5 and INV6 are delay drive units. When the SW1 control signal sends a turn-off signal, the field-effect transistor N10 turns on first, and the base of the second power transistor NPN2 begins to discharge. After a delay by inverters INV5 and INV6, the field-effect transistor N11 turns on, and the base of the second power transistor NPN2 discharges rapidly until the second power transistor NPN2 turns off.

[0077] Among them, INV3 and INV5 have the same structure as INV2, and INV4 and INV6 have the same internal structure as INV2.

[0078] like Figure 5 As shown, the current peak sampling unit includes a field-effect transistor N1 and a comparator CMP1;

[0079] The gate of the field-effect transistor N1 is electrically connected to the logic control unit, the drain of the field-effect transistor N1 is electrically connected to the emitter of the second power transistor NPN2, the source of the field-effect transistor N1 is electrically connected to the inverting input of the comparator CMP1, the non-inverting input of the comparator CMP1 is connected to the reference voltage V1, and the output of the comparator CMP1 is electrically connected to the drive current generating unit.

[0080] The working principle of the above-mentioned peak current sampling unit is as follows:

[0081] When the SW1 control signal of the logic control unit sends an enable signal, the field-effect transistor N1 is turned on, and the voltage signal V_RCS of the sampling resistor RCS is connected to the comparator CMP1. When V_RCS is greater than the reference voltage V1, the comparator CMP1 outputs 0.

[0082] The specific structure and circuit connection of comparator CMP1 are as follows: Figure 10 As shown, it includes P13, P14, P15, P16, N19, N20, and N21; the gates of P13 and P14 are connected to provide current bias for comparator CMP1; the sources of P15 and P16 are connected to form the differential input of comparator CMP1; the gate and drain of N19 are shorted and connected to the drain of P15; the gate of N20 is connected to the gate of N19; the drain of N20 is connected to the drain of P16; and the gate of N21 is connected to the drain of N20, the drain of P16, and the drain of P14.

[0083] like Figure 6 As shown, the drive current generating unit includes a transconductance amplifier Gm1, a field-effect transistor N2, a resistor R1, a resistor R2, a switch N3, a field-effect transistor P1, and a field-effect transistor P2;

[0084] The positive input terminal of the transconductance amplifier Gm1 is electrically connected to the emitter of the second power transistor NPN2. The negative input terminal of the transconductance amplifier Gm1 is electrically connected to the source of the field-effect transistor N2 and one end of the resistor R1. The output terminal of the transconductance amplifier Gm1 is electrically connected to the gate of the field-effect transistor N2. The drain of the field-effect transistor N2 is electrically connected to the drain of the field-effect transistor P1. The drain of the field-effect transistor P1 is shorted to the gate of the field-effect transistor P2. The source of the field-effect transistor P1 is electrically connected to the source of the field-effect transistor P2. The drain of the field-effect transistor P2 is electrically connected to the drain of the field-effect transistor N3.

[0085] The other end of resistor R1 is electrically connected to one end of resistor R2 and the drain of switch N3, the other end of resistor R2 is electrically connected to the source of switch N3 and then grounded, and the gate of switch N3 is electrically connected to the output of comparator CMP1.

[0086] The working principle of the above-mentioned drive current generating unit is as follows:

[0087] Transconductance amplifier Gm1 and field-effect transistor N2 form an operational amplifier closed-loop feedback system. Based on the virtual short principle of closed-loop operational amplifiers, the voltages at the positive and negative input terminals of transconductance amplifier Gm1 are the same. The source voltage of the field-effect transistor N2 is equal to the voltage of the sampling resistor Rcs. One end of resistor R1 is connected to the source of field-effect transistor N2, and the other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is grounded. The drain of field-effect transistor N2 is connected to the gate and drain of field-effect transistor P1. The gate of field-effect transistor P1 is connected to the gate of field-effect transistor P2. The drain of field-effect transistor P2 outputs Iout1 to the second driving unit.

[0088] The specific structure and circuit connection of the transconductance amplifier Gm1 are as follows: Figure 11 As shown, the transconductance amplifier Gm1 includes: P17, P18, P19, P20, P21, P22, P23, P24, N22, N23, N24, N25, N26, and C1. The drain of P17 is connected to the source of P23 and the source of P24. The drain of P23 is connected to the source of N25. The drain of P24 is connected to the source of N26. The gate and drain of N23 are shorted and connected to the gate of N24 and the source of N25. The drain of N24 is connected to the source of N26 and the drain of P24. The drain of N25 is connected to the drain of P20 and the gate of P19. The drain of N26 is connected to the drain of P22. The source of P20 is connected to the drain of P19. The source of P22 is connected to the drain of P21. C1 is connected to the drain of P22 and the drain of N26.

[0089] When the sampling voltage of the current peak sampling unit is less than V1, it indicates that the output power is less than medium power. The comparator CMP1 outputs A1 high, N3 is turned on, resistor R2 is short-circuited, and the voltage-to-current conversion of the drive current generation unit is VCS / R1. At this time, the voltage-to-current transconductance is 1 / R1, which is a high-gain state. The drive current is obtained from the main control.

[0090] When the sampling voltage of the peak current sampling unit is greater than V1, it indicates that the output power is greater than the medium power, and the comparator CMP1 outputs A1 as 0. The voltage-to-current conversion of the drive current generation unit is VCS / (R1+R2), and the voltage-to-current transconductance is 1 / (R1+R2), which is a high-gain state. The drive current is obtained from the main controller and the first power transistor NPN1.

[0091] This enables the switching between light, medium, and full load drives, achieving optimal efficiency under full load.

[0092] The present invention has been described with reference to the foregoing embodiments and accompanying drawings; however, the foregoing embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the present invention. Conversely, modifications and equivalents included within the spirit and scope of the claims are all included within the scope of the present invention.

Claims

1. A dual-transistor drive circuit suitable for high-frequency applications, characterized in that, It includes a logic control unit, a first drive unit, a second drive unit, a third drive unit, a first power transistor NPN1, a second power transistor NPN2, a current peak sampling unit, and a drive current generation unit; The logic control unit is electrically connected to the first driving unit, the second driving unit, the third driving unit, the current peak sampling unit, and the driving current generating unit, respectively. The second driving unit is electrically connected to the base of the first power transistor NPN1; the first driving unit is electrically connected to the base of the second power transistor NPN2; the third driving unit is electrically connected to the base of the second power transistor NPN2. The collector of the first power transistor NPN1 and the collector of the second power transistor NPN2 are electrically connected to the Lp of the external transformer, respectively. The emitter of the first power transistor NPN1 is electrically connected to the base of the second power transistor NPN2. The emitter of the second power transistor NPN2 is electrically connected to the external sampling resistor Rcs, the current peak sampling unit, the logic control unit, and the drive current generation unit, respectively. The peak current sampling unit is electrically connected to the drive current generating unit, and the drive current generating unit is electrically connected to the second drive unit; the first drive unit includes a current source Iref1, a current source Iref2, a field-effect transistor N8, and a field-effect transistor N9. The current source Iref1 is electrically connected to the drain of the field-effect transistor N8, and the current source Iref2 is electrically connected to the drain of the field-effect transistor N9; the gates of the field-effect transistor N8 and the field-effect transistor N9 are respectively electrically connected to the logic control unit. The source of the field-effect transistor N8 is electrically connected to the base of the first power transistor NPN1; the source of the field-effect transistor N9 is electrically connected to the base of the second power transistor NPN2. The second driving unit includes an inverter INV2, a field-effect transistor N5, a field-effect transistor N6, and a resistor R3; The input terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N5 and the logic control unit, respectively. The output terminal of the inverter INV2 is electrically connected to the gate of the field-effect transistor N6. The source of the field-effect transistor N5 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the drain of the field-effect transistor N6 and the base of the first power transistor NPN1, respectively. The third driving unit includes inverters INV3, INV4, INV5, and INV6, as well as field-effect transistors N10 and N11. The input terminal of inverter INV3 is electrically connected to the logic control unit. The output terminal of inverter INV3 is electrically connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is electrically connected to the input terminal of inverter INV5 and the gate of field-effect transistor N10. The output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is electrically connected to the gate of field-effect transistor N11. The drains of field-effect transistors N10 and N11 are electrically connected to the base of the second power transistor NPN2. The sources of field-effect transistors N10 and N11 are both grounded.

2. The dual-transistor drive circuit suitable for high-frequency applications according to claim 1, characterized in that, The first driving unit also includes an inverter INV1, a field-effect transistor P5, a resistor R4, a field-effect transistor N7, a capacitor C2, and an AND gate circuit And1; The input terminal of the inverter INV1 and one input terminal of the AND gate And1 are electrically connected to the logic control unit, respectively; the output terminal of the inverter INV1 is electrically connected to the gate of the field-effect transistor N7 and the gate of the field-effect transistor P5, respectively; the drain of the field-effect transistor P5 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to one end of the capacitor C2, the drain of the field-effect transistor N7, and the other input terminal of the AND gate And1, respectively; the source of the field-effect transistor N7 and the other end of the capacitor C2 are both grounded; the output terminal of the AND gate And1 is electrically connected to the gate of the field-effect transistor N8 and the gate of the field-effect transistor N9, respectively.

3. A two-transistor driver circuit suitable for high frequency applications according to claim 1, characterized in that, The second driving unit also includes field-effect transistor N3, field-effect transistor N4, field-effect transistor P3, and field-effect transistor P4; The gate and drain of the field-effect transistor N3 are short-circuited and electrically connected to the drive current generating unit. The gate of the field-effect transistor N3 is electrically connected to the gate of the field-effect transistor N4. The source of the field-effect transistor N3 is electrically connected to the source of the field-effect transistor N4 and the source of the field-effect transistor N6, respectively. The drain of the field-effect transistor N4 is electrically connected to the drain of the field-effect transistor P3. The drain and gate of the field-effect transistor P3 are short-circuited and electrically connected to the gate of the field-effect transistor P4. The drain of the field-effect transistor P4 is electrically connected to the drain of the field-effect transistor N5. The source of the field-effect transistor P3 is electrically connected to the source of the field-effect transistor P4.

4. A two tube driver circuit suitable for high frequency applications according to claim 3, characterized in that The current peak sampling unit includes a field-effect transistor N1 and a comparator CMP1; The gate of the field-effect transistor N1 is electrically connected to the logic control unit, the drain of the field-effect transistor N1 is electrically connected to the emitter of the second power transistor NPN2, the source of the field-effect transistor N1 is electrically connected to the inverting input of the comparator CMP1, the non-inverting input of the comparator CMP1 is connected to the reference voltage V1, and the output of the comparator CMP1 is electrically connected to the drive current generating unit.

5. A two tube driver circuit suitable for high frequency applications according to claim 4, characterized in that, The drive current generating unit includes a transconductance amplifier Gm1, a field-effect transistor N2, a resistor R1, a resistor R2, a switch N3, a field-effect transistor P1, and a field-effect transistor P2. The positive input terminal of the transconductance amplifier Gm1 is electrically connected to the emitter of the second power transistor NPN2. The negative input terminal of the transconductance amplifier Gm1 is electrically connected to the source of the field-effect transistor N2 and one end of the resistor R1. The output terminal of the transconductance amplifier Gm1 is electrically connected to the gate of the field-effect transistor N2. The drain of the field-effect transistor N2 is electrically connected to the drain of the field-effect transistor P1. The drain of the field-effect transistor P1 is shorted to the gate of the field-effect transistor P2. The source of the field-effect transistor P1 is electrically connected to the source of the field-effect transistor P2. The drain of the field-effect transistor P2 is electrically connected to the drain of the field-effect transistor N3. The other end of resistor R1 is electrically connected to one end of resistor R2 and the drain of switch N3, the other end of resistor R2 is electrically connected to the source of switch N3 and then grounded, and the gate of switch N3 is electrically connected to the output of comparator CMP1.

6. A dual-transistor drive circuit suitable for high-frequency applications according to claim 1, characterized in that, The emitter of the second power transistor NPN2 is electrically connected to one end of the sampling resistor Rcs, and the other end of the sampling resistor Rcs is grounded.

7. A dual-transistor drive circuit suitable for high-frequency applications according to claim 1, characterized in that, It also includes diode D1 and capacitor C0; One end of the external transformer Ls is electrically connected to the positive terminal of diode D1, the negative terminal of diode D1 is electrically connected to one end of capacitor C0, and the other end of capacitor C0 is electrically connected to the other end of the external transformer Ls.

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