Current-limiting threshold compensation protection circuit and reference current generation device

Abstract

The present invention provides a current-limiting threshold compensation protection circuit and a reference current generation device. The current-limiting threshold compensation protection circuit includes a ramp current-limiting threshold compensation module, a temperature current-limiting threshold compensation module, and a current-limiting protection module. Through the ramp current-limiting threshold compensation module, the current-limiting protection voltage can be compensated by the ramp current-limiting threshold to obtain a first current-limiting protection compensation voltage, which not only ensures the loop stability but also ensures that the current-limiting protection threshold will not become smaller. When the current sampling ratio decreases as the temperature rises, through the temperature current-limiting threshold compensation module, the first current-limiting protection compensation voltage is further compensated by the temperature current-limiting threshold to obtain a second current-limiting protection compensation voltage, which can ensure that the current-limiting protection threshold will not become smaller due to the decrease in the current sampling ratio after the temperature rises. Through the current-limiting protection module, the output third current-limiting protection compensation voltage is clamped and protected, which can effectively prevent the output voltage and current from being too large and achieve current-limiting protection.

Description

Technical Field

[0001] The present invention relates to the technical field of DC-DC converters with peak current mode pulse width modulation control, and particularly to a current limiting threshold compensation protection circuit and a reference current generating device. Background Art

[0002] The function of a DC-DC converter is to achieve voltage conversion, which can convert the input voltage into the supply voltage actually required by the load. It has the characteristics of a wide operating voltage range, high efficiency, small size, large load current, high power density, etc. DC-DC converters are widely used in communication systems such as mobile terminals and base stations, and have good market prospects. Among various modulation methods of DC-DC converters, the peak current mode pulse width modulation (PWM) control method has the characteristic of fast load response speed and is applied to most DC-DC converter system architectures. It includes two control loops, an outer voltage loop and an inner current loop. The current loop will generate a subharmonic oscillation problem when the duty cycle D>50%, resulting in loop instability. The common method to solve the subharmonic oscillation problem is to add a slope compensation circuit and introduce a slope current to compensate the peak current.

[0003] Traditional slope compensation methods include first-order linear compensation, second-order linear compensation, and exponential slope compensation. The compensation method is to subtract the slope current I COMP from the output current I of the voltage-current converter SLOPE and use it as the reference current I REF of the peak current comparator. When the duty cycle D<50%, the current loop is stable and no slope compensation is required. When D>50%, slope compensation is required. Since the current limiting protection threshold of the DC-DC converter is determined by the maximum current limiting value output by the voltage-current converter, the current limiting protection threshold will decrease after slope compensation. After slope compensation, the current limiting protection threshold of the DC-DC converter will be smaller when D>50% than when D<50%. Usually, in the extreme cases of D = 15% and D = 85%, the difference in the current limiting protection threshold will be about 2 times, affecting the circuit performance. Traditional slope compensation methods all sacrifice the current limiting protection threshold of the DC-DC converter to improve the loop stability, which is not an ideal compensation method.

[0004] At the same time, DC-DC converters mostly work with a load. The larger the load current, the higher the temperature rise. Temperature changes will affect current sampling. The higher the temperature, the smaller the current sampling ratio, resulting in a smaller current limiting protection threshold. Therefore, temperature compensation needs to be considered for the current limiting protection threshold.

[0005] Therefore, there is an urgent need for a current limiting threshold compensation technical solution to solve the problem of the decrease in the current limiting protection threshold caused by slope compensation and the problem of the decrease in the current limiting protection threshold caused by the decrease in the current sampling ratio after the temperature rises. Summary of the Invention

[0006] In view of the disadvantages of the prior art described above, the object of the present invention is to provide a current limiting threshold compensation and protection technical solution to solve the problem of the reduction of the current limiting protection threshold caused by ramp compensation and the problem of the reduction of the current limiting protection threshold caused by the decrease of the current sampling ratio after the temperature rises.

[0007] To achieve the above object and other objects, the detailed technical solution provided by the present invention is as follows.

[0008] A current limiting threshold compensation protection circuit includes:

[0009] A ramp current limiting threshold compensation module, which is connected to the ramp current and the current limiting protection voltage, periodically senses the ramp current and converts the ramp current into a ramp voltage, and then performs ramp current limiting threshold compensation on the current limiting protection voltage through the ramp voltage to obtain a first current limiting protection compensation voltage;

[0010] A temperature current limiting threshold compensation module, which is connected to the temperature voltage, the reference voltage and the first current limiting protection compensation voltage, and performs temperature current limiting threshold compensation on the first current limiting protection compensation voltage through the temperature voltage and the reference voltage when the current sampling ratio decreases as the temperature rises, to obtain a second current limiting protection compensation voltage;

[0011] A current limiting protection module, which is connected to the output voltage of the error amplifier and the second current limiting protection compensation voltage, and clamps and protects the output voltage through the output voltage of the error amplifier and the second current limiting protection compensation voltage to obtain and output a third current limiting protection compensation voltage.

[0012] Optionally, the ramp current limit threshold compensation module includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a first current source, a second current source, a first NMOS transistor, and a second NMOS transistor. The power supply voltage is grounded after sequentially connecting the first current source, the first resistor, and the second current source in series. One end of the first resistor connected to the second current source is also connected to the current limit protection voltage. One end of the first resistor connected to the first current source is also connected to the positive input terminal of the first operational amplifier. The negative input terminal of the first operational amplifier is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is also connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the positive input terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is connected to the negative input terminal of the first operational amplifier after sequentially connecting the second resistor in series. The negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier. The output terminal of the second operational amplifier outputs the first current limit protection compensation voltage.

[0013] Optionally, the first current source and the second current source respectively provide a ramp current.

[0014] Optionally, the ramp current limit threshold compensation module further includes a third resistor, a first capacitor, and a bias current source. The positive input terminal of the second operational amplifier is grounded after sequentially connecting the third resistor and the first capacitor in series. The positive input terminal of the second operational amplifier is also grounded after sequentially connecting the bias current source in series.

[0015] Optionally, the temperature current limiting threshold compensation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth current source, a fourth resistor, and a fifth resistor. The source of the third PMOS transistor is connected to the power supply voltage. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the third PMOS transistor is grounded after being connected in series with the fourth current source. The source of the fourth PMOS transistor is connected to the power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is connected to the source of the first PMOS transistor after being connected in series with the fourth resistor. The gate of the first PMOS transistor is connected to the temperature voltage. The drain of the first PMOS transistor is grounded. The source of the fifth PMOS transistor is connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor. The source of the fourth NMOS transistor is connected to the source of the second PMOS transistor after being connected in series with the fifth resistor. The gate of the second PMOS transistor is connected to the reference voltage. The drain of the second PMOS transistor is grounded. The source of the sixth PMOS transistor is connected to the power supply voltage. The gate of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fifth NMOS transistor is connected to the source of the third NMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage. The gate of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor. The drain of the seventh PMOS transistor is connected to the source of the second PMOS transistor.

[0016] Optionally, the temperature current-limiting threshold compensation module further includes an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a sixth resistor. The source of the eighth PMOS transistor is connected to the power supply voltage. The gate of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the sixth NMOS transistor is grounded. The source of the ninth PMOS transistor is connected to the power supply voltage. The gate of the ninth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor after being connected in series with the sixth resistor. The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor. The source of the seventh NMOS transistor is grounded. The drain of the seventh NMOS transistor is connected to the first current-limiting protection compensation voltage. The drain of the ninth PMOS transistor outputs the second current-limiting protection compensation voltage.

[0017] Optionally, the size of the first PMOS transistor is the same as that of the second PMOS transistor. The sizes of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are the same. The sizes of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are the same. The size of the third NMOS transistor is the same as that of the fourth NMOS transistor. The size of the sixth NMOS transistor is the same as that of the seventh NMOS transistor. The resistance values of the fourth resistor, the fifth resistor, and the sixth resistor are the same.

[0018] Optionally, the current limiting protection module includes a third operational amplifier, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a second capacitor. The negative input terminal of the third operational amplifier is connected to the second current limiting protection compensation voltage. The output terminal of the third operational amplifier is connected to the gate of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the output voltage of the error amplifier. The output terminal of the third operational amplifier is also connected to the drain of the eighth NMOS transistor after being sequentially connected in series with the ninth resistor and the second capacitor. The positive input terminal of the third operational amplifier is connected to the gate of the ninth NMOS transistor. The source of the ninth NMOS transistor is grounded after being connected in series with the eighth resistor. The drain of the ninth NMOS transistor is connected to the gate of the ninth NMOS transistor. The drain of the ninth NMOS transistor is also connected to the source of the tenth NMOS transistor after being connected in series with the seventh resistor. The gate of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor after being connected in series with the tenth resistor. The drain of the tenth NMOS transistor is connected to the power supply voltage. The third current limiting protection compensation voltage is output from the gate of the tenth NMOS transistor.

[0019] Optionally, the size of the ninth NMOS transistor is the same as that of the tenth NMOS transistor, and the resistance value of the seventh resistor is the same as that of the eighth resistor.

[0020] A reference current generating device includes an error amplifier, the current limiting threshold compensation protection circuit described in any one of the above, a voltage-current converter, and a subtractor. The error amplifier is connected to a second reference voltage and a feedback voltage. The current limiting threshold compensation protection circuit is connected to the output voltage of the error amplifier. The voltage-current converter is connected to the third current limiting protection compensation voltage output by the current limiting threshold compensation protection circuit. The voltage-current converter performs voltage-current conversion on the third current limiting protection compensation voltage to obtain a protection compensation current. The subtractor is connected to the protection compensation current and the ramp current. The subtractor performs a subtraction operation on the protection compensation current and the ramp current to obtain and output a reference current.

[0021] As described above, the current limiting threshold compensation protection circuit and the reference current generating device of the present invention have at least the following beneficial effects:

[0022] Through the ramp current limiting threshold compensation module, the current limiting protection voltage can be compensated by the ramp current limiting threshold to obtain the first current limiting protection compensation voltage, which not only ensures the loop stability but also ensures that the current limiting protection threshold will not become smaller; when the current sampling ratio decreases with the increase of temperature, through the temperature current limiting threshold compensation module, the first current limiting protection compensation voltage is further compensated by the temperature current limiting threshold to obtain the second current limiting protection compensation voltage, which can ensure that the current limiting protection threshold will not become smaller due to the decrease of the current sampling ratio after the temperature increases; through the current limiting protection module, the clamped protection is carried out on the output third current limiting protection compensation voltage, which can effectively prevent the output voltage and current from being too large and realize the current limiting protection. Brief Description of the Drawings

[0023] Figure 1 It shows the structural block diagram of the current limiting threshold compensation protection circuit in the present invention.

[0024] Figure 2 It shows the circuit diagram of the ramp current limiting threshold compensation module 1 in an optional embodiment of the present invention.

[0025] Figure 3 It shows the input and output voltage waveform diagrams of the ramp current limiting threshold compensation module 1 under the condition that the duty cycle D < 50% in an optional embodiment of the present invention.

[0026] Figure 4 It shows the input and output voltage waveform diagrams of the ramp current limiting threshold compensation module 1 under the condition that the duty cycle D > 50% in an optional embodiment of the present invention.

[0027] Figure 5 It shows the circuit diagram of the temperature current limiting threshold compensation module 2 in an optional embodiment of the present invention.

[0028] Figure 6 It shows the input and output voltage waveform diagrams of the temperature current limiting threshold compensation module 2 in an optional embodiment of the present invention.

[0029] Figure 7 It shows the circuit diagram of the current limiting protection module 3 in an optional embodiment of the present invention.

[0030] Figure 8 It shows the input and output voltage waveform diagrams of the current limiting protection module 3 in an optional embodiment of the present invention.

[0031] Figure 9 It shows the structural block diagram of the reference current generating device in an optional embodiment of the present invention. Detailed Description of the Invention

[0032] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please refer to Figures 1 to 9 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. The structures, proportions, sizes, etc. shown in the diagrams of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the implementation conditions of the present invention. Therefore, they do not have technical substantive significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0034] As described in the background art above, the inventors have found through research that traditional slope compensation methods all sacrifice the current limiting protection threshold of the DC-DC converter to improve the stability of the loop, which is not an ideal compensation method. After slope compensation, the current limiting protection threshold will become smaller. At the same time, in most cases, the DC-DC converter operates with a load. The greater the load current, the higher the temperature rise. The temperature change will affect the current sampling. The higher the temperature, the smaller the current sampling ratio, which will also cause the current limiting protection threshold to become smaller.

[0035] Based on this, the inventors of the present invention propose a technical solution for current limiting threshold compensation protection: through a slope current limiting threshold compensation module, perform slope current limiting threshold compensation on the current limiting protection voltage to ensure that the current limiting protection threshold after slope compensation will not become smaller; through a temperature current limiting threshold compensation module, perform temperature current limiting threshold compensation to ensure that the current limiting protection threshold will not become smaller due to the decrease in the current sampling ratio after the temperature rises; at the same time, through a current limiting protection module, clamp and protect the output voltage to prevent the output voltage and current from being too large and achieve current limiting protection.

[0036] Specifically, as Figure 1 shown, the present invention provides a current limiting threshold compensation protection circuit, which includes:

[0037] A slope current limiting threshold compensation module 1, connected to the slope current I SLOPE and the current limiting protection voltage V LIM , periodically senses the slope current ISLOPE And convert the ramp current I SLOPE into a ramp voltage, and then use the ramp voltage to perform ramp current-limiting threshold compensation on the current-limiting protection voltage V LIM to obtain the first current-limiting protection compensation voltage V LIM_OUT1 ;

[0038] The temperature current-limiting threshold compensation module 2 is connected to the temperature voltage V TEMP , the reference voltage V REF1 and the first current-limiting protection compensation voltage V LIM_OUT1 . When the current sampling ratio decreases as the temperature rises, use the temperature voltage V TEMP and the reference voltage V REF1 to perform temperature current-limiting threshold compensation on the first current-limiting protection compensation voltage V LIM_OUT1 to obtain the second current-limiting protection compensation voltage V LIM_OUT2 ;

[0039] The current-limiting protection module 3 is connected to the output voltage V of the error amplifier EA_OUT and the second current-limiting protection compensation voltage V LIM_OUT2 . Use the output voltage V of the error amplifier EA_OUT and the second current-limiting protection compensation voltage V LIM_OUT2 to clamp and protect the output voltage, and obtain and output the third current-limiting protection compensation voltage V COMP .

[0040] More specifically, in an alternative embodiment of the present invention, as Figure 2 shown, the ramp current-limiting threshold compensation module 1 includes a first operational amplifier AMP1, a second operational amplifier AMP2, a first resistor R1, a second resistor R2, a first current source I1, a second current source I2, a first NMOS transistor NM1, and a second NMOS transistor NM2. The power supply voltage VCC is grounded to GND through the first current source I1, the first resistor R1, and the second current source I2 connected in series in sequence. One end of the first resistor R1 connected to the second current source I2 is also connected to the current-limiting protection voltage V LIM, one end of the first resistor R1 connected to the first current source I1 is also connected to the non-inverting input terminal of the first operational amplifier AMP1. The inverting input terminal of the first operational amplifier AMP1 is connected to the drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is connected to the drain of the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is connected to the output terminal of the first operational amplifier AMP1. The output terminal of the first operational amplifier AMP1 is also connected to the drain of the second NMOS transistor NM2. The gate of the second NMOS transistor NM2 is connected to the drain of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is connected to the non-inverting input terminal of the second operational amplifier AMP2. The inverting input terminal of the second operational amplifier AMP2 is connected to the inverting input terminal of the first operational amplifier AMP1 after being serially connected with the second resistor R2. The inverting input terminal of the second operational amplifier AMP2 is connected to the output terminal of the second operational amplifier AMP2. The output terminal of the second operational amplifier AMP2 outputs the first current limiting protection compensation voltage V LIM_OUT1 .

[0041] Among them, the first current source I1 and the second current source I2 respectively provide a ramp current I SLOPE ; the first NMOS transistor NM1 and the second NMOS transistor NM2 are respectively in diode connection mode.

[0042] More specifically, as Figure 2 shown, the ramp current limiting threshold compensation module 1 further includes a third resistor R3, a first capacitor C1 and a bias current source I Bias , the non-inverting input terminal of the second operational amplifier AMP2 is grounded through the third resistor R3 and the first capacitor C1 connected in series in sequence. The non-inverting input terminal of the second operational amplifier AMP2 is also grounded through the bias current source I Bias connected in series.

[0043] Among them, the third resistor R3 and the first capacitor C1 form an integrating circuit.

[0044] More specifically, as Figure 2As shown in the figure, the first operational amplifier AMP1 has two voltage negative feedback loops: for the first voltage negative feedback loop, the path is from the positive input terminal of the first operational amplifier AMP1 - the output terminal of the first operational amplifier AMP1 - the first NMOS transistor NM1 - the negative input terminal of the first operational amplifier AMP1; for the second voltage negative feedback loop, the path is from the positive input terminal of the first operational amplifier AMP1 - the output terminal of the first operational amplifier AMP1 - the second NMOS transistor NM2 - the positive input terminal of the second operational amplifier AMP2 - the output terminal of the second operational amplifier AMP2 - the second resistor R2 - the negative input terminal of the first operational amplifier AMP1. Among them, the output terminal of the second operational amplifier AMP2 is connected to its negative input terminal, which is the voltage follower circuit structure.

[0045] More specifically, as Figure 2 shown, the working principle of the ramp current limiting threshold compensation module 1 is as follows:

[0046] 1), When the duty cycle D < 50%, there is no ramp current input, that is, the ramp current I SLOPE = 0, the voltage difference across the first resistor R1 is 0, and the voltage at the positive input terminal of the first operational amplifier AMP1 is equal to V LIM , at this time, the output voltage of the first operational amplifier AMP1 is input to the second operational amplifier AMP2 through the second NMOS transistor NM2 and fed back to the negative input terminal of the first operational amplifier AMP1 through the second resistor R2, forming a negative feedback closed loop, and the output first current limiting protection compensation voltage V LIM_OUT1 is equal to V LIM .

[0047] 2), When D > 50%, a ramp current is generated, that is, the ramp current I SLOPE ≠0, the ramp current I SLOPE gradually increases as the duty cycle D increases, the positive terminal sensing voltage of the first resistor R1 (i.e., the voltage at the positive input terminal of the first operational amplifier AMP1) rises and becomes V LIM +V SLOPE , and V SLOPE = I SLOPE ×R1, the output first current limiting protection compensation voltage V LIM_OUT1 follows the positive terminal input voltage of the first operational amplifier AMP1 through the negative feedback loop of the second NMOS transistor NM2, the second operational amplifier AMP2 and the second resistor R2, so the output first current limiting protection compensation voltage V LIM_OUT1 is equal to V LIM +V SLOPE .

[0048] 3), For the ramp current I SLOPEWhen it is not generated, the sensed voltage at the positive terminal of the first resistor R1 drops, and the output of the first operational amplifier AMP1 decreases. Due to the unidirectional conduction characteristic of the diode connection of the second NMOS transistor NM2, it becomes an off state at this time, and the negative feedback loop formed by the first operational amplifier AMP1, the second NMOS transistor NM2, the second operational amplifier AMP2, and the second resistor R2 is cut off, and the output first current-limiting protection compensation voltage V LIM_OUT1 cannot follow the voltage at the positive input terminal of the first operational amplifier AMP1. At this time, due to the decrease in the output of the first operational amplifier AMP1, the first NMOS transistor NM1 conducts and is connected to the negative input terminal of the first operational amplifier AMP1 to form a closed loop, preventing the first operational amplifier AMP1 from entering the saturation state. When the voltage at the positive input terminal of the first operational amplifier AMP1 decreases, since the output first current-limiting protection compensation voltage V LIM_OUT1 cannot follow the positive input terminal of the first operational amplifier AMP1, and the second operational amplifier AMP2 is a voltage follower structure, the first current-limiting protection compensation voltage V LIM_OUT1 follows the voltage at the positive input terminal of the second operational amplifier AMP2. There is an integrating circuit composed of a third resistor R3 and a first capacitor C1 at the positive input terminal of the second operational amplifier AMP2. The design bias current source I Bias is a 100 nA current. In a short time, the integrating circuit will maintain the voltage peak sensed by the first resistor R1, and the first current-limiting protection compensation voltage V LIM_OUT1 output by the second operational amplifier AMP2 continues to maintain this peak voltage, similar to the envelope detection function. When the ramp current I SLOPE is not sensed for a long time, under the action of the bias current source I Bias , the voltage at the positive input terminal of the second operational amplifier AMP2 will slowly drop to the current-limiting protection voltage V LIM , and at the same time, the output first current-limiting protection compensation voltage V LIM_OUT1 is also V LIM , returning to the initial state.

[0049] That is to say, as Figure 2 shown, the ramp current-limiting threshold compensation module 1 can periodically sense the ramp current I SLOPE and convert it into a ramp voltage, and output a first current-limiting protection compensation voltage (DC voltage) V SLOPE linearly related to the peak value of the ramp current I LIM_OUT1 , realizing the ramp current-limiting threshold compensation function and solving the technical problem of the reduction of the current-limiting protection threshold caused by ramp compensation.

[0050] More specifically, in an alternative embodiment of the present invention, the effect of the ramp current-limiting threshold compensation module 1 as Figure 2 shown is verified, and the simulation experiment results are as Figures 3 - 4 shown.

[0051] Among them, Figure 3 are the input and output voltage waveforms of the ramp current limiting threshold compensation module 1 under the condition that the duty cycle D < 50%. From top to bottom, they are the switch node SW waveform, the ramp current I SLOPE waveform, the output first current limiting protection compensation voltage V LIM_OUT1 voltage waveform, the positive input terminal V LIM +VS LOPE waveform and the current limiting protection voltage V LIM waveform. It can be seen from Figure 3 that under the condition that the duty cycle D < 50%, the ramp current I SLOPE is 54 nA (almost 0), and the output first current limiting protection compensation voltage V LIM_OUT1 = V LIM +VS LOPE = V LIM .

[0052] Among them, Figure 4 are the input and output voltage waveforms of the ramp current limiting threshold compensation module 1 under the condition that the duty cycle D > 50%. From top to bottom, they are the switch node SW waveform, the ramp current I SLOPE waveform, the output first current limiting protection compensation voltage V LIM_OUT1 voltage waveform, the positive input terminal V LIM +VS LOPE waveform and the current limiting protection voltage V LIM waveform. It can be seen from Figure 4 that under the condition that the duty cycle D > 50%, the maximum value of the ramp current I SLOPE is 4.89 μA, and the voltage waveform of the positive input terminal V LIM +V SLOPE is V LIM +I SLOPE × R1. In the design, the first resistor R1 = 33.4 kΩ, and the output first current limiting protection compensation voltage V LIM_OUT1 is equal to the peak value of V LIM +V SLOPE voltage, realizing the ramp current limiting threshold compensation function.

[0053] More specifically, in an alternative embodiment of the present invention, as Figure 5 shown, the temperature current limiting threshold compensation module 2 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a fourth current source Ia , the fourth resistor R4 and the fifth resistor R5, the source of the third PMOS transistor PM3 is connected to the power supply voltage VCC, the gate of the third PMOS transistor PM3 is connected to the drain of the third PMOS transistor PM3, and the drain of the third PMOS transistor PM3 is connected to the ground GND through the series-connected fourth current source I a . The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VCC, the gate of the fourth PMOS transistor PM4 is connected to the gate of the third PMOS transistor PM3, and the drain of the fourth PMOS transistor PM4 is connected to the drain of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 is connected to the drain of the third NMOS transistor NM3, and the source of the third NMOS transistor NM3 is connected to the source of the first PMOS transistor PM1 through the series-connected fourth resistor R4. The gate of the first PMOS transistor PM1 is connected to the temperature voltage V TEMP . The drain of the first PMOS transistor PM1 is connected to the ground GND. The source of the fifth PMOS transistor PM5 is connected to the power supply voltage VCC, the gate of the fifth PMOS transistor PM5 is connected to the gate of the third PMOS transistor PM3, and the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4. The gate of the fourth NMOS transistor NM4 is connected to the gate of the third NMOS transistor NM3, and the source of the fourth NMOS transistor NM4 is connected to the source of the second PMOS transistor PM2 through the series-connected fifth resistor R5. The gate of the second PMOS transistor PM2 is connected to the reference voltage V REF1 . The drain of the second PMOS transistor PM2 is connected to the ground GND. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VCC, the gate of the sixth PMOS transistor PM6 is connected to the drain of the sixth PMOS transistor PM6, and the drain of the sixth PMOS transistor PM6 is connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is connected to the drain of the fourth NMOS transistor NM4, and the source of the fifth NMOS transistor NM5 is connected to the source of the third NMOS transistor NM3. The source of the seventh PMOS transistor PM7 is connected to the power supply voltage VCC, the gate of the seventh PMOS transistor PM7 is connected to the gate of the sixth PMOS transistor PM6, and the drain of the seventh PMOS transistor PM7 is connected to the source of the second PMOS transistor PM2.

[0054] More specifically, as Figure 5As shown, the temperature current limiting threshold compensation module 2 further includes an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and a sixth resistor R6. The source of the eighth PMOS transistor PM8 is connected to the power supply voltage VCC. The gate of the eighth PMOS transistor PM8 is connected to the drain of the sixth PMOS transistor PM6. The drain of the eighth PMOS transistor PM8 is connected to the drain of the sixth NMOS transistor NM6. The gate of the sixth NMOS transistor NM6 is connected to the drain of the sixth NMOS transistor NM6. The source of the sixth NMOS transistor NM6 is grounded to GND. The source of the ninth PMOS transistor PM9 is connected to the power supply voltage VCC. The gate of the ninth PMOS transistor PM9 is connected to the drain of the sixth PMOS transistor PM6. The drain of the ninth PMOS transistor PM9 is connected to the drain of the seventh NMOS transistor NM7 after being connected in series with the sixth resistor R6. The gate of the seventh NMOS transistor NM7 is connected to the gate of the sixth NMOS transistor NM6. The source of the seventh NMOS transistor NM7 is grounded to GND. The drain of the seventh NMOS transistor NM7 is connected to the first current limiting protection compensation voltage V LIM_OUT1 , and the drain of the ninth PMOS transistor PM9 outputs the second current limiting protection compensation voltage V LIM_OUT2 .

[0055] Among them, the size of the first PMOS transistor PM1 is the same as that of the second PMOS transistor PM2. The sizes of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are the same. The sizes of the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, and the ninth PMOS transistor PM9 are the same. The size of the third NMOS transistor NM3 is the same as that of the fourth NMOS transistor NM4. The size of the sixth NMOS transistor NM6 is the same as that of the seventh NMOS transistor NM7. The resistance values of the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are the same.

[0056] More specifically, as Figure 5 shown, the working principle of the temperature current limiting threshold compensation module 2 is as follows:

[0057] 1). The first PMOS transistor PM1 and the second PMOS transistor PM2 are source followers. The third NMOS transistor NM3 and the fourth NMOS transistor NM4 form a common-gate amplifier. Due to the mirroring effect of the current mirror, they have the same drain current I a , and the source of the fifth NMOS transistor NM5 feeds back the current I b into the node N1 to form a negative feedback closed loop, making the source node voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 equal, that is, the voltage of N1 is equal to the voltage of N2. The drain current I bCompensate it into the second PMOS transistor PM2 so that the drain currents of the first PMOS transistor PM1 and the second PMOS transistor PM2 are equal, both equal to I a +I b . Since the first PMOS transistor PM1 and the second PMOS transistor PM2 have the same size, the gate-source voltage difference V GSPM1 of the first PMOS transistor PM1 and the gate-source voltage difference V GSPM2 of the second PMOS transistor PM2 are the same.

[0058] 2), from Figure 5 it can be known that the voltage of node N1 is V TEMP +V GSPM1 +(I a +I b )×R4, and the voltage of node N2 is V REF1 +V GSPM2 +I a ×R5. Since the voltage of N1 is equal to the voltage of N2, it can be deduced that I b ×R4 = V REF1 -V TEMP . And V LIM_OUT2 -V LIM_OUT1 = I b ×R6, and R4 = R6, it can be deduced that V LIM_OUT2 = V LIM_OUT1 +(V REF1 -V TEMP ). Since the current I b is a positive value ≥0, so only when V TEMP < V REF1 will temperature compensation be performed, and when V TEMP > V REF1 no temperature compensation will be performed. Therefore, the second current limiting protection compensation voltage V LIM_OUT2 output by the temperature current limiting threshold compensation module 2 is a signal that superimposes an inverted signal of the temperature voltage V LIM_OUT1 on the first current limiting protection compensation voltage V TEMP , realizing the ramp and temperature current limiting compensation functions. Usually, the forward conduction voltage of a PN junction is used to detect the temperature. The higher the temperature, the smaller the forward conduction voltage of the PN junction. When the temperature voltage V TEMP uses the forward conduction voltage of the PN junction, the temperature voltage V TEMP is inversely proportional to the temperature, and V LIM_OUT2 is directly proportional to the temperature, thus realizing the temperature current limiting threshold compensation function.

[0059] More specifically, in an optional embodiment of the present invention, the effect of the temperature current limiting threshold compensation module 2 as Figure 5 shown is verified, and the simulation experiment results are as Figure 6 shown.

[0060] Among them, Figure 6 are the input and output voltage waveforms of the temperature current limiting threshold compensation module 2. From top to bottom, they are the reference voltage V REF1 , the temperature voltage V TEMP , the first current limiting protection compensation voltage V LIM_OUT1 and the second current limiting protection compensation voltage V LIM_OUT2 . From Figure 6 it can be seen that before the 1ms moment, the temperature voltage V TEMP > the reference voltage V REF1 , no temperature compensation is performed, and the second current limiting protection compensation voltage V LIM_OUT2 output by the temperature current limiting threshold compensation module 2 = V LIM_OUT1 . After the 1ms moment, the temperature voltage V TEMP < the reference voltage V REF1 , and the second current limiting protection compensation voltage V LIM_OUT2 gradually increases as the temperature voltage V TEMP decreases. The change relationship is V LIM_OUT2 = V LIM_OUT1 +(V REF1 -V TEMP ).

[0061] More specifically, in an alternative embodiment of the present invention, as Figure 7 shown, the current limiting protection module 3 includes a third operational amplifier AMP3, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a second capacitor C2. The negative input terminal of the third operational amplifier AMP3 is connected to the second current limiting protection compensation voltage V LIM_OUT2 , the output terminal of the third operational amplifier AMP3 is connected to the gate of the eighth NMOS transistor NM8, the source of the eighth NMOS transistor NM8 is grounded to GND, and the drain of the eighth NMOS transistor NM8 is connected to the output voltage V EA_OUT, the output terminal of the third operational amplifier AMP3 is also connected to the drain of the eighth NMOS transistor NM8 after being successively connected in series with the ninth resistor R9 and the second capacitor C2. The non-inverting input terminal of the third operational amplifier AMP3 is connected to the gate of the ninth NMOS transistor NM9. The source of the ninth NMOS transistor NM9 is grounded through the series-connected eighth resistor R8. The drain of the ninth NMOS transistor NM9 is connected to the gate of the ninth NMOS transistor NM9. The drain of the ninth NMOS transistor NM9 is also connected to the source of the tenth NMOS transistor NM10 through the series-connected seventh resistor R7. The gate of the tenth NMOS transistor NM10 is connected to the drain of the eighth NMOS transistor NM8 through the series-connected tenth resistor R10. The drain of the tenth NMOS transistor NM10 is connected to the power supply voltage VCC, and the third current limiting protection compensation voltage V is output from the gate of the tenth NMOS transistor NM10. COMP .

[0062] Among them, the series-connected ninth resistor R9 and the second capacitor C2 form a Miller compensation circuit, which, together with the tenth resistor R10, ensures that the loop is stable when forming a voltage negative feedback closed loop. The size of the ninth NMOS transistor NM9 is the same as that of the tenth NMOS transistor NM10, and the resistance value of the seventh resistor R7 is the same as that of the eighth resistor R8.

[0063] More specifically, as Figure 7 shown, the working principle of the current limiting protection module 3 is as follows:

[0064] 1). Assume that the voltage at the non-inverting input terminal of the third operational amplifier AMP3 is Va. Then, according to the current conservation on the branch composed of the tenth NMOS transistor NM10, the seventh resistor R7, the ninth NMOS transistor NM9, and the eighth resistor R8, we have: (Va - V GSNM9 ) / R8 = (V COMP - V GSNM10 - Va) / R7. Since the size of the ninth NMOS transistor NM9 is the same as that of the tenth NMOS transistor NM10, V GSNM9 = V GSNM10 , and the resistance value of the seventh resistor R7 is the same as that of the eighth resistor R8, R7 = R8. Then 2Va = V COMP , and Va = V COMP / 2;

[0065] 2). The third operational amplifier AMP3 compares the voltages at both input terminals. When the voltage at the non-inverting input terminal of the third operational amplifier AMP3 is less than the voltage at the inverting input terminal, that is, V COMP / 2 is less than V LIM_OUT2 , the output of the third operational amplifier AMP3 is at a low level, the eighth NMOS transistor NM8 is turned off, and the output third current limiting protection compensation voltage V COMP = V EA_OUT . When V COMP / 2 is greater than or equal to VLIM_OUT2 When the output of the third operational amplifier AMP3 is at a high level, a pull-down current is generated through the eighth NMOS transistor NM8. At this time, the third operational amplifier AMP3 forms a voltage negative feedback closed loop, making V COMP / 2 equal to VLIM_OUT2 , and the output third current-limiting protection compensation voltage V COMP is clamped to 2 × V LIM_OUT2 , realizing the current-limiting protection function.

[0066] More specifically, in an alternative embodiment of the present invention, the effect of the current-limiting protection module 3 as shown in Figure 7 is verified, and the simulation experiment results are as shown in Figure 8 .

[0067] Among them, Figure 8 are the input and output voltage waveforms of the current-limiting protection module 3. From top to bottom, they are the load current I LOAD , the second current-limiting protection compensation voltage V LIM_OUT2 , the voltage at the positive input terminal of the third operational amplifier AMP3, 1 / 2V COMP , and the third current-limiting protection compensation voltage V COMP . Before the 1.5 ms moment, 1 / 2V COMP < V LIM_OUT2 , and the output third current-limiting protection compensation voltage V COMP = V EA_OUT . After the 1.5 ms moment, 1 / 2V COMP is greater than V LIM_OUT2 , 1 / 2V COMP is limited to be equal to V LIM_OUT2 , and the output third current-limiting protection compensation voltage V COMP = 2V EA_OUT , thus realizing the current-limiting protection function.

[0068] In addition, the present invention also provides a reference current generating device, as shown in Figure 9 , which includes an error amplifier 01, the above-mentioned current-limiting threshold compensation protection circuit 02, a voltage-current converter 03, and a subtractor 04. The error amplifier 01 is connected to the first reference voltage V REF and the feedback voltage V FB . The current-limiting threshold compensation protection circuit 02 is connected to the output voltage V EA_OUT of the error amplifier 01, the ramp current I SLOPE , the temperature voltage V TEMP , the current-limiting protection voltage V LIM , and the reference voltage V REF1 . The voltage-current converter 03 is connected to the third current-limiting protection compensation voltage V COMP, the voltage-current converter 03 performs voltage-current conversion on the third current-limiting protection compensation voltage V COMP to obtain the protection compensation current I COMP . The subtractor 04 receives the protection compensation current I COMP and the ramp current I SLOPE . The subtractor 04 performs subtraction on the protection compensation current I COMP and the ramp current I SLOPE to obtain and output the reference current I REF . The reference current I REF serves as the reference current for the subsequent peak current comparator.

[0069] In summary, the current-limiting threshold compensation protection circuit and the reference current generation device provided by the present invention can perform ramp current-limiting threshold compensation on the current-limiting protection voltage through the ramp current-limiting threshold compensation module to obtain the first current-limiting protection compensation voltage, which not only ensures the loop stability but also ensures that the current-limiting protection threshold will not become smaller; when the current sampling ratio decreases as the temperature rises, through the temperature current-limiting threshold compensation module, the first current-limiting protection compensation voltage is further subjected to temperature current-limiting threshold compensation to obtain the second current-limiting protection compensation voltage, which can ensure that the current-limiting protection threshold will not become smaller due to the decrease in the current sampling ratio after the temperature rises; through the current-limiting protection module, the output third current-limiting protection compensation voltage is clamped and protected, which can effectively prevent the output voltage and current from being too large and achieve current-limiting protection.

[0070] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A current-limiting threshold compensation protection circuit, characterized in that, Comprising: A ramp current limiting threshold compensation module, which receives a ramp current and a current limiting protection voltage, periodically senses the ramp current and converts the ramp current into a ramp voltage, and then performs ramp current limiting threshold compensation on the current limiting protection voltage through the ramp voltage to obtain a first current limiting protection compensation voltage; the ramp current limiting threshold compensation module includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a first current source, a second current source, a first NMOS transistor and a second NMOS transistor. The power supply voltage is grounded after sequentially connecting the first current source, the first resistor and the second current source in series. One end of the first resistor connected to the second current source is also connected to the current limiting protection voltage. One end of the first resistor connected to the first current source is also connected to the positive input terminal of the first operational amplifier. The negative input terminal of the first operational amplifier is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is also connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the positive input terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is connected to the negative input terminal of the first operational amplifier after sequentially connecting the second resistor in series. The negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier. The output terminal of the second operational amplifier outputs the first current limiting protection compensation voltage; A temperature current limiting threshold compensation module, which receives a temperature voltage, a reference voltage and the first current limiting protection compensation voltage, and performs temperature current limiting threshold compensation on the first current limiting protection compensation voltage through the temperature voltage and the reference voltage when the current sampling ratio decreases as the temperature increases to obtain a second current limiting protection compensation voltage; A current limiting protection module, which receives the output voltage of an error amplifier and the second current limiting protection compensation voltage. The input terminals of the error amplifier are connected to a second reference voltage and a feedback voltage, and clamps and protects the output voltage through the output voltage of the error amplifier and the second current limiting protection compensation voltage to obtain and output a third current limiting protection compensation voltage.

2. The current limiting threshold compensation protection circuit according to claim 1, wherein The first current source and the second current source respectively provide one of the ramp currents.

3. The current-limiting threshold compensation protection circuit according to claim 2, characterized in that, The ramp current limiting threshold compensation module further includes a third resistor, a first capacitor and a bias current source. The positive input terminal of the second operational amplifier is grounded after sequentially connecting the third resistor and the first capacitor in series. The positive input terminal of the second operational amplifier is also grounded after sequentially connecting the bias current source in series.

4. The current limiting threshold compensation protection circuit according to claim 3, characterized in that The temperature current-limiting threshold compensation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth current source, a fourth resistor, and a fifth resistor. The source of the third PMOS transistor is connected to the power supply voltage. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the third PMOS transistor is grounded through the series-connected fourth current source. The source of the fourth PMOS transistor is connected to the power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is connected to the source of the first PMOS transistor through the series-connected fourth resistor. The gate of the first PMOS transistor is connected to the temperature voltage. The drain of the first PMOS transistor is grounded. The source of the fifth PMOS transistor is connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor. The source of the fourth NMOS transistor is connected to the source of the second PMOS transistor through the series-connected fifth resistor. The gate of the second PMOS transistor is connected to the reference voltage. The drain of the second PMOS transistor is grounded. The source of the sixth PMOS transistor is connected to the power supply voltage. The gate of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fifth NMOS transistor is connected to the source of the third NMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage. The gate of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor. The drain of the seventh PMOS transistor is connected to the source of the second PMOS transistor.

5. The current-limiting threshold compensation protection circuit according to claim 4, characterized in that The temperature current-limiting threshold compensation module further includes an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a sixth resistor. The source of the eighth PMOS transistor is connected to the power supply voltage. The gate of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the sixth NMOS transistor is grounded. The source of the ninth PMOS transistor is connected to the power supply voltage. The gate of the ninth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor after being connected in series with the sixth resistor. The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor. The source of the seventh NMOS transistor is grounded. The drain of the seventh NMOS transistor is connected to the first current-limiting protection compensation voltage. The drain of the ninth PMOS transistor outputs the second current-limiting protection compensation voltage.

6. The current limiting threshold compensation protection circuit according to claim 5, characterized in that The size of the first PMOS transistor is the same as that of the second PMOS transistor. The sizes of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are the same. The sizes of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are the same. The size of the third NMOS transistor is the same as that of the fourth NMOS transistor. The size of the sixth NMOS transistor is the same as that of the seventh NMOS transistor. The resistance values of the fourth resistor, the fifth resistor, and the sixth resistor are the same.

7. The current-limiting threshold compensation protection circuit according to claim 6, wherein The current-limiting protection module includes a third operational amplifier, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a second capacitor. The negative input terminal of the third operational amplifier is connected to the second current-limiting protection compensation voltage. The output terminal of the third operational amplifier is connected to the gate of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the output voltage of the error amplifier. The output terminal of the third operational amplifier is also connected to the drain of the eighth NMOS transistor after being connected in series with the ninth resistor and the second capacitor in sequence. The positive input terminal of the third operational amplifier is connected to the gate of the ninth NMOS transistor. The source of the ninth NMOS transistor is grounded after being connected in series with the eighth resistor. The drain of the ninth NMOS transistor is connected to the gate of the ninth NMOS transistor. The drain of the ninth NMOS transistor is also connected to the source of the tenth NMOS transistor after being connected in series with the seventh resistor. The gate of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor after being connected in series with the tenth resistor. The drain of the tenth NMOS transistor is connected to the power supply voltage. The gate of the tenth NMOS transistor outputs the third current-limiting protection compensation voltage.

8. The current-limiting threshold compensation protection circuit according to claim 7, characterized in that The size of the ninth NMOS transistor is the same as that of the tenth NMOS transistor, and the resistance value of the seventh resistor is the same as that of the eighth resistor.

9. A reference current generating device, characterized in that, It includes an error amplifier, the current limiting threshold compensation protection circuit according to any one of claims 1-8, a voltage-current converter, and a subtractor. The error amplifier is connected to a second reference voltage and a feedback voltage. The current limiting threshold compensation protection circuit is connected to the output voltage of the error amplifier. The voltage-current converter is connected to the third current limiting protection compensation voltage output by the current limiting threshold compensation protection circuit. The voltage-current converter performs voltage-current conversion on the third current limiting protection compensation voltage to obtain a protection compensation current. The subtractor is connected to the protection compensation current and the ramp current. The subtractor performs subtraction operation on the protection compensation current and the ramp current to obtain and output a reference current.

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