Isolation Logic Test Circuits and Related Test Methods

Abstract

Embodiments of the present invention relate to isolated logic test circuits and related test methods. One circuit includes: a first power domain comprising an isolation unit, a first selection circuit having inputs for receiving a first functional signal and a first test signal and for controlling the output of the isolation unit, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation unit; and a second power domain comprising the first circuit having an input coupled to the signal output of the isolation unit, a first observation element coupled to the signal output of the isolation unit, and a second observation element coupled to the output of the first circuit; wherein, when in test mode, the first selection circuit controls the isolation unit based on the first test signal, and the second selection circuit provides a second test signal to the signal input of the isolation unit.

Description

Technical Field

[0001] This disclosure generally relates to electronic systems and methods, and in certain embodiments relates to isolated logic test circuits and related test methods. Background Technology

[0002] The state of signals originating from unpowered logic circuits is typically indeterminate (usually indicated by the symbol "X"). If such signals are fed into active logic circuits, the active logic circuits may operate incorrectly. For example, Figure 1A and Figure 1B Schematic diagrams and related waveforms of two inverters (102 and 104) connected in series are shown respectively.

[0003] like Figure 1A As shown, inverter 102 is powered by power supply voltage V. CC Powered by, and inverter 104 is powered by power supply voltage V DD Power supply. For example... Figure 1B As shown, when the power supply voltage V CC and V DD When both are powered (before time t1), signal V2 is the inverted version of signal V1, and signal V3 is the inverted version of signal V2. When inverter 102 becomes unpowered (when the power supply voltage V...), ... CC When the voltage is low (e.g., at time t1), voltages V2 and V3 become uncertain.

[0004] To avoid the uncertain state of signal V3, an isolation circuit, also known as an isolation unit, can be used. For example, Figure 2A and Figure 2B Schematic diagrams of inverters 102 and 104 connected in series and having an isolation unit 202 between them, along with corresponding waveforms, are shown. Figure 2A As shown, inverters 102 and 104, as well as AND gate 202, are symbolically depicted. Similarly, as... Figure 2A As shown, inverter 102 is powered by power supply voltage V. CC Power is supplied by the inverter 104 and the AND gate 202, which are powered by the power supply voltage V. DD powered by.

[0005] AND gate 202 operates as an isolation unit (referred to here as isolation unit 202). For example, when isolation unit 202 is disabled (when the signal Iso_en... 202 When Iso_en is 1, signal V'2 is equal to signal V2. When isolation unit 202 is enabled (when Iso_en...),... 202 When V'2 is 0, regardless of its state, signal V'2 is 0. When inverter 102 becomes unpowered (when V'2 is 0), signal V'2 is 0. CCWhen the threshold is lowered, isolation unit 202 can be enabled. This response is as follows: Figure 2B As shown in the diagram.

[0006] like Figure 2A and Figure 2B As illustrated, the use of isolation unit 202 allows for operation at power supply voltage V. CC To avoid uncertain states in the output of inverter 104 when it is not powered.

[0007] Figure 2A This illustrates a possible implementation of an isolation cell that generates 0 when enabled. It is also possible to implement an isolation cell that generates 1 when enabled. For example, Figure 3 A schematic diagram shows inverters 102 and 104 connected in series and having an isolation unit 302 between them. (See diagram) Figure 3 As shown, for clarity, the supply terminals of logic gates 102, 104 and 302 have been omitted and replaced with power domain labels.

[0008] like Figure 3 As can be seen, when isolation 302 is disabled (when the signal Iso_en... 302 When Iso_en is 0, signal V'2 equals signal V2. When isolation unit 202 is enabled (when Iso_en...),... 202 When V'2 is 1, regardless of the state of V2, signal V'2 is 1. When inverter 102 becomes unpowered (when V'2 is 1), signal V'2 is 1. CC When the value is low, isolation unit 202 can be enabled.

[0009] Integrated circuits (ICs) with multiple power domains typically use isolation cells for signals propagating from the unpowered domain to the always-on domain (the power domain that is powered whenever the IC is powered). Summary of the Invention

[0010] According to one embodiment, an electronic circuit includes a first power domain and a second power domain. The first power domain includes: a first isolation unit comprising a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit; a first selection circuit having a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit; and a second selection circuit having a first input configured to receive a second functional signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit. The second power domain includes: a first circuit having an input coupled to the signal output of the first isolation unit; and a first observation element coupled to a first intermediate node, the first intermediate node being coupled to the signal output of the first isolation unit and the first... The circuit includes inputs and a second observation element coupled to the output of the first circuit. The electronic circuit includes multiple functional modes and a first test mode. For each of the multiple functional modes, a first power domain is configured to be on when a second power domain is on, and the second power domain is configured to be off in at least one functional mode where the first power domain is configured to be on. When the electronic circuit is in the first test mode, a first selection circuit is configured to provide a first test signal to the control input of the first isolation unit, and a second selection circuit is configured to provide a second test signal to the signal input of the first isolation unit. When the electronic circuit is in any of the multiple functional modes, the first selection circuit is configured to provide a first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide a second functional signal to the signal input of the first isolation unit.

[0011] According to one embodiment, an integrated circuit includes a first power domain and a second power domain. The first power domain includes: a power-on reset (POR) circuit configured to generate a POR signal, wherein the POR circuit is configured to activate the POR signal when a first power supply voltage of the first power domain reaches a predetermined threshold; a first isolation unit including a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit; a first selection circuit having a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit; and a second selection circuit having a first input configured to receive a POR signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit. The second power domain includes: a test controller having an input coupled to the signal output of the first isolation unit; and a first pin or pad coupled to the first isolation unit. The first intermediate node is coupled between the signal output of the first isolation unit and the test controller, and a second pin or pad is coupled to the output of the test controller. The integrated circuit includes multiple functional modes and a first test mode. For each of the multiple functional modes, a first power domain is configured to be turned on when a second power domain is turned on, and the second power domain is configured to be turned off in at least one functional mode in which the first power domain is configured to be turned on. When the integrated circuit is in the first test mode, a first selection circuit is configured to provide a first test signal to the control input of the first isolation unit, and a second selection circuit is configured to provide a second test signal to the signal input of the first isolation unit. When the integrated circuit is in any of the multiple functional modes, the first selection circuit is configured to provide a first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide a POR signal to the signal input of the first isolation unit.

[0012] According to one embodiment, a method for testing an integrated circuit having multiple power domains, multiple functional modes, and a first test mode includes, during the first test mode: causing a first selection circuit having an output having a first input for receiving a first functional signal, a second input for receiving a first test signal, and a control input coupled to a first isolation unit to deliver a first test signal to the control input of the first isolation unit; causing a second selection circuit having an output having a first input for receiving a second functional signal, a second input for receiving a second test signal, and a signal input coupled to the first isolation unit to deliver a second test signal to the signal input of the first isolation unit, wherein the first power domain among the multiple power domains includes the first and second selection circuits and the first isolation unit; setting the second test signal to logic 1; enabling the first test signal to activate the first isolation unit; after setting the second test signal to logic 1 and enabling the first test signal, measuring a first voltage at a first pin or pad of the signal output coupled to the first isolation unit, wherein the second power domain among the multiple power domains includes the first pin or pad, wherein, for each of the multiple functional modes, when the second power domain is enabled, the first... The power domain is enabled, and the second power domain is disabled in at least one functional mode where the first power domain is enabled; the second test signal is set to logic 0; the first test signal is deactivated to disable the first isolation unit; after setting the second test signal to logic 0 and deactivating the first test signal, a second voltage is measured at the first pin or pad; the first test bit of the first power domain is set to logic 0, wherein the first test bit is coupled to the first input of an OR gate, the OR gate having a second input and an output, the second input being coupled to the signal output of the first isolation unit and the first pin or pad, and the output being coupled to the input of the test controller, wherein the second power domain includes the OR gate and the test controller; after setting the second test signal to logic 0, deactivating the first test signal, and setting the first test bit to logic 0, a third voltage is measured at the second pin or pad coupled to the output of the test controller, wherein the second power domain includes the second pin or pad; when the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is in reset mode, a first indication is generated, the first indication indicating that the first path of the signal input coupled to the first isolation unit does not have a stuck-at fault. The second path of the signal output coupled to the first isolation unit does not have a stuck-in-1 fault; when the first voltage corresponds to logic 0 and the second voltage corresponds to logic 1, a second indication is generated indicating that the first path has a stuck-in-1 fault; and when the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is not in reset mode, a third indication is generated indicating that the second path has a stuck-in-1 fault. Attached Figure Description

[0013] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1A and Figure 1B The schematic diagrams and related waveforms of two inverters connected in series are shown respectively;

[0015] Figure 2A and Figure 2B Schematic diagrams and related waveforms of two inverters connected in series and having an isolation unit between them are shown respectively;

[0016] Figure 3 A schematic diagram of two inverters connected in series and having an isolation unit between them is shown.

[0017] Figure 4 A schematic diagram of an IC having multiple power domains according to an embodiment of the present invention is shown;

[0018] Figure 5 The figure illustrates an embodiment of the present invention. Figure 4 Some power domains of the IC Figure 4 A table showing the states of the IC under different power modes;

[0019] Figure 6 A schematic diagram of a test circuit according to an embodiment of the present invention is shown;

[0020] Figure 7 The figure illustrates an embodiment of the present invention. Figure 4 A table of various test modes for the IC;

[0021] Figure 8 A flowchart of an embodiment of a method for testing an isolation unit according to an embodiment of the present invention is shown;

[0022] Figure 9 An isolated insertion and simulation process according to an embodiment of the present invention is illustrated; and

[0023] Figure 10 A schematic diagram of a test circuit according to an embodiment of the present invention is shown.

[0024] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Implementation

[0025] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of manufacturing and using the invention and do not limit the scope of the invention.

[0026] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. These embodiments may be obtained without one or more specific details, or may be obtained by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described in relation to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer exactly to the same embodiment. Furthermore, particular formats, structures, or features may be combined in any suitable manner in one or more embodiments.

[0027] Embodiments of the invention will be described in the specific content. An integrated circuit (IC) has multiple power domains and includes isolation units for signals propagating from a powered domain to an unpowered domain, and includes a power-on reset (POR) circuit and associated isolation unit test methods. Some embodiments can be implemented in circuits without POR circuitry and / or for signals unrelated to POR circuitry. In some embodiments, one or more test methods can be performed during IC design simulation, IC characterization, IC debugging, IC production, and / or in the field.

[0028] In one embodiment of the invention, test circuitry is used to determine the location of missing isolation units, incorrectly connected isolation units, and stuck-at-1 faults in the signal path through the isolation units. In some embodiments, the test circuitry is inserted into register transfer level (RTL) code, while the isolation units are automatically inserted by synthesis tools based on RTL and Unified Power Format (UPF).

[0029] Figure 4A schematic diagram of an IC 400 according to an embodiment of the present invention is shown. The IC 400 includes three distinct power domains: an ultra-low power (ULP) domain, a low power (LP) domain, and an operational domain. The IC 400 includes a POR circuit 402 in the ULP domain and a test controller 404 in the operational domain. The IC 400 also includes multiple isolation units (406, 408, 410, 412, 414, 416). The IC 400 may also include one or more analog circuits and / or one or more digital circuits. Examples of such analog circuits include PLLs, OTPs, NVMs, etc.

[0030] The POR circuit 402 is configured to monitor the supply levels of one or more ULP domains and, when the supply levels of one or more ULP domains (e.g., the output of a bandgap or normally open LDO) reach one or more corresponding threshold voltages (when the ULP domain is powered), trigger the reset signal (POR). rst The reset signal POR takes effect. rst The analog and / or digital circuitry of the ULP domain is configured to reset when active, to initialize these blocks to a known state. In some embodiments, the POR circuit 402 may be implemented in any manner known in the art.

[0031] As will be described in more detail later, in some embodiments, the signal POR rst It can also be used to reset analog and / or digital circuits in power domains that are different from the ULP domain (e.g., the LP domain and / or the operating domain).

[0032] Test controller 404 is configured to perform or assist in performing tests on one or more circuits of IC 400. For example, in some embodiments, test controller 404 may include a conventional Automated Test Pattern Generator (ATPG) for running test patterns in a known manner to detect faults associated with one or more circuits of IC 400. In some embodiments, test controller 404 may also include a Joint Test Action Group (JTAG) interface, which may be implemented in any manner known in the art.

[0033] IC 400 may include multiple pins and / or pads. For example, Figure 4 The diagram illustrates pin or pad numbers 420, 422, 422', 422”, 424, 426, 426', 426”, 432, 434, 436, 438, 440, and 442. Fewer pins or pads, or more pins or pads, can also be used.

[0034] like Figure 4As shown, in some embodiments, pins or pads 420, 422, 422', 422”, 424, 426, 426', and 426” are accessible by circuitry in the ULP domain in all power modes, and are accessible by circuitry in other domains when that domain is powered (e.g., by circuitry in the LP domain in all power modes except standby mode, and by circuitry in the Run domain in Run mode, and in other power modes if powered). Pins or pads 432, 434, and 436 are accessible by circuitry in both the LP and ULP domains, by circuitry in the Run domain when in Run mode, and in other power modes if powered. Pins or pads 438, 440, and 442 are accessible by circuitry in the Run, LP, and ULP domains.

[0035] One or more isolation units 406, 408, 410, 412, 414, 416 may be implemented in any manner known in the art (e.g., as isolation units 202 or 302). In some embodiments, isolation units 408, 412, 410, and 414 are powered by the ULP domain, and isolation units 406 and 416 are powered by the LP domain.

[0036] As shown in the figure, in some embodiments, IC 400 includes three different power domains. In some embodiments, IC 400 may have only two different power domains. In some embodiments, IC 400 may have three or more different power domains.

[0037] In some embodiments, the ULP domain is designed as a normally-on power domain, the LP domain is designed to be enabled in all power modes except standby, and the operating domain is designed to be enabled only in operating power mode. For example, Figure 5 Table 500 illustrates the states of some power domains of IC 400 in different power modes of IC 400 according to an embodiment of the present invention.

[0038] like Figure 5 As illustrated, there exists at least one state in which a signal crossing from the LP domain to the ULP domain crosses from the unpowered domain to the powered domain. There exists at least one state in which a signal crossing from the operating domain to the ULP domain crosses from the unpowered domain to the powered domain. There exists at least one state in which a signal crossing from the operating domain to the LP domain crosses from the unpowered domain to the powered domain.

[0039] In some embodiments, all signals crossing from the unpowered domain to the powered domain pass through isolation units to avoid causing uncertain states in the powered domain circuitry. For example, in some embodiments, all signals crossing from the operating domain to the LP domain pass through corresponding isolation units, all signals crossing from the operating domain to the ULP domain pass through corresponding isolation units, and all signals crossing from the LP domain to the ULP domain pass through corresponding isolation units. Isolation units 406, 408, and 410 illustrate isolation units for signals crossing from the unpowered domain to the powered domain.

[0040] In some embodiments, some signals crossing from a powered domain to a non-powered domain may cross domains without passing through an isolation unit (e.g., because there may be no risk of causing an uncertain state in the non-powered domain). As will be described in more detail later, some embodiments may benefit from having isolation units for at least some (e.g., critical) signals crossing from a powered domain to a non-powered domain. Isolation units 412, 414, and 416 are illustrated as isolation units for signals crossing from a powered domain to a non-powered domain.

[0041] Examples of signals that can benefit from bridging a powered domain to an unpowered domain with isolation units include reset signals, enable signals, and power-ok signals. For example, in some embodiments, the unpowered domain (e.g., the LP domain, the operating domain) can be implemented without a POR circuit. After IC 400 is powered on, the POR circuit 402 resets the logic in the ULP domain (e.g., using the POR signal). rst In some embodiments, the signal POR rst They are routed to the LP domain and / or the operating domain via isolation units (e.g., 414, 412, respectively) to reset the logic on the LP / operating domain when it is powered on.

[0042] In some embodiments, the isolation unit that routes signals from the powered domain to the unpowered domain can be disabled only when the unpowered domain is powered on. For example, in some embodiments, the signal POR rst After passing through isolation unit 412, isolation unit 412 remains enabled until the operating domain is powered on, and after the operating domain is powered on, isolation unit 412 is disabled. Since isolation unit 412 is enabled before the operating domain is powered on, the logic circuitry of the operating domain is in a known (e.g., default) state when the operating domain is powered on.

[0043] During IC design, isolation cells (e.g., especially isolation cells for signals crossing from a powered domain to an unpowered domain) are missing and / or the enable signal (Iso_en) is missing. 4xxIt is not uncommon for isolation units to be connected to incorrect ones. In some embodiments, test circuit 403 is configured to detect missing isolation units and / or detect incorrect connection / placement of isolation units. In some embodiments, test circuit 403 may be configured to detect a stuck-in fault on the buffer of the input coupled to the output of the isolation unit and / or detect a stuck-in fault on the buffer of the output coupled to the input of the isolation unit.

[0044] Figure 6 A schematic diagram of a test circuit 600 according to an embodiment of the present invention is shown. Test circuit 403 can be implemented as test circuit 600. Figure 7 Table 700 illustrates various test modes of IC 400 according to an embodiment of the present invention. Figure 6 and Figure 7 We can understand them together.

[0045] The test circuit 600 includes multiple test bits (602, 604, 606, 608, 610, 612) and multiplexers (MUX) 614, 616, 618, 620. These test bits can be programmed, for example, using JTAG or any other conventional digital communication protocol. In some embodiments, one or more of the test bits can be controlled by pins or pads of the IC 400.

[0046] Circuit 634 can be a digital circuit or an analog circuit. For example, in some embodiments, circuit 634 may correspond to a digital circuit, such as a test controller 404. In some embodiments, circuit 634 may correspond to an analog circuit, such as a clock source (e.g., an oscillator or a PLL) or a memory (NVM [non-volatile memory] or a fuse [one-time programmable]). For illustrative purposes, Figure 7 Assume that circuit 634 corresponds to test controller 404.

[0047] Figure 6The illustration shows a test circuit 600 for a single isolation cell (412 in this example), which is coupled to a test circuit 634 in this example. Similar circuitry can be implemented for other isolation cells, for example, it can be coupled (e.g., for reset purposes) to other digital circuitry. For example, pins or pads 422' and 422" illustrate typical input pins or pads for other isolation cells of IC 400 (e.g., 414 or 416). For example, pin or pad 422' can be coupled via MUX 618' and 620' (e.g., arranged similarly to MUX 618 and 620) to control another isolation cell (e.g., 414), and pin or pad 422" can be coupled via MUX 618" and 620 (e.g., arranged similarly to MUX 618 and 620) to control another isolation cell (e.g., 416). Similar arrangements (e.g., using pins or pads to control the isolation enable signal via MUX 618, 620, and using pins or pads to observe the signal during isolation testing) can be used for isolation cells, such as all isolation cells of IC 400. IC 400 may include multiple pins or pads 422 for controlling the respective isolation cells of IC 400 during isolation test mode.

[0048] like Figure 6 As shown, in some embodiments, buffers 622, 624, and 626 can be used in the POR signal. rst In the path. Such buffers and the POR signal. rst Other components in the path may be susceptible to the failure that is stuck at step 1.

[0049] During normal operation (during functional mode), the POR signal... rst It is activated during power-on (e.g., low) when the supply level of the ULP domain is below a predetermined threshold, and deactivated (e.g., high) once the supply level of the ULP domain reaches the predetermined threshold. In the POR signal... rst After activation, test bits 602 (TESTBIT0), 604 (TESTBIT1), 608 (TESTBIT3), 610 (TESTBIT4), and 612 (TESTBIT5) are reset (e.g., low). Therefore, during normal operation, the POR signal... rst Flow to isolation unit 412 (POR) rst =POR 412 The isolation unit is controlled by the signal Func_EN (enabled / disabled). When the signal Func_EN is deactivated to disable isolation unit 412, the signal POR... rst Flow circuit 634 (POR) rst =POR 412 =POR'412 For example, this causes circuit 634 to be reset to a known state.

[0050] By using isolation units from the power supply domain to the non-power supply domain, such as isolation units for signals originating from POR circuit 402, some embodiments can implement (e.g., a single) POR circuit in the normally open power domain (e.g., ULP), and can also use isolation units from POR circuit 402 (e.g., POR) rst Signals routed via isolation units (e.g., 412, 414) can advantageously omit POR circuitry in other power domains (e.g., LP domain, operating domain) to reset circuitry in unpowered domains by enabling the relevant isolation units, for example, after power is applied to these domains, and to disable the isolation units only when the power in these domains exceeds a threshold of the voltage monitor that allows these domains to start functioning.

[0051] In some embodiments, isolation unit 412 may be implemented such that it is low when isolation unit 412 is enabled (e.g., as isolation unit 202). Therefore, after isolation unit 412 is enabled, signal POR' 412 The signal is low, thus keeping circuit 634 in reset mode (in a known static state), and after disabling isolation unit 412, the signal POR' 412 The transition is from low to high, and circuit 634 starts operating from a known state.

[0052] As illustrated in Table 700, when circuit 634 corresponds to test controller 404, the pins or pads of IC 400 operate according to the function mode (“F”), and test controller 404 is in reset mode (because signal POR' 412 Reset test controller 404 during power-on or whenever isolation unit 412 is enabled.

[0053] As illustrated in Table 700, in some embodiments, the test controller 404 remains in a reset state during functional modes. In some embodiments, keeping the test controller 404 in a reset or known state during functional modes can advantageously prevent unstable responses that may arise from interactions between the test controller 404 and other functional circuitry.

[0054] Test modes can be entered after power-on (e.g., ATPG mode or any isolated test mode illustrated in Table 700). For example, test modes can be entered (e.g., at the POR signal) by programming one or more test bits of the IC 400 (602, 604, 606, 608, 610, 612) (e.g., according to Table 700). rst (After it is cancelled).

[0055] During ATPG mode (as illustrated in Table 700), test controller 404 is active and forcibly enabled by test bit 608 (TESTBIT3) to prevent the test controller from being reset while it is executing ATPG mode. During ATPG mode, isolation unit 412 is controlled by the signal ATPG_EN. During ATPG mode, the pins or pads of IC 400 can operate according to the mode (“P”).

[0056] During isolation test modes 1 to 8 (as illustrated in Table 700), test bits 602 (TESTBIT0), 604 (TESTBIT1), and 612 (TESTBIT5) are enabled (e.g., high), and test bit 610 is deactivated (e.g., low) to enable the signal POR. 412 It is controlled by test bit 606 (TESTBIT2), and isolation unit 412 is controlled by pin or pad 422.

[0057] In some embodiments, when test bit 602 (TESTBIT0) is active (e.g., high), one or more pins or pads of IC 400 (e.g., 420, 422, 426, 432, 434, 436, 438, 440, 442) are configured as test-mode input / output pins or pads. For example, in some embodiments, when test bit 602 (TESTBIT0) is active, pins or pads 420 and 422 (e.g., including 422', 422" etc.) are configured as inputs, and pins or pads 426, 438, and 440 are configured as outputs.

[0058] like Figure 6 As shown, for example, the output of isolation unit 412 can be observed in pins or pads 438 and 440. Using pins or pads associated with the operating domain to observe the output of isolation unit 412 advantageously allows for observation of the signal POR'. 412 The signal can be observed without going through an additional isolation unit (if the signal needs to cross to another power domain, such as returning to the ULP domain, it may need to go through an additional isolation unit).

[0059] When test bit 604 (TESTBIT1) is active (e.g., high), it configures MUX614 and 616 to make the signal POR 412 Controlled by test bit 606 (TESTBIT2).

[0060] When test bit 608 (TESTBIT3) is active (e.g., high), its forced enable signal SEN 404 Set to high to keep test controller 404 enabled.

[0061] Test bits 610 (TESTBIT4) and 612 (TESTBIT5) control the states of MUX 620 and 618, respectively.

[0062] In some embodiments, test bits 602, 604, 606, 608, 610, and 612 (TESTBIT0, TESTBIT1, TESTBIT2, TESTBIT3, TESTBIT4, and TESTBIT5) can be programmed via JTAG (or other digital interfaces). Figure 6 As shown, in some embodiments, test bits 602, 604, 608, 610, and 612 (TESTBIT0, TESTBIT1, TESTBIT3, TESTBIT4, TESTBIT5) can be in POR rst When activated, it is asynchronously reset to logic 0, and can also be programmed to logic 1 or logic 0 (e.g., via JTAG).

[0063] In some embodiments, test bit 606 (TESTBIT2) can be used in POR rst When activated (or when signal Sin420 is forced low when TESTBIT1 equals logic 1), it is asynchronously set (to logic 1) and can also be programmed to logic 1 or logic 0 (e.g., via JTAG). In some embodiments, providing a pin or pad 420 to asynchronously set TESTBIT2 advantageously allows causing the test controller 404 (and, for example, JTAG logic) to be removed from a reset. For example, in some embodiments, causing TESTBIT2 to be logic 0 (e.g., as...) Figure 7 As illustrated in the diagram, in some isolation tests, the JTAG logic may be in reset mode, and therefore when the JTAG logic is in reset mode, pin or pad 420 can be used to set TESTBIT2 to logic 1.

[0064] The outputs of isolation tests 1 through 8 (columns 438, 440 and “TCU status”) reflect the status of pins and pads 438 and 440 and test controller 404 when the corresponding isolation test passes.

[0065] As illustrated in Table 700, during isolation test 1, pin or pad 422 is set to 0 (e.g., by forcing 0V on pin or pad 422) to enable isolation unit 412, and TESTBIT2 is set to 1 to transmit the signal POR. 412Set to 1. If a value of 0 is measured at pin or pad 438 (e.g., if a low voltage, such as 0V, is measured at pin or pad 438), then isolation test 1 passes, and there is no fault stuck at 1 in the path from the output of isolation unit 412 to pin or pad 438. If a value of 1 is measured at pin or pad 438 (e.g., if a high voltage, such as 1.0V, is measured at pin or pad 438), then isolation test 1 fails.

[0066] In some embodiments, isolation test 2 can be performed after isolation test 1 fails. As illustrated in Table 700, during isolation test 2, one of the other pins or pads 422 (e.g., 422', 422" etc.) is set to 0, while pin or pad 422 is set to 1, and TESTBIT2 is set to 1 to reset the POR signal. 412 Set to 1. If a value of 0 is measured at pin or pad 438, then isolation test 2 passes, and other pins or pads 422 (e.g., 422', 422" etc.) are controlling isolation unit 412. Passing isolation test 2 means that isolation unit 412 is not missing, but indicates an incorrect isolation connection because pin or pad 422 is not properly controlling isolation unit 412 (because isolation test 1 failed) and other pins or pads 422 (e.g., 422', 422" etc.) are controlling isolation unit 412. In some embodiments, if isolation test 1 fails, isolation test 2 is performed on each of the other pins or pads 422 (422', 422', etc.) to check whether the isolation unit 412 is incorrectly connected (isolation test 2 passes) or missing (isolation test 2 fails). When both isolation tests 1 and 2 fail, it may be due to a missing isolation or a stuck-in fault from pin or pad 422 / other pins or pads 422 to isolation unit 412 (if there is a stuck-in fault between pin or pad 422 / other pins or pads 422 and isolation unit 412, this is equivalent to a missing isolation).

[0067] In some embodiments, isolation test 3 can be performed after confirming that isolation unit 412 is correctly placed (e.g., after isolation test 1 or 2 passes) or if isolation unit 412 is seen to be missing or if there is a stuck-at-1 fault between pin or pad 422 / other pin or pad 422 and isolation unit 412 (e.g., when both isolation tests 1 and 2 fail). As illustrated in Table 700, during isolation test 3, isolation unit 412 is disabled, for example, by setting pin or pad 422 to 1 (if isolation test 1 passes) and other pins or pads 422 (e.g., 422', 422" etc.) to 1 (if isolation test 2 passes). In some embodiments, all pins or pads 422 (e.g., 422, 422', 422" etc.) are set to 1 (if both isolation tests 1 and 2 fail, then an isolation missing condition exists). During isolation test 3, TESTBIT2 is forced to 0 (e.g., using JTAG) to send the signal POR 412 Set to 0. If a 0 is measured at pin or pad 438, then there is no fault stuck at 1 in the path from the output of test bit 606 (TESTBIT2) to pin or pad 438. If a 1 is measured at pin or pad 438, then isolation test 3 has failed.

[0068] During isolation test 4, signal POR' 412 It is forced to 0, and TESTBIT3 is set to 0. If test controller 404 is observed to be in reset mode at pad 440 (e.g., by observing 0 in pin or pad 440), then there is no fault from the output of buffer 624 to test controller 404 stuck at 1. If test controller 404 is not in reset mode, then isolation test 4 fails.

[0069] As shown in Table 700, when isolation test 4 fails, isolation test 5 passes. Therefore, passing isolation test 5 indicates a stuck fault (I) in the path from buffer 624 to test controller 404.

[0070] As shown in Table 700, isolation test 6 passes when isolation test 3 fails. Therefore, if the isolation unit is correct (isolation test 1 passes) or the isolation unit is faulty (if isolation test 2 passes), passing isolation test 6 indicates a stuck-on-1 fault in the path from TESTBIT2 to isolation unit 412, and if isolation is missing (if both isolation tests 1 and 2 fail), it indicates a stuck-on-1 fault in the path from TESTBIT2 to pin or pad 438.

[0071] As shown in Table 700, during isolation test 7, isolation unit 412 is enabled, thus signal POR' is transmitted in a manner similar to that in isolation tests 1 and 2.412 The value is forced to 0. Therefore, passing isolation test 7 indicates that there is no stuck-at-1 fault between buffer 624 and test controller 404. Failing isolation test 7 indicates that there is a stuck-at-1 fault between buffer 624 and test controller 404.

[0072] As shown in Table 700, when isolation test 7 fails, isolation test 8 passes. Therefore, passing isolation test 8 indicates a fault stuck at step 1 in the path from buffer 624 to test controller 404.

[0073] like Figure 6 and Figure 7 As shown, the output of isolation unit 412 can be observed at different points along the path using pins or pads 438 and 440. In some embodiments, the output of isolation unit 412 can be observed without using pins or pads, or in addition to using pins or pads, using non-volatile memory such as triggers. For example, as Figure 6 As shown, in some embodiments, pins or pads 440 can be used, and additionally, a test shift register 632 can be used to observe the output of circuit 634. The output of AND gate 630 can also be accessed via test shift register 632. In some embodiments, test shift register 632 can be, for example, a scan chain accessible via JTAG.

[0074] Despite Figure 7 The diagram illustrates various isolation tests, but other tests are also possible. For example, in some embodiments, isolation tests can be performed to find pins or pads (e.g., 426) that are multiplexed in the isolation cell test mode corresponding to FUNC_EN (e.g., checking whether pin or pad 422 is multiplexed with FUNC_EN corresponding to the transition from the ULP power domain to the operating power domain) or to check whether there is a stuck-at-1 fault between pin or pad 422 and the enable input of isolation cell 412 (by observing pin or pad 426).

[0075] Figure 8 A flowchart of an embodiment method 800 for testing an isolation unit 412 according to an embodiment of the present invention is shown. (In conjunction with...) Figure 6 and Figure 7 Understandable Figure 8 .

[0076] During step 802, isolation test 1 is performed. Passing isolation test 1 indicates that isolation unit 412 is present and correctly connected, and there is no stuck-at-1 fault from pin or pad 422 to pin or pad 438. If isolation test 1 fails, isolation test 2 is performed during step 806. If isolation test 1 passes, isolation test 2 can be skipped. If isolation test 2 passes after isolation test 1 fails, it indicates that isolation unit 412 is present but the connection is incorrect (controlled by other pins or pads 422 (such as 422' or 422") instead of pin or pad 422 itself), and there is no stuck-at-1 fault from other pins or pads 422 to pin or pad 438. Failure of both isolation tests 1 and 2 indicates that isolation unit 412 is absent (missing) or there is a stuck-at-1 fault from pin or pad 422 to pin or pad 438 / other pins or pads 422 to pin or pad 438.

[0077] During step 812, isolation test 3 is performed. In some embodiments, the settings for isolation test 3 may depend on the results of isolation 1 and 2. For example, if isolation test 3 is performed after step 804 (after isolation test 1 has passed), then pin or pad 422 is set to 1 to disable isolation unit 412. If isolation test 3 is performed after step 808 (after isolation test 1 has failed and isolation test 2 has passed), then pin or pad 422 (e.g., 422', 422" etc.) that is found to be controlling isolation unit 412 is set to 1 to disable isolation unit 412. If isolation test 3 is performed after step 810 (after isolation tests 1 and 2 have failed), then the state of pin or pad 422, 422', 422" etc. is irrelevant, and the settings for pin or pad 422, 422', 422" etc. may be omitted.

[0078] Because TESTBIT2 is forced to 0 during isolation test 3 (e.g., via JTAG), and because isolation cell 412 is disabled or missing (and therefore does not block the path from TESTBIT2 to pin or pad 438), if isolation test 3 fails (reading a 1 in pin or pad 438), then if isolation test 1 or isolation test 2 had passed earlier, there is a stuck 1 fault in the path from TESTBIT2 to isolation cell 412, or if both isolation test 1 and isolation test 2 had failed earlier, there is a stuck 1 fault in the path from TESTBIT2 to pin or pad 438. If isolation test 3 passes, then there is no stuck 1 fault in the path from TESTBIT2 to pin or pad 438.

[0079] During step 818, isolation test 4 is performed. During isolation test 4, the signal POR' 412It is forced to 0 (e.g., by having a setting similar to that in Isolation Test 3), and TESTBIT3 is set to 0 to avoid the OR gate 628 masking signal POR. 412 If isolation test 4 fails after isolation test 3 passes, a stuck-at-1 fault is detected in the path from the output of buffer 624 to circuit 634. If isolation test 4 passes (e.g., regardless of the state of isolation tests 1 and 2), then no stuck-at-1 fault is detected in the path from the output of buffer 624 to circuit 634.

[0080] like Figure 8 As illustrated, by combining different isolation tests, some embodiments can advantageously detect faults (e.g., missing isolation units, incorrect connections of isolation units, and / or stuck-in-fault situations) and the location of these faults. For example, in some embodiments:

[0081] The result of passing isolation test 1, then isolation test 3, and then isolation test 4 is that isolation unit 412 exists, is correctly connected, and there is no stuck fault 1 in the signal path before or after isolation unit 412, and there is no stuck fault 1 in the enabled path of isolation unit (the path from pin or pad 422 to isolation unit 412).

[0082] The result of isolation test 1 passing, then isolation test 3 passing, and then isolation test 4 failing is that isolation unit 412 exists, is correctly connected, and has a stuck-on-1 fault in the output signal of buffer 624 present in the fanout coupled to isolation unit 412.

[0083] The result of isolation test 1 passing and then isolation test 3 failing is that isolation unit 412 exists, is correctly connected, and has a stuck fault 1 in the signal path coupled to the input of isolation unit 412;

[0084] The result of isolation test 1 passing, then isolation test 3 failing, and then isolation test 4 passing is that isolation unit 412 exists, is correctly connected, and has a stuck-on-1 fault in the signal path coupled to the input of isolation unit 412, and has no stuck-on-1 fault in the signal coupled to the output of isolation unit 412.

[0085] The result of isolation test 1 passing, then isolation test 3 failing, and then isolation test 4 failing is that isolation unit 412 exists, is correctly connected, and has a stuck-on-1 fault in the signal path before isolation unit 412 and after buffer 624 present in isolation unit 412;

[0086] The result of isolation test 1 failing, then isolation test 2 passing, then isolation test 3 passing, and then isolation test 4 passing is that isolation unit 412 exists, is incorrectly connected, and there is no stuck-on-1 fault in the signal path before or after isolation unit 412, and there is no stuck-on-1 fault in the enabled path of isolation unit (the path from other pins or pad 422 to isolation unit 412).

[0087] The result of isolation test 1 failing, then isolation test 2 passing, then isolation test 3 passing, and then isolation test 4 failing is that isolation unit 412 exists, is incorrectly connected, and has a stuck-on-1 fault in the signal coupled to the output of buffer 624 present in the fan-out of isolation unit 412.

[0088] The result of isolation test 1 failing, then isolation test 2 passing, and then isolation test 3 failing is that isolation unit 412 exists, is incorrectly connected, and has a stuck-on-1 fault in the signal path coupled to the input of isolation unit 412;

[0089] The result of isolation test 1 failing, then isolation test 2 passing, then isolation test 3 failing, and then isolation test 4 passing is that isolation unit 412 exists, is incorrectly connected, and has a stuck-on-1 fault in the signal path coupled to the input of isolation unit 412, but does not have a stuck-on-1 fault in the signal coupled to the output of isolation unit 412.

[0090] The result of isolation test 1 failing, then isolation test 2 passing, then isolation test 3 failing, and then isolation test 4 failing is that isolation unit 412 exists, is incorrectly connected, and has a stuck-on-1 fault in the signal path before isolation unit 412 and after buffer 624 present in the fan-out of isolation unit 412;

[0091] The result of isolation test 1 failing, then isolation test 2 failing, then isolation test 3 passing, and then isolation test 4 passing is that isolation unit 412 is missing or has a stuck-on-1 fault on the path from pin or pad 422 / other pin or pad 422 to isolation unit 412, and there is no stuck-on-1 fault on the signal path from test bit 606 to circuit 634.

[0092] The result of isolation test 1 failing, then isolation test 2 failing, then isolation test 3 passing, and then isolation test 4 failing is that isolation unit 412 is missing or has a stuck-on-1 fault on the path from pin or pad 422 / other pin or pad 422 to isolation unit 412, and has a stuck-on-1 fault in the signal path between buffer 624 and circuit 634.

[0093] The result of isolation test 1 failing, then isolation test 2 failing, and then isolation test 3 failing is that isolation unit 412 is missing or has a stuck-1 fault on the path from pin or pad 422 / other pin or pad 422 to isolation unit 412, and has a stuck-1 fault in the signal path between test bit 606 and pin or pad 438.

[0094] The result of isolation test 1 failing, then isolation test 2 failing, then isolation test 3 failing, and then isolation test 4 failing is that isolation unit 412 is missing or has a stuck-1 fault on the path from pin or pad 422 / other pin or pad 422 to isolation unit 412, and has a stuck-1 fault in the signal path between test bit 606 and pin or pad 438 and between buffer 624 and circuit 634.

[0095] like Figures 6-8 As illustrated, a combination of one or more isolation tests in isolation tests 1-8 advantageously allows for the detection of missing isolation units, incorrectly connected isolation units, and locations of faults stuck at 1 in the paths before or after the isolation unit and on the enabled path of the isolation unit.

[0096] In some embodiments, the test coverage obtained by one or more isolation tests among isolation tests 1-8 is greater than that of conventional test methods that rely solely on ATPG modes. For example, when circuit 634 corresponds to test controller 404, ATPG modes may not detect a stuck-at-1 fault in the path from OR gate 628 to test controller 404 (because the signal SEN...). 404 (Forced high by TESTBIT3 to prevent test controller 404 from being reset during operation in ATPG mode). In some embodiments, this coverage is achieved, for example, by performing isolation test 4.

[0097] In some embodiments, the ability to detect a stuck-in-1 fault after isolation unit 412 can prevent problems in the field. For example, in some embodiments, such as when circuit 634 corresponds to test controller 404, the second input of AND gate 630 may correspond to a JTAG reset pin. The JTAG reset pin may be forced to 0, for example, during the execution of functional tests (such as low-power enter / exit and standby modes), to keep test controller 404 in reset mode. If an undetected stuck-in-1 fault still remains in the path from OR gate 628 to test controller 404, pulling the JTAG reset pin high in the field may cause the test controller to exit reset mode during functional modes, which could lead to a fault. For example, the isolation test 4 performed may advantageously detect such a stuck-in-1 fault.

[0098] In some embodiments, the signal PORrst This can correspond to the normal power supply signal of an oscillator, PLL, NVM, or OTP. In some such embodiments, since the oscillator, PLL, NVM, or OTP may be operational during testing, the signal POR... rst It can be forced high during testing (cancel the effect). In some embodiments, the test circuit 600 advantageously allows the detection of a stuck-at-1 fault in the normal power supply signal (which can prevent one or more circuits from resetting when exiting standby / low power mode), which can advantageously prevent problems in the field.

[0099] In some embodiments, the test circuit 600 advantageously allows the determination of the location of a stuck-in (e.g., before or after an isolation cell and also on the enable pin of the isolation cell), which can advantageously allow IC designers to address weaknesses in IC layout based on the location of more frequently detected stuck-in failures.

[0100] In some embodiments, the test circuit 600 can advantageously detect missing or incorrectly connected isolation cells during IC testing. Such coverage may not be achievable using the ATPG mode alone.

[0101] In some embodiments, when the test controller 404 is in reset mode (or disabled), the test circuit 600 and associated isolation tests (e.g., Figure 7 and Figure 8 (As shown in the diagram).

[0102] In some embodiments, one or more isolation tests (e.g., such as...) Figure 7 and Figure 8 The test (as shown) can be performed by a conventional automated test equipment (ATE). In some embodiments, the ATE can (e.g., using log files, signals, images coupled to the screen of the ATE, digital flags, or any other conventional mechanism) report the results of each isolation test (e.g., whether a particular isolation test passed or failed), whether a particular isolation unit exists and is correctly connected, exists but is incorrectly connected, or is missing, whether a stuck-at-1 fault was detected, and / or the location of the detected stuck-at-1 fault.

[0103] In some embodiments, test circuit 600 can advantageously assist in detecting missing or erroneously connected isolation cells during the IC design and simulation phases. For example, in some embodiments, circuit design software tools (e.g., running in a computer with a processor coupled to memory) can be used to incorporate test circuit 403 into the IC design, which can result in one or more embodiments of isolation testing (e.g., as...) Figure 7 and Figure 8(As shown in the image) It runs during circuit simulation and may generate indications of the presence, absence, or incorrect connection of isolation cells.

[0104] Although Figures 6-8 The diagram illustrates a circuit and method for testing an isolation unit (e.g., 412) from a powered domain (e.g., ULP) to a non-powered domain (e.g., the operating domain), but it is understood that similar circuits and methods can be used to test isolation units (e.g., such as isolation units 406, 408, 410) from a non-powered domain to a powered domain.

[0105] Figure 9 An isolated insertion and simulation process 900 according to an embodiment of the present invention is illustrated. In some embodiments, method 900 can be performed, for example using a conventional computer and conventional circuit design software tools, such as those from Synopsys, Cadence, and Mentor Graphics.

[0106] During step 902, register transfer level (RTL) code is generated. For example, Verilog or VHDL can be used to generate the RTL. In one embodiment, isolation unit enable logic (e.g., iso_en) is added to the RTL. 412 ) and test logic (e.g., components 602, 604, 606, 608, 610, 612, 614, 616, 618, 620) without adding isolation units (e.g., 412).

[0107] During step 904, digital simulations (such as RTL simulations and / or gate-level simulations (GLS)) can be performed without information from a Uniform Power Format (UPF) file. UPF files typically include information about the power states and supply networks for different power domains of the IC. Because there is no power supply information for the different power domains, and because the circuit is typically initialized upon power-up during digital simulation, the digital simulation may pass even without isolation.

[0108] During step 906, a UPF file is generated. The UPF file provides the name of the signal to be inserted into the isolation unit (e.g., POR). rst ).

[0109] During step 908, information from the UPF file can be used to perform a digital simulation (e.g., RTL).

[0110] During step 910, a netlist is generated based on the RTL code using a synthesis tool. The netlist includes the desired isolation cells, which are automatically inserted by the synthesis tool based on RTL and UPF.

[0111] During step 912, netlist simulation (e.g., GLS) is performed using information from the UPF file.

[0112] During step 914, analog and mixed-signal simulations are performed using information from the UPF file. During step 616, full-chip simulation circuit simulator (spice) simulations are performed for entering and exiting low-power and ultra-low-power modes.

[0113] UPF-based digital simulations (e.g., during steps 908, 912, and 914) force the signal to an unpowered domain in an uncertain state "X". Therefore, UPF-based simulations fail when there is a missing isolation unit from the unpowered domain to the powered domain, or if the isolation unit is incorrectly connected (e.g., controlled by an error signal). Similarly, UPF-based simulations may fail when there is a missing isolation unit on a critical signal (such as POR from the powered domain to the unpowered domain), as the isolation unit might reset the unpowered domain upon power-up (low-power exit / standby exit), or if the isolation unit is incorrectly connected (e.g., controlled by an error signal). However, simulations typically do not provide additional information and manual debugging may be required to determine the cause of the simulation failure (e.g., identifying which isolation unit is missing or incorrectly connected).

[0114] In some embodiments, simulating one or more of the isolation tests 1-8 during steps 912, 914 and / or 916 can advantageously result in the detection of isolation units with missing or incorrect connections, and the identification of isolation units with missing or incorrect connections.

[0115] Some embodiments offer advantages such as the ability to automatically add isolation cells to an IC design using synthesis tools, while ensuring that the isolation cells are present and correctly connected. In some embodiments, compared to performing manual debugging, using one or more isolation tests, such as isolation tests 1-8, advantageously and more quickly verifies the presence and correct connection of isolation cells, and identifies missing or incorrectly connected isolation cells.

[0116] Additional advantages of some embodiments include the ability to avoid human error associated with the manual placement of isolation units (e.g., in RTL) by relying on the automatic placement of isolation units.

[0117] Although Figures 6-9 An isolation unit that provides isolation from the ULP domain to the operating domain has been described, but similar implementations (circuit and test modes) can be implemented for isolation units that provide isolation from the ULP domain to the LP domain, from the operating domain to the LP domain, from the operating domain to the ULP domain, from the LP domain to the operating domain, and from the LP domain to the ULP domain.

[0118] In some embodiments, the synthesis tool may reroute signals for optimization purposes (e.g., POR). rst The path of the signal POR. For example, in some embodiments, the synthesis tool can identify the path of the signal POR. rst Instead of direct routing to the operational domain, the signal is rerouted via the LP domain. In this case, the synthesis tool may not place the isolation unit in the domain spanning the ULP domain to the LP domain, or in the domain spanning the LP domain and the operational domain. This missing isolation unit may not be reported during simulation (e.g., during steps 904, 912, 914, or 916) because the signal is crossing from the powered domain to the unpowered domain.

[0119] In some embodiments, redundant signal paths (e.g., paths covering all possible domain traversals) are specified during RTL and UPF. By specifying redundant paths, even if the synthesis tool reroutes the signal, this rerouting will have a specified isolation unit. For example... Figure 10 A schematic diagram of a test circuit 1000 according to an embodiment of the present invention is shown. Test circuit 403 can be implemented as test circuit 1000. Test circuit 1000 operates in a similar manner to test circuit 600. However, test circuit 1000 includes additional MUX 618' and 620' for testing isolation unit 414, additional MUX 618" and 620" for testing isolation unit 416, and AND gate 1028.

[0120] In some embodiments, MUX 618', 618”, 620', 620” and the signal Iso_en 414 and iso_en 416 It is specified in the RTL (e.g., during step 902), for example to allow the synthesis tool (e.g., during step 910) to automatically insert isolation cells (e.g., 414, 416).

[0121] Isolation units 414 and 416 can be connected with Figures 6-8 The test was conducted in a manner similar to that shown for isolation unit 412.

[0122] like Figure 10 As can be seen, the signal POR rst OR gate 628 can be reached via a signal path that crosses from the ULP domain to the operating domain using isolation 412, or via a signal path that crosses from the ULP domain to the LP domain using isolation unit 414, and then crosses from the LP domain to the operating domain using isolation unit 416.

[0123] If the synthesis tool (e.g., during step 910) routes the signal POR via isolation unit 412 rstTo optimize the design, the synthesis tool can omit the implementation of the paths through isolation cells 414 and 416, as well as related circuitry (e.g., 618', 618”, 620', 620”) and AND gate 1028. In this scenario, test circuit 1000 may become identical to test circuit 600.

[0124] If the synthesis tool (e.g., during step 910) routes the signal POR via isolation units 414 and 416 rst To optimize the design, the synthesis tool can omit the implementation path through isolation cell 412 and associated circuitry (e.g., 618, 620) and AND gate 1028. In this scenario, isolation cells 414 and 416 are automatically inserted by the synthesis tool based on RTL and UPF files (e.g., during step 910), and such isolation cells can be tested, for example, in a manner similar to that described with respect to isolation cell 412.

[0125] If both paths are implemented using synthesis tools, then test circuit 1000 can be implemented as follows: Figure 10 As shown, IC 400 can operate normally because the redundant path is ANDed by AND gate 1028. In this case, the testing of isolation units 412, 414, and 416 can be performed with respect to... Figures 6-8 The isolation unit 412 described herein can be performed in a similar manner. For example, testing of the isolation unit 412 can be performed simultaneously with checking the pins or pads 438 and related information. Figures 6-8 The methods described are similar to those described (isolation tests 1, 2, 3) and can be performed simultaneously. The combined test of isolation units 414 and 416 can be performed while checking pins or pads 432 and 442 respectively. Figures 6-8 The isolation test is performed in a manner similar to that described for isolation unit 412 (isolation tests 1, 2, 3). Isolation test 4 can then be performed by forcing TESTBIT3 to "0" and observing the output on the pin or pad 440.

[0126] Some embodiments offer the advantage that, by adding redundancy to critical paths that can benefit from isolation, some embodiments advantageously allow synthesis tools to perform circuit optimizations without missing isolation units on critical paths leading to unpowered domains.

[0127] Other advantages of some embodiments include the ability to perform tests during digital simulation using an independent test mode to detect missing or faulty connections in isolation units on critical paths for signals such as enable, reset, and power-on signals. In some embodiments, the independent test mode advantageously allows testing of buffers in the paths of isolation units (e.g., for a stuck-at-1 fault) during periods when coverage of the functional mode is unavailable (such as periods characterized by low temperatures, e.g., -30°C), because cold-state testing can be performed in an EWS (Electronic Wafer Classification) where external SMPS components may be unavailable.

[0128] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entirety of the specification and the claims filed herein.

[0129] Example 1. An electronic circuit comprising: a first power domain, the first power domain including: a first isolation unit, the first isolation unit including a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit; a first selection circuit having a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit; and a second selection circuit having a first input configured to receive a second functional signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit; and a second power domain, the second power domain including: a first circuit having an input coupled to the signal output of the first isolation unit; and a first observation element coupled to a first intermediate node, the first intermediate node being coupled to the first isolation unit. The signal output of the isolation unit and the input of the first circuit are coupled together, as well as the output of the first circuit via a second observation element; wherein the electronic circuit includes multiple functional modes and a first test mode; wherein, for each of the multiple functional modes, a first power domain is configured to be turned on when a second power domain is turned on, and the second power domain is configured to be turned off in at least one functional mode in which the first power domain is configured to be turned on; wherein, when the electronic circuit is in the first test mode, a first selection circuit is configured to provide a first test signal to the control input of the first isolation unit, and a second selection circuit is configured to provide a second test signal to the signal input of the first isolation unit; wherein, when the electronic circuit is in any of the multiple functional modes, the first selection circuit is configured to provide a first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide a second functional signal to the signal input of the first isolation unit.

[0130] Example 2. The electronic circuit of Example 1, wherein the second power domain further includes an OR gate having a first input, a second input, and an output, the first input being coupled to a signal output of a first isolation unit and a first observation element, the second input being configured to receive a third test signal from the first power domain, and the output being coupled to an input of the first circuit, wherein the third test signal is configured to be low when the electronic circuit is in any of a plurality of functional modes.

[0131] Example 3. An electronic circuit of one of Examples 1 or 2, wherein a third test signal is configured to cross from the first power domain to the second power domain without passing through an isolation unit.

[0132] Example 4. An electronic circuit of one of Examples 1 to 3, wherein the second power domain further includes an AND gate having a first input, a second input, and an output, the first input being coupled to a signal output of a first isolation unit and a first observation element, the second input being configured to receive a third test signal, and the output being coupled to an input of a first circuit, wherein the third test signal is configured to be high when the electronic circuit is in any of a plurality of functional modes.

[0133] Example 5. An electronic circuit of one of Examples 1 to 4, wherein a first selection circuit includes a third input configured to receive a third test signal, wherein the electronic circuit includes a second test mode, and wherein, when the electronic circuit is in the second test mode, the first selection circuit is configured to provide the third test signal to a control input of a first isolation unit.

[0134] Example 6. An electronic circuit of one of Examples 1 to 5, wherein the first selection circuit includes: a first multiplexer having a first input coupled to a first input of the first selection circuit and a second input coupled to a second input of the first selection circuit; and a second multiplexer having a first input coupled to an output of the first multiplexer, a second input coupled to a third input of the first multiplexer, and an output coupled to an output of the first selection circuit.

[0135] Example 7. An electronic circuit of one of Examples 1 to 6, wherein the first circuit includes a test controller configured to control a third test signal when the electronic circuit is in a second test mode.

[0136] Example 8. An electronic circuit of one of Examples 1 to 7, wherein the second selection circuit includes a multiplexer having a first input coupled to a first input of the second selection circuit, a second input coupled to a second input of the second selection circuit, and an output coupled to an output of the second selection circuit.

[0137] Example 9. An electronic circuit of one of Examples 1 to 8, wherein the first power domain further includes a third selection circuit having a first input configured to receive a second function signal, a second input configured to receive a third test signal, and an output configured to control the second test signal, wherein the third selection circuit is configured to provide the second function signal to the second input of the second selection circuit when the electronic circuit is in any of a plurality of function modes.

[0138] Example 10. An electronic circuit of one of Examples 1 to 9, wherein the first power domain further includes: a first test bit configured to control a first selection circuit; a second test bit configured to control a second selection circuit; and a third test bit configured to provide a second test signal.

[0139] Example 11. An electronic circuit of one of Examples 1 through 10, wherein the first, second, and third test bits can be programmed via a Joint Test Action Group (JTAG) interface.

[0140] Example 12. An electronic circuit of one of Examples 1 to 11, further comprising a plurality of pins or pads, wherein the first and second observation elements are the first and second pins or pads of the plurality of pins or pads, respectively.

[0141] Example 13. An electronic circuit of one of Examples 1 to 12, wherein a first power domain includes a third pin or pad, wherein the third pin or pad is configured to control a second test signal when the electronic circuit is in a first test mode.

[0142] Example 14. An electronic circuit of one of Examples 1 to 13, wherein a first isolation unit includes an AND gate having a first input, a second input, and an output, the first input being coupled to a signal input of the first isolation unit, the second input being coupled to a control input of the first isolation unit, and the output being coupled to a signal output of the first isolation unit.

[0143] Example 15. An electronic circuit of one of Examples 1 to 14, wherein the first power domain includes a power-on reset (POR) circuit configured to generate a second functional signal.

[0144] Example 16. An electronic circuit according to one of Examples 1 to 15 further includes a third power domain comprising a second isolation unit, wherein, for each of the functional modes, the first power domain is configured to be on when the third power domain is on, the third power domain is configured to be off in at least one functional mode in which the first power domain is configured to be on, the third power domain is configured to be on when the second power domain is on, and the second power domain is configured to be off in at least one functional mode in which the third power domain is configured to be on; wherein the second power domain includes an AND gate having a first input, a second input, and an output, the first input being coupled to a signal output of the first isolation unit. The second input is coupled to the signal output of the second isolation unit, and the output is coupled to the input of the first circuit; and wherein the first power domain includes: a third isolation unit having a signal input coupled to the output of the second selection circuit and a signal output coupled to the signal input of the second isolation unit; a third selection circuit having a first input configured to receive a third function signal, a second input configured to receive a third test signal, and an output coupled to the control input of the third isolation unit; and a fourth selection circuit having a first input configured to receive a fourth function signal, a second input configured to receive a fourth test signal, and an output coupled to the control input of the second isolation unit.

[0145] Example 17. An integrated circuit, comprising: a first power domain including: a power-on reset (POR) circuit configured to generate a POR signal, wherein the POR circuit is configured to activate the POR signal when a first supply voltage of the first power domain reaches a predetermined threshold; a first isolation unit including a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit; a first selection circuit having a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit; and a second selection circuit having a first input configured to receive a POR signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit; and a second power domain including: a test controller having an input coupled to the signal output of the first isolation unit, a first pin or pad coupled to the first isolation unit. An intermediate node is provided, the first intermediate node being coupled between the signal output of the first isolation unit and the input of the test controller, and a second pin or pad being coupled to the output of the test controller; wherein the integrated circuit includes multiple functional modes and a first test mode; wherein, for each of the multiple functional modes, the first power domain is configured to be turned on when the second power domain is turned on, and the second power domain is configured to be turned off in at least one functional mode in which the first power domain is configured to be turned on; wherein, when the integrated circuit is in the first test mode, the first selection circuit is configured to provide a first test signal to the control input of the first isolation unit, and the second selection circuit is configured to provide a second test signal to the signal input of the first isolation unit; wherein, when the integrated circuit is in any of the multiple functional modes, the first selection circuit is configured to provide a first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide a POR signal to the signal input of the first isolation unit.

[0146] Example 18. An integrated circuit of Example 17, wherein the second power domain further includes an OR gate having a first input, a second input, and an output, the first input being coupled to a signal output of a first isolation unit and a first pin or pad, the second input being configured to receive a third test signal, and the output being coupled to an input of a test controller, wherein the third test signal is configured to be low when the integrated circuit is in any of a plurality of functional modes.

[0147] Example 19. An integrated circuit of one of Examples 17 or 18, wherein the first power domain further includes: a first test bit configured to control a first selection circuit; a second test bit configured to control a second selection circuit; a third test bit configured to provide a second test signal; and a fourth test bit configured to provide the third test signal to a second input of an OR gate without passing through an isolation unit.

[0148] Example 20. An integrated circuit of one of Examples 17 to 19, wherein the first power domain is a normally open power domain.

[0149] Example 21. An integrated circuit of one of Examples 17 to 20, wherein the POR circuit is the only POR circuit of the integrated circuit.

[0150] Example 22. A method for testing an integrated circuit having multiple power domains, multiple functional modes, and a first test mode, the method comprising, during the first test mode: causing a first selection circuit having an output having a first input for receiving a first functional signal, a second input for receiving a first test signal, and a control input coupled to a first isolation unit to deliver a first test signal to the control input of the first isolation unit; causing a second selection circuit having an output having a first input for receiving a second functional signal, a second input for receiving a second test signal, and a signal input coupled to the first isolation unit to deliver a second test signal to the signal input of the first isolation unit, wherein the first power domain among the multiple power domains includes The system includes first and second selection circuits and a first isolation unit; setting a second test signal to logic 1; enabling a first test signal to activate the first isolation unit; after setting the second test signal to logic 1 and enabling the first test signal, measuring a first voltage at a first pin or pad coupled to the signal output of the first isolation unit, wherein a second power domain among a plurality of power domains includes the first pin or pad, wherein, for each of a plurality of functional modes, the first power domain is enabled when the second power domain is enabled, and the second power domain is disabled in at least one functional mode in which the first power domain is enabled; setting the second test signal to logic 0; and deactivating the first test signal to disable the first isolation unit. After setting the second test signal to logic 0 and deactivating the first test signal, measure the second voltage at the first pin or pad; set the first test bit of the first power domain to logic 0, wherein the first test bit is coupled to the first input of an OR gate, the OR gate having a second input and an output, the second input being coupled to the signal output of the first isolation unit and the first pin or pad, and the output being coupled to the input of the test controller, wherein the second power domain includes the OR gate and the test controller; after setting the second test signal to logic 0, deactivating the first test signal, and setting the first test bit to logic 0, measure the third voltage at the second pin or pad coupled to the output of the test controller, wherein the second power domain includes the first... Two pins or pads; when the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is in reset mode, a first indication is generated, indicating that the first path of the signal input coupled to the first isolation unit does not have a stuck-at-1 fault and the second path of the signal output coupled to the first isolation unit does not have a stuck-at-1 fault; when the first voltage corresponds to logic 0 and the second voltage corresponds to logic 1, a second indication is generated, indicating that the first path has a stuck-at-1 fault; and when the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is not in reset mode, a third indication is generated, indicating that the second path has a stuck-at-1 fault.

[0151] Example 23. The method of Example 22 further includes, during a first test mode: when the first voltage corresponds to logic 1; enabling a third test signal to activate the second isolation unit; after enabling the third test signal and setting the second test signal to logic 1, measuring a fourth voltage at the first pin or pad; when the fourth voltage corresponds to logic 0, generating an indication that the first isolation unit is incorrectly connected.

[0152] Example 24. A method from one of Examples 22 or 23, wherein generating the first, second, or third instruction includes generating log files using an Automated Test Equipment (ATE).

[0153] While the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. By referring to the description, those skilled in the art will clearly understand various modifications and combinations of the illustrative embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An electronic circuit, comprising: A first power domain, the first power domain comprising: A first isolation unit includes a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit. A first selection circuit has a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit. The second selection circuit has a first input configured to receive a second functional signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit; The second power domain includes: A first circuit has an input coupled to the signal output of the first isolation unit. A first observation element is coupled to a first intermediate node, the first intermediate node being coupled between the signal output of the first isolation unit and the input of the first circuit. A second observation element is coupled to the output of the first circuit; The electronic circuit described therein includes multiple functional modes and a first test mode; Wherein, for each of the plurality of functional modes, the first power domain is configured to be turned on when the second power domain is turned on, and the second power domain is configured to be turned off in at least one functional mode in which the first power domain is configured to be turned on; Wherein, when the electronic circuit is in the first test mode, the first selection circuit is configured to provide the first test signal to the control input of the first isolation unit, and the second selection circuit is configured to provide the second test signal to the signal input of the first isolation unit; and When the electronic circuit is in any of the plurality of functional modes, the first selection circuit is configured to provide the first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide the second functional signal to the signal input of the first isolation unit.

2. The electronic circuit of claim 1, wherein the second power domain further comprises an OR gate having a first input, a second input, and an output, the first input being coupled to the signal output of the first isolation unit and the first observation element, the second input being configured to receive a third test signal from the first power domain, and the output being coupled to the input of the first circuit, wherein, When the electronic circuit is in any of the multiple functional modes, the third test signal is configured to be low.

3. The electronic circuit of claim 2, wherein the third test signal is configured to cross from the first power domain to the second power domain without passing through an isolation unit.

4. The electronic circuit of claim 1, wherein the second power domain further comprises an AND gate having a first input, a second input, and an output, the first input being coupled to the signal output of the first isolation unit and the first observation element, the second input being configured to receive a third test signal, and the output being coupled to the input of the first circuit, wherein, When the electronic circuit is in any of the plurality of functional modes, the third test signal is configured to be high.

5. The electronic circuit of claim 1, wherein the first selection circuit includes a third input configured to receive a third test signal, wherein the electronic circuit includes a second test mode, and wherein, When the electronic circuit is in the second test mode, the first selection circuit is configured to provide the third test signal to the control input of the first isolation unit.

6. The electronic circuit according to claim 5, wherein the first selection circuit comprises: A first multiplexer has a first input coupled to the first input of the first selection circuit and a second input coupled to the second input of the first selection circuit; as well as The second multiplexer has a first input coupled to the output of the first multiplexer, a second input coupled to a third input of the first multiplexer, and an output coupled to the output of the first selection circuit.

7. The electronic circuit of claim 5, wherein the first circuit includes a test controller configured to control the third test signal when the electronic circuit is in the second test mode.

8. The electronic circuit of claim 1, wherein the second selection circuit includes a multiplexer having a first input coupled to the first input of the second selection circuit, a second input coupled to the second input of the second selection circuit, and an output coupled to the output of the second selection circuit.

9. The electronic circuit of claim 1, wherein the first power domain further comprises a third selection circuit, the third selection circuit having a first input configured to receive the second functional signal, a second input configured to receive a third test signal, and an output configured to control the second test signal, wherein, When the electronic circuit is in any of the plurality of functional modes, the third selection circuit is configured to provide the second functional signal to the second input of the second selection circuit.

10. The electronic circuit according to claim 1, wherein the first power domain further comprises: The first test bit is configured to control the first selection circuit; The second test bit is configured to control the second selection circuit; as well as The third test bit is configured to provide the second test signal.

11. The electronic circuit of claim 10, wherein the first test bit, the second test bit, and the third test bit are programmable via a Joint Test Action Group (JTAG) interface.

12. The electronic circuit according to claim 1 further includes a plurality of pins or pads, wherein the first observation element and the second observation element are respectively the first pin or pad and the second pin or pad among the plurality of pins or pads.

13. The electronic circuit of claim 12, wherein the first power domain includes a third pin or pad, wherein, When the electronic circuit is in the first test mode, the third pin or pad is configured to control the second test signal.

14. The electronic circuit of claim 1, wherein the first isolation unit comprises an AND gate having a first input, a second input, and an output, the first input being coupled to the signal input of the first isolation unit, the second input being coupled to the control input of the first isolation unit, and the output being coupled to the signal output of the first isolation unit.

15. The electronic circuit of claim 1, wherein the first power domain includes a power-on reset (POR) circuit configured to generate the second functional signal.

16. The electronic circuit according to claim 1, further comprising a third power domain, the third power domain including a second isolation unit, wherein, For each of the functional modes, the first power domain is configured to be enabled when the third power domain is enabled, the third power domain is configured to be disabled in at least one functional mode in which the first power domain is configured to be enabled, the third power domain is configured to be enabled when the second power domain is enabled, and the second power domain is configured to be disabled in at least one functional mode in which the third power domain is configured to be enabled. The second power domain includes an AND gate having a first input, a second input, and an output, wherein the first input is coupled to the signal output of the first isolation unit, the second input is coupled to the signal output of the second isolation unit, and the output is coupled to the input of the first circuit; as well as The first power domain includes: The third isolation unit has a signal input coupled to the output of the second selection circuit and a signal output coupled to the signal input of the second isolation unit. The third selection circuit has a first input configured to receive a third function signal, a second input configured to receive a third test signal, and an output coupled to a control input of the third isolation unit. The fourth selection circuit has a first input configured to receive a fourth function signal, a second input configured to receive a fourth test signal, and an output coupled to a control input of the second isolation unit.

17. An integrated circuit, comprising: A first power domain, the first power domain comprising: A power-on reset (POR) circuit is configured to generate a POR signal, wherein the POR circuit is configured to activate the POR signal when the first power supply voltage of the first power domain reaches a predetermined threshold. A first isolation unit includes a signal input, a signal output, and a control input, wherein the first isolation unit is configured to be enabled or disabled based on the control input of the first isolation unit. A first selection circuit has a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation unit. The second selection circuit has a first input configured to receive the POR signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation unit. The second power domain includes: The test controller has an input coupled to the signal output of the first isolation unit. A first pin or pad is coupled to a first intermediate node, which is coupled between the signal output of the first isolation unit and the input of the test controller. The second pin or pad is coupled to the output of the test controller; The integrated circuit mentioned above includes multiple functional modes and a first test mode; Wherein, for each of the plurality of functional modes, the first power domain is configured to be turned on when the second power domain is turned on, and the second power domain is configured to be turned off in at least one functional mode in which the first power domain is configured to be turned on; Wherein, when the integrated circuit is in the first test mode, the first selection circuit is configured to provide the first test signal to the control input of the first isolation unit, and the second selection circuit is configured to provide the second test signal to the signal input of the first isolation unit; and When the integrated circuit is in any of the plurality of functional modes, the first selection circuit is configured to provide the first functional signal to the control input of the first isolation unit, and the second selection circuit is configured to provide the POR signal to the signal input of the first isolation unit.

18. The integrated circuit of claim 17, wherein the second power domain further comprises an OR gate having a first input, a second input, and an output, the first input being coupled to the signal output of the first isolation unit and the first pin or pad, the second input being configured to receive a third test signal, and the output being coupled to the input of the test controller, wherein, When the integrated circuit is in any of the plurality of functional modes, the third test signal is configured to be low.

19. The integrated circuit of claim 18, wherein the first power domain further comprises: The first test bit is configured to control the first selection circuit; The second test bit is configured to control the second selection circuit; The third test bit is configured to provide the second test signal; as well as The fourth test bit is configured to provide the third test signal to the second input of the OR gate without passing through the isolation unit.

20. The integrated circuit of claim 17, wherein the first power domain is a normally open power domain.

21. The integrated circuit of claim 17, wherein the POR circuit is the only POR circuit of the integrated circuit.

22. A method for testing an integrated circuit having multiple power domains, multiple functional modes, and a first test mode, the method comprising, during the first test mode: A first selection circuit having a first input for receiving a first functional signal, a second input for receiving a first test signal, and an output coupled to a control input of a first isolation unit delivers the first test signal to the control input of the first isolation unit; A second selection circuit having a first input for receiving a second functional signal, a second input for receiving a second test signal, and an output coupled to a signal input of the first isolation unit delivers the second test signal to the signal input of the first isolation unit, wherein the first power domain of the plurality of power domains includes the first selection circuit, the second selection circuit, and the first isolation unit; Set the second test signal to logic 1; Enable the first test signal to activate the first isolation unit; After setting the second test signal to logic 1 and enabling the first test signal, a first voltage is measured at the first pin or pad of the signal output coupled to the first isolation unit, wherein the second power domain of the plurality of power domains includes the first pin or pad, wherein, for each of the plurality of functional modes, the first power domain is enabled when the second power domain is enabled, and the second power domain is disabled in at least one functional mode in which the first power domain is enabled. Set the second test signal to logic 0; The first test signal is deactivated to disable the first isolation unit; After setting the second test signal to logic 0 and deactivating the first test signal, measure the second voltage at the first pin or pad. The first test bit of the first power domain is set to logic 0, wherein the first test bit is coupled to the first input of an OR gate, the OR gate having a second input and an output, the second input being coupled to the signal output of the first isolation unit and the first pin or pad, and the output being coupled to the input of a test controller, wherein the second power domain includes the OR gate and the test controller; After setting the second test signal to logic 0, deactivating the first test signal, and setting the first test bit to logic 0, a third voltage is measured at the second pin or pad coupled to the output of the test controller, wherein the second power domain includes the second pin or pad; When the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is in reset mode, a first indication is generated. The first indication indicates that the first path of the signal input coupled to the first isolation unit does not have a stuck-on-1 fault, and the second path of the signal output coupled to the first isolation unit does not have a stuck-on-1 fault. When the first voltage corresponds to logic 0 and the second voltage corresponds to logic 1, a second indication is generated indicating that the first path has a fault stuck at 1; and When the first voltage corresponds to logic 0, the second voltage corresponds to logic 0, and the third voltage indicates that the test controller is not in reset mode, a third indication is generated indicating that the second path has a stuck-at-1 fault.

23. The method of claim 22, further comprising: During the first test mode: When the first voltage corresponds to logic 1; Enable the third test signal to activate the second isolation unit; After activating the third test signal and setting the second test signal to logic 1, measure the fourth voltage at the first pin or pad. as well as When the fourth voltage corresponds to logic 0, an indication is generated indicating that the first isolation unit is incorrectly connected.

24. The method of claim 22, wherein generating the first, second, or third instruction comprises generating a log file using an automated test equipment (ATE).

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