Apparatus and method for pipeline control

Abstract

An apparatus and method for pipeline control are provided. The apparatus can include a preload predictor, an arithmetic logic unit, and a data buffer. The preload predictor is configured to determine whether a load instruction satisfies at least one specific condition to generate a preload determination result. The arithmetic logic unit is configured to perform arithmetic logic operations, and the data buffer is configured to provide data to the arithmetic logic unit. In particular, when the preload determination result indicates that the load instruction satisfies the at least one specific condition, the data buffer extracts preload data from a cache based on information carried by the load instruction and stores the preload data in the data buffer, where the preload data is data requested by a subsequent load instruction.

Description

Technical Field

[0001] This invention relates to an instruction pipeline, and more particularly to an apparatus and method for pipeline control. Background Technology

[0002] The memory architecture in electronic devices can contain multiple levels, such as registers, caches, main memory, and auxiliary memory. Since the memory level closest to the central processing unit has the fastest access speed but the smallest storage space, the access speed from fastest to slowest is registers, caches, main memory, and auxiliary memory, while the storage space from largest to smallest is auxiliary memory, main memory, cache, and registers.

[0003] The outermost level has the slowest access speed but the largest storage space.

[0004] In a pipelined instruction architecture, the CPU can load data from the cache into registers via load instructions for rapid retrieval by subsequent instructions. However, the data in the cache is only ready for use in the registers several cycles after executing the load instruction. This causes delays in the execution of some instructions, resulting in "bubbles" in the pipeline scheduling and reducing the CPU's performance in a pipelined instruction architecture. In particular, modern CPUs utilize deeper pipeline stages to achieve faster clock synchronization frequencies, and the aforementioned problems are especially severe in architectures with deeper pipeline stages.

[0005] Therefore, a novel method and apparatus are needed to optimize the performance of the instruction pipeline without or with relatively little to no side effects. Summary of the Invention

[0006] One of the objectives of this invention is to provide an apparatus and method for pipeline control to solve the problems in related technologies.

[0007] At least one embodiment of the present invention provides an apparatus for pipeline control. The apparatus may include a preload predictor, an arithmetic logic unit (ALU), and a data buffer, wherein the data buffer is coupled to the preload predictor and the ALU. The preload predictor determines whether a load instruction meets at least one specific condition to generate a preload determination result. The ALU performs arithmetic logic operations, and the data buffer provides data to the ALU, wherein the ALU retrieves data from the data buffer faster than it retrieves data from a cache. Specifically, when the preload determination result indicates that a load instruction meets at least one specific condition, the data buffer fetches preload data from the cache based on information carried in the load instruction and stores the preload data in the data buffer, wherein the preload data is the data requested by a subsequent load instruction.

[0008] At least one embodiment of the present invention provides a method for pipeline control. The method may include: using a preload predictor to determine whether a load instruction meets at least one specific condition, to generate a preload determination result; when the preload determination result indicates that the load instruction meets at least one specific condition, a data buffer retrieves preload data from a cache based on information carried by the load instruction and stores the preload data in the data buffer, wherein the preload data is data requested by subsequent load instructions; and using the data buffer to provide the preload data to an arithmetic logic unit for arithmetic logic operations, wherein the arithmetic logic unit retrieves data from the data buffer faster than it retrieves data from the cache.

[0009] The apparatus and method provided by embodiments of the present invention can effectively reduce latency caused by load-use instruction pairs based on spatial and temporal locality. In particular, embodiments of the present invention do not significantly increase additional costs, thus the present invention can solve related technical problems without or with relatively few side effects. Attached Figure Description

[0010] Specific embodiments of the inventive concept will now be described by way of example, with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of an apparatus operating under an instruction pipeline architecture according to an embodiment of the present invention is shown.

[0012] Figure 2A schematic diagram of loading and using a data buffer according to an embodiment of the present invention is shown.

[0013] Figure 3 A schematic diagram of loading and using a data buffer according to an embodiment of the present invention is shown.

[0014] Figure 4 A schematic diagram of an apparatus operating under an instruction pipeline architecture according to an embodiment of the present invention is shown.

[0015] Figure 5 The loading instructions according to an embodiment of the present invention are shown in Figure 4 A schematic diagram showing some details of the instruction pipeline architecture.

[0016] Figure 6 A flowchart of a method for assembly line control according to an embodiment of the present invention is shown.

[0017] Figure 7 A flowchart illustrating a preload request executed according to an embodiment of the present invention is shown.

[0018] Figure 8 A flowchart of a load instruction executed according to an embodiment of the present invention is shown. Detailed Implementation

[0019] A cache is a type of memory that enables fast access to store recently used or frequently accessed data or instructions. To meet the need for fast access, a cache can be composed of static random access memory (SRAM). However, SRAM still needs to latch the access address in the cycle it receives and cannot return the corresponding data until the next cycle.

[0020] Figure 1This is a schematic diagram of an apparatus 100 (e.g., a central processing unit) operating under an instruction pipeline architecture according to an embodiment of the present invention. In this embodiment, the instruction pipeline architecture can be a five-stage pipeline, including an instruction fetch (IF) stage, an instruction decode (ID) stage, an instruction execution stage, a memory access stage, and a data write-back stage, wherein the above stages are respectively labeled "IF", "ID", "EXE", "MEM", and "WB" in the figure for simplicity. The apparatus 100 first obtains an instruction in the instruction fetch stage through the instruction fetch component 110 (labeled "instruction fetch" for simplicity), and then enters the instruction decode stage. In the instruction decode stage, the apparatus can use the instruction decoder 120 (labeled "instruction decode" for simplicity) to decode the instruction to obtain the information carried by the instruction, such as instruction type, base address, offset, etc., and then enter the instruction execution stage. During the instruction execution phase, if the instruction is a load instruction, the device 100 can use its address generator 130 to generate an access address based on the base address and offset value carried in the instruction, and then proceed to the memory access phase. If the instruction is an arithmetic instruction, the device can use its arithmetic logic unit (ALU) 140 to perform arithmetic logic operations, such as those corresponding to arithmetic instructions. During the memory access phase, the device 100 can retrieve the data corresponding to the access address from its load storage unit 150 (especially the cache 151 within the load storage unit 150), and then proceed to the data write-back phase. During the data write-back phase, device 100 can write the retrieved data back to the memory closest to the central processing unit, such as register file 160, for use by subsequent instructions. If cache 151 is not hit (e.g., cache 151 does not store the data requested by the load instruction), device 100 can use its bus interface unit 170 to issue a bus request to retrieve the data requested by the load instruction from external memory (e.g., hard disk drive, solid-state drive, or external auxiliary storage). Figure 1 The bus data shown is shown.

[0021] exist Figure 1In this embodiment, although the load instruction can retrieve data from cache 151 during the memory access phase, if an arithmetic instruction is executed back to back in the pipeline architecture (e.g., the arithmetic instruction immediately follows the load instruction), the arithmetic instruction still needs to wait until the next cycle (e.g., until the load instruction enters the data write-back phase) before it can use the data retrieved from the cache.

[0022] Table 1

[0023]

[0024] Table 1 is an example of an instruction combination, where the instruction in the first row of Table 1 (hereinafter referred to as the first load instruction) loads the data at address [r8] in cache 151 into register r0, the instruction in the second row of Table 1 (hereinafter referred to as the addition instruction) stores the arithmetic result of adding 8 to the value of register r0 in register r5, and the instruction in the third row of Table 1 (hereinafter referred to as the second load instruction) loads the data at address [r9] in flash memory into register r1.

[0025] Table 2

[0026]

[0027] Table 2 shows the scheduling of the three instructions in Table 1 across three cycles in the pipeline architecture. The instruction decoding stage, instruction execution stage, memory access stage, and data write-back stage are labeled "ID", "EXE", "MEM", and "WB" respectively in Table 2 for clarity. In the first cycle, the first load instruction is in the instruction execution stage, while the addition instruction is in the instruction decoding stage. In the second cycle, the first load instruction enters the memory access stage. However, since the data requested by the first load instruction has not yet been retrieved from cache 151, the device 100 delays the entry of the addition instruction into the instruction execution stage, creating a "bubble" between the first load instruction and the addition instruction. In the third cycle, since the first load instruction enters the data write-back stage (indicating that the data in register r0 is ready), the addition instruction can enter the instruction execution stage for related operations, while the second load instruction can enter the instruction decoding stage.

[0028] Since the first load instruction and the addition instruction are a pair of load-use instructions, meaning the addition instruction involves the first load instruction and the first load instruction and the addition instruction are executed back to back, the addition instruction must wait for the data corresponding to the load instruction (such as the data loaded into register r0) before it can enter the instruction execution stage, thus causing a load-use stall, which also affects the overall computational efficiency.

[0029] Figure 2 This is a schematic diagram of a load-use data buffer 200 according to an embodiment of the present invention. In this embodiment, the load-use data buffer 200 provides a data temporary storage space, wherein the data temporary storage space inside the load-use data buffer utilizes flip-flops as storage units to achieve single-cycle access. For example, upon receiving an access address, the load-use data buffer 200 can return the corresponding data in the current cycle for use by subsequent instructions. Based on the above characteristics, the load-use data buffer 200 can be used to remove load-use bubbles generated by the aforementioned load-use instruction pairs (e.g., a first load instruction and an addition instruction executed back-to-back). In this embodiment, the load-use data buffer 200 may include a data storage area and a tag storage area. N sets of data, such as DATA[0], DATA[1], ..., and DATA[N] (N can be a positive integer), can be stored in N entries in the data storage area, and N addresses corresponding to the N sets of data, such as TAG[0], TAG[1], ..., and TAG[N], can be stored in N entries in the tag storage area. Furthermore, the state of each of the N entries in the tag storage area can be determined by its valid bit (VLD) and lock bit (LOCK). For example, when the valid bit of an entry is "1", it indicates that the address stored in this entry and the corresponding data are valid or usable; when the valid bit of this entry is "0", it indicates that the data corresponding to the address stored in this entry is invalid or unusable. Similarly, when the lock bit of an entry is "1", it indicates that the address stored in this entry and the corresponding data are in a locked state (e.g., being updated and therefore not allowed to be used); when the lock bit of this entry is "0", it indicates that the address stored in this entry and the corresponding data are not in a locked state. Specifically, the valid bit VLD[0] and the lock bit LOCK[0] can be used to represent the status of the tag address TAG[0] and the data DATA[0]. The valid bit VLD[1] and the lock bit LOCK[1] can be used to represent the status of the tag address TAG[1] and the data DATA[1]. Similarly, the valid bit VLD[N] and the lock bit LOCK[N] can be used to represent the status of the tag address TAG[N] and the data DATA[N].

[0030] In this embodiment, when the load-use data buffer 200 receives the access address ADDR, the load-use data buffer 200 can compare at least a portion of the access address ADDR with the tag addresses stored in the tag storage area of ​​the load-use data buffer 200 one by one to confirm whether the data requested by the access address ADDR has been stored in the load-use data buffer 200. For example, when each of the N sets of data is 64 bits, the load-use data buffer 200 can compare the 31st to the 3rd bits of the access address ADDR (which can be represented as ADDR[31:3]) with the tag addresses TAG[0], TAG[1], ..., and TAG[N] one by one to generate N comparison results. Additionally, the selection controller 220 within the load-use data buffer 200 can generate a load-use buffer based on these N comparison results (e.g., performing OR logic processing on these N comparison results to generate a valid signal LUB_VALID). If any of these N comparison results indicates a "hit," the valid signal LUB_VALID indicates that the load-use data buffer 200 has a hit (meaning that the data requested by the access address ADDR can be found in the load-use data buffer 200). In particular, when the valid signal LUB_VALID indicates a hit in the load-use data buffer 200, the selection controller 220 can generate a selection signal SEL based on these N comparison results, causing the selection circuitry within the load-use data buffer 200, such as the multiplexer 230, to select the corresponding entry based on the selection signal SEL to output the corresponding data. If all N comparison results are "miss", it means that the data requested by the access address ADDR is not stored in the load-use data buffer 200. The load-use buffer (LUB) controller 210 in the load-use data buffer 200 can obtain cached data from the cache 151 or obtain bus data from the outside through the bus interface unit 170, but the present invention is not limited to this.

[0031] When the access address ADDR retrieves the new data requested by the access address ADDR from the cache 151 or external memory, the LUB controller 210 can store this new data in the data storage area within the load-use data buffer 200. This way, when the load-use data buffer 200 receives the access address ADDR again in the future, it can quickly provide this new data. It should be noted that if the storage space in the load-use data buffer 200 is full, the LUB controller 210 needs to discard data in one of the entries according to an update alternative before providing storage space for the new data. Therefore, each of these N sets of data can correspond to a weight value, which is used to determine the frequency of use of the corresponding data, so that the LUB controller 210 can update the data accordingly. For example, one set of data in the N sets of data may have a lower weight value because it has not been used for a long time, while another set of data in the N sets of data may have a higher weight value because it is used more frequently. When the storage space in the load-use data buffer 200 is full, but the LUB controller 210 still decides to store a new set of data that has not yet been stored in the load-use data buffer 200, the LUB controller 210 can choose to discard the set of data with the lowest weight value among these N sets of data and replace it with the aforementioned new data. Therefore, this method can optimize the overall performance of the device 100 by utilizing the temporal locality of data, allowing frequently used data to be stored in the load-use data buffer 200 with faster access speed.

[0032] Table 3

[0033]

[0034] Table 3 shows another example of an instruction combination, which includes six instructions numbered i0, i1, i2, i3, i4, and i5. Instruction i0 writes the value "10" to register r2 as an initial value; instruction i1 loads the data at address [r0] in cache 151 into register r1; instruction i2 adds the value of register r4 to the value of register r1 and writes the result to register r5; instruction i3 adds the value of register r1 to the value of register r2 and writes the result to register r3; instruction i4 subtracts the value "1" from the value of register r2 and writes the result to register r2; and instruction i5 returns the program flow to instruction i1. Table 3 shows that instructions i1 and i2 are a load-use pair; however... Figure 2The load-use data buffer 200 shown still cannot prevent load-use pauses caused by the instruction combinations shown in Table 3. Specifically, when instruction i2 is executed, it adds 16 to the previous base address [r0] to use as the current target address. For example, in the first cycle, instruction i2 loads the data at address [r0] in cache 151 into register r1; and in the second cycle, instruction i2 loads the data at address [r0 + 16] in cache 151 into register r1. As can be seen from the above, although instruction i2 is executed repeatedly, the target address is shifted by "16" each time. Therefore, the load-use data buffer 200 will always "miss" the target address and cannot prevent load-use pauses.

[0035] Figure 3 This is a schematic diagram of a load-use data buffer 300 according to an embodiment of the present invention, wherein the load-use data buffer 300 can be regarded as Figure 2 The load-use data buffer 300 is an enhanced version of the load-use data buffer 200. Specifically, the load-use data buffer 300 is based on the architecture of the load-use data buffer 200, with improvements made to the status bits of each of the N entries in the tag storage area. For example, in addition to the valid bit VLD and the lock bit LOCK, the status of each of the N entries can be determined by an additional ready bit RDY such as RDY[0], RDY[1], RDY[2], ... and RDY[N]. Furthermore, the load-use data buffer 300 may also include a selection circuit such as a multiplexer 240, wherein the multiplexer 240 is coupled to the data buffer's internal data buffer space via an internal path (specifically to the output terminal of the multiplexer 230), and is coupled to the cache 151 outside the load-use data buffer 300 via a bypass path. When the data buffer 300 does not store loaded data (e.g., all N comparison results from the comparison of access address ADDR[INDEX_RANGE] are "missed"), the load-use data buffer 300 can select an entry, such as the i-th entry (i is an integer in the range of 0 to N), according to the above-described update alternative scheme to update the data in the data buffer space, such as the data stored in the i-th entry, according to the loaded data. In this embodiment, the range of bits used for comparison in access address ADDR, INDEX_RANGE, can vary depending on the size of the data stored in each entry, and will not be elaborated here for the sake of simplicity. If the loaded data can be found in cache 151, the LUB controller 210 can retrieve the loaded data from cache 151 (in... Figure 3(represented by cached data CACHE_DATA); if the loaded data cannot be found in cache 151, the LUB controller 210 can obtain the loaded data separately through bus interface unit 170 (in... Figure 3 (represented by bus data BUS_DATA).

[0036] It should be noted that after the LUB controller 210 obtains the cached data CACHE_DATA, the data update for the selected entry cannot be completed immediately. In this embodiment, the multiplexer 230 can select one of the internal path and the bypass path based on the ready bit of the selected entry (e.g., the ready bit RDY[i] of the i-th entry) to provide the load data requested by the load instruction (e.g., the first load instruction mentioned above) to the arithmetic logic unit 140 during the instruction execution phase. For example, when the data buffer space of the load-use data buffer 300 does not store the load data but the cache 151 stores the load data, the LUB controller 210 can update the ready bit RDY[i] of the i-th entry from "0" to "1", and the multiplexer 240 can enable the bypass path to allow the arithmetic logic unit 140 to obtain the load data (e.g., cached data CACHE_DATA) from the cache 151 before the data in the data buffer space (e.g., the data of the i-th entry mentioned above) has been updated. For example, when loading data is stored in the data buffer space of the data buffer 300, the ready bit RDY[i] can be maintained at "0", and the multiplexer 230 can enable the internal path to allow the arithmetic logic unit to retrieve the loaded data from the data buffer space.

[0037] Figure 4 This is a schematic diagram of an apparatus 400 (e.g., a central processing unit) operating under an instruction pipeline architecture according to an embodiment of the present invention, wherein the apparatus 400 can be considered as Figure 1 An enhanced version of the illustrated device. In this embodiment, device 400 may include a preload predictor 310, a load-use instruction detector 320, and... Figure 3 The load-use data buffer 300 is shown. The preload predictor 310 can be used to determine whether a load instruction meets at least one specific condition to generate a preload determination result PRELOAD. The load-use data buffer 300 can be coupled to the preload predictor 310 and can also be coupled to the arithmetic logic unit 140 to provide data for the arithmetic logic unit 140. Additionally, the load-use instruction detector 320 can detect whether the load instruction and its immediately following instruction are a load-use instruction pair to generate a load-use detection result lu_instr, where if the load-use detection result lu_instr indicates that the load instruction and its immediately following instruction are a load-use instruction pair, it means that the immediately following instruction involves the data requested by the load instruction.

[0038] When an instruction set contains multiple load instructions, and the memory addresses corresponding to these load instructions are arranged in ascending or descending order, such as in Table 3, instruction i1 will be executed repeatedly. Figure 1 Even with the aid of the device 100 shown Figure 2 The load-use data buffer 200 shown still cannot avoid generating bubbles in the instruction pipeline process. In this embodiment, when the preload judgment result PRELOAD indicates that the load instruction meets at least one specific condition, the load-use data buffer 300 can extract preload data from the cache 151 according to the information message carried by the load instruction and store the preload data in the load-use data buffer 300, wherein the preload data is the data requested by the subsequent load instruction. For example, when the preload predictor 310 detects the above-mentioned load instructions arranged in ascending or descending order, and the load-use instruction detector detects that the load instruction and the subsequent instruction are a load-use instruction pair, the preload predictor 310 can issue a preload request to the load-use data buffer 300, and the LUB controller 210 can trigger the preload process to access the load-use data buffer 300 according to the load-use information obtained in the instruction decoding stage. When the load-use data buffer 300 matches the result of the comparison of the access address ADDR (in Figure 4 The load-use data buffer 300 (marked as "LU hit") can output the target data during the instruction execution phase of the load instruction, allowing the arithmetic logic unit 140 to access the target data when subsequent instructions enter the instruction execution phase. If the target data requested by the load instruction cannot be found in the load-use data buffer 300, the preload request can check whether the target data can be found in the cache 151 during the memory access phase. If the cache 151 hits (indicating that the target data can be found), the target data (e.g., cached data CACHE_DATA) can be preloaded into the load-use data buffer 300, or it can be used separately. Figure 3 The control of the ready bit RDY[i] shown indicates that the target data is output directly (labeled "preload ready"). When cache 151 misses (i.e. the target data is not found in cache 151), device 400 can issue a bus request through bus interface unit 170 to obtain the target data from an external storage device (labeled "bus data").

[0039] Figure 5 According to an embodiment of the present invention, the loading instruction is drawn based on Figure 4 The diagram shows some details of the instruction pipeline architecture, in which... Figure 5For simplicity, only the instruction decoding stage, instruction execution stage, and memory access stage are shown. In this embodiment, the preload predictor generates a preload judgment result based on at least one field of the load instruction, and the preload judgment result PRELOAD is used to indicate whether the load address corresponding to the load instruction has been updated after the load instruction is executed. The preload data corresponds to the updated load address generated by updating the load address. When the preload judgment result PRELOAD indicates that the load address has been updated after the load instruction is executed, the load instruction meets at least one specific condition. In this embodiment, when the load instruction is decoded and a post-increment or post-decrement field is obtained, it indicates that the load instruction meets at least one specific condition. The post-increment field may include fields Inc and P, and the post-decrement field may include fields Dec and P. Furthermore, the decoded load instruction may contain a base address (in... Figure 5 The preload register (labeled as "base address register") and its offset value are used to determine the load address. When the preload result PRELOAD indicates that the load address is updated after the load instruction is executed, the updated load address is equal to the load address plus the offset value or equal to the load address minus the offset value. For example, if the load instruction is decoded and the fields Inc and P are obtained, it means that the base address can be updated to the base address plus the offset value after the load instruction is executed; and if the load instruction is decoded and the fields Dec and P are obtained, it means that the base address can be updated to the base address minus the offset value after the load instruction is executed.

[0040] In this embodiment, the address generator 130 can generate the load address corresponding to the load instruction based on the preload judgment result PRELOAD. For example... Figure 5As shown, the address generator 130 may include a first selector, such as a multiplexer 131, a second selector, such as a multiplexer 132, and a summing circuit 133 coupled to multiplexers 131 and 132. Multiplexer 131 can be used to select a final base address from the base address ADDR(n) carried by the load instruction and the previous load address ADDR(n-1) corresponding to the previous load instruction based on the preload judgment result PRELOAD, while multiplexer 132 can be used to select a final offset value from the offset value OFFSET(n) carried by the load instruction and the previous offset value OFFSET(n-1) carried by the previous load instruction based on the preload judgment result PRELOAD, wherein the summing circuit 133 is used to add (or subtract) the final offset value to the final base address to generate the load address (which may be referred to as the "final address"). Specifically, when the preload determination result PRELOAD indicates that the load address will be updated after the load instruction is executed (e.g., the logical value of PRELOAD is "1"), multiplexer 131 selects the previously loaded address ADDR(n-1) as the final base address, and multiplexer 132 selects the previously offset value OFFSET(n-1) as the final offset value. Conversely, when the preload determination result PRELOAD indicates that the load address will not be updated after the load instruction is executed (e.g., the logical value of PRELOAD is "0"), multiplexer 131 selects the base address ADDR(n) as the final base address, and multiplexer 132 selects the offset value OFFSET(n) as the final offset value. It should be noted that this embodiment uses the case where the load instruction is decoded and the fields Inc and P are obtained as an example, but the invention is not limited to this. Those skilled in the art can infer the relevant details when the load instruction is decoded and the fields Dec and P are obtained, which will not be elaborated here for the sake of brevity.

[0041] Table 4

[0042]

[0043] Table 4 shows the process of certain instructions in Table 3 in the pipeline architecture over three cycles. The instruction decoding stage, instruction execution stage, memory access stage, and data write-back stage are labeled "ID", "EXE", "MEM", and "WB" respectively in Table 4 for clarity. In the first cycle, the load instruction i1 loads the data at address 0x00 during the instruction execution stage, while the add instruction i2 loads the data at address 0x00 during the instruction decoding stage. Since the load instruction i1 and the add instruction i2 are a load-use pair and the access address of the load instruction i1 is arranged in ascending order (the access address is shifted by 16 after each execution), the preload predictor 310 can issue a preload request. In the second cycle, load instruction i1 enters the memory access phase, addition instruction i2 enters the instruction execution phase, and addition instruction i3 enters the instruction decoding phase. While addition instruction i2 is in the instruction execution phase, a preload request preloads the data at access address 0x10 (the address obtained by shifting access address 0x00 by 16) into the load-use data buffer 300 (marked as preload 0x10). In the third cycle, load instruction i1 enters the data write-back phase, addition instruction i2 enters the memory access phase, addition instruction i3 enters the instruction execution phase, and subtraction instruction i4 enters the instruction decoding phase. After several cycles, return instruction i5 returns the program flow to load instruction i1. Since the data at access address 0x10 has been preloaded into the load-use data buffer 300, load instruction i1 in cycle M (M is a positive integer) will achieve a load-use buffer hit. Similarly, in cycle M+1, during the instruction execution phase of the addition instruction i2, a preload request can preload the data at access address 0x20 (the address obtained by shifting access address 0x10 by 16) into the load-use data buffer 300 (marked as preload 0x20). Therefore, this data can be obtained when the load instruction i1 is executed in a subsequent cycle. The result of the load-use buffer hit is then obtained. Since the operations from cycle M to cycle M+2 are similar to those from the first to the third cycle, for the sake of simplicity, the relevant details will not be repeated.

[0044] It should be noted that cache 151 is typically implemented using static random access memory, while the load-use data buffer 300 of this invention can use flip-flops as storage units. Therefore, the arithmetic logic unit 140 retrieves data from the load-use data buffer 300 faster than it retrieves data from the cache 151. Based on these characteristics, when a load instruction receives a load-use buffer hit during instruction execution (i.e., the data requested by the load instruction can be found in the load-use data buffer 300), the load-use data buffer 300 can output the data requested by the load instruction in a single cycle, thereby avoiding bubbles in the instruction pipeline scheduling. In particular, when a load instruction is executed repeatedly and the target addresses are arranged in ascending or descending order each time, it indicates that the target addresses of subsequent load instructions are predictable. The preload predictor 310 of the present invention can issue a preload request based on such spatial locality so that the data of the target addresses arranged in ascending or descending order can be moved into the load-use data buffer 300 in advance before they are needed, thereby avoiding the problem of load-use pause.

[0045] Figure 6 This is a workflow of a method for production line control according to an embodiment of the present invention, wherein the method can be applied to Figure 4 The device 400 is shown. It should be noted that... Figure 6 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. In particular, one or more steps may be based on... Figure 6 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 6 Execute in the order shown.

[0046] In step S610, the device 400 may use the preload predictor 310 to determine whether the load instruction meets at least one specific condition in order to generate a preload judgment result PRELOAD.

[0047] In step S620, when the preload determination result PRELOAD indicates that the load instruction meets at least one specific condition, the device 400 can use the load-use data buffer 300 to extract preload data from the cache 151 according to the information carried in the load instruction and store the preload data in the load-use data buffer 300, wherein the preload data is the data requested by a subsequent load instruction.

[0048] In step S630, the device 400 may use the load-use data buffer 300 to provide preloaded data to the arithmetic logic unit for arithmetic logic operations, wherein the arithmetic logic unit retrieves data from the data buffer faster than the arithmetic logic unit retrieves data from the cache.

[0049] Figure 7 To implement the workflow of a preload request according to embodiments of the present invention, wherein the preload request may be performed by... Figure 4 The preload predictor 310 shown is issued, and the workflow can be... Figure 3 The LUB controller 210 shown is used for control, but the invention is not limited thereto. It should be noted that... Figure 7 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. In particular, one or more steps may be performed... Figure 7 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 7 Execute in the order shown.

[0050] In step S700, the preload request begins.

[0051] In step S702, the LUB controller 210 may check whether a LUB has been hit (e.g., load-use data buffer 300) to generate a LUB check result.

[0052] In step S704, if the LUB check result is "yes", the workflow proceeds to step S722; if the LUB check result is "no", the workflow proceeds to step S706.

[0053] In step S706, the LUB controller 210 can set the valid bit VLD[i] to "1", the ready bit to "0", and the lock bit LOCK[i] to "1".

[0054] In step S708, the LUB controller 210 may check whether a cache (e.g., cache 151) has been hit to generate a cache check result.

[0055] In step 710, if the cache check result is "yes", the workflow proceeds to step S712; if the cache check result is "no", the workflow proceeds to step S720.

[0056] In step S712, the LUB controller 210 may preload data into the LUB from a cache (e.g., cache 151) (e.g., load-using data buffer 300).

[0057] In step S714, the LUB controller 210 can set the valid bit VLD[i] to "1", the ready bit to "1", and the lock bit LOCK[i] to "1".

[0058] In step S716, the LUB controller 210 can update the LUB data using SRAM data (e.g., cache data CACHE_DATA).

[0059] In step S718, the LUB controller 210 can set the valid bit VLD[i] to "1", the ready bit to "0", and the lock bit LOCK[i] to "0".

[0060] In step S720, the LUB controller 210 can set the valid bit VLD[i] to "0", the ready bit to "0", and the lock bit LOCK[i] to "0".

[0061] In step S720, the preloading request ends.

[0062] Figure 8 The workflow for executing load instructions according to an embodiment of the present invention, wherein the load instructions are applicable to Figure 4 The device 400 is shown. It should be noted that... Figure 8 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. In particular, one or more steps may be performed... Figure 8 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 8 Execute in the order shown.

[0063] In step S800, the loading instruction begins.

[0064] In step S802, the device 400 may check whether a LUB is hit (e.g., load-use data buffer 300) to produce a LUB result.

[0065] In step S804, if the LUB result shows "Yes", the workflow proceeds to step S806; if the LUB result shows "No", the workflow proceeds to step S818.

[0066] In step S806, the device 400 can determine whether the lock bit LOCK[i] is "1". If the determination result is "yes", the workflow proceeds to step S812; if the determination result is "no", the workflow proceeds to step S808.

[0067] In step S808, the device 400 may update the alternative (e.g., update the weight values ​​corresponding to each of the above entries).

[0068] In step S810, device 400 may use load-use data buffer 300 to back-feed LUB data (e.g., data of entries hit in load-use data buffer 300) to the core pipeline and declare the LUB data valid (e.g., output a valid signal LUB_VALID with a logic value "1").

[0069] In step S812, device 400 may check whether LUB preloading is in progress (e.g., check the ready bit RDY[i] of the corresponding entry).

[0070] In step S814, device 400 can determine whether the ready bit RDY[i] is "1". If the determination result is "yes", the workflow proceeds to step S816; if the determination result is "no", the workflow proceeds to step S824.

[0071] In step S816, device 400 may send back SRAM data (e.g., cache data CACHE_DATA extracted from cache 151) to the core pipeline and declare LUB data valid (e.g., output a valid signal LUB_VALID with a logic value "1").

[0072] In step S818, the device 400 can determine whether the load instruction and the subsequent instruction are a load-use instruction pair (labeled as "lu_instr?" for brevity). If the determination result is "yes", the workflow proceeds to step S820; if the determination result is "no", the workflow proceeds to step S824.

[0073] In step S820, the device 400 may select entry index i (i.e., select the i-th entry) based on an alternative scheme (e.g., update the weight values ​​corresponding to each of the above entries).

[0074] In step S822, the device 400 may set the lock bit LOCK[i] of the i-th entry to "1".

[0075] In step S824, device 400 may check whether a cache hit (e.g., whether a cache 151 hit) is occurred to generate a cache check result.

[0076] In step S826, if the cache judgment result is "yes", the workflow proceeds to step S828; if the cache judgment result is "no", the workflow proceeds to step S836.

[0077] In step S828, device 400 may send back cached data, such as CACHE_DATA, to the core pipeline.

[0078] In step S830, device 400 may determine whether the LUB is hit (e.g., whether the load-use data buffer 300 is hit). If the determination result is "no", the workflow proceeds to step S844; if the determination result is "yes", the workflow proceeds to step S832.

[0079] In step S832, device 400 may update LUB data (e.g., DATA[i] of the i-th entry) with SRAM data (e.g., cache data CACHE_DATA).

[0080] In step S834, the device 400 may set the lock bit LOCK[i] of the i-th entry to "0".

[0081] In step S836, the device 400 can send a request, such as a bus request, to the bus through the bus interface unit 170, and return the bus data obtained by the bus interface unit 170 to the core pipeline.

[0082] In step S838, device 400 may determine whether the LUB is hit (e.g., whether the load-use data buffer 300 is hit). If the determination result is "no", the workflow proceeds to step S844; if the determination result is "yes", the workflow proceeds to step S840.

[0083] In step S840, device 400 can update LUB data (e.g., DATA[i] of the i-th entry) using bus data.

[0084] In step S842, the device 400 may set the lock bit LOCK[i] of the i-th entry to "0".

[0085] In step S844, the loading instruction ends.

[0086] In summary, based on temporal locality (e.g., some data has been used recently or frequently) and spatial locality (e.g., data at certain addresses is expected to be used), this invention can pre-move certain data to a load-use data buffer with faster access speed. This allows the instruction pipeline to execute operations with minimal or no bubble generation when load-use instruction pairs appear, thereby reducing the probability of load-use pauses. In particular, embodiments of this invention do not significantly increase additional costs; therefore, this invention solves the problems of related technologies without or with relatively minimal side effects.

[0087] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the invention application should be included in the scope of the present invention.

[0088] [Symbol Explanation]

[0089] 100: Device

[0090] 110: Command Extraction

[0091] 120: Instruction Decoding

[0092] 130: Address Generator

[0093] 131: Multiplexer

[0094] 132: Multiplexer

[0095] 133: Summarizing circuit

[0096] 140: Arithmetic Logic Unit

[0097] 150: Load storage unit

[0098] 151: Cache

[0099] 160: Register File

[0100] 170: Bus Interface Unit

[0101] 200: Load - Using data buffer

[0102] 210: LUB Controller

[0103] 220: Select Controller

[0104] 230: Multiplexer

[0105] 240: Multiplexer

[0106] 300: Load - Using Data Buffer

[0107] 310: Preloaded predictor

[0108] 320: Load - Use Command Detector

[0109] 400: Device

[0110] PRELOAD: Preload judgment result

[0111] lu_instr: Load - Use detection results

[0112] CACHE_DATA: Cached data

[0113] BUS_DATA: Bus data

[0114] ADDR: Access address

[0115] VALID[0]~VALID[N]: Valid bits

[0116] LOCK[0]~LOCK[N]: Lock bits

[0117] TAG[0]~TAG[N]: Tag address

[0118] DATA[0]~DATA[N]: Data

[0119] SEL: Select Signal

[0120] LUB_VALID: Valid signal

[0121] ADDR(n): Base address

[0122] ADDR(n-1): Previously loaded address

[0123] OFFSET(n) : Offset value

[0124] OFFSET(n-1): Previous offset value

[0125] Inc, P: Field

[0126] S610~S630, S700~S722, S800~S844: Steps

Claims

1. An apparatus for pipeline control, comprising: a preload predictor to determine whether a load instruction meets at least one condition to generate a preload determination result; an arithmetic logic unit (ALU) to perform arithmetic logic operations; a data buffer coupled to the preload predictor and the arithmetic logic unit to provide data to the arithmetic logic unit, wherein the arithmetic logic unit fetches data from the data buffer faster than the arithmetic logic unit fetches data from a cache; wherein when the preload determination result indicates that the load instruction meets the at least one condition, the data buffer fetches preload data from the cache based on information carried by the load instruction and stores the preload data in the data buffer, and the preload data is data requested by a subsequent load instruction, wherein the load instruction meets the at least one condition when the preload determination result indicates that a load address corresponding to the load instruction is updated after the load instruction is executed.

2. The apparatus of claim 1, wherein the data buffer comprises: a selection circuit coupled to a data register space inside the data buffer through an internal path and coupled to the cache outside the data buffer through a bypass path; wherein the selection circuit selects one of the internal path and the bypass path to provide load data requested by the load instruction to the arithmetic logic unit.

3. The apparatus of claim 2, wherein when the data register space of the data buffer stores the load data, the selection circuit enables the internal path to allow the arithmetic logic unit to fetch the load data from the data register space.

4. The apparatus of claim 2, wherein when the data register space of the data buffer does not store the load data, the data buffer updates data in the data register space based on the load data, and the selection circuit enables the bypass path to allow the arithmetic logic unit to fetch the load data from the cache before the data in the data register space is updated.

5. The apparatus of claim 1, wherein the preload predictor generates the preload determination result based on at least one field of the load instruction, and the preload determination result indicates whether a load address corresponding to the load instruction is updated after the load instruction is executed, wherein the preload data corresponds to an updated load address generated by updating the load address.

6. The apparatus of claim 5, wherein the load instruction carries an offset value, and when the preload decision indicates that the load address is to be updated after the load instruction completes execution, the updated load address is equal to the load address plus the offset value or the load address minus the offset value.

7. The apparatus of claim 6, further comprising: an address generator to generate the load address based on the preload decision, wherein the address generator comprises: a first selector to select a final base address from a base address carried by the load instruction and a previous load address corresponding to a previous load instruction based on the preload decision; a second selector to select a final offset value from the offset value carried by the load instruction and a previous offset value carried by the previous load instruction based on the preload decision; and an adder circuit coupled to the first selector and the second selector to add or subtract the final offset value from the final base address to generate the load address.

8. The apparatus of claim 7, wherein when the preload decision indicates that the load address is to be updated after the load instruction completes execution, the first selector selects the previous load address as the final base address and the second selector selects the previous offset value as the final offset value.

9. A method for pipeline control, comprising: determining, using a preload predictor, whether a load instruction satisfies at least one condition to generate a preload decision; when the preload decision indicates that the load instruction satisfies the at least one condition, using a data buffer to fetch preload data from a cache based on information carried by the load instruction and store the preload data in the data buffer, wherein the preload data is data requested by a subsequent load instruction, wherein the load instruction satisfies the at least one condition when the preload decision indicates that a load address corresponding to the load instruction is to be updated after the load instruction completes execution; and providing, using the data buffer, the preload data to an arithmetic logic unit (ALU) for arithmetic logic operations, wherein the ALU fetches data from the data buffer faster than the ALU fetches data from the cache.

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