Approximate Binary Multiplier Based on Static Segment Compensation Method

Abstract

The present invention proposes an approximate binary multiplier structure based on a static segmented truncation compensation method. This structure considers the distribution of the multiplier input and performs segmentation. When the probability of high-order redundant bits in the multiplier input is high, redundant partial products are truncated, reducing hardware resource consumption while maintaining good accuracy. When the probability of high-order non-redundant bits in the multiplier input is high, an error compensation circuit design based on partial product probability analysis is performed after truncating the partial products of the less significant bits, making it suitable for general fault-tolerant application scenarios. Furthermore, in both cases, the partial products generated by the partial product generation circuit of the multiplier input are input to the same partial product compression circuit that further utilizes the truncation compensation method, eliminating the need for different partial product compression circuits for the two cases. This achieves resource sharing and reduces hardware resource consumption, ensuring that the present invention achieves a good compromise between circuit hardware performance and accuracy in most application scenarios.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an approximate binary multiplier based on a static segmented compensation method. Background Art

[0002] With the rapid development of businesses and scenarios such as the Internet of Things and artificial intelligence, and the increasing number of smart terminal devices, there is a growing demand for edge computing applications. The massive amounts of data and complex calculations required by these applications pose unprecedented challenges to the design of operator circuits. High performance and low power consumption are design requirements for operator circuits in edge computing applications. At the same time, precise or high-precision calculations are not always necessary in edge computing applications. For example, the industry often chooses 8-bit fixed-point quantization. In applications such as image processing and digital signal processing that require a large number of floating-point calculations, high-precision 32-bit single-precision floating-point numbers can be converted to low-precision 8-bit fixed-point numbers for processing. The results of the fixed-point operations are still acceptable. Approximate computing is a common low-power design approach in these fault-tolerant applications, improving the performance of operator circuits with limited loss of accuracy. Because multipliers are the primary source of power consumption in operator circuits, the design of approximate multipliers is a key focus of approximate computing research.

[0003] An important class of approximate multipliers is the piecewise multiplier. The design concept of this type of multiplier is to extract a low-width significant bit segment from each operand, multiply the two bit segments using an internal low-width multiplier, and then expand the multiplier output to the full-width product. There are two main segmentation methods for piecewise multipliers: dynamic segmentation and static segmentation. In a dynamic segmentation multiplier, a most significant bit detector detects the most significant bit of each operand and extracts the significant bit segment. The significant bit segments are then multiplied using an internal multiplier. Finally, a shifter shifts and expands the product of the significant bit segments to obtain the final product. The approximate method for a dynamic piecewise multiplier primarily achieves different levels of approximate accuracy by truncation compensation of the significant bit segment and approximating the internal low-width multiplier. This design is implemented using a relatively complex hardware architecture. In addition to the internal low-width multiplier, the internal most significant bit detector and shifter significantly increase hardware resource consumption. In a static segmented multiplier, each operand is statically segmented and a valid segment of a defined width is extracted. This approach greatly simplifies hardware implementation and reduces power consumption, as it eliminates the need for a pre-detector or shifter. However, due to the inability to precisely select the valid segment, a static segmented multiplier using the same approximate design method for the internal multiplier exhibits greater error than a dynamic segmented multiplier. Therefore, static segmented multipliers require more sophisticated error recovery circuitry and analysis of the method for determining the static segment width of the operands.

[0004] However, most existing segmented multipliers do not consider the distribution of the input and directly perform segmentation, and also lack error compensation based on probability analysis of partial products. Summary of the Invention

[0005] To address the problem that traditional segmented multipliers cannot achieve a good compromise between power consumption and accuracy, the present invention proposes an approximate binary multiplier structure based on static segmented compensation, which achieves performance improvement and power consumption reduction through structural innovation.

[0006] The technical solution of the present invention to realize an approximate binary multiplier based on static segmented compensation is as follows:

[0007] An approximate binary multiplier based on static segmented compensation comprises a partial product generating module, a partial product compressing module and an adder module.

[0008] The partial product generation module is used to encode the multiplier and decode the multiplicand according to the encoded signal to generate a partial product array.

[0009] The partial product compression module is used to compress the partial product array, and finally compress it into two rows of partial products.

[0010] The last-stage adder module adds the compressed two-row partial products to obtain the output of the approximate binary multiplier.

[0011] The partial product generation module utilizes radix-4 Booth encoding. Radix-4 Booth encoding involves encoding each adjacent three bits of the multiplier into a coded bit segment, with each segment overlapping by one bit. The multiplier is statically divided into multiple coded bit segments during the Booth encoding process. When determining the multiplier architecture, the redundancy of the input data distribution is analyzed to determine the width of the truncated bit segments at the upper or lower bits. During the actual calculation, the multiplier is evaluated for redundant bits and the valid bit segments are selected for Booth encoding. The remaining bit segments are truncated, which is reflected in the generated simplified partial product array as a horizontal truncation. If the most significant bit segment of the multiplier is redundant, the first two bits in the segment are sign-extended, and the least significant bit represents the most significant bit of the actual value. The present invention discards the Booth encoding process for the most significant bit segment, while retaining the actual value. The remaining three valid bit segments participate in the Booth encoding process, without altering the actual represented value. If the highest coded bit segment of the multiplier is not redundant, the three most significant bit segments participate in the Booth coding process, and the Booth coding process of the lowest coded bit segment is discarded and introduces errors.

[0012] The partial product compression module performs error expectation analysis and truncation compensation design on the simplified partial product array generated based on the static segmentation method. For the case where the highest coding bit segment is redundant, the most significant partial product row in the partial product array is truncated, and the partial product array is simplified to include only the remaining valid partial product rows and the partial product extension bits contained in each row. For the case where the highest coding bit segment is non-redundant, after error compensation calculation and optimization, the partial product array is the same as the partial product array in the case where the highest coding bit segment is redundant.

[0013] To further reduce size, the partial product compression module truncates the lower bits using conventional truncation compensation. Using an OR gate circuit and partial product shift compression, the most significant column of the truncated portion is then offset into the least significant column of the partial product compression circuit for error compensation. The specific number of partial product columns used for this truncation compensation can be adjusted based on accuracy requirements, achieving a compromise between accuracy and performance.

[0014] The partial product compression module compresses the truncated and compensated partial product array using a full adder and a half adder.

[0015] The output of the product results is also considered for both redundant and non-redundant cases. In the non-redundant case, the compression tree truncates the first row of the partial products and the least significant bits of the partial product array. In this case, the output product result simply padded with zeros in the lower bits to the full bit width of the output product result. In the redundant case, the upper bits of the product result are supplemented with a sign extension bit, whose value is equal to the most significant bit of the compressed partial product result. Zeros are also padded in the lower bits to the full bit width of the output product result. The output of the product result is a concatenation of the obtained results, without the need for additional logic such as shifting.

[0016] The beneficial effects of the present invention are as follows: the present invention proposes an approximate binary multiplier structure based on a static segmented compensation method, which performs segmentation in consideration of the distribution law of the multiplier input, maintains accuracy well when the probability of high-bit redundancy of the multiplier input is high, and performs an error compensation circuit design based on partial product probability analysis, making it also applicable to general fault-tolerant application scenarios, ensuring that the present invention achieves a good compromise between circuit hardware performance and accuracy in most application scenarios. The present invention can be used for multiplication-intensive applications, so that these applications can be better deployed on portable devices or large-scale high-performance computing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the Booth encoding process based on the static segmentation method in the multiplier proposed by the present invention.

[0018] Figure 2Schematic diagram of a partial product array generated when the highest encoding bit segment of the multiplier is redundant in the present invention.

[0019] Figure 3 Schematic diagram of a partial product array generated when the highest coded bit segment of the multiplier is not redundant and an error compensation method thereof in the present invention.

[0020] Figure 4 This is a schematic diagram of the partial product compression circuit in the multiplier proposed by the present invention.

[0021] Figure 5 This is a schematic diagram of the product result output method in the multiplier proposed by the present invention. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the Booth encoding process based on the static segmentation method in the multiplier proposed in the present invention. In the approximate binary multiplier based on static segmentation compensation proposed in the present invention, the step of generating the partial product array is achieved by static segmentation truncated radix-4 Booth encoding. First, it is necessary to perform redundancy judgment on the most significant bit segment in the radix-4 Booth encoding. The radix-4 Booth encoding process is to encode each adjacent three bits of the multiplier into a coding bit segment and overlap one bit between each segment. For an 8×8 signed number radix-4 Booth multiplier, the multiplier is divided into 4 coding bit segments for encoding, represented by m3 to m0, as shown in FIG. Figure 1 As shown. If the most significant bit segment of the multiplier is redundant, it means that the first two bits in this bit segment are sign extension bits, and the lowest bit represents the most significant bit of the actual value. The present invention discards the Booth encoding process of the highest coding bit segment m3, while the actual value can be retained and the remaining three valid bit segments m2 to m0 participate in the Booth encoding process, which will not cause the actual represented value to change. If the highest coding bit segment of the multiplier is not redundant, then the valid bit segments m3 to m1 participate in the Booth encoding process, and the Booth encoding process of the lowest coding bit segment m0 ​​is discarded and introduces an error. The error value caused by the discarding has little effect on the accuracy of the product result after error analysis and compensation.

[0024] The static segmented truncated radix-4 Booth encoding circuit for generating partial product arrays consists of a redundancy judgment circuit, a multiplier bit segment selection circuit, and a Booth encoder. Figure 1. The redundancy judgment circuit is used to judge whether the most significant bit segment of the multiplier is redundant. The specific principle is to judge whether the most significant coding bit segment is 111 or 000, and then obtain the redundancy judgment result and input it into the multiplier bit segment selection circuit. In the multiplier bit segment selection circuit, if the most significant coding bit segment is redundant, the most significant coding bit segment m3 of the multiplier is truncated, and the remaining three valid bit segments m2 to m0 are input into the corresponding Booth encoders EN2 to EN0; if the most significant bit segment is non-redundant, the least significant coding bit segment m0 ​​of the multiplier is truncated (including a 0 added to the least significant bit). The remaining three valid bit segments are input into the corresponding Booth encoder. The multiplicand in groups of two and the multiplier valid bit segment in groups of three are input into the encoders EN0 to EN2 together to generate the partial products PPR0 to PPR2 of the first to third rows.

[0025] Figure 2 and Figure 3 The diagram shows the partial product array generated in the present invention with and without redundant highest encoding bit segments of the multiplier and the error compensation method. For an 8×8 signed radix-4 Booth multiplier, the complete partial product array has 4 rows and 16 columns. Figure 1 The partial product arrays generated by the partial product generation circuit shown below have two cases: when the highest coded bit segment m3 is redundant and when it is not. When m3 is redundant, truncating the redundant partial products in the partial product array allows for compression of the partial products while maintaining high accuracy using less hardware resources. When m3 is not redundant, error analysis and compensation can also maintain good accuracy without consuming additional compensation circuitry.

[0026] For the case where the highest coding segment m3 is redundant, the highest coding segment m3 of the multiplier is truncated, and the remaining three valid segments are input to the corresponding Booth encoding unit EN, which is reflected in the partial product array as the 4th row is truncated, as shown in Figure 2 Regarding the partial product rows in the dashed box, since the fourth row of partial products originally contains no information, truncation of the fourth row does not lose precision. The partial product array is now streamlined to include only the first three rows, including partial product rows PPR0 through PPR2, as well as the partial product extension bits and sign compensation bits contained in each row. This reduces the required compression unit consumption. In applications with a high probability of high-bit redundancy, the partial products are likely compressed using the partial product compression tree with high-bit redundancy, achieving high precision with minimal resource consumption.

[0027] In the case that the highest coding bit segment is not redundant, in order to maintain good accuracy, the lowest coding bit segment m0 ​​of the multiplier is truncated, and the remaining three groups of coding bit segments are input to the corresponding Booth encoding unit EN. This is reflected in the partial product array, where the first row is directly truncated without being generated by the Booth encoder, as shown in the following example: Figure 3The partial plot rows are in the dotted box.

[0028] Further, the first row of the dotted box is partially integrated into the upper 4-bit dotted box and the lower dotted box. After error analysis, the lower partial product is truncated in advance and the expected error is calculated. The error analysis is performed on the probability of the upper 4 bits appearing through different partial product combinations. There are only 4 combinations of the upper 4 bits. The analysis results show that approximating the first 4 bits to 1000 can well balance the error caused by truncation. Therefore, the first partial product row can be approximately compensated for the MSB of the most significant bit in the first row. After repeating the sign extension bit optimization here, the optimized compressed tree array can be obtained, as shown in Figure 3 shown.

[0029] like Figure 3 As shown, use s i Indicates the value of the sign extension bit of the partial product in row i, which is equal to the partial product of the most significant bit in the partial product row. i Non-use The remaining common parts are as follows Figure 3 The white circle symbol in the figure is represented by . Considering the 1 in the first row of partial product approximation compensation and the sign extension bit in the second row of partial products, represented by Sgn, we can get:

[0030]

[0031] Among them, when s1=1, the value in the bracket of the last term in the above formula is 3, which is the binary representation of When s1=0, the value in the bracket of the last term in the above formula is 4, which is also Therefore, we can replace the contents in the brackets above with That is, s1, s1 and s2 are compensated in the 11th, 12th and 13th columns of the partial product array respectively. This expression will not make the 1 in the first row of partial product compensation occupy a single row. The optimized Sgn is expressed as:

[0032]

[0033] At this time, the optimized partial product array is exactly the same as that in the redundant case, including the partial product rows PPR0 to PPR2 and the partial product extension bits and sign compensation bits contained in each row, such as Figure 3 As shown, similar to the compression window sliding to the next three rows, the error is compensated using the same compression tree array without additional circuitry.

[0034] In this compensation case, the error probability is analyzed and the average value of the overall error ME1 of the first row is obtained as follows:

[0035] ME1=μ2-μ1-0.5=-0.25

[0036] The positive and negative errors in the first row are basically offset by error compensation, and the overall error average is very close to 0. Through the partial product expansion optimization algorithm, the same method as the method of generating a special sign extension bit in the first row of the conventional partial product array can be used to integrate this 1 into the simplified partial product array. Figure 3 As shown, the reduced partial product array in this case is identical to the reduced partial product array in the case of the highest coding bit segment redundancy. By performing the same low-bit truncation compensation optimization, the partial products can be compressed using the same compression tree as in the case of the highest coding bit segment redundancy. In other words, the partial products generated by the multiplier input through the partial product generation circuit are directly input into the same compression tree, eliminating the need for different compression trees for the two cases. This enables resource sharing, reduces hardware resource consumption, and therefore power consumption.

[0037] Figure 4 This is a schematic diagram of the partial product compression circuit in the multiplier proposed by the present invention. Due to the reduction in the height of the partial product array, the compression tree can completely eliminate the need for 4-2 compressors, and instead use full adders and half adders to implement the compression process.

[0038] In order to achieve a compromise between error and hardware consumption, the approximation in the partial product compression circuit of the multiplier proposed in the present invention further adopts a conventional truncation compensation method, and compensates through the information of the less significant bits of the partial product. The present invention uses a simple logic circuit and shift compression of the partial product to perform error compensation. Figure 4 As shown, for an 8×8 signed radix-4 Booth multiplier, Figure 2 and Figure 3 The remaining partial product array, consisting of partial product rows PPR0 through PPR2 and the partial product extension bits and sign compensation bits contained in each row, undergoes further truncation compensation. The remaining partial product array, comprising three rows and fourteen columns, now no longer distinguishes between redundant and non-redundant highest coded bit segments. The partial products of the lower four columns of the partial product array, along with the sign compensation bits belonging to the third row, are truncated. The two partial products at the first and second rows of the fifth column are input into an OR gate, as indicated by the oval box. The result is output to the sixth column of the partial product array for subsequent compression. The partial products at the third row of the fifth column are directly moved to the sixth column of the partial product array for subsequent compression. Compensation in the compression tree primarily involves these two aspects. This compensation does not require additional compression processing; it only adds a full adder to the second stage of compression. The number of columns truncated in the compression tree is configurable to meet varying accuracy requirements. After compression of the compression tree, the final two rows of partial products can be obtained. After addition through the adder module, an 8-bit compression tree result can be obtained. Further splicing of the results can expand the bit width to obtain the product result.

[0039] Figure 5 This is a schematic diagram of the method for outputting the product result in the multiplier proposed in the present invention. After obtaining the compressed tree result, the output of the product result also considers the redundant and non-redundant situations, such as Figure 5 As shown in the figure, the redundant signal is the same one used when selecting the Booth encoder input. It is used again here to determine redundancy. If the highest encoding bit segment is non-redundant, the output product result only needs to add 8 bits of zero to the low-order bits of the compressed tree result. If the highest encoding bit segment is redundant, the output product result needs to add two sign extension bits Sr to the high-order bits of the compressed tree result. The value of these bits is equal to the highest bit of the compressed tree result, ranging from 0 to 1, and 6 bits of zero are added to the low-order bits of the compressed tree result.

[0040] In summary, the approximate binary multiplier structure based on the static segmented compensation method proposed in the present invention considers the distribution pattern of the multiplier input and performs segmentation. When the probability of high-bit redundancy in the multiplier input is high, the redundant partial products are truncated, thereby reducing hardware resource consumption while maintaining good accuracy. When the probability of high-bit non-redundancy in the multiplier input is high, an error compensation circuit design based on partial product probability analysis is performed after truncating the partial products of the low-significant bits, making it also applicable to general fault-tolerant application scenarios. In both cases, the partial products generated by the partial product generation circuit of the multiplier input are input to the same partial product compression circuit, without the need to use different partial product compression circuits in the two cases. This achieves resource sharing and thus reduces hardware resource consumption, ensuring that the present invention achieves a good compromise between circuit hardware performance and accuracy in most application scenarios.

[0041] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific descriptions and embodiments. Those skilled in the art can make various other specific variations and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such variations and combinations are still within the scope of protection of the present invention.

Claims

1. An approximate binary multiplier based on static segmented compensation, characterized in that: It includes a partial product generating module, a partial product compressing module and an adder module; The partial product generation module is used to encode the multiplier and decode the multiplicand according to the encoded signal to generate a partial product array; The partial product compression module is used to compress the partial product array, and finally compress it into two rows of partial products; The adder module adds the compressed partial products of the two rows to obtain the output of the approximate binary multiplier; The partial product generation module adopts a radix-4 Booth encoding method, specifically: the multiplier is statically divided into multiple coding bit segments, redundant bit determination is performed, and a valid bit segment is selected for Booth encoding, while the remaining bit segments are truncated; the redundant bit determination method is to determine whether the highest coding bit segment is redundant, and the multiplier is defined as being divided into four coding bit segments for encoding, represented by m3 to m0, and then it is determined whether m3 is all 1s or all 0s. If so, the highest coding bit segment is redundant, m3 is truncated, and m2 to m0 participate in the Booth encoding process; otherwise, m0 is truncated, and m3 to m1 participate in the Booth encoding process; The partial product compression module compresses the partial product array generated by Booth coding after truncation compensation, which is divided into two cases: the highest coding bit segment is redundant and the highest coding bit segment is non-redundant. Specifically: For an 8×8 signed radix-4 Booth multiplier, the complete partial product array has 4 rows and 16 columns; If the highest coded bit segment is redundant, the fourth row in the partial product array is truncated. In this case, the remaining partial product array includes the first three rows of partial products and the partial product extension bits and sign compensation bits contained in each row. If the highest coded bit segment is not redundant, the first row in the partial product array is truncated, and the 11th, 12th, and 13th columns of the partial product in the second row of the partial product array are compensated respectively. , and , Equal to the partial product of the highest digit of the partial product row, yes In this case, the remaining partial product array is the same as that in the case of the highest coded bit segment redundancy, including the first three rows of partial products and the partial product extension bits and sign compensation bits contained in each row; Truncation compensation is continued for the remaining partial product array consisting of the first three rows of partial products and the partial product extension bits contained in each row. The remaining partial product array includes three rows and fourteen columns. At this time, no distinction is made between the redundant and non-redundant cases of the highest coding bit segment. The partial products of the lower four columns of the partial product array and the sign compensation bits belonging to the partial products in the third row are all truncated. The two partial products at the first and second rows of the partial products in the fifth column are input into an OR gate and output to the partial product array in the sixth column to participate in the subsequent compression process. The partial products at the third row of the partial products in the fifth column are directly moved to the partial product array in the sixth column to participate in the subsequent compression process.

2. The approximate binary multiplier based on static piecewise compensation according to claim 1, wherein: After the adder module adds the compressed partial products of the two rows to obtain the compressed tree result, the final product result is output. The processing of the compressed tree result is divided into two cases: the highest coding bit segment is redundant and the highest coding bit segment is non-redundant. Specifically, If the highest coded bit segment is redundant, the output product result needs to add two sign extension bits Sr to the high bit of the compressed tree result, whose value is equal to the highest bit of the compressed tree result and the value range is 0 or 1, and add 6 bits of 0 to the low bit of the compressed tree result; If the highest coded bit segment is not redundant, the output product result only needs to add 8 bits of 0 to the low order of the compressed tree result.

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