A data processing method and apparatus for a two-dimensional systolic array

Abstract

The application provides a data processing method and device of a two-dimensional systolic array, which comprises a data buffer subsystem and a systolic array. The systolic array can be divided into upper and lower parts or left and right parts for operation processing according to the row and column conditions of an input matrix, and the priority order of loading data is controlled. In the operation unit designed based on the two-dimensional systolic array, the non-blocking loading of the data matrix (in the array) is realized with small hardware resource consumption, the hardware resource allocation in different scenarios is realized through region division, the operation execution efficiency is significantly improved, and the control logic design complexity is reduced.

Description

Technical Field

[0001] This invention relates to the processing of a two-dimensional pulsating array, and more particularly to a data processing method and apparatus for a two-dimensional pulsating array. Background Technology

[0002] A systolic array is an array structure. The term "systolic" refers to its working method and process, which resembles the working method and process of the human circulatory system.

[0003] In this array structure, data flows rhythmically between the array's processing units in a predetermined "pipeline" pattern. During the data flow, all processing units process the data flowing through them simultaneously and in parallel, thus achieving a very high parallel processing speed.

[0004] Meanwhile, the pre-defined data flow pattern ensures that all necessary processing is completed as data flows from the array into the processing unit array to the array out of the processing unit array, eliminating the need for re-entry of this data. Furthermore, only the array's "boundary" processing units (i.e., the first row and first column of the array) communicate with the outside world. This allows for an increase in the array's processing speed without increasing its input and output rates. Because the array and processing units have simple and consistent structures, they achieve a high degree of modularity, making them ideal for the design and manufacture of very large-scale integrated circuits.

[0005] The concept of systolic arrays was first proposed by HT Kung in 1982. At the 44th International Symposium on Computer Architecture (ISCA) on June 26, 2017, Google proposed the Tensor Processing Unit (TPU) for accelerating neural network inference on data center servers. It is nearly 15-30 times faster than CPUs and GPUs on servers.

[0006] Figure 1a This is a traditional computing system model. A processing element (PE) reads data from memory, processes it, and then writes it back to memory. The biggest problem with this system is that the speed of data access is often much lower than the speed of data processing. Therefore, the overall system processing power (MOPS, operations per second) is largely limited by memory access capabilities. This problem has been one of the most important topics in computer architecture research for many years, and can be considered a major driving force behind processor and memory design. The systolic architecture uses a very simple method: to allow data to flow through the processing unit for as many cycles as possible.

[0007] like Figure 1b As described, the first data enters the first process controller (PE), is processed, and then passed to the next PE, while the second data enters the first PE. This process continues until the first data reaches the last PE, having been processed multiple times. Therefore, the systolic architecture effectively reuses input data multiple times. This allows it to achieve high computational throughput with relatively low memory bandwidth consumption. Of course, the systolic architecture also offers other advantages, such as modular design for easy expansion, simple and regular data and control flow, use of simple and uniform cells, avoidance of global broadcasting and fan-in, and fast response time.

[0008] In summary, the pulse architecture has several characteristics:

[0009] 1) It consists of multiple isomorphic PEs, which can be one-dimensional or two-dimensional, and can be in a serial, array, or tree structure (we see arrays more often now).

[0010] 2) The PE function is relatively simple. The system improves the efficiency of operation by implementing a large number of PEs in parallel.

[0011] 3) PE can only send data to adjacent PE (in some two-dimensional structures, there may also be data channels in the diagonal direction). Data flows "downstream" in a pipeline manner until it flows out of the last PE.

[0012] In summary, the systolic architecture is a very special design, with a simple structure and low implementation cost. However, it has poor flexibility and is only suitable for specific operations.

[0013] Furthermore, the most frequent operation in neural network computation is convolution, which is essentially matrix multiplication. Figure 2 It is a mathematical model of convolution. Figure 3 This is a method provided by HT Kung (broadcast inputs, move results, weights stay): In Figure 3 In this process, the X value is broadcast to each computational unit, the W value is pre-stored in the PE and remains unchanged, while a portion of the result Y is propagated to the right in a pulsating manner between the PE arrays (initially with a value of zero). It is easy to see that after three time steps, the output of the rightmost PE is the first result of the convolution operation of the X and W sequences, and then the Y value will be continuously output.

[0014] A typical example of a two-dimensional pulsating array application is Google's TPU matrix operation unit, such as... Figure 4As shown in the publicly available materials for TPUv1, its matrix operation unit is a typical pulsating array. Weight flows from top to bottom, and Activation data flows from left to right. At the bottom, there are some accumulation units and buffers, mainly used to save part of the results when the Weight or Activation matrix exceeds the range of the matrix operation unit. The control unit actually translates the instructions into control signals, controlling how Weight and Activation are passed into the pulsating array and how they are processed and flow within the pulsating array.

[0015] The characteristics of a systolic array dictate that data must enter sequentially in a pre-arranged order. Therefore, a certain startup time is required to fill the entire matrix each time, often resulting in wasted hardware resources. The startup time can typically be calculated as "number of rows + number of columns - 1" of the systolic array. After the startup time has elapsed, the entire systolic array enters a fully loaded state, achieving maximum throughput.

[0016] It's important to note that when the convolution kernel is too large or there are too many channels, concatenating all the channel weights in a single column would result in an excessively large or distorted systolic array, hindering practical circuit design. In such cases, a segmented computation and end-to-end accumulation approach is often used to address this issue. The system divides the multi-channel weight data into several parts, each suitable for the size of the systolic array. Then, the weights of each part are calculated sequentially, and the results are temporarily stored in a set of accumulators at the bottom of the systolic array. When another set of weight blocks is introduced, the results are accumulated until all weight blocks have been traversed. The accumulators then sum all the results and output the final value.

[0017] Figure 5 The diagram shows a cell in a systolic array. Several registers store weight, activation, and partial multiplication sums from the cells above. Weight propagates downwards and can be stored in the Weight Path Register, held in place, or transferred to the Weight Register for computation. The Weight Register can send data to the multiplier for processing or directly to the cell below; similarly, the Activation Register can send data to the multiplier for processing or directly to the cell to the right. The multiplier output is summed with the value in the Sum In Register and passed to the cell below. All operations and transfers are controlled by control registers (determined by instructions).

[0018] Therefore, the core issue in pulsating array design is how to maintain data loading efficiency and hardware utilization at the highest possible level.

[0019] One of the pain points mentioned above is that data access speed is often much lower than data processing speed. Without special handling, this will cause a lot of pipeline pauses, reducing system performance. At the same time, to reflect the computational efficiency (hardware utilization) of the systolic array, the input data (Weight and Activation) needs to undergo many transformations. For the TPU, this task is handled by the "User Space driver" in the software stack. "It sets up and controls TPU execution, reformats data into TPU order, translates API calls into TPU instructions, and turns them into an application binary." Specific optimization methods are unknown.

[0020] References

[0021] [1] HT Kung, "Why systolic architectures", IEEE Computer, Vol. 15,N°1, pp 37-46, 1982.

[0022] [2] Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer, "EfficientProcessing of Deep Neural Networks: A Tutorial and Survey".

[0023] [3] Norman P. Jouppi, et al. "In-Datacenter Performance Analysis of aTensor Processing Unit", accepted by ISCA 2017. Summary of the Invention

[0024] This invention provides a data processing method and apparatus for a two-dimensional pulsating array, used to solve how to:

[0025] 1) Ensure that the "bubbles" caused by pipeline pauses and the design complexity of the control path are minimized during matrix operations.

[0026] 2) Try to keep the hardware utilization rate at a high level in different scenarios.

[0027] The above two points are the problems that this invention solves with a relatively simple and efficient solution, without adding extra restrictions to the software design or burdening its own control logic.

[0028] The technical solution is as follows:

[0029] A data processing device for a two-dimensional pulsating array includes a data buffer subsystem and a pulsating array. The pulsating array comprises n rows × m columns of cells. Each cell has an internal structure including a weight buffer register, a weight register, an input register, a control register, an accumulation register, a multiplier, and an adder. The data buffer subsystem inputs weight matrix data to the pulsating array through a weight triangulation FIFO module, and the data buffer subsystem inputs activation matrix data to the pulsating array through an input triangulation FIFO module.

[0030] The output of the summation of the product of the cells in n / 2 rows of the pulsating array is connected to the accumulator via a lead wire.

[0031] The m / 2 column of the pulsating array has a data selector at the back end of the cell. The front end of the data selector is connected to the cell of the previous column, and the back end is connected to the cell of the next column, which is used to realize the transmission of activation from left to right. The data selector is also connected to the activation data entry of the input triangulation FIFO module, which is used to realize the activation of the receiving data buffer subsystem.

[0032] A data processing method for a two-dimensional pulsating array includes the following steps:

[0033] S1: Perform matrix operations. If the number of rows in the Activation matrix is ​​not greater than 1 / 2 of the number of rows n in the systolic array, proceed to step S2. If the number of rows in the Weight matrix is ​​not greater than 1 / 2 of the number of columns m in the systolic array, proceed to step S3.

[0034] S2: When performing operations on two sets of Activation matrices with the same Weight matrix, determine whether the number of rows in both sets of Activation matrices is not greater than 1 / 2 of the number of rows n in the pulsation array. If yes, divide the pulsation array into upper and lower parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations.

[0035] S3: When performing operations on two sets of Weight matrices with the same Activation matrix, determine whether the number of rows in both sets of Weight matrices is not greater than 1 / 2 of the number of columns m in the pulsation array. If so, divide the pulsation array into left and right parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations.

[0036] Furthermore, in step S1, performing matrix operations includes the following steps:

[0037] S11: The first column of the Weight matrix is ​​transposed into the first row by the weight triangulation FIFO module and enters the Weight Path Register in the first row cell of the pulsation array. After the Weight Path Register in the first row cell of the pulsation array is filled with Weight, the first column of the Activation matrix enters the Activation Register in the first column cell of the pulsation array by the input triangulation FIFO module.

[0038] S12: The first column of the Weight matrix, Weight, is moved from the Weight Path Register to the Weight Register, and the new Weight is moved to the empty Weight Path Register;

[0039] S13: The multiplication and accumulation operation between Weight in Weight Register and Activation in Activation Register is performed. After the first row of Cells in the systolic array is completed, the subsequent multiplication and accumulation operations are carried out in the execution pipeline of the data buffer subsystem.

[0040] S14: When the multiplication and accumulation operation of the previous set of Weight matrices and Activation matrices is about to end, update the corresponding Weight Register of the cell that has completed the operation, and pulse the new Activation matrix.

[0041] Furthermore, in step S13, the paths loaded from the data buffer subsystem by the Weight matrix and the Activation matrix are independent of each other, and the pipeline pause / backpressure for handling read conflicts or pulsation waits is restricted within the data buffer subsystem.

[0042] The data buffer subsystem is also designed as a pipeline structure, and each stage can be back-pressed. When data comes out of the data buffer subsystem and enters the corresponding triangulated pulsating FIFO module, the subsequent paths of the data buffer subsystem should not be back-pressed or the pipeline of the data should be paused.

[0043] Furthermore, in step S14, when loading Weight and loading Activation conflict while reading the data buffer during the same set of matrix operations, loading Weight Path Register takes priority.

[0044] In step S14, a conflict occurs when loading the Activation Register of the previous group and loading the Weight Path Register of the next group while reading the data buffer. Therefore, loading the Activation Register of the previous group is executed first.

[0045] The data processing method and apparatus for the two-dimensional pulsating array achieves non-blocking loading of the data matrix (in the array) with relatively small hardware resource overhead in the computing unit designed based on the two-dimensional pulsating array. By dividing the region, hardware resources are allocated under different scenarios, which significantly improves the computing execution efficiency and reduces the complexity of control logic design. Attached Figure Description

[0046] Figure 1a This is a schematic diagram of the traditional computing system.

[0047] Figure 1b This is a schematic diagram of the described pulsating architecture;

[0048] Figure 2 It is a mathematical model of convolution;

[0049] Figure 3 This is a schematic diagram of the operation of the convolution in a systolic architecture;

[0050] Figure 4 This is a schematic diagram of Google's TPU matrix operation unit;

[0051] Figure 5 This is a schematic diagram of one of the cells in the pulsating array;

[0052] Figure 6 This is a schematic diagram of the basic structure of the two-dimensional pulsating array computing unit;

[0053] Figure 7 This is a schematic diagram of the new Activation pulse entering;

[0054] Figure 8 This is a schematic diagram showing the pulse array being processed by dividing it into upper and lower parts;

[0055] Figure 9 This is a schematic diagram showing the pulse array being processed by dividing it into left and right parts;

[0056] Figure 10This is a schematic diagram of the data processing device structure of the two-dimensional pulsating array. Detailed Implementation

[0057] This invention provides a data processing method for a two-dimensional pulsating array, used for loading data during computation by the two-dimensional pulsating array's computing unit. Combined with... Figure 5 and Figure 6 As shown, the two-dimensional systolic array operation unit includes a data buffer subsystem and a systolic array. The systolic array includes n rows × m columns of computational units (cells), where n and m are natural numbers, and n can be the same as m. The internal structure of each computational unit in the systolic array is equipped with a weight path register, a weight register, an input register, a control register, a sum in register, a multiplier, and an adder.

[0058] The data buffer subsystem inputs the weight matrix data, represented by weight, into the systolic array through the weighted triangulation FIFO module. The weight propagates from top to bottom and can be stored in the weight path register, remaining stationary, or transmitted to the weight register for computation. The weight register can send the weight to the multiplier for processing, or it can directly pass it to the weight path register of the cell below.

[0059] The data buffer subsystem inputs the Activation matrix data into the pulsating array through the input triangulation FIFO module. This data is represented by Activation, which propagates from left to right. The Activation Register can send the data to the multiplier for processing or directly pass it to the Activation Register of the right cell.

[0060] The Sum In Register stores the partial multiplication and accumulation sum of the cell above. The output of the multiplier is summed with the value in the Sum In Register and passed to the Sum In Register of the cell below. The control register controls all operations and data transfer within the cell.

[0061] The data processing method for the two-dimensional pulsating array includes the following steps when performing matrix operations:

[0062] S1: Perform matrix operations. If the number of rows in the Activation matrix is ​​not greater than 1 / 2 of the number of rows n in the systolic array, proceed to step S2. If the number of rows in the Weight matrix is ​​not greater than 1 / 2 of the number of columns m in the systolic array, proceed to step S3.

[0063] When performing matrix operations, Weight is loaded before Activation, including the following steps:

[0064] S11: The first column of the Weight matrix is ​​transposed into the first row by the weight triangulation FIFO module and enters the Weight Path Register in the first row cell of the pulsation array. After the Weight Path Register in the first row cell of the pulsation array is filled with Weight, the first column of the Activation matrix enters the Activation Register in the first column cell of the pulsation array by the input triangulation FIFO module.

[0065] S12: The first column of the Weight matrix, Weight, enters WeightRegister from Weight Path Register, and the next round of new Weight can enter the empty Weight Path Register;

[0066] S13: The multiplication and accumulation operation between Weight in Weight Register and Activation in Activation Register can be performed in the execution pipeline of the data buffer subsystem after the first row of Cells in the systolic array is completed (the subsequent multiplication and accumulation operation is performed while loading new Activation).

[0067] The weight matrix and the activation matrix are loaded from the data buffer subsystem through independent paths, respectively via the weight triangulation FIFO module and the input triangulation FIFO module. In order to mask the latency of data buffer reading, data buffer reading can be initiated as early as possible. Pipeline pauses / backpressure for handling read conflicts or pulsation waits should be limited to within the data buffer subsystem.

[0068] The data buffer subsystem is also designed as a pipelined structure, with each stage capable of being backflushed. Once data exits the data buffer subsystem and enters the triangulated pulsating FIFO (weight matrix data exits the data buffer subsystem and enters the weight triangulated pulsating FIFO, and activation matrix data exits the data buffer subsystem and enters the input triangulated pulsating FIFO), subsequent paths in the data buffer subsystem should not backflushed or pause the pipeline for that data.

[0069] S14: As Figure 7 As shown in the figure, the upper part indicates that the multiplication and accumulation operation of the previous set of Weight and Activation matrices is about to end, that is, the Activation data of the Activation matrix has been pulsated through the upper left cell of the figure to complete the calculation. The lower part of the figure indicates that the corresponding cell has finished the operation and the corresponding Weight Register can be updated. At this time, the new Activation matrix can also be pulsated in.

[0070] It is important to note here that there are priorities during data loading and execution, as well as pipeline backpressure in case of conflicts. Logically, it cannot be guaranteed that Activation and Weight can completely avoid data buffer read / write conflicts when reading from the data buffer subsystem. That is, Activation and Weight may issue read requests to the same memory component, or there may be write requests to the lower-level storage unit at the same time. Therefore, it is necessary to handle the corresponding scenarios.

[0071] The first scenario is: Weight matrix loading uses weighted triangulation FIFO pulsating loading, meaning data is read from the data buffer subsystem in whole rows (or columns). Before the Weight PathRegister in the first row of the pulsating array is fully loaded, data buffer read / write conflicts can be waited for. It's important to note that if a conflict occurs between loading Weight and loading Activation during data buffer reads, loading Weight PathRegister takes priority. Once the Weight Path Register in the first row of the pulsating array is fully loaded, subsequent (same batch) Weights are expected to have been completely read from the data buffer subsystem, and loading will not result in conflicts, whether between reading two rows of Weights or between Weight and Activation. This prevents blocking Weight pulsating loading and avoids the risk of data correspondence errors in subsequent matrix multiplication and accumulation operations.

[0072] The second scenario is: when Activation reads data from the data buffer subsystem, it reads one column of data (bit width) from the systolic array per clock cycle, entering the systolic array via an input triangulated FIFO. If a conflict arises between loading the previous ActivationRegister and loading the subsequent Weight Path Register while reading from the data buffer, loading the previous ActivationRegister takes precedence.

[0073] In different application scenarios, the number of rows in the Activation and Weight matrices needs to be considered for efficient utilization of hardware resources. By partitioning the systolic array, the computational throughput can be doubled with existing resources. During operation, the number of rows and columns in the Weight and Activation matrices needs to be determined, including steps S2 and S3.

[0074] S2: When performing operations on the two sets of Activation matrices with the same Weight matrix, determine whether the number of rows in both sets of Activation matrices is not greater than 1 / 2 of the number of rows n in the pulsation array. If yes, divide the pulsation array into upper and lower parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations.

[0075] To optimize scenarios with small rows, if the rows of both Activation matrices are small (no more than n / 2) and are processed with the same Weight matrix, then after transposing each Weight matrix, the calculation of both Activation matrices will only occupy a portion of the systolic array.

[0076] like Figure 8 As shown, the systolic array can be divided into upper and lower parts. Each clock cycle, two activation matrices, no greater than n / 2, are simultaneously read from the data cache subsystem, resulting in a first matrix and a second matrix. These two activation matrices need to be dot-productd using the same weight matrix. The upper part of the systolic array performs operations on the first matrix and the weight matrix, while the lower part performs operations on the second matrix and the weight matrix.

[0077] S3: When performing operations on two sets of Weight matrices with the same Activation matrix, determine whether the number of rows in both sets of Weight matrices is not greater than 1 / 2 of the number of columns m in the pulsation array. If so, divide the pulsation array into left and right parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations.

[0078] To optimize scenarios with small columns, if the rows of both weight matrices are small, the corresponding columns after transposition are all no larger than m / 2, and they are all processed with the same activation matrix. After transposition, the calculation of the activation matrix for each weight matrix only occupies a portion of the systolic array.

[0079] like Figure 9As shown, the systolic array can be divided into left and right parts. Two weight matrices, each no larger than Column / 2, are simultaneously read from the data buffer subsystem, resulting in a third matrix and a fourth matrix. The rows of both the third and fourth matrices are no larger than m / 2. These two weight matrices need to be dot-productd using the same activation matrix. The left half of the systolic array is processed by combining the third matrix and the activation matrix, while the right half is processed by combining the fourth matrix and the activation matrix.

[0080] like Figure 10 As shown, the data processing device for the two-dimensional pulsating array includes a data buffer subsystem pulsating array, a weighted triangulation FIFO module, and an input triangulation FIFO module. The pulsating array is configured with n rows and m columns of cells.

[0081] To achieve vertical segmentation of the systolic array, an additional lead is provided to the accumulation cell for the product summation output of the horizontally centered row of cells. A lead is placed at the bottom of the cell in row n / 2; the upper end of this lead is connected to the adder of the cell above via the accumulation data output, and the lower end is connected to... Figure 4 The accumulator shown is located below the pulsating array.

[0082] To achieve left-right segmentation of the pulsating array, a 2-to-1 MUX (data selector) is configured for the activation entry of the vertically centered column of cells in the pulsating array. A data selector (MUX) is set at the rear end of the cell in column m / 2. The front end of the data selector is connected to the cell in the preceding column and to the activation data entry of the input triangulation FIFO module. The rear end of the data selector is connected to the cell in the following column, so as to enable the transmission of activation from left to right.

[0083] By performing the aforementioned processing on the activation data inlet and accumulated data outlet of the cell at a set position in the pulsating array, the two-dimensional pulsating array can be segmented. The accumulated data outlet refers to the data outlet connected to the adder.

[0084] The hardware resources of the computing unit account for the vast majority of the total area of ​​a computationally intensive processor chip, and the quality of its design directly affects the chip's computing power and cost. The two-dimensional pulsating array data processing device provided by this invention can be applied to the hardware design of arithmetic operation units in general-purpose processors (CPU, GPU, DSP) or artificial intelligence cloud inference / training processor chips, and can significantly improve the efficiency of the computing pipeline and the utilization rate of the computing unit hardware.

[0085] The main beneficial effects of this invention are:

[0086] (1) Ensures that no pipeline interruption occurs during the loading and calculation of the two-dimensional pulsating array Weight, reducing the complexity of the control logic implementation and the risk of computational errors caused by potential data mismatch. Reduces the scenarios of pipeline stalls.

[0087] (2) By adding a small number of logical components, in scenarios where the width of Activation and Weight is small, the computing throughput of the above scenarios can be doubled with existing resources by dividing the two-dimensional pulsation array.

Claims

1. A data processing method for a two-dimensional pulsating array, implemented by a data processing device for a two-dimensional pulsating array, the data processing device comprising a data buffer subsystem and a pulsating array, the pulsating array comprising n rows Each cell contains a weight buffer register, a weight register, an input register, a control register, an accumulation register, a multiplier, and an adder. The data buffer subsystem inputs the weight matrix data to the systolic array through the weight triangulation FIFO module, and the data buffer subsystem inputs the activation matrix data to the systolic array through the input triangulation FIFO module. The data processing method for the two-dimensional systolic array includes the following steps: S1: Perform matrix operations. If the number of rows in the Activation matrix is ​​not greater than 1 / 2 of the number of rows n in the systolic array, proceed to step S2. If the number of rows in the Weight matrix is ​​not greater than 1 / 2 of the number of columns m in the systolic array, proceed to step S3. The matrix operation includes the following steps: S11: The first column of the Weight matrix is ​​transposed into the first row by the weight triangulation FIFO module and enters the Weight Path Register in the first row cell of the pulsation array. After the Weight Path Register in the first row cell of the pulsation array is filled with Weight, the first column of the Activation matrix enters the Activation Register in the first column cell of the pulsation array by the input triangulation FIFO module. S12: The first column of the Weight matrix, Weight, is moved from the Weight Path Register to the Weight Register, and the new Weight is moved to the empty Weight Path Register; S13: The multiplication and accumulation operation between Weight in Weight Register and Activation in Activation Register is performed. After the first row of Cells in the systolic array is completed, the subsequent multiplication and accumulation operations are carried out in the execution pipeline of the data buffer subsystem. S14: When the multiplication and accumulation operation of the previous set of Weight matrices and Activation matrices is about to end, update the corresponding Weight Register of the cell that has completed the operation, and pulse the new Activation matrix; S2: When performing operations on two sets of Activation matrices with the same Weight matrix, determine whether the number of rows in both sets of Activation matrices is not greater than 1 / 2 of the number of rows n in the pulsation array. If yes, divide the pulsation array into upper and lower parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations. S3: When performing operations on two sets of Weight matrices with the same Activation matrix, determine whether the number of rows in both sets of Weight matrices is not greater than 1 / 2 of the number of columns m in the pulsation array. If so, divide the pulsation array into left and right parts and perform the operations separately. Otherwise, go to step S1 to continue performing matrix operations.

2. The data processing method for a two-dimensional pulsating array according to claim 1, characterized in that: In step S13, the paths loaded from the data buffer subsystem by the Weight matrix and the Activation matrix are independent of each other, and the pipeline pause / backpressure for handling read conflicts or pulsation waits is restricted within the data buffer subsystem.

3. The data processing method for a two-dimensional pulsating array according to claim 2, characterized in that: The data buffer subsystem is also designed as a pipeline structure, and each stage can be back-pressed. When data comes out of the data buffer subsystem and enters the corresponding triangulated pulsating FIFO module, the subsequent paths of the data buffer subsystem should not back-press or pause the pipeline of the data.

4. The data processing method for a two-dimensional pulsating array according to claim 1, characterized in that: In step S14, when loading Weight and loading Activation conflict while reading the data buffer during the same set of matrix operations, loading Weight Path Register takes priority.

5. The data processing method for a two-dimensional pulsating array according to claim 1, characterized in that: In step S14, a conflict occurs between loading the Activation Register in the previous group and loading the Weight Path Register in the next group when reading the data buffer. Loading the Activation Register in the previous group takes priority.

6. The data processing method for a two-dimensional pulsating array according to claim 1, characterized in that: The output of the summation of the product of the cells in n / 2 rows of the pulsating array is connected to the accumulator via a lead wire.

7. The data processing method for a two-dimensional pulsating array according to claim 1, characterized in that: The m / 2 column of the pulsating array has a data selector at the back end of the cell. The front end of the data selector is connected to the cell of the previous column, and the back end is connected to the cell of the next column, which is used to realize the transmission of activation from left to right. The data selector is also connected to the activation data entry of the input triangulation FIFO module, which is used to realize the activation of the receiving data buffer subsystem.

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