FPGA digital design verification platform for multi-protocol fast charging chip

Abstract

The application discloses a FPGA digital design verification platform for a multi-protocol fast charging chip, which comprises: a current amplification module which samples and amplifies output current to generate amplified output current; a detection module which generates a current signal and a voltage signal of a device to be charged according to the amplified output current and in combination with voltage detection of a port of the device to be charged; a FPGA data processing module which communicates with the device to be charged according to the voltage signal or the current signal, analyzes a fast charging protocol type, and generates a reference voltage or a maximum current; a comparison module which generates a current comparison result or a voltage comparison result; an isolation module which generates an adjustment signal according to the current comparison result or the voltage comparison result; and an adjustment module which adjusts output current or output voltage so that the adjusted output current or output voltage is adapted to the fast charging protocol type. The verification platform has fast verification speed and reliable results, can shorten the development cycle of the chip, and improve the success rate of chip tape-out.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuit technology, and in particular to an FPGA digital design verification platform for a multi-protocol fast charging chip. Background Art

[0002] With the continuous improvement of the performance of electronic devices and the increasing dependence of people on electronic devices, people's requirements for the charging speed of electronic devices are also getting higher and higher. In recent years, the fast charging protocol has developed rapidly, and new fast charging protocols have continued to emerge in the market. Moreover, the same fast charging protocol version has also had a relatively fast iteration and adjustment. The types of fast charging protocols that have appeared so far include: MTK protocol, QC protocol, PD protocol, PPS protocol, FCP protocol, AFC protocol and VOOC protocol, etc. For power adapter manufacturers, it is a development trend to develop a power adapter that can identify and support multiple types of fast charging protocols. Among them, the development of multi-protocol fast charging chips is a relatively important part of power adapter development.

[0003] During the chip design and development process, it is often necessary to verify its digital design. This involves simulating the chip's functions and application environment to verify whether the chip's overall functionality and performance can achieve the expected results. As power adapters support more and more fast-charging protocols, the data processing methods within the multi-protocol fast-charging chip will become increasingly complex. Therefore, when verifying the digital design of a multi-protocol fast-charging chip, a verification platform with fast verification speed and reliable verification results is required to shorten the development cycle of the multi-protocol fast-charging chip and improve the chip's tape-out success rate. Summary of the Invention

[0004] In order to shorten the development cycle of multi-protocol fast charging chips and improve the chip tape-out success rate, this application provides an FPGA digital design verification platform for multi-protocol fast charging chips.

[0005] This application provides an FPGA digital design verification platform for a multi-protocol fast charging chip, using the following technical solutions:

[0006] An FPGA digital design verification platform for a multi-protocol fast charging chip, the verification platform is connected to a device to be charged, and the verification platform includes:

[0007] Current amplification module, detection module, FPGA data processing module, comparison module, isolation module, regulation module, transformer T;

[0008] The current amplification module is used to amplify the output current I of the secondary side of the transformer T. OUT Sample and amplify to generate the amplified output current EN-I OUT ;

[0009] A detection module is used to receive the amplified output current EN-I OUT , generating a current signal of the device to be charged; and also used to detect the voltage value of the port of the device to be charged and generate a voltage signal of the device to be charged;

[0010] An FPGA data processing module is configured to receive a voltage signal or a current signal from the device to be charged, communicate with the device to be charged through the detection module, parse the fast charging protocol type of the device to be charged, and generate a reference voltage CV-REF or a maximum current CC-REF adapted to the fast charging protocol type;

[0011] Comparison module, for receiving the amplified output current EN-I OUT , reference voltage CV-REF and maximum current CC-REF, and obtain the output voltage V of the secondary side of the transformer T OUT ; And according to the maximum current CC-REF value, amplify the output current EN-I OUT value, reference voltage CV-REF value, output voltage V OUT value, generating the current comparison result I result Or the voltage comparison result V result ;

[0012] Isolation module, used to receive the current comparison result I result Or the voltage comparison result V result , according to the current comparison result I result Or the voltage comparison result V result generating a regulation signal;

[0013] The regulating module is used to receive the regulating signal and regulate the output current I according to the regulating signal. OUT value or output voltage V OUT value, so that the regulated output current I OUT Or output voltage V OUT Adapt to the fast charging protocol type of the device to be charged.

[0014] By adopting the above technical solution, this verification platform is centered around the FPGA digital processing module. The FPGA digital processing module obtains the voltage and current signals output by the detection module, analyzes them, and determines the fast-charging protocol type of the device to be charged. The adjustment module then matches the output voltage and current to the device to be charged, enabling fast-charging operations for the device to be charged. This verification platform's clear processing logic and the high processing speed of the FPGA digital processing module enable fast verification, shortening the development cycle of multi-protocol fast-charging chips. Furthermore, the FPGA digital processing module supports multiple programming modifications, resulting in highly reliable verification results and improving the chip's tape-out success rate.

[0015] In a specific embodiment, the verification platform further includes an AD module, and the current amplification module amplifies the output current I after adjustment. OUT Sampling and amplification to generate regulated amplified output current EN-I OUT The AD module receives the adjusted amplified output current EN-I OUT , and obtain the regulated output voltage V OUT and adjust the amplified output current EN-I OUT and the regulated output voltage V OUT Converts the signal into a digital signal and outputs it to the FPGA data processing module; the FPGA data processing module outputs the signal according to the adjusted amplified output current EN-I OUT , regulated output voltage V OUT The current output voltage value and current value are obtained by analysis, and the current output voltage value and current value are fed back to the device to be charged through the detection module.

[0016] By adopting the above technical solution, the current output voltage and current values ​​are fed back to the device to be charged, so that the device to be charged can make corresponding adjustments based on the current output voltage and current values, thereby avoiding excessive deviation between the current output voltage and current values ​​and the requirements of the device to be charged, which may affect the service life of the battery of the device to be charged.

[0017] In a specific embodiment, the detection module includes a D+ / D- detection circuit, a CC line detection circuit, an output current detection circuit and a switching circuit; the D+ / D- detection circuit is used to detect the voltage value of the D+ port and the D- port of the device to be charged; the CC line detection circuit is used to detect the voltage value of the CC1 port or the CC2 port of the device to be charged; the output current detection circuit is used to detect the output current I OUT The switching circuit is used to output different voltage values ​​to the D+ port and D- port of the device to be charged.

[0018] By adopting the above technical solution, the voltage values ​​of multiple ports of the charging device are detected, and the output current I OUT The FPGA data processing module communicates with the device to be charged multiple times by detecting the change in the output voltage value of the switching circuit, thereby improving the accuracy of the FPGA data processing module in judging the fast charging protocol type of the device to be charged.

[0019] In a specific embodiment, the CC line detection circuit includes a first comparator and a second comparator, wherein the non-inverting input terminals of the first comparator and the second comparator are both connected to the CC1 port or the CC2 port of the device to be charged;

[0020] The voltage value of the non-inverting input terminal of the first comparator is controlled by a first enable switch group, which includes a plurality of enable switches connected in parallel, and the enable switch in each path is connected in series with a current source; the voltage value of the inverting input terminal of the first comparator is controlled by a second enable switch group, which includes a plurality of enable switches, and the enable switch in each path is configured with a corresponding voltage;

[0021] The voltage value of the non-inverting input terminal of the second comparator is controlled by a third enable switch group, which includes multiple enable switches connected in parallel, and the enable switch in each path is connected in series with a current source; the voltage value of the inverting input terminal of the second comparator is controlled by a fourth enable switch group, which includes multiple enable switches, and the enable switch in each path is configured with a corresponding voltage.

[0022] By adopting the above technical solution, by closing different enable switches, the output levels of the first comparator and the second comparator will change, so that the FPGA data processing module can detect the voltage of the CC1 port or the CC2 port multiple times, thereby improving the accuracy of the judgment of the voltage of the CC1 port or the CC2 port.

[0023] In a specific implementation scheme, the switching circuit includes multiple enable switches, and the FPGA data processing module controls the closing of each enable switch in the switching circuit to enable the switching circuit to output different voltage values ​​to the D+ port and D- port of the device to be charged.

[0024] By adopting the above technical solution, the FPGA data processing module controls the closing of each enable switch and then controls the voltage value output by the switching circuit, thereby realizing communication between the FPGA data processing module and the device to be charged, with high communication efficiency.

[0025] In a specific implementation scheme, the comparison module includes a DA chip, a third comparator, and a fourth comparator; the DA chip converts the reference voltage CV-REF and the maximum current CC-REF into analog signals, and the third comparator compares the reference voltage CV-REF value with the output voltage V OUT value, generating a voltage comparison result V result The fourth comparator compares the maximum current CC-REF value with the amplified output current EN-I OUT value, generating the current comparison result I result .

[0026] By adopting the above technical solution, the two comparators in the comparison module are used to compare the reference voltage CV-REF value with the output voltage V OUT value, one is used to compare the maximum current CC-REF value with the amplified output current EN-I OUTThe value is clear to the comparison logic of the comparison module circuit, and the comparison logic is not easy to be disordered.

[0027] In a specific implementation, the isolation module is an optical coupling, a magnetic coupling or a capacitive coupling, and the isolation module is connected to the output end of the secondary side of the transformer T through a resistor in series.

[0028] By adopting the above technical solution, the primary side circuit and the secondary side circuit of the transformer T are electrically isolated through the isolation module, and signal transmission can be performed at the same time. The resistor in series can prevent the chip of the isolation module from being damaged due to excessive current, thereby improving the safety of the system.

[0029] In a specific implementation, the communication between the FPGA data processing module and the comparison module and the AD module adopts an I2C communication mode.

[0030] By adopting the above technical solution, the I2C communication mode can be implemented only by using one data line and one clock line, thereby optimizing the space of the multi-protocol fast charging chip. The I2C communication mode has low power consumption and strong anti-interference capability, thereby improving the performance of the verification platform.

[0031] In summary, the technical solution of the present application has at least the following beneficial technical effects:

[0032] 1. The FPGA digital design verification platform can detect and analyze the fast charging protocol type of the device to be charged, control the output voltage or output current to match the device to be charged, and realize the fast charging operation of the device to be charged. The verification speed of the verification platform is fast, the development cycle of the multi-protocol fast charging chip is shortened, the verification result is reliable, the chip tape-out success rate is improved, and the chip tape-out success rate reaches more than 90%. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 FIG. 1 is a whole circuit diagram of an FPGA digital design verification platform for a multi-protocol fast charging chip in an embodiment of the present application.

[0034] Figure 2 FIG. 2 is a circuit diagram of a detection module 2 in an embodiment of the present application.

[0035] Figure 3 FIG. 3 is a circuit diagram of an FPGA digital processing module 3 in an embodiment of the present application.

[0036] Figure 4 FIG. 4 is a circuit diagram of a comparison module 4 in an embodiment of the present application.

[0037] Figure 5 FIG. 5 is a circuit diagram of an isolation module 5 in an embodiment of the present application.

[0038] Figure 6It is a circuit diagram of the AD module 7 in the embodiment of the present application.

[0039] Description of reference numerals:

[0040] 1. Current amplification module; 2. Detection module; 21. D+ / D- detection circuit; 211. Fifth comparator; 212. Sixth comparator; 213. Seventh comparator; 214. Eighth comparator; 215. Ninth comparator; 216. Tenth comparator; 217. Eleventh comparator; 218. Twelfth comparator; 22. CC line detection circuit; 221. First comparator; 222. Second comparator; 23. Output current detection circuit; 231. Thirteenth comparator; 232. Fourteenth comparator; 233. Fifteenth comparator; 24. Switching circuit; 3. FPGA digital processing module; 4. Comparison module; 41. DA chip; 42. Third comparator; 43. Fourth comparator; 5. Isolation module; 51. Optocoupler; 6. Regulation module; 7. AD module; 71. AD chip. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0042] This application discloses an FPGA digital design verification platform for multi-protocol fast charging chips, such as Figure 1 As shown, ports 1 and 2 of the transformer T are connected to the primary circuit, and ports 3 and 4 of the transformer T are connected to the secondary circuit. The secondary circuit of the transformer T is connected to the device to be charged, and the device to be charged is powered by the output end of the secondary side of the transformer T.

[0043] Port 1 and port 2 of the transformer T are connected to the regulating module 6. Since the ratio of the primary output voltage of the transformer T to the secondary output voltage is the turns ratio of the primary coil of the transformer T to the secondary coil, the regulating module 6 changes the primary output voltage value of the transformer T by using this characteristic of the transformer T, so as to realize the secondary output voltage V OUT and the secondary output current I OUT of adjustment.

[0044] Port 3 of transformer T is connected in series with diode D1, the anode of diode D1 is connected to port 3, the cathode of diode D1 is connected to the device to be charged, the cathode of diode D1 is also connected to the anode of capacitor C1, and the cathode of capacitor C1 is connected to port 4 of transformer T. Diode D1 is used to OUT The AC power is rectified into DC power, and then the rectified DC power is filtered by capacitor C1 to make the voltage output to the device to be charged more stable.

[0045] In this application, the operation process of the FPGA digital design verification platform is as follows:

[0046] S1: The current amplification module 1 includes an amplifier. The two input terminals of the amplifier are connected to the two ends of the resistor R2, and the output current I OUT The sample is sampled and amplified according to the preset multiple to generate the amplified output current EN-I OUT .

[0047] Optionally, the above preset multiple is 50 times.

[0048] S2: Detection module 2 receives the amplified output current EN-I output by current amplifier module 1 OUT , generating a current signal of the device to be charged; the detection module 2 is also connected to multiple ports of the device to be charged, detects the voltage values ​​of multiple ports, and generates a voltage signal of the device to be charged.

[0049] The detection module 2 includes a D+ / D- detection circuit 21, a CC line detection circuit 22, an output current detection circuit 23 and a switching circuit 24; the D+ / D- detection circuit 21 is used to detect the voltage values ​​of the D+ port and the D- port of the device to be charged; the CC line detection circuit 22 is used to detect the voltage value of the CC1 port or the CC2 port of the device to be charged; the output current detection circuit 23 is used to detect the output current I OUT switching circuit 24 is used to output different voltage values ​​to the D+ port and D- port of the device to be charged.

[0050] like Figure 2 As shown, the D+ / D- detection circuit 21 includes a fifth comparator 211, a sixth comparator 212, a seventh comparator 213, an eighth comparator 214, a ninth comparator 215, a tenth comparator 216, an eleventh comparator 217, and a twelfth comparator 218; the non-inverting input terminals of the fifth to eighth comparators 211 to 214 are connected to the D+ port of the device to be charged, and the inverting input terminals are configured with different voltage values ​​for comparing the voltage value of the D+ port of the device to be charged and outputting the voltage comparison result of the D+ port to the FPGA digital processing module 3; the non-inverting input terminals of the ninth to twelfth comparators 215 to 218 are connected to the D- port of the device to be charged, and the inverting input terminals are configured with different voltage values ​​for comparing the voltage value of the D- port of the device to be charged and outputting the voltage comparison result of the D- port to the FPGA digital processing module 3.

[0051] Optionally, the voltage values ​​configured for the inverting input terminals of the fifth to eighth comparators 211 to 214 are 2.9 V, 2.1 V, 2.0 V, and 0.325 V, respectively. The voltage values ​​configured for the inverting input terminals of the ninth to twelfth comparators 215 to 218 are 2.9 V, 2.1 V, 2.0 V, and 0.325 V, respectively.

[0052] The CC line detection circuit 22 includes a first comparator 221 and a second comparator 222. The non-inverting input of the first comparator 221 is connected to the CC1 port or CC2 port of the device to be charged (the interface of the device to be charged supports both forward and reverse insertion. During forward insertion, the non-inverting input of the first comparator 221 is connected to the CC1 port of the device to be charged, and during reverse insertion, the input of the first comparator 221 is connected to the CC2 port of the device to be charged). The voltage value of the non-inverting input of the first comparator 221 is controlled by a first enable switch group, which includes multiple enable switches connected in parallel, each of which is connected in series with a current source. The voltage value of the inverting input of the first comparator 221 is controlled by a second enable switch group, which includes multiple enable switches, each of which is configured with a corresponding voltage. The first comparator 221 and the second comparator 222 are used to compare the voltage values ​​of the CC1 port or CC2 port of the device to be charged and output the voltage comparison results of the CC1 port or CC2 port to the FPGA digital processing module 3.

[0053] In one embodiment of the present application, a first enabling switch group includes three parallel enabling switches K1, K2, and K3, each connected in series with a current source. A second enabling switch group also includes three enabling switches K1, K2, and K3, each configured with a corresponding voltage. Closing different enabling switches can change the voltage values ​​at the non-inverting and inverting inputs of the first comparator 221.

[0054] Optionally, the currents of the three current sources of the first enabling switch group from left to right are set to 80uA, 180uA, and 330uA respectively; the three configuration voltages of the second enabling switch group K1, K2, and K3 are set to 1.6V, 1.6V, and 2.6V respectively.

[0055] The non-inverting input of the second comparator 222 is connected to the CC1 port or CC2 port of the device to be charged (the principle is the same as that described above for the first comparator 221). The voltage value of the non-inverting input of the second comparator 222 is controlled by the third enabling switch group, which includes multiple enabling switches connected in parallel, and the enabling switches in each path are connected in series with a current source. The voltage value of the inverting input of the second comparator 222 is controlled by the fourth enabling switch group, which is composed of multiple enabling switches, and the enabling switches in each path are configured with a corresponding voltage.

[0056] In one embodiment of the present application, the third enabling switch group includes three parallel enabling switches K1, K2, and K3, each connected in series with a current source. The fourth enabling switch group also includes three enabling switches K1, K2, and K3, with each enabling switch configured to a corresponding voltage. Closing different enabling switches can change the voltage values ​​at the non-inverting input and the inverting input of the second comparator 222.

[0057] Optionally, the currents of the three current sources of the third enabling switch group from left to right are set to 80uA, 180uA, and 330uA respectively; the three configuration voltages of the fourth enabling switch group K1, K2, and K3 are set to 0.2V, 0.4V, and 0.8V respectively.

[0058] In one embodiment of the present application, the output current detection circuit 23 includes a thirteenth comparator 231, a fourteenth comparator 232, and a fifteenth comparator 233. The non-inverting input terminals of the thirteenth comparator 231 to the fifteenth comparator 233 are connected to the output terminal of the current amplification module 1 to obtain the amplified output current EN-I OUT The inverting input terminals of the thirteenth comparator 231 to the fifteenth comparator 233 are configured with different voltage values, and the output terminals of the thirteenth comparator 231 to the fifteenth comparator 233 output the current comparison results to the FPGA digital processing module 3.

[0059] Optionally, the voltage values ​​configured at the inverting input terminals of the thirteenth to fifteenth comparators 231 to 233 are 0.15V, 0.125V, and 0.065V, respectively.

[0060] In one embodiment of the present application, the switching circuit 24 includes an enable switch K-apple, an enable switch K-samsng, an enable switch K-bc12, an enable switch K-HW, an enable switch K-dat-lkg, resistors R5, R6, R7, and R8. When different enable switches in the switching circuit 24 are closed, the switching circuit 24 outputs different voltage values ​​to the D+ port and D- port of the device to be charged. The specific connections of the switching circuit 24 are as follows:

[0061] One end of resistor R5 is configured with a voltage value, and the other end of resistor R5 outputs the voltage value to the D+ port of the device to be charged through a series enable switch K-apple. One end of resistor R6 is configured with another voltage value, and resistor R6 outputs the voltage value to the D- port of the device to be charged through a series enable switch K-samsng. An enable switch K-bc12 is connected between enable switch K-apple and enable switch K-samsng. One end of enable switch K-samsng is grounded through a series resistor R7 and a series enable switch K-HW. One end of enable switch K-apple is grounded through a series resistor R8 and a series enable switch K-dat-lkg.

[0062] Optionally, the voltage value configured at one end of the resistor R5 is 2.7V, and the voltage value configured at one end of the resistor R6 is 1.2V.

[0063] S3: FPGA data processing module 3 receives the voltage signal or current signal of the device to be charged output by the detection module 2, and communicates with the device to be charged through the detection module 2, parses the fast charging protocol type of the device to be charged, and generates a reference voltage CV-REF or maximum current CC-REF adapted to the fast charging protocol type.

[0064] Among them, the voltage signal is the voltage comparison result of the D+ port and the voltage comparison result of the D- port output by the D+ / D- detection circuit 21, and the voltage comparison result of the CC1 port or the CC2 port output by the CC line detection circuit 22; the current signal is the output current comparison result output by the output current detection circuit 23.

[0065] The FPGA data processing module 3 closes the corresponding enable switch in the switching circuit 24 according to the voltage signal of the device to be charged, so that the switching circuit 24 outputs different voltage values ​​to the D+ port and D- port of the device to be charged, and communicates with the device to be charged; the device to be charged receives the voltage value output by the switching circuit 24, thereby changing the voltage value of the D+ port, D- port or CC1 port or CC2 port; the detection module 2 detects again, and generates a voltage signal and a current signal again to output to the FPGA data processing module 3. The FPGA data processing module 3 can parse the fast charging protocol type of the device to be charged, and generate a reference voltage CV-REF or a maximum current CC-REF adapted to the fast charging protocol type.

[0066] Alternatively, the FPGA data processing module 3 continuously receives the current signal of the device to be charged multiple times, that is, continuously receives the current signal output by the current detection circuit 23 multiple times, so as to parse out the fast charging protocol type of the device to be charged and generate a reference voltage CV-REF or maximum current CC-REF adapted to the fast charging protocol type.

[0067] In particular, the FPGA data processing module 3 does not output the reference voltage CV-REF and the maximum current CC-REF at the same time.

[0068] S4: Comparison module 4, used to receive the amplified output current EN-I output by the current amplifier module 1 OUT , and receive the reference voltage CV-REF and maximum current CC-REF output by the FPGA data processing module 3, and obtain the output voltage V of the secondary side of the transformer T OUT ; Comparison module 4 amplifies the output current EN-I according to the maximum current CC-REF value OUTvalue, reference voltage CV-REF value, output voltage V OUT value, generating the current comparison result I result Or the voltage comparison result V result .

[0069] In one embodiment of the present application, Figure 4 As shown, the comparison module 4 includes a DA chip 41, a third comparator 42, a fourth comparator 43, a resistor R3, a resistor R4, a diode D2, and a diode D3. The DA chip 41 is connected to the output end of the FPGA data processing module 3 to convert the reference voltage CV-REF and the maximum current CC-REF into analog signals. The non-inverting input end of the third comparator 42 receives the reference voltage CV-REF output by the DA chip 41, and the inverting input end of the third comparator 42 is connected to the secondary output end of the transformer T through a series resistor R3. The other end of the resistor R3 is grounded through a series resistor R4. The inverting input end of the third comparator 42 obtains the output voltage V OUT The output terminal of the third comparator 42 is connected to the cathode of the diode D2. The third comparator 42 compares the reference voltage CV-REF with the output voltage V OUT value, generating a voltage comparison result V result , output to the isolation module 5 through the diode D2. The non-inverting input terminal of the fourth comparator 43 receives the maximum current CC-REF output by the DA chip 41, and the inverting input terminal of the fourth comparator 43 is connected to the output terminal of the amplifier module 1 to obtain the amplified output current EN-I OUT The output end of the fourth comparator 43 is connected to the cathode of the diode D3. The fourth comparator 43 compares the maximum current CC-REF value with the amplified output current EN-I OUT value, generating the current comparison result I result , and output to the isolation module 5 through the series diode D3.

[0070] Among them, when the output voltage V OUT When the output voltage V OUT When the amplified output current EN-I is less than the reference voltage CV-REF, the third comparator 42 outputs a high level. OUT When the current CC-REF is greater than the maximum current, the fourth comparator 43 outputs a low level. OUT When the current CC-REF is less than the maximum current CC-REF, the fourth comparator 43 outputs a high level.

[0071] In particular, since the FPGA data processing module 3 does not output the reference voltage CV-REF and the maximum current CC-REF at the same time, the third comparator 42 and the fourth comparator 43 will not output comparison results at the same time.

[0072] In particular, the communication method between the DA chip and the FPGA data processing module 3 is I2C communication.

[0073] S5: Isolation module 5, used to receive the current comparison result I output by comparison module 4 result Or the voltage comparison result V result , according to the current comparison result I result Or the voltage comparison result V result Generate a conditioning signal.

[0074] The isolation module 5 is an optical coupler, a magnetic coupler or a capacitive coupler.

[0075] In one embodiment of the present application, the isolation module 5 is an optical coupler 51, such as Figure 5 As shown, the optocoupler 51 includes a light-emitting diode D4 and a phototransistor Q1, wherein both ends of the phototransistor Q1 are connected to the regulating module 6, and the anode of the light-emitting diode D4 is connected to the cathode of the diode D1 through the series resistor R1, for receiving the output voltage V of the output end of the secondary circuit of the transformer T. OUT The cathode of the light-emitting diode D4 is connected to the anode of the diode D2, and the cathode of the light-emitting diode D4 is connected to the anode of the diode D3. When the third comparator 42 or the fourth comparator 43 outputs a high level, the light-emitting diode D4 is not turned on and does not emit light, and the phototransistor Q1 has no current; when the third comparator 42 or the fourth comparator 43 outputs a low level, the light-emitting diode D4 is turned on and emits light, and the phototransistor Q1 changes its own current by sensing the light emitted by the light-emitting diode D4.

[0076] S6: Adjustment module 6, used to receive the adjustment signal output by the isolation module 5 and adjust the output current I according to the adjustment signal OUT value or output voltage V OUT value, so that the regulated output current I OUT Or output voltage V OUT Adapt to the fast charging protocol type of the device to be charged. Specifically:

[0077] The adjustment module 6 can determine the output voltage V according to the current change of the phototransistor Q1. OUT The value and the reference voltage CV-REF value, or the amplified output current EN-I OUT The value and the maximum current CC-REF value, the regulating module 6 can realize the output voltage V of the secondary side of the transformer T by controlling the output voltage value of the primary side of the transformer T. OUT and the secondary output current I OUT of adjustment.

[0078] S7: The output current I after the current amplifier module 1 is adjusted OUTThe sample is sampled and amplified according to the preset multiple to generate the adjusted amplified output current EN-I OUT AD module 7 is connected to the output terminal of the current amplifier module 1, and receives the adjusted amplified output current EN-I OUT The AD module 7 is also connected to the secondary output terminal of the transformer T to obtain the regulated output voltage V OUT ; AD module 7 will adjust the amplified output current EN-I OUT and the regulated output voltage V OUT Converted into digital signal and output to FPGA data processing module 3; FPGA data processing module 3 amplifies the output current EN-I according to the adjustment OUT , regulated output voltage V OUT , analyze and obtain the current output voltage and current values, and feed back the current output voltage and current values ​​to the device to be charged through the D+ port, D- port or CC1 port / CC2 port connected to the device to be charged by the detection module 2, so that the device to be charged can make corresponding adjustments to avoid excessive deviation between the current output voltage and current values ​​and the requirements of the device to be charged, which may affect the service life of the battery of the device to be charged.

[0079] The AD module 7 includes an AD chip 71 .

[0080] In particular, the communication method between the AD module 7 and the FPGA data processing module 3 is I2C communication.

[0081] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. An FPGA digital design verification platform for a multi-protocol fast charging chip, the verification platform is connected to the device to be charged, characterized in that: The verification platform includes: Current amplification module (1), detection module (2), FPGA data processing module (3), comparison module (4), isolation module (5), regulation module (6), transformer T; The current amplifying module (1) is used to amplify the output current I of the secondary side of the transformer T. OUT Sample and amplify to generate the amplified output current EN-I OUT ; Detection module (2), used for receiving the amplified output current EN-I OUT , generating a current signal of the device to be charged; and also used to detect the voltage value of the port of the device to be charged and generate a voltage signal of the device to be charged; An FPGA data processing module (3) is used to receive a voltage signal or a current signal of the device to be charged, communicate with the device to be charged through the detection module (2), parse out a fast charging protocol type of the device to be charged, and generate a reference voltage CV-REF or a maximum current CC-REF adapted to the fast charging protocol type; Comparison module (4), used for receiving the amplified output current EN-I OUT , reference voltage CV-REF and maximum current CC-REF, and obtain the output voltage V of the secondary side of the transformer T OUT ; And according to the maximum current CC-REF value, amplify the output current EN-I OUT value, reference voltage CV-REF value, output voltage V OUT value, generating the current comparison result I result Or the voltage comparison result V result ; An isolation module (5) is used to receive the current comparison result I result Or the voltage comparison result V result , according to the current comparison result I result Or the voltage comparison result V result generating a regulation signal; A regulating module (6) is used to receive the regulating signal and regulate the output current I according to the regulating signal. OUT value or output voltage V OUT value, so that the regulated output current I OUT Or output voltage V OUT Adapt to the fast charging protocol type of the device to be charged; The detection module (2) comprises a D+ / D- detection circuit (21), a CC line detection circuit (22), an output current detection circuit (23) and a switching circuit (24); the D+ / D- detection circuit (21) is used to detect the voltage values ​​of the D+ port and the D- port of the device to be charged; the CC line detection circuit (22) is used to detect the voltage value of the CC1 port or the CC2 port of the device to be charged; the output current detection circuit (23) is used to detect the output current IOUT value; The CC line detection circuit (22) comprises a first comparator (221) and a second comparator (222), wherein the non-inverting input terminals of the first comparator (221) and the second comparator (222) are both connected to the CC1 port or the CC2 port of the device to be charged; The voltage value of the non-inverting input terminal of the first comparator (221) is controlled by a first enabling switch group, the first enabling switch group comprising a plurality of enabling switches connected in parallel, the enabling switches in each path being connected in series with a current source; the voltage value of the inverting input terminal of the first comparator (221) is controlled by a second enabling switch group, the second enabling switch group comprising a plurality of enabling switches, the enabling switches in each path being configured with a corresponding voltage; The voltage value of the non-inverting input terminal of the second comparator (222) is controlled by a third enabling switch group, the third enabling switch group including multiple enabling switches connected in parallel, the enabling switches in each path being connected in series with a current source; the voltage value of the inverting input terminal of the second comparator (222) is controlled by a fourth enabling switch group, the fourth enabling switch group including multiple enabling switches, the enabling switches in each path being configured with a corresponding voltage; The FPGA data processing module (3) closes the corresponding enabling switch in the switching circuit (24) according to the voltage signal of the device to be charged, so that the switching circuit (24) outputs different voltage values ​​to the D+ port and the D- port of the device to be charged.

2. The FPGA digital design verification platform for a multi-protocol fast charging chip according to claim 1, characterized in that: The verification platform further comprises an AD module (7), and the current amplification module (1) amplifies the regulated output current I OUT Sampling and amplification to generate regulated amplified output current EN-I OUT The AD module (7) receives the adjusted amplified output current EN-I OUT , and obtain the regulated output voltage V OUT and adjust the amplified output current EN-I OUT and the regulated output voltage V OUT Converted into a digital signal and output to the FPGA data processing module (3); the FPGA data processing module (3) outputs the regulated amplified output current EN-I OUT , regulated output voltage V OUT The current output voltage value and current value are obtained by analysis, and the current output voltage value and current value are fed back to the device to be charged through the detection module (2).

3. The FPGA digital design verification platform for a multi-protocol fast charging chip according to claim 1, characterized in that: The switching circuit (24) includes a plurality of enabling switches, and the FPGA data processing module (3) controls the closing of each enabling switch in the switching circuit (24) so ​​that the switching circuit (24) outputs different voltage values ​​to the D+ port and the D- port of the device to be charged.

4. The FPGA digital design verification platform for a multi-protocol fast charging chip according to claim 1, characterized in that: The comparison module (4) comprises a DA chip (41), a third comparator (42), and a fourth comparator (43); the DA chip (41) converts the reference voltage CV-REF and the maximum current CC-REF into analog signals, and the third comparator (42) compares the reference voltage CV-REF value with the output voltage V OUT value, generating a voltage comparison result V result The fourth comparator (43) compares the maximum current CC-REF value with the amplified output current EN-I OUT value, generating the current comparison result I result .

5. The FPGA digital design verification platform for a multi-protocol fast charging chip according to claim 1, characterized in that: The isolation module (5) is an optical coupler, a magnetic coupler or a capacitive coupler, and the isolation module (5) is connected to the output end of the secondary side of the transformer T via a resistor connected in series.

6. The FPGA digital design verification platform for a multi-protocol fast charging chip according to claim 2, characterized in that: The communication between the FPGA data processing module (3), the comparison module (4) and the AD module (7) all adopts the I2C communication mode.

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