Circuit structure and chip based on 9t-sram, in- memory boolean logic and multiply-accumulate operation

Abstract

The present application relates to the field of integrated circuit design, especially to the circuit structure of in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM and chip, the circuit structure of the present application includes computing unit, redundant biasing unit, sensitive amplifier SA, the circuit structure of the present application utilizes redundant biasing unit to carry out auxiliary calculation according to the basic operation result of computing unit, and is output through sensitive amplifier SA, saves the large area expense of connecting ADC analog-digital conversion circuit, realizes the Boolean logic operation and multiply-accumulate operation of in-memory, guarantees the independence of storage data, improves the stability of unit, also makes the operation efficiency greatly improve, and the circuit structure of the present application is based on 9T-SRAM, can guarantee the independence of data during operation, and the anti-interference ability is also good.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and particularly relates to a circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM and a chip. BACKGROUND

[0002] The expansion of artificial intelligence technology to multiple types of devices for use has increasingly high requirements for computing efficiency and energy consumption. In the traditional von Neumann architecture, the operation module and the memory are separated, and when data is needed, it needs to be read from the memory to the operation module. The current operation module development process has far exceeded the development process of memory access speed, and a large amount of running time and power consumption is used for data access, and the actual part used for operation is very small. For example, the existing 9T-SRAM applied to Boolean logic generally needs to connect the reference voltage to the sensitive amplifier SA or use the ADC analog-digital conversion circuit, which causes high energy consumption and large area overhead. Similarly, when performing multiply-accumulate operation, the same problem will occur. SUMMARY

[0003] Therefore, it is necessary to provide a circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM and a chip in view of the problem of high energy consumption and large area overhead of the existing 9T-SRAM when performing Boolean logic and multiply-accumulate operation, so as to realize the in-memory NAND operation logic, NOR operation logic, and column multiply-accumulate operation.

[0004] The present application adopts the following technical solutions:

[0005] In a first aspect, the present application provides a circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM, which is used to realize in-memory NAND operation logic, NOR operation logic, and column multiply-accumulate operation.

[0006] The circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM comprises a calculation unit, a redundant bias unit, and a sensitive amplifier SA.

[0007] The calculation unit is used to perform basic operation. The calculation unit comprises M1 rows and N columns of M1xN 9T-SRAMs, and N is greater than or equal to 1. The redundant bias unit is used to perform auxiliary calculation according to the basic operation result of the calculation unit. The redundant bias unit comprises M2 rows and N columns of M2xN 9T-SRAMs. The calculation unit and the redundant bias unit form an array of (M1+M2) rows and N columns. The 9T-SRAMs in the same row share the same word line WL and the same word line RIN, and the 9T-SRAMs in the same column share the same bit line RBL and the same bit line RBLB.

[0008] The sensitive amplifier SA is provided with N. The sensitive amplifier SA corresponds to the bit line RBL and the bit line RBLB one by one, and outputs results according to the voltage data of the bit line RBL and the bit line RBLB. The bit line RBL is connected with the input end one of the corresponding conversion switch SA, and the bit line RBLB is connected with the input end two of the corresponding conversion switch SA. When the circuit structure carries out NAND operation logic or OR operation logic, M1=2, M2=1; when the circuit structure carries out multiply-accumulate operation, M1 is equal to the number of input data, and M2>1.

[0009] The implementation of the circuit structure for the in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM is according to the method or process of the embodiment of the present disclosure.

[0010] In the second aspect, the present disclosure discloses a chip for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM, which is packaged by using the circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM.

[0011] The implementation of the chip for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM is according to the method or process of the embodiment of the present disclosure.

[0012] Compared with the prior art, the present disclosure has the following beneficial effects:

[0013] The circuit structure of the present disclosure uses the redundant biasing unit to assist in calculation according to the basic operation result of the calculation unit, and outputs through the sensitive amplifier SA, which saves the large area overhead of connecting the ADC analog-digital conversion circuit, realizes the in-memory Boolean logic operation and multiply-accumulate operation, guarantees the independence of the storage data, improves the stability of the unit, and greatly improves the operation efficiency. Moreover, the circuit structure of the present disclosure is based on 9T-SRAM, which can guarantee the independence of the data during operation and has good anti-interference ability. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0015] Figure 1 The structural diagram of the circuit structure for in-memory Boolean logic and multiply-accumulate operation based on 9T-SRAM in the embodiment of the present disclosure;

[0016] Figure 2 The structural diagram of the 9T-SRAM in the embodiment of the present disclosure; Figure 1

[0017] ​Figure 3 for Figure 2 A schematic diagram of dot product operation performed by 9T-SRAM.

[0018] Figure 4 The circuit structure of this embodiment of the invention is shown in the diagram when performing Boolean logic calculations, taking a single column as an example.

[0019] Figure 5 The circuit structure of this embodiment of the invention is shown in the diagram when performing multiplication and accumulation calculations, taking a single column as an example.

[0020] Figure 6 for Figure 4 The linearity and integral nonlinearity results are shown in the figure when the single-column structure has 32 rows. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] See Figure 1 This is a structural diagram of a circuit structure based on 9T-SRAM for in-memory Boolean logic and multiply-accumulate operations. The circuit structure based on 9T-SRAM for in-memory Boolean logic and multiply-accumulate operations includes a calculation unit, a redundancy bias unit, and a sensitive amplifier SA.

[0025] The computing unit is configured to perform basic operations. The computing unit includes M1 rows, N columns of M1 x N 9T-SRAMs; N≥1. The redundant bias unit is configured to perform auxiliary calculation according to the basic operation result of the computing unit. The redundant bias unit includes M2 rows, N columns of M2 x N 9T-SRAMs.

[0026] Referring to Figure 2 , Figure 2 is a structural diagram of the 9T-SRAM. As shown in Figure 2 , the 9T-SRAM includes seven NMOS transistors and two PMOS transistors, the seven NMOS transistors are sequentially denoted as N1-N7, and the two PMOS transistors are sequentially denoted as P1-P2.

[0027] P1, P2 and N1, N2 have a cross-coupled structure, that is, the gate of P1 is electrically connected with the gate of N1, the drain of P1 is electrically connected with the drain of N1, the gate of P2 is electrically connected with the gate of N2, the drain of P2 is electrically connected with the drain of N2, the gate of P1 is electrically connected with the drain of P2, and the gate of P2 is electrically connected with the drain of P1, so that the data of the storage nodes Q, QB is latched. P1, P2 are pull-up tubes, that is, the source of P1 is electrically connected with the source of P2 and connected to VDD, so as to open the power supply path of the Q, QB node pair. N1, N2 are pull-down tubes, that is, the source of N1 is electrically connected with the source of N2 and connected to VSS, so as to open the ground path of the Q, QB node pair.

[0028] The two storage nodes Q and QB are connected with the bit lines BL and BLB through N3 and N4 respectively, and N3 and N4 are controlled by the word line WL. Two bit lines RBL and RBLB are electrically connected with the sources of N5 and N6 respectively, and N5 and N6 are controlled by the storage nodes Q and QB respectively. N1-N4, P1 and P2 constitute a 6T cell as a storage unit.

[0029] More specifically, the connection relationship of each transistor in the 9T-SRAM is as follows:

[0030] The gate of P1 is electrically connected with the gate of N1, the drain of N4, the gate of N6, and the drain of P2, the drain of P1 is electrically connected with the drain of N1, the drain of N3, the gate of N5, and the gate of N2;

[0031] The gate of P2 is electrically connected with the gate of N2, the drain of N3, the gate of N5, and the drain of P1, the drain of P2 is electrically connected with the drain of N2, the drain of N4, the gate of N6, and the gate of N1;

[0032] The gate of N1 is electrically connected with the gate of P1, the drain of P2, the drain of N4, and the gate of N6, the drain of N1 is electrically connected with the drain of P1, the drain of N3, the gate of N5, and the gate of N2;

[0033] The gate of N2 is electrically connected with the gate of P2, the drain of P1, the drain of N3, and the gate of N5, and the drain of N2 is electrically connected with the drain of P2, the drain of N4, the gate of N6, and the gate of N1;

[0034] The drain of N3 is electrically connected with the drain of N1, the gate of N2, and the gate of N5, the gate of N3 is electrically connected with the word line WL, and the source of N3 is electrically connected with the bit line BL;

[0035] The drain of N4 is electrically connected with the drain of N2, the gate of N1, and the gate of N6, the gate of N4 is electrically connected with the word line WL, and the source of N4 is electrically connected with the bit line BLB;

[0036] The gate of N5 is electrically connected with the drain of N3, the drain of N1, and the gate of N2, the source of N5 is electrically connected with the bit line RBL, and the drain of N5 is electrically connected with the drains of N6 and N7;

[0037] The gate of N6 is electrically connected with the drain of N4, the drain of N2, and the gate of N1, the source of N6 is electrically connected with the bit line RBLB, and the drain of N6 is electrically connected with the drains of N5 and N7.

[0038] The drain of N7 is electrically connected with the drains of N5 and N6, the gate of N7 is electrically connected with the word line RIN, and the source of N7 is grounded.

[0039] On the basis of the above-mentioned 9T-SRAM, an array structure is built to realize an in-memory Boolean logic operation and a column-wise multiply-accumulate operation circuit structure. That is, the calculation part and the redundant bias part form an (M1+M2) row and N column array. The 9T-SRAMs located in the same row share the same word line WL and the same word line RIN, and the 9T-SRAMs located in the same column share the same bit line RBL and the same bit line RBLB.

[0040] N sensitive amplifiers SA are provided. The sensitive amplifiers SA correspond to the bit lines RBL and RBLB one by one and output results according to the voltage data of the bit lines RBL and RBLB. The bit line RBL is connected with the input end one of the corresponding conversion switch SA, and the bit line RBLB is connected with the input end two of the corresponding conversion switch SA.

[0041] The circuit structure provided in the embodiment has four working modes, which are an SRAM mode, a dot product operation mode, an in-memory Boolean logic calculation mode, and a column-wise multiply-accumulate calculation mode.

[0042] 1. SRAM mode

[0043] Referring to Figure 1 As far as the structure composed of a single 9T-SRAM and a sensitive amplifier SA is concerned:

[0044] (1) Hold operation: During the storage unit holds data, the word line WL, RIN keeps low level, resulting in N3, N4 being off, the bit line BL, BLB being pre-charged to high level, the internal circuit keeping the initial state, and the circuit not working.

[0045] (2) Write operation

[0046] In the write data stage, the word line WL is high, and the word line RIN is low. If the bit line BL is high and the bit line BLB is low, then '1' is written to the storage node Q through N3; if the bit line BL is low and the bit line BLB is high, then '1' is written to the storage node QB through transistor N4.

[0047] (3) Read operation

[0048] In the read data stage, the word line WL is low, and the word line RIN is high, resulting in N7 being on. If the data stored in the circuit is '0', then "Q=0, QB=1", and the bit line RBLB is discharged to the ground through N6, N7, so that a voltage difference is generated between the bit line RBLB and RBL, and then the data "0" is read through the sense amplifier. If the data stored in the circuit is '1', then "Q=1, QB=0", and the bit line RBL is discharged to the ground through N5, N7, so that a voltage difference is generated between the bit line RBLB and RBL, and then the data "1" is read through the sense amplifier.

[0049] It should be noted that the structure adopts read-write separation operation, and the read data path is not generated on the original bit line BL, BLB, but the data result is generated through the bit line RBL, RBLB, so that the original stored data is not disturbed.

[0050] 2. Dot product operation mode

[0051] Referring to Figure 3 , it is a schematic diagram of performing dot product operation on the 9T-SRAM in Figure 2 . The mode is a dot product operation according to the input of the word line RIN and the weight weight stored in the unit.

[0052] Figure 3 In , H represents high (high level), and L represents low (low level). The word line RIN is used as the data input Input, and the storage nodes Q, QB are used as the weight weight. When RIN is high, Input is "1"; when RIN is low, Input is "0". When the storage node Q=1 and QB=0, weight is "+1"; otherwise, weight is "-1".

[0053] The implementation principle is as follows: when the RIN input is low (i.e. "0"), N7 is in an off state, RBL and RBLB are always in a high level state, at this time, no matter what the value of weight is, the dot product result is "0".

[0054] When the RIN input is high (i.e. "1"), N7 is in an on state; when weight is "+1" (i.e. Q=1, QB=0), RBL will put a unit voltage ΔV to ground through N5 and N7, and the dot product result is "+1"; on the contrary, when weight is "-1" (i.e. Q=0, QB=1), RBLB will put a unit voltage ΔV to ground through N6 and N7, and the dot product result is "-1".

[0055] 3. In-memory Boolean logic calculation mode

[0056] Referring to Figure 4 , when the circuit structure performs NAND operation logic and NOR operation logic, M1=2, M2=1.

[0057] Taking a column as an example, the two 9T-SRAMs of the calculation part are two-row calculation units, which are denoted as A and B, and one 9T-SRAM of the redundant bias part is a redundant row bias unit, which is denoted as C.

[0058] In the pre-charge stage, RBL and RBLB are both high level VDD.

[0059] In any column of the circuit structure, the data stored in A is "1" or "0", the data stored in B is "1" or "0", and the data stored in C is "1" or "0"; in the operation stage, the word line RIN is opened, the bit line RBL puts a unit voltage ΔV to ground through N5 and N7 in the 9T-SRAM storing data "1", and the bit line RBLB puts a unit voltage ΔV to ground through N6 and N7 in the 9T-SRAM storing data "0";

[0060] The voltages after discharging on the bit line RBL and the bit line RBLB are compared by the sensitive amplifier SA, and the logic operation result is output.

[0061] In short, it is to control the opening and closing of the word line RIN, and through the bias of the redundant row part, the NAND and NOR operations are finally realized on RBL and RBLB.

[0062] Specifically:

[0063] (1) The data stored in A is "1", the data stored in B is "1", and the data stored in C is "0", and the output result is "0", otherwise the output result is "1", thus realizing the NAND logic operation.

[0064] For example, if the data stored in A is "1" (i.e. Q=1, QB=0), the data stored in B is "0" (i.e. Q=0, QB=1), and the data stored in C is "0" (i.e. Q=0, QB=1), in the calculation stage, the word line RIN is opened, so that the bit line RBL discharges a unit voltage △V through N5, N7 in A to the ground. The bit line RBLB discharges a unit voltage △V through N6, N7 in B to the ground, and the bit line RBLB discharges a unit voltage △V through N6, N7 in C to the ground, that is, the bit line RBLB discharges a total of 2△V. The voltage on the bit line RBL is VDD-△V, and the voltage on the bit line RBLB is VDD-2△V. Finally, the logic operation result is output as "1" by comparing the voltages on the bit lines RBL and RBLB through the sense amplifier SA.

[0065] The specific truth table of the NAND logic is as follows:

[0066]

[0067] (2) The data stored in A is "0", the data stored in B is "0", and the data stored in C is "1", and the output result is "1", otherwise the output result is "0", which realizes the logic operation of OR-NOT.

[0068] For example, if the data stored in A is "0" (i.e. Q=0, QB=1), the data stored in B is "1" (i.e. Q=1, QB=0), and the data stored in C is "1" (i.e. Q=1, QB=0), in the calculation stage, the word line RIN is opened, so that the bit line RBL discharges a unit voltage △V through N5, N7 in B to the ground, the bit line RBLB discharges a unit voltage △V through N6, N7 in A to the ground, and the bit line RBL discharges a unit voltage △V through N5, N7 in C to the ground, that is, the bit line RBL discharges a total of 2△V. The voltage on the bit line RBL is VDD-2△V, and the voltage on the bit line RBLB is VDD-△V. Finally, the logic operation result is output as "0" by comparing the voltages on the bit lines RBL and RBLB through the sense amplifier SA.

[0069] The specific truth table of the NAND logic is as follows:

[0070]

[0071] 4. Multiplication and accumulation calculation mode

[0072] Referring to Figure 5 , when the circuit structure performs multiplication and accumulation operation, M1 is equal to the number of input data, and M2>1.

[0073] Similarly, take a column as an example, M1 9T-SRAMs of the calculation part are M1 calculation rows, and M2 9T-SRAMs of the redundant bias part are M2 redundant bias rows.

[0074] In the pre-charge phase, the bit lines RBL and RBLB are high voltage VDD, and the word line RIN is low voltage.

[0075] In the operation phase, M1 input data (1 or 0) are loaded through M1 word lines RIN of the calculation part respectively; wherein, the input is "1", and the word line RIN is high voltage; the input is "0", and the word line RIN is low voltage; the calculation part performs dot product operation according to the input data, and stores in the corresponding storage unit, and accumulates voltage on the bit lines RBL and RBLB.

[0076] According to the set judgment standard value D, the redundant bias part performs auxiliary calculation, and continues to accumulate voltage on the bit lines RBL and RBLB.

[0077] The accumulated voltages on the bit lines RBL and RBLB are compared by the sensitive amplifier SA, and the output result is output.

[0078] It should be noted that the judgment standard interval realized by the redundant bias part is [-M2, M2], and D∈[-M2, M2]. If D exceeds the judgment standard interval, it means that the performance of the redundant bias part is insufficient, and needs to be increased.

[0079] Figure 5 Taking M1=24 and M2=8 as an example, the first 24 rows are used as calculation rows, and the last 8 rows are used as redundant bias rows.

[0080] Specifically, assuming that 14 rows of the first 24 rows store weight "+1" (i.e. "Q=1, QB=0"), and the other 10 rows store weight "-1" (i.e. "Q=0, QB=1"), if the input 24 data Input are all "1", the voltage accumulated on the bit line RBL should be 14△V (i.e. the dot product calculation result of the 14 rows is "+14"), and the voltage accumulated on the bit line RBLB should be 10△V (i.e. the dot product calculation result of the other 10 rows is "-10"), and the results of the bit lines RBL and RBLB differ by "+4".

[0081] Suppose that the calculation result needs to be greater than or equal to "+3" to output high voltage "1", otherwise output "0", at this time, the last 8 rows perform auxiliary calculation.

[0082] For the last 8 rows, the achievable judging standard interval is -8 to +8. Since the set judging standard value is "+3", it falls within the interval, thus the last 8 rows only need to achieve that 3△V voltage is additionally accumulated on the bit line RBLB. Specifically, 3 rows in the last 8 rows can be selected to be enabled, i.e. the word lines RIN of the 3 rows are needed to be turned on, and the weights stored in the three rows should be "-1" (i.e. "Q=0, QB=1"). Of course, the number of rows to be enabled in the last 8 rows and the weights stored in the enabled rows can be selected according to requirements.

[0083] In addition, referring to Figure 6 , Figure 6 the linearity of the bit line voltage when the above-mentioned example (32 rows in total) performs the multiply-accumulate calculation, different calculation results represent different voltage values, wherein INL is a mathematical calculation method for auxiliary analysis of the linearity result, and the smaller the INL is, the better the linearity is. According to the curve of Figure 6 , it can be seen that the calculation linearity of the above-mentioned example is good.

[0084] It should be noted that the calculation unit and the redundant bias unit can be selected to be constructed in the existing storage array structure. The existing storage array structure is generally 2 i ×2 i , i>2. In this way, when M1, M2 and N are selected, the corresponding N columns are turned on according to the number of columns of the storage array, and M1 and M2 select and turn on the number of rows according to the specific input.

[0085] In addition, on the basis of the above-mentioned circuit structure of the 9T-SRAM-based storage-internal Boolean logic and multiply-accumulate operation, the embodiment also discloses a chip of the 9T-SRAM-based storage-internal Boolean logic and multiply-accumulate operation, which is packaged by using the above-mentioned circuit structure of the 9T-SRAM-based storage-internal Boolean logic and multiply-accumulate operation. The mode of being packaged into a chip is more conducive to the popularization and application of the circuit structure of the 9T-SRAM-based storage-internal Boolean logic and multiply-accumulate operation.

[0086] The pins of the chip of the 9T-SRAM-based storage-internal Boolean logic and multiply-accumulate operation include: In1 pin, In2 pin, …, In (M1+M2) pin; Out1 pin, Out2 pin, …, Out N pin; BL1 pin, BL2 pin, …, BL N pin; BLB1 pin, BLB2 pin, …, BLB N pin; WL1 pin, WL2 pin, …, WL (M1+M2) pin.

[0087] The In1 pin is electrically connected with the word line RIN of the first row, the In2 pin is electrically connected with the word line RIN of the second row, …, and the In(M1+M2) The pin is electrically connected with the word line RIN of the (M1+M2)th row;

[0088] The Out1 pin is electrically connected with the output end of the SA of the first column, the Out2 pin is electrically connected with the output end of the SA of the second column, …, the Out N The pin is electrically connected with the output end of the sensitive amplifier SA of the Nth column;

[0089] The BL1 pin is electrically connected with the bit line BL of the first column, the BL1 pin is electrically connected with the bit line BL of the first column, …, the BL N The pin is electrically connected with the bit line BL of the Nth column;

[0090] The BLB1 pin is electrically connected with the bit line BLB of the first column, the BLB1 pin is electrically connected with the bit line BLB of the first column, …, the BLB N The pin is electrically connected with the bit line BLB of the Nth column;

[0091] The WL1 pin is electrically connected with the word line WL of the first row, the WL2 pin is electrically connected with the word line WL of the second row, …, the WL (M1+M2) The pin is electrically connected with the word line WL of the (M1+M2)th row.

[0092] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present disclosure.

[0093] The above-described embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that, for ordinary skilled persons in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A circuit architecture for implementing in-memory NAND operation logic, NOR operation logic, and column-wise multiply-accumulate operations based on 9T-SRAM, characterized in that, The circuit structure comprises: a calculation section for performing basic operations; the calculation section includes M 1 row, N a column of M 1 x N 9T-SRAMs; N ≥ 1; A redundant bias unit is used to perform auxiliary calculations based on the basic operation results of the calculation unit; the redundant bias unit includes... M 2 lines N Columns M 2× N Each 9T-SRAM; the computing unit and the redundancy bias unit constitute ( M 1+ M 2) line, N The array of 9T-SRAMs includes: seven NMOS transistors N1~N7 and two PMOS transistors P1~P2; the source of P1 is electrically connected to VDD; the source of P2 is electrically connected to VDD; the source of N1 is electrically connected to the drain of P1 and forms a storage node Q, the gate of N1 is electrically connected to the gate of P1, and the drain of N1 is electrically connected to VSS; the source of N2 is electrically connected to the drain of P2 and forms a storage node QB, the gate of N2 is electrically connected to the gate of P2, and the drain of N2 is electrically connected to VSS; the drain of N3 is electrically connected to the drain of N1 and the gate of N2; the drain of N4 is electrically connected to the gate of N1 and the drain of N2; the gate of N5 is electrically connected to the drain of N1 and the gate of N2. The drain of N3; the gate of N6 is electrically connected to the gate of N1, the drain of N2, and the drain of N4; the drain of N7 is electrically connected to the drain of N5 and the drain of N6; the source of N7 is grounded; the gate of N7 is electrically connected to the word line RIN; the source of N3 is electrically connected to the bit line BL; the source of N4 is electrically connected to the bit line BLB; the gates of N3 and N4 are electrically connected to the word line WL; the source of N5 is electrically connected to the bit line RBL; the source of N6 is electrically connected to the bit line RBLB; wherein, 9T-SRAMs located in the same row share the same word line WL and the same word line RIN, and 9T-SRAMs located in the same column share the same bit line RBL and the same bit line RBLB; and, N a sensitive amplifier SA corresponding to the bit line RBL and RBLB, and outputting results according to the voltage data of the bit line RBL and RBLB; the bit line RBL is connected with the input end one of the corresponding sensitive amplifier SA, and the bit line RBLB is connected with the input end two of the corresponding sensitive amplifier SA; The circuit structure carries out NAND operation logic, or non-operation logic operation, M 1=2, M 2=1; the circuit structure carries out multiplication accumulation operation, M 1 is equal to the number of input data, M 2>1.

2. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 1, wherein, For any column of the circuit structure, During the data retention period, the word line WL, the RIN remains low, N3, N4 is turned off, the bit line BL, BLB is precharged to high level, the circuit internal keeps the initial state, and the circuit does not work; In the data writing stage, the word line WL is high, the word line RIN is low, if the bit line BL is high and the bit line BLB is low, '1' is written to the storage node Q through N3; if the bit line BL is low and the bit line BLB is high, '1' is written to the storage node QB through N4; In the data reading stage, the word line WL is low, RIN is high, and N7 is turned on; if the data stored in the circuit is '0', that is, "Q=0, QB=1", the bit line RBLB is discharged to the ground through N6 and N7, a voltage difference is generated between the bit line RBLB and RBL, and '0' is output through the sensitive amplifier SA; if the data stored in the circuit is '1', that is, "Q=1, QB=0", the bit line RBL is discharged to the ground through N5 and N7, a voltage difference is generated between the bit line RBLB and RBL, and '1' is output through the sensitive amplifier SA.

3. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 2, wherein, The word line RIN serves as data input Input, and the storage nodes Q and QB serve as weight weight; The word line RIN is high, and Input is '1'; The word line RIN is low, Input is '0', weight is '+1' when the storage nodes Q=1 and QB=0, otherwise, weight is '-1'.

4. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 3, wherein, If the word line RIN is low, N7 is in the off state, and the bit lines RBL and RBLB are always in the high level state, at this time, the dot product result is '0' regardless of the value of weight; If the word line RIN is high, N7 is in the on state, when the storage nodes Q=1 and QB=0, the bit line RBL discharges a unit voltage △V to the ground through N5 and N7, and the dot product result is '+1'; when the storage nodes Q=0 and QB=1, the bit line RBLB discharges a unit voltage △V to the ground through N6 and N7, and the dot product result is '-1'.

5. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 1, wherein, When the circuit structure performs NAND operation logic and NOR operation logic, In the precharge stage, the bit lines RBL and RBLB are high VDD; In any column of the circuit structure, the data stored in one 9T-SRAM in the calculation part is '1' or '0', the data stored in another 9T-SRAM is '1' or '0', and the data stored in the 9T-SRAM in the redundant bias part is '1' or '0'; in the operation stage, the word line RIN is opened, the bit line RBL discharges a unit voltage V to the ground through N5 and N7 in the 9T-SRAM storing data '1', and the bit line RBLB discharges a unit voltage V to the ground through N6 and N7 in the 9T-SRAM storing data '0'; The voltages on the bit lines RBL and RBLB after discharging are compared through the sensitive amplifier SA, and the logic operation result is output.

6. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 5, wherein, When the data stored in the 9T-SRAM in the redundancy biasing part is "0", the data stored in the two 9T-SRAMs in the computing part is "1", the output result of the sense amplifier SA is "0", otherwise the output result is "1", realizing the NOR logic operation; When the data stored in the 9T-SRAM in the redundancy biasing part is "1", the data stored in the two 9T-SRAMs in the computing part is "1", the output result of the sense amplifier SA is "0", otherwise the output result is "1", realizing the NOR logic operation.

7. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 6, wherein, When the circuit structure performs the multiply-accumulate operation, In the pre-charge stage, the bit lines RBL and RBLB are high VDD, and the word line RIN is low. In any column of the circuit structure, during the computation phase, M One input data is processed by the computing unit. M One word line RIN is loaded; when the input is "1", word line RIN is high; when the input is "0", word line RIN is low; the calculation unit performs dot product operation based on the input data and accumulates voltage on bit lines RBL and RBL. According to the set judgment standard value D The redundant bias part is assisted to calculate, and the voltage continues to accumulate in the bit line RBL, RBL; The accumulated voltage on the bit lines RBL and RBLB is compared by the sense amplifier SA, and the output result is outputted.

8. The 9T-SRAM based in-memory Boolean logic and multiply-accumulate operation based circuit structure of claim 7, wherein, The judgment standard interval realized by the redundant biasing part is [- M 2, M 2], D ∈[- M 2, M 2]。 9. A chip based on 9T-SRAM-based in-memory Boolean logic and multiply- accumulate operations, characterized by, The circuit structure of the in-memory Boolean logic and the multiply-accumulate operation using the 9T-SRAM as claimed in any one of claims 1-8 is packaged.

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