A method for preparing a battery cell

Abstract

The application discloses a preparation method of a battery piece, comprising the following steps: step S100, providing an N-type silicon piece after texturing, and performing a doping treatment on the front surface of the silicon piece to form a front surface doping layer; step S101, reacting the back surface of the silicon piece after alkali throwing with oxygen in air to generate a first oxide layer; step S102, testing the thickness TH1 of the first oxide layer; step S103, depositing a tunneling oxide layer on the surface of the first oxide layer; step S104, testing the total thickness TH2 of the tunneling oxide layer and the first oxide layer; step S105, calculating the thickness TH3 of the tunneling oxide layer, TH3=TH2-TH1; and step S106, if the thickness TH3 of the tunneling oxide layer is less than 1.2 nm or greater than 2.0 nm in step S105, adjusting the process and re-executing steps S100-S105. Compared with the prior art, the application adds a thickness testing step before depositing the tunneling oxide layer, so that the testing result of the thickness of the tunneling oxide layer is more accurate, and favorable conditions are created for the subsequent production of the battery piece.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a method for preparing a solar cell. Background Technology

[0002] TOPCon is a tunnel oxide passivated contact solar cell technology based on the selective carrier principle. Its cell structure is an N-type silicon substrate cell. A tunnel oxide layer is prepared on the back of the cell, and then a doped polycrystalline silicon layer is deposited. The two together form a passivated contact structure, which effectively reduces surface recombination and metal contact recombination.

[0003] Currently, the commonly used methods for testing the thickness of tunneled oxide layers include:

[0004] One method involves observing the cross-section of the entire solar cell using SEM and directly measuring it using the system's built-in measuring tools. This method requires testing fragments, and the test results often vary from person to person.

[0005] Secondly, it is measured directly using an ellipsometer. This method calculates relative values, and the test results tend to be higher than the actual values. Summary of the Invention

[0006] The purpose of this invention is to provide a method for preparing solar cells to solve the technical problem of inaccurate measurement of the thickness of the tunneling oxide layer in the prior art, and to create favorable conditions for the production of compliant solar cells.

[0007] This invention provides a method for preparing a battery cell, comprising the following steps:

[0008] Step S100: Provide a texturized N-type silicon wafer, and perform doping treatment on the front surface of the silicon wafer to form a front doped layer;

[0009] Step S101: A polished surface is formed on the back surface of the silicon wafer. After alkaline polishing, the back surface of the silicon wafer reacts with oxygen in the air to form a first oxide layer.

[0010] Step S102: Test the thickness TH1 of the first oxide layer;

[0011] Step S103: Deposit a tunneling oxide layer on the surface of the first oxide layer;

[0012] Step S104: Test the total thickness TH2 of the tunneling oxide layer and the first oxide layer;

[0013] Step S105: Calculate the thickness of the tunneling oxide layer TH3 = TH2 - TH1;

[0014] Step S106: In step S105, if the tunneling oxide layer thickness TH3 is less than 1.2 nm or greater than 2.0 nm, then adjust the process and re-execute steps S100-S105 until the tunneling oxide layer thickness TH3 is 1.2-2.0 nm.

[0015] Step S107: Deposit passivation films on the front and back surfaces of the silicon wafer, respectively;

[0016] Step S108: Prepare metal electrodes on the front and back surfaces of the silicon wafer, respectively.

[0017] In the method for preparing a battery cell as described above, preferably, step S103 further includes:

[0018] Step S1031: Ensure that the temperature of the diffusion furnace tubes reaches the set value, with the set temperature range being 500-800℃;

[0019] Step S1032: Place the silicon wafer into the furnace tube;

[0020] Step S1033: Reduce the pressure to the lowest level, test the leak rate, and ensure that the airtightness is qualified;

[0021] Step S1034: Raise the furnace tube temperature to the target value of 550-650℃;

[0022] Step S1035: Stabilize the temperature of each zone of the furnace tube at the target value of 550-650℃;

[0023] Step S1036: Constant temperature high concentration oxidation, maintain for the first time, control the pressure at 700,000-1,000,000 mTorr, control the temperature at the first temperature, and maintain the oxygen flow rate at the first flow rate;

[0024] Step S1037: Remove the residual oxygen from step S1036;

[0025] Step S1038: Cool the furnace tube temperature to room temperature;

[0026] Step S1039: Fill the tube with nitrogen to reduce the pressure difference between the inside and outside of the tube, and then take out the sample to be tested.

[0027] In the method for preparing a battery cell as described above, preferably, the adjustment process in step S106 specifically includes:

[0028] If the tunneling oxide layer thickness TH3 in step S105 is less than 1.2 nm, then the first time is increased, the first temperature is increased, and the first flow rate is increased.

[0029] If the tunneling oxide layer thickness TH3 in step S105 is greater than 2.0 nm, then the first time is reduced, the first temperature is lowered, and the first flow rate is reduced.

[0030] In the method for preparing a solar cell as described above, preferably, in step S103, the tunneling oxide layer is deposited inside a diffusion furnace tube, and the silicon wafer is sent out of the diffusion furnace tube at a preset temperature.

[0031] In the method for preparing a battery cell as described above, preferably, the preset temperature is 20℃-25℃.

[0032] In the method for preparing a solar cell as described above, preferably, in step S104, after the silicon wafer is sent out of the diffusion furnace tube, it is plastic-wound for a preset time to isolate it from air.

[0033] In the method for preparing a battery cell as described above, preferably, the preset time is 20-30 minutes.

[0034] In the method for preparing a solar cell as described above, preferably, in steps S102 and S104, a plurality of silicon wafers are horizontally spaced within a quartz boat, and the thickness data of one of the silicon wafers located in the middle is measured.

[0035] In the method for preparing a battery cell as described above, preferably, in steps S102 and S104, a laser ellipsometer is used to measure the thickness data.

[0036] In the method for preparing a battery cell as described above, preferably, the thickness TH1 of the first oxide layer is 0.4-0.6 nm, and the total thickness TH2 of the tunneling oxide layer and the first oxide layer is 1.7-2.4 nm.

[0037] Compared with the prior art, the present invention adds a thickness measurement step before depositing the tunnel oxide layer, which makes the test results of the tunnel oxide layer thickness more accurate and creates favorable conditions for the subsequent production of solar cells. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of the battery cell provided in an embodiment of the present invention;

[0039] Figure 2 This is a flowchart of the battery cell preparation method provided in the embodiments of the present invention.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Silicon wafer, 2-Front surface, 3-Back surface, 4-First oxide layer, 5-Tunneling oxide layer, 6-Back doped layer, 7-Back passivation layer, 8-Front doped layer, 9-Front passivation layer, 10-First electrode, 11-Second electrode. Detailed Implementation

[0042] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0043] TOPCon (Tunnel Oxide Passivating Contacts) cells are a type of solar cell based on the principle of selective charge carriers using tunneling oxide passivating contacts. Their back side typically employs a structure combining an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer to achieve passivation, preventing direct contact between the metal electrode and c-Si. This helps reduce carrier recombination and facilitates carrier separation and collection.

[0044] The thickness of the tunneling oxide layer is an important parameter. A suitable thickness range can achieve excellent interface passivation and selective collection of charge carriers. Traditional methods for testing the thickness of the tunneling oxide layer ignore the oxide layer thickness before the tunneling oxide layer production process (the silicon wafer surface is more sensitive to the environment after alkaline polishing, and the oxide layer grows faster), resulting in an overestimation of the actual value, which causes problems for the subsequent development of tunneling structures.

[0045] To more accurately measure the thickness of the tunneling oxide layer and obtain better battery conversion efficiency, embodiments of the present invention provide a method for preparing a battery cell. By adding a thickness measurement step before preparing the tunneling oxide layer, the test results of the tunneling oxide layer thickness are more accurate, creating favorable conditions for subsequent battery cell production.

[0046] In the embodiments provided in this application, reference is made to Figure 1 As shown, the prepared solar cell includes:

[0047] A silicon wafer 1 has a front surface 2 and a back surface 3, which are disposed opposite to each other along the thickness direction of the silicon wafer 1. The front surface 2 is the light-receiving surface facing the direction of sunlight irradiation, and the back surface 3 is the surface opposite to the front surface 2. In the embodiments provided in this application, the solar cell is a bifacial cell, and the back surface 3 also serves as a light-receiving surface. The silicon wafer 1 can be, for example, a crystalline semiconductor containing dopants of a first conductivity type. The crystalline semiconductor can be polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon. The embodiments of this invention do not limit the specific type of crystalline semiconductor, and the first conductivity type dopant can be an N-type dopant such as group V elements including phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb), or a P-type dopant such as group III elements including boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0048] The tunneling oxide layer 5 is located on the back surface 3. The tunneling oxide layer 5 is used to passivate the interface of the back surface 3 of the silicon wafer 1, reduce the recombination of charge carriers at the interface, and ensure the transport efficiency of charge carriers.

[0049] In the embodiments provided in this application, the tunneling oxide layer 5 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride. These materials have good interfacial dangling bond passivation and tunneling effects, and the thickness of the tunneling oxide layer 5 is between 0.85 nm and 1.9 nm. Specifically, the thickness of the tunneling oxide layer 5 is 0.85 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 1.9 nm, etc., and of course, other values ​​within the above range are also possible, and are not limited here.

[0050] The tunneling oxide layer 5 allows majority carriers to tunnel into the back doped layer 6 while blocking minority carriers. The majority carriers then undergo lateral transport within the back doped layer 6 and are collected by the first electrode 10. The tunneling oxide layer 5 and the back doped layer 6 form a passivated contact structure, achieving excellent interface passivation and selective carrier collection, reducing carrier recombination, and improving the photoelectric conversion efficiency of the solar cell. It should be noted that the tunneling oxide layer 5 may not actually possess a perfect tunnel barrier, as it may contain defects such as pinholes. This can cause other charge carrier transport mechanisms (e.g., drift, diffusion) to dominate over the tunneling effect.

[0051] A back-side doped layer 6 is disposed on the surface of the tunneling oxide layer 5. In the embodiments provided in this application, the back-side doped layer 6 is formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc., with an N-type dopant. In the embodiments provided in this application, the back-side doped layer 6 is a doped polycrystalline silicon layer, and the first doping element of the doped polycrystalline silicon layer is adapted to the first conductivity type dopant of the silicon wafer 1. In a feasible embodiment, when the silicon wafer 1 is an N-type crystalline silicon wafer 1, the first doping element of the doped polycrystalline silicon layer is phosphorus; when the silicon wafer 1 is a P-type crystalline silicon wafer 1, the first doping element of the doped polycrystalline silicon layer is boron. The thickness of the back-side doped layer 6 is 20nm to 300nm, for example, it can be 20nm, 40nm, 50nm, 80nm, 100nm, 120nm, 150nm, 200nm, 220nm, 250nm, or 300nm. Of course, other values ​​within this range are also possible and are not limited here.

[0052] A back passivation layer 7 is disposed on the back doped layer 6, and the back passivation layer 7 includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer. The back passivation layer 7 can passivate the back surface 3 of the battery, reduce the carrier recombination rate on the back surface 3, and improve the photoelectric conversion efficiency.

[0053] The first electrode 10 penetrates the back passivation layer 7 and forms an electrical contact with it. In some embodiments, the material of the first electrode 10 includes at least one conductive metal material such as silver, aluminum, copper, or nickel. As an optional technical solution of this application, the back passivation layer 7 may have openings to allow the first electrode 10 to pass through and make electrical contact with it, thereby reducing the contact area between the metal electrode and the back passivation layer 7, further reducing the contact resistance, and increasing the open-circuit voltage.

[0054] The front doped layer 8 is located on the front surface 2 of the silicon wafer 1. The second doping element of the front doped layer 8 is opposite to the first conductivity type dopant of the silicon wafer 1. In one feasible embodiment, when the silicon wafer 1 is an N-type crystal silicon wafer 1, the second doping element of the front doped layer 8 is boron; when the silicon wafer 1 is a P-type crystal silicon wafer 1, the second doping element of the front doped layer 8 is phosphorus.

[0055] The front passivation layer 9 is located on the front doped layer 8. The front passivation layer 9 can passivate the front surface 2 of the silicon wafer 1, reduce carrier recombination at the interface, improve carrier transport efficiency, and thus improve the photoelectric conversion efficiency of the solar cell. Optionally, the front passivation layer 9 includes at least one or more of the following stacked structures: silicon oxide layer, silicon nitride layer, aluminum oxide layer, and silicon oxynitride layer.

[0056] The second electrode 11 penetrates the front passivation layer 9 and forms an electrical contact with the front doped layer 8. In some embodiments, the material of the second electrode 11 includes at least one conductive metal material such as silver, aluminum, copper, and nickel.

[0057] Based on the battery cell provided in the above embodiments, between the tunneling oxide layer 5 and the silicon wafer 1, since the surface of the silicon wafer 1 is more sensitive to the environment after alkaline polishing, the oxide layer grows faster, so there will be a first oxide layer 4. The presence of the first oxide layer 4 will affect the measurement of the thickness of the tunneling oxide layer 5.

[0058] Based on this, this application provides a method for preparing a battery cell. After obtaining a tunneling oxide layer 5 of suitable thickness, subsequent processes are performed. Specifically, refer to... Figure 2 As shown, it includes the following steps:

[0059] Step S100: Provide a texturized N-type silicon wafer 1, and perform doping treatment on the front surface 2 of the silicon wafer 1 to form a front doped layer 8. The front doped layer 8 can be part of the silicon wafer 1, that is, a P-type dopant element diffuses into the front surface 2 of the original silicon wafer 1 through a high-temperature diffusion process to form the front doped layer 8. Optionally, the P-type dopant element is boron, and the doping source is boron tribromide or boron trichloride.

[0060] Step S101: A polished surface is formed on the back surface 3 of silicon wafer 1 to create a flat texture, which helps to ensure the uniformity and density of the subsequent tunnel oxide layer 5 deposition. After alkaline polishing, the surface of silicon wafer 1 is more sensitive to the environment and the oxide layer grows faster. The back surface 3 of silicon wafer 1 reacts with oxygen in the air to generate the first oxide layer 4. The first oxide layer 4 has a certain thickness. In the prior art, the existence of the first oxide layer 4 is often ignored when measuring the thickness of the tunnel oxide layer 5, which will lead to inaccurate measurement of the subsequent tunnel oxide layer 5.

[0061] Step S102: Test the thickness TH1 of the first oxide layer 4. In one feasible implementation, the thickness data is measured using a laser ellipsometer. A laser ellipsometer is a device that uses light with a defined polarization state to illuminate a sample and calculates the optical properties (refractive index and film thickness, etc.) of the sample by measuring the polarization state of the reflected light. The structure of the laser ellipsometer and the method for measuring the thickness using the laser ellipsometer can be referred to in the prior art, and will not be described in detail here.

[0062] Step S103: Deposit a tunneling oxide layer 5 on the surface of the first oxide layer 4. In the embodiments provided in this application, the tunneling oxide layer 5 is prepared by any one of the following methods: low-pressure chemical vapor deposition, high-temperature thermal oxidation, nitric acid oxidation, and ozone oxidation.

[0063] Step S104: Test the total thickness TH2 of the tunneling oxide layer 5 and the first oxide layer 4. In one feasible embodiment, after the silicon wafer 1 is sent out of the diffusion furnace tube, it is plastic-sealed for a preset time to isolate air, thereby avoiding interference from oxidation and improving detection accuracy. The total thickness TH2 of the tunneling oxide layer 5 and the first oxide layer 4 is also measured by a laser ellipsometry, which will not be described in detail here.

[0064] Step S105: Calculate the thickness of the tunneling oxide layer 5, TH3 = TH2 - TH1. To improve measurement accuracy and avoid air interference on both sides, several silicon wafers 1 are distributed horizontally in the quartz boat. Select one silicon wafer 1 located in the middle to measure the thickness data. The left and right sides of this silicon wafer 1 are adjacent silicon wafers 1, thereby reducing airflow interference.

[0065] Step S106: In step S105, if the thickness TH3 of the tunneling oxide layer 5 is less than 1.2 nm or greater than 2.0 nm, then after adjusting the process, steps S100-S105 are re-executed until the thickness TH3 of the tunneling oxide layer 5 is 1.2-2.0 nm. In the embodiments provided in this application, the thickness TH1 of the first oxide layer 4 is 0.4-0.6 nm, the total thickness TH2 of the tunneling oxide layer 5 and the first oxide layer 4 is 1.7-2.4 nm, and the thickness TH3 of the tunneling oxide layer 5 is between 1.2-2.0 nm. If the thickness of the tunneling oxide layer 5 is too large, the tunneling effect of most carriers will be affected, and carriers will have difficulty passing through the tunneling oxide layer 5, and the photoelectric conversion efficiency of the battery will gradually decrease. If the thickness of the tunneling oxide layer 5 is too small, it will be detrimental to the tunneling and passivation effects of the tunneling oxide layer 5.

[0066] Step S107: Deposit passivation film layers on the front surface 2 and back surface 3 of the silicon wafer 1 respectively. In the embodiments provided in this application, the passivation film layer on the front surface 2 includes a front passivation layer 9, and the passivation film layer on the back surface includes a back passivation layer 7 and a back doped layer 6. The formation process can refer to the content of the prior art and is not limited here.

[0067] Step S108: Metal electrodes are prepared on the front surface 2 and back surface 3 of the silicon wafer 1 respectively. In the embodiments provided in this application, the metal electrode on the front surface 2 is the first electrode 10, and the first electrode 10 on the back surface 3 is the second electrode 11. The preparation methods of the first electrode 10 and the second electrode 11 can refer to the content of the prior art and are not limited here.

[0068] In the embodiments provided in this application, step S103 specifically further includes:

[0069] Step S1031: Ensure that the temperature of the diffusion furnace tubes reaches the set value, with the set temperature range being 500-800℃;

[0070] Step S1032: Place silicon wafer 1 into the furnace tube;

[0071] Step S1033: Reduce the pressure to the lowest level, test the leak rate, and ensure that the airtightness is qualified;

[0072] Step S1034: Raise the furnace tube temperature to the target value of 550-650℃;

[0073] Step S1035: Stabilize the temperature of each zone of the furnace tube at the target value of 550-650℃;

[0074] Step S1036: Constant temperature high-concentration oxidation, maintaining a first time, controlling the pressure at 700,000-1,000,000 mTorr, controlling the temperature at a first temperature, and maintaining the oxygen flow rate at a first flow rate. This first time, first temperature, and first flow rate are variable parameters, and their specific values ​​will depend on the results measured in step S105. If the thickness TH3 of the tunneling oxide layer 5 in step S105 is less than 1.2 nm, then increase the first time, increase the first temperature, and increase the first flow rate; if the thickness TH3 of the tunneling oxide layer 5 in step S105 is greater than 2.0 nm, then decrease the first time, decrease the first temperature, and decrease the first flow rate. The first time ranges from 100 to 1000 s, the first temperature ranges from 550 to 650°C, and the first flow rate ranges from 10,000 to 50,000 sccm. Within this range, the priority of adjustment is: first temperature > first flow rate > first time, with preference given to adjusting the first temperature to better control the thickness of the tunneling oxide layer 5.

[0075] Step S1037: Remove the residual oxygen from step S1036;

[0076] Step S1038: Cool the furnace tube temperature to room temperature;

[0077] Step S1039: Fill the tube with nitrogen to reduce the pressure difference between the inside and outside of the tube, and take out the sample to be tested. In the embodiments provided in this application, the silicon wafer 1 is sent out of the diffusion furnace tube at a preset temperature. In one feasible embodiment, the preset temperature is 20℃-25℃.

[0078] When the thickness TH3 of the tunneling oxide layer 5 is less than 1.2 nm, N-type dopants can easily penetrate the tunneling oxide layer 5 during the formation of the back doped layer 6, and the tunneling oxide layer 5 cannot play a passivation role. When the thickness of the tunneling oxide layer 5 is 1.2 nm < TH3 < 2.0 nm, carrier transport mainly occurs through tunneling. When the thickness TH3 of the tunneling oxide layer 5 is greater than 2.0 nm, carriers mainly transport through pinholes in the tunneling oxide layer 5. Although a high pinhole density is beneficial for transport, it is detrimental to passivation, and carrier transport will be limited. Setting the thickness TH3 of the tunneling oxide layer 5 to be less than 1.2 nm and greater than 2.0 nm balances the tunneling effect and the passivation effect, maximizing the efficiency advantage.

Claims

1. A method for preparing a battery cell, characterized in that, Includes the following steps: Step S100: Provide a texturized N-type silicon wafer, and perform doping treatment on the front surface of the silicon wafer to form a front doped layer; Step S101: A polished surface is formed on the back surface of the silicon wafer. After alkaline polishing, the back surface of the silicon wafer reacts with oxygen in the air to form a first oxide layer. Step S102: Test the thickness TH1 of the first oxide layer; Step S103: Deposit a tunneling oxide layer on the surface of the first oxide layer; Step S104: Test the total thickness TH2 of the tunneling oxide layer and the first oxide layer; Step S105: Calculate the thickness of the tunneling oxide layer TH3 = TH2 - TH1; Step S106: In step S105, if the tunneling oxide layer thickness TH3 is less than 1.2 nm or greater than 2.0 nm, then adjust the process and re-execute steps S100-S105 until the tunneling oxide layer thickness TH3 is 1.2-2.0 nm. Step S107: Deposit passivation films on the front and back surfaces of the silicon wafer, respectively; Step S108: Prepare metal electrodes on the front and back surfaces of the silicon wafer, respectively.

2. The method for preparing the battery cell according to claim 1, characterized in that... Step S103 specifically also includes: Step S1031: Ensure that the temperature of the diffusion furnace tubes reaches the set value, with the set temperature range being 500-800℃; Step S1032: Place the silicon wafer into the furnace tube; Step S1033: Reduce the pressure to the lowest level, test the leak rate, and ensure that the airtightness is qualified; Step S1034: Raise the furnace tube temperature to the target value of 550-650℃; Step S1035: Stabilize the temperature of each zone of the furnace tube at the target value of 550-650℃; Step S1036: Constant temperature high concentration oxidation, maintain for the first time, control the pressure at 700,000-1,000,000 mTorr, control the temperature at the first temperature, and maintain the oxygen flow rate at the first flow rate; Step S1037: Remove the residual oxygen from step S1036; Step S1038: Cool the furnace tube temperature to room temperature; Step S1039: Fill the tube with nitrogen to reduce the pressure difference between the inside and outside of the tube, and then take out the sample to be tested.

3. The method for preparing the battery cell according to claim 2, characterized in that... The adjustment process in step S106 is as follows: If the tunneling oxide layer thickness TH3 in step S105 is less than 1.2 nm, then the first time is increased, the first temperature is increased, and the first flow rate is increased. If the tunneling oxide layer thickness TH3 in step S105 is greater than 2.0 nm, then the first time is reduced, the first temperature is lowered, and the first flow rate is reduced.

4. The method for preparing a battery cell according to claim 1, characterized in that: In step S103, the tunneling oxide layer is deposited inside the diffusion furnace tube, and the silicon wafer is sent out of the diffusion furnace tube at a preset temperature.

5. The method for preparing a battery cell according to claim 4, characterized in that: The preset temperature is 20℃-25℃.

6. The method for preparing a battery cell according to claim 4, characterized in that: In step S104, after the silicon wafer is sent out of the diffusion furnace tube, it is plastic-wound for a preset time to isolate it from the air.

7. The method for preparing a battery cell according to claim 6, characterized in that: The preset time is 20-30 minutes.

8. The method for preparing a battery cell according to claim 1, characterized in that: In steps S102 and S104, several silicon wafers are distributed horizontally at intervals within a quartz boat, and the thickness data of one of the silicon wafers located in the middle is measured.

9. The method for preparing a battery cell according to claim 1, characterized in that: In steps S102 and S104, a laser ellipsometer is used to measure thickness data.

10. The method for preparing a battery cell according to claim 1, characterized in that: The thickness TH1 of the first oxide layer is 0.4-0.6 nm, and the total thickness TH2 of the tunneling oxide layer and the first oxide layer is 1.7-2.4 nm.

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