A method for locating chip failure sites

Abstract

This invention provides a method for locating chip failure locations. The method includes: S1) providing a sample chip to be tested, the sample chip including a functional unit area and a peripheral wiring area, the peripheral wiring area being located on the outer periphery of the functional unit area; S2) removing the back metal layer of the sample chip located within the functional unit area; S3) performing a failure location test on the sample chip based on a failure point location system; S4) obtaining the position coordinates of the failure point in the functional unit area based on the test results of the failure location test, thus completing the location. The chip failure location location method provided by this invention can solve the problems in existing chip failure location methods where failure points related to the front metal layer cannot be detected and failure points under high voltage conditions cannot be located.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor devices, and in particular to a method for locating the failure site of a chip. Background Technology

[0002] Failure location has always been the most crucial and challenging part of the chip failure analysis process. Accurate and efficient failure location methods help failure analysis engineers quickly find the cause of failure and solve the problem, help the R&D department accelerate the R&D progress, and help the production department improve the yield.

[0003] Silicon carbide-based power chips currently mainly include SBDs (Schottky diodes) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), both of which are used in high-voltage environments. In the process of FAB's research and development and production of silicon carbide power chips, failures are frequently related to high-voltage leakage.

[0004] Taking an N-channel silicon carbide MOSFET as an example, it has a multilayer structure, including: an n+ substrate, an n-epitaxial layer formed on the n+ substrate, a device layer formed within the n-epitaxial layer (the device layer forms a well region, isolation structure, gate, source, etc.), a front metal layer formed on the upper surface of the device layer, and a back metal layer formed on the lower surface of the n+ substrate; the front metal layer is generally made of aluminum and serves as the gate trace, source trace, and pad; the back metal layer is generally made of metals such as titanium, nickel, and silver and serves as the drain trace.

[0005] When performing failure location analysis on silicon carbide MOSFETs, conventional failure location equipment, such as EMMI (Electronic Microscopy), OBIRCH (Laser Beam Resistance Anomaly Detection Microscopy), and Thermal (Thermal Radiation Microscopy), uses infrared light for detection when stimulating the failure circuit. However, the front and back metal layers almost completely block the IR signal, and the n+ substrate also blocks part of the IR signal, making it impossible for these failure location equipment to detect and locate the failure point. Therefore, conventional failure location methods require first etching away the front metal layer to prevent the detection beam from being blocked by the front metal layer and affecting the location. However, this presents a problem: failure modes related to the front metal layer (source contact, gate contact, and pad contact) in silicon carbide MOSFETs cannot be detected. At the same time, because the front metal is etched away, there is a certain probability that the etching will affect the normal function of the device layer, and may even damage some areas of the device, leading to inaccurate location of failure models related to high voltage leakage. Furthermore, when high voltage is applied to the front of the chip, the energized area is easily burned out, making failure location impossible. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for locating chip failure locations, which solves the problems in existing chip failure location methods where failure points related to the front metal layer cannot be detected and failure points under high voltage conditions cannot be located.

[0007] To achieve the above objectives, the present invention provides a method for locating the failure location of a chip, the method comprising:

[0008] S1) A sample chip to be tested is provided, the sample chip including a functional unit area and a peripheral wiring area, the peripheral wiring area being located on the outer periphery of the functional unit area;

[0009] S2), remove the back metal layer of the sample chip located in the functional unit area;

[0010] S3), perform a failure location test on the sample chip based on the failure point location system;

[0011] S4) Based on the test results of the failure location test, the location coordinates of the failure point in the functional unit area are obtained, and the location is completed.

[0012] Optionally, when performing S4), if there is a failure point in the peripheral wiring area in the test results, the orientation of the failure point in the peripheral wiring area relative to the functional unit area is also obtained, and subsequent steps are performed.

[0013] S5), remove the back metal layer in the peripheral wiring area corresponding to the said orientation;

[0014] S6) Based on the failure point location system, a failure location test is performed on the sample chip, and the position coordinates of the failure point in the peripheral wiring area are obtained to complete the location.

[0015] Optionally, the sample chip includes a silicon carbide power chip, which includes a silicon carbide field-effect transistor or a silicon carbide Schottky diode.

[0016] Optionally, during S2), after removing the back metal layer of the sample chip located in the functional unit region, the substrate of the sample chip located in the functional unit region is also thinned.

[0017] Optionally, during S2), the substrate of the sample chip located within the functional unit region is thinned until the epitaxial layer located within the functional unit region is exposed.

[0018] Optionally, when performing S2), the method for removing the back metal layer of the sample chip located in the functional unit region includes:

[0019] A mask layer with an opening pattern is formed on the back side of the sample chip, the mask layer exposing the back metal layer of the sample chip located within the functional unit area;

[0020] The back metal layer is removed by etching based on the mask layer.

[0021] Optionally, between S1) and S2), the positioning method includes the step of forming a protective film on the front side of the sample chip; between S2) and S3), the positioning method further includes the step of removing the protective film.

[0022] Optionally, low-voltage failure location testing and high-voltage failure location testing are performed on the sample chip based on the failure point location system.

[0023] Optionally, the failure point location system includes one or more of the following: a thermal radiation microscope system, a laser excitation resistance change tester, and a photon excitation microscope system.

[0024] As described above, the chip failure location location method of the present invention avoids affecting the failure point location information fed back by etching away the back metal layer of the sample chip; at the same time, the removal of the back metal layer does not affect the chip's ability to withstand high voltage, and the failure point location of the chip under high voltage conditions can be obtained; and the failure point location information obtained by test analysis is accurate. Attached Figure Description

[0025] Figure 1 The flowchart shown is a method for locating the chip failure location according to the present invention.

[0026] Figure 2 This is a schematic diagram of the layout structure of a functional unit area and its peripheral wiring area in this embodiment.

[0027] Figure 3 The diagram shown is a schematic representation of the device structure of the silicon carbide Schottky diode chip described in this invention.

[0028] Figure 4 The diagram shown is a schematic representation of the device structure of the silicon carbide field-effect transistor chip described in this invention.

[0029] Figure 5 Displayed as Figure 4 The equivalent circuit diagram of the device structure within the dashed box.

[0030] Figure 6 This is a schematic diagram of the structure after a first mask layer with a first opening pattern is formed on the back side of the sample chip in this embodiment.

[0031] Figure 7 This is a schematic diagram of the structure after removing the back metal layer and substrate in this embodiment.

[0032] Figure 8 This is a schematic diagram showing the structure when the sample chip is connected to the failure point location system in this embodiment.

[0033] Component labeling explanation

[0034] 10 Sample Chips

[0035] 101 Functional Unit Area (Cell Area)

[0036] 102 Peripheral cabling area

[0037] 11 First mask layer

[0038] 12 Protective film

[0039] 13 Second mask layer

[0040] 31. Substrate (substrate for silicon carbide Schottky diode chip)

[0041] 32 Epitaxial layer (epitaxy layer of silicon carbide Schottky diode chip)

[0042] 33 Front metal layer (front metal layer of silicon carbide Schottky diode chip)

[0043] 34. Back metal layer (back metal layer of silicon carbide Schottky diode chip)

[0044] 21. Substrate (substrate for silicon carbide field-effect transistor chip)

[0045] 22 Epitaxial layer (epitaxy layer of silicon carbide field-effect transistor chip)

[0046] 23 Source Structure

[0047] 24-gate structure

[0048] 25. Front metal layer (front metal layer of silicon carbide field-effect transistor chip)

[0049] 26 Back metal layer (back metal layer of silicon carbide field-effect transistor chip) Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] When describing the embodiments of the present invention in detail, for ease of explanation, the cross-sectional views showing the device structure will be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention.

[0052] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one structure or feature shown in the accompanying drawings and other structures or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The term “between” as used herein includes both endpoint values.

[0053] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] This embodiment provides a method for locating the failure site of a chip, such as... Figure 1 As shown, the method for locating the chip failure location includes steps S1) to S4). Specifically, it also includes steps S5) to S6).

[0056] Step S1): Provide a sample chip 10 to be tested, such as... Figure 2 As shown, the sample chip 10 is divided into a functional unit area 11 and a peripheral wiring area 12 located around the functional unit area.

[0057] In this embodiment, a semiconductor chip is divided into functional unit areas 101 (cell areas 101) and peripheral wiring areas 102 according to different functions and design precision. These cell areas and peripheral wiring areas 102 are arranged in an array, such as... Figure 2The diagram shows the layout structure of one of the cells and its surrounding circuitry (peripheral wiring area 102). The area within the dashed box is cell area 101, and the peripheral wiring area 102 is located around cell area 101. Furthermore, the peripheral wiring area 102 is divided into four directions based on its position relative to cell area 101, for example, the peripheral wiring area 102 located to the left of cell area, the peripheral wiring area 102 located to the right of cell area, the peripheral wiring area 102 located in front of cell area, and the peripheral wiring area 102 located behind cell area. Cell area 101 is used to provide basic device functions for the chip (such as the function of a voltage-resistant switch in a power semiconductor device; of course, different chips have different functions, and the cell units are also different). The peripheral wiring area is used for electrical connections, signal control, device power supply, etc.

[0058] Specifically, the sample chip 10 is a silicon carbide power chip.

[0059] In this embodiment, as one example, such as Figure 3 The diagram shows a schematic of the device structure of sample chip 10 when the silicon carbide power chip is a silicon carbide Schottky diode (SiC SBD); Figure 3 As shown, an epitaxial layer 32 is epitaxially grown on the substrate 31. The substrate 31 has a higher n-type doping concentration than the epitaxial layer 32, so the substrate is n+ doped and the epitaxial layer is n- doped. The front metal layer 33 is connected to the epitaxial layer 32, and the two form a Schottky contact. At the same time, the front metal layer serves as the anode trace and chip pad of the SiC SBD. The negative metal layer 34 is connected to the substrate 31, and the two form an ohmic contact. At the same time, the back metal layer serves as the cathode trace of the SiC SBD.

[0060] As another example, such as Figure 4 The diagram shows a schematic of the device structure of sample chip 10 when the silicon carbide power chip is a silicon carbide field-effect transistor (SiC MOSFET) (using an N-channel as an example); Figure 4 As shown, an epitaxial layer 22 is epitaxially grown on the substrate 21. The substrate 21 has a higher n-type doping concentration than the epitaxial layer 22, so the substrate is n+ doped and the epitaxial layer is n- doped. A device layer is formed in the epitaxial layer 22, and a source structure 23 and a gate structure 24 are formed in the device layer. A front metal layer 25 is formed above the device layer, and a back metal layer 26 is formed below the substrate 21. The front metal layer 25 serves as the source trace, the gate trace, and the chip pad, while the back metal layer 26 serves as the drain trace.

[0061] It should be noted that since the methods for locating the failure location of SiC SBD chips and SiC MOSFET chips are no different, the following will use the method for locating the failure location of SiC MOSFETs as an example to better explain the chip failure location location method described in this embodiment.

[0062] Step S2): Remove the back metal layer 26 of the sample chip 10 located in the functional unit area 101.

[0063] In this embodiment, the back metal layer 26 can completely block the light beam, so it needs to be completely etched away. Simultaneously, if the substrate 21 is thick, it will also block light. Therefore, depending on the actual positioning requirements, it is necessary to consider whether to completely etch away the substrate 21 or to etch away and thin the substrate 21 so that the substrate 21 does not affect light transmission and the optical path (e.g., infrared light path) during failure point positioning. Preferably, as... Figure 6 As shown, the back metal layer 26 and substrate 21 located on the back of cell region 101 are completely etched away to prevent the substrate 21 from blocking light and affecting the positioning accuracy of the failure point.

[0064] Specifically, when performing S2), the method for removing the back metal layer 26 of the sample chip 10 located in the functional unit region includes: forming a mask layer with an opening pattern on the back of the sample chip 10, the mask layer exposing the back metal layer 26 of the sample chip 10 located in the functional unit region 101; and etching the back metal layer based on the mask layer to remove it.

[0065] In this embodiment, as Figure 6 As shown, firstly, a first mask layer 11 with a first opening pattern is formed on the back side of the sample chip 10, exposing the back metal layer 26 located within the functional unit region 101; then, based on the first opening pattern, at least the back metal layer 26 is etched away, and the sample chip 10 is flipped to obtain the following... Figure 7 The structure shown.

[0066] As one example, the first mask layer 11 is a photoresist layer; the specific formation method includes: forming a photoresist material layer on the upper surface of the back metal layer using a coating process, exposing and developing the photoresist material layer, forming an opening pattern in the photoresist material layer that exposes the back metal layer 26, thereby obtaining the first mask layer 11;

[0067] In another example, the first mask layer 11 is a hard mask layer; the specific formation method includes: forming a hard mask material layer on the upper surface of the back metal layer 26, and forming a patterned photoresist layer on the upper surface of the hard mask material layer; etching the hard mask material layer based on the patterned photoresist layer to form an opening pattern in the hard mask material layer that exposes the back metal layer 26; and removing the patterned photoresist layer to obtain the first mask layer 11.

[0068] Specifically, between S1) and S2), the positioning method includes the step of forming a protective film 12 on the front side of the sample chip 10; between S2) and S3), the positioning method further includes the step of removing the protective film 12.

[0069] In this embodiment, as Figure 6 As shown, before inverting the sample chip 10, a protective film 12 needs to be formed on the front side of the sample chip 10 to protect the front metal layer 25 of the sample chip 10 from being accidentally etched in subsequent processes. The protective film 12 can be a blue film.

[0070] Step S3): Perform a failure location test on the sample chip 10 based on the failure point location system.

[0071] In this embodiment, the failure point location system includes one or more of the following: a thermal radiation microscope, a laser excitation resistance change tester, and a photon excitation microscope; such as Figure 8 As shown, after removing the protective film 12 on the front of the sample chip 10, the sample chip 10 is connected in series with the failure point location system. That is, the peripheral wiring circuit of the sample chip 10 is connected to the failure point location system to detect the failure points of the sample chip 10 under different working conditions, such as the failure points of the sample chip 10 under low voltage and high voltage conditions (that is, to perform low voltage failure location test and high voltage failure location test on the sample chip 10).

[0072] Taking the failure location of a laser-excited resistance change tester as an example. Figure 8 The testing equipment in the test is a laser-excited resistance change tester. The tester box is used to control the working parameters of the sample chip 10. The laser emitted by the laser-excited resistance change tester scans the cell area of ​​the chip and locates the circuit connection position within the cell area 101 of the sample chip 10. The resistance difference generated by the laser excitation at the location of leakage, short circuit, or abnormal circuit resistance of the sample chip 10 will be significantly different from that at the normal circuit. This significant difference will be converted into an electrical signal and detected and marked by the laser-excited resistance change tester. The marked coordinates are recorded to obtain the location coordinates of the failure point.

[0073] like Figure 5 As shown, it is displayed as Figure 4 The equivalent circuit diagram of the device structure within the dashed box shows the following: R1 represents the contact resistance between the source structure 23 and the source trace, and the resistance of the source trace; R2 represents the contact resistance between the gate structure 24 and the gate trace, and the resistance of the gate trace; R3 represents the resistance of the epitaxial layer 22; R4 represents the resistance of the substrate 21; R5 represents the resistance of the drain trace (back metal layer) and the contact resistance between the drain and the drain trace; J1 represents the PN junction between the n+ source region and the p-well in the source structure; and J2 represents the PN junction between the p-well and the n- epitaxial layer. When locating failures in SiC MOSFETs, each electronic component in R1-R5 and J1-J2, as well as the parts connected to each electronic component, may fail. However, in the method described in the background art of removing the front metal layer before failure location, the failure points related to R1 and R2 will be masked by the removal of the front metal layer and cannot be analyzed and located. At the same time, since the front metal layer is removed by etching, there is a certain probability that the gate structure 24 and the source structure 23 will be damaged, which will lead to the found failure point not being the correct failure point. Furthermore, when performing high-voltage failure location, since the front metal layer 25 is removed, the sample chip 10 is very likely to explode under high voltage (for power chips, the distribution and analysis of failure points under high voltage conditions are crucial). All of the above situations will greatly hinder the accurate location of failure points, resulting in inaccurate failure location.

[0074] In this embodiment, the method of removing the back metal layer 26 as described in steps S1 to S3 results in a very low probability of failure at the substrate 21 and the back metal layer 26. Furthermore, any failures that occur are easily identified by physical failure analysis, eliminating the need for electrical failure analysis. Since the substrate 21 functions almost identically to a resistor during chip operation, the removal of the substrate 21 and the back metal layer 26 will not significantly affect the sample chip 10, preventing it from being unable to withstand high-voltage testing. In other words, the sample chip 10 can still withstand high voltage during high and low voltage tests without exploding, allowing for the detection of failure locations related to the high-voltage failure model. Moreover, since the front metal layer 25 is not removed, the location method described in this embodiment can also obtain failure points related to the front metal layer 25. Simultaneously, since the front metal layer 25 is not etched away, the reliability of the gate structure 24 and the source structure 23 will not be affected, meaning the obtained failure points will not be inaccurate.

[0075] Step S4): Based on the test results of the failure location test, obtain the location coordinates of the failure point in the functional unit area to complete the location.

[0076] In this embodiment, since the testing of cell region 101 requires the connection of the peripheral wiring circuit to ensure the normal operation of the device circuits within cell region 101 of sample chip 10, this positioning can only accurately obtain the location coordinates of the failure point within cell region 101 of sample chip 10. For peripheral wiring region 102, since the coverage area of ​​the back metal layer 26 on the back of peripheral wiring region 102 is small, its area ratio is small, and the back metal layer 102 on its back is mostly narrow connection lines (such as...). Figure 2 As shown in the diagram, each connecting line component has gaps that allow light to pass through. Therefore, when there are failure points in the outer wiring area 102, these gaps can be used to observe the failure points, but the accurate coordinates of the failure points cannot be obtained. So, when all failure points are located within the cell area 101, the coordinates of all failure points can be obtained, thus locating the failure points. When there are failure points located in the outer wiring area 102, only the orientation of these failure points within the outer wiring area 102 relative to the cell area can be determined, such as whether they are located on the left, right, front, or back side of the cell area. To obtain the coordinates of these failure points located in the outer wiring area 102, further steps are needed for accurate location.

[0077] Step S5): Remove the back metal layer 26 in the peripheral wiring area 102 corresponding to the said orientation.

[0078] In this embodiment, a protective film 12 is first formed on the front side of the sample chip 10. Then, the sample chip 10 is inverted and a second mask layer is formed on the back side of the sample chip 10. The opening of the second mask layer exposes the peripheral wiring area 102 corresponding to the orientation, that is, the back metal layer 26 in the peripheral wiring area 102 corresponding to the orientation is exposed. Finally, the back metal layer 26 and the substrate 21 can be removed by etching process.

[0079] As an example, when the failure point of the peripheral wiring area 102 is located on the left side of the cell area 101, the second mask layer will expose the back metal layer 26 in the left peripheral wiring area separately. Similarly, the case where the failure point of the peripheral wiring area 102 is located on other sides of the cell area 101 will not be described here.

[0080] Step S6): Perform a failure location test on the sample chip 10 based on the failure point location system, and obtain the position coordinates of the failure point in the peripheral wiring area to complete the location.

[0081] In this embodiment, as in step S3), the same method is used to perform failure location test on the sample chip 10. Since the outer wiring area 102 on the left side of the cell area 101 is no longer blocked by the back metal layer 26 and the substrate 21, this test can directly obtain the position coordinates of the failure point located in the outer wiring area 102, and at the same time complete the failure point location operation.

[0082] In summary, the chip failure location method provided by this invention avoids the influence of the back metal layer of the sample chip on the feedback of the failure point location information by etching away the back metal layer; at the same time, the removal of the back metal layer does not affect the chip's ability to withstand high voltage, thus enabling the acquisition of the failure point location of the chip under high voltage conditions; and the location information of the failure point obtained by test analysis is accurate. Therefore, this invention has great industrial application value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for locating the failure site of a chip, characterized in that, The positioning method includes: S1) A sample chip to be tested is provided, the sample chip including a functional unit area and a peripheral wiring area, the peripheral wiring area being located on the outer periphery of the functional unit area; S2), remove the back metal layer of the sample chip located in the functional unit region, and retain the back metal layer in the peripheral wiring region; wherein, when performing S2), the method for removing the back metal layer of the sample chip located in the functional unit region includes: forming a mask layer with an opening pattern on the back of the sample chip, the mask layer exposing the back metal layer of the sample chip located in the functional unit region; and etching away the back metal layer based on the mask layer; S3) Perform a failure location test on the sample chip based on the failure point location system; wherein, the peripheral wiring area is used to connect the sample chip to the failure point location system; S4) Based on the test results of the failure location test, the location coordinates of the failure point in the functional unit area are obtained, and the location is completed.

2. The method for locating the chip failure location according to claim 1, characterized in that, When executing S4), if there is a failure point in the peripheral wiring area in the test results, the orientation of the failure point in the peripheral wiring area relative to the functional unit area is also obtained, and subsequent steps are executed. S5), remove the back metal layer in the peripheral wiring area corresponding to the said orientation; S6) Based on the failure point location system, a failure location test is performed on the sample chip, and the position coordinates of the failure point in the peripheral wiring area are obtained to complete the location.

3. The method for locating the chip failure location according to claim 1 or 2, characterized in that, The sample chip includes a silicon carbide power chip, which includes a silicon carbide field-effect transistor or a silicon carbide Schottky diode.

4. The method for locating the chip failure location according to claim 1, characterized in that, During S2), after removing the back metal layer of the sample chip located in the functional unit region, the substrate of the sample chip located in the functional unit region is also thinned.

5. The method for locating the chip failure location according to claim 4, characterized in that, During S2), the substrate of the sample chip located within the functional unit region is thinned until the epitaxial layer located within the functional unit region is exposed.

6. The method for locating the chip failure location according to claim 1, characterized in that, Between S1) and S2), the positioning method includes the step of forming a protective film on the front side of the sample chip; between S2) and S3), the positioning method further includes the step of removing the protective film.

7. The method for locating the chip failure location according to claim 1, characterized in that, The sample chip is subjected to low-voltage failure location test and high-voltage failure location test based on the failure point location system.

8. The method for locating the chip failure location according to claim 1, characterized in that, The failure point location system includes one or more of the following: a thermal radiation microscope system, a laser excitation resistance change tester, and a photon excitation microscope system.

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