Thin film transistor and manufacturing method thereof, display panel, and display device

Abstract

Provided are a thin film transistor, a manufacturing method thereof, a display panel, and a display device. The thin film transistor comprises a gate, a semiconductor layer, and a source / drain electrode. The semiconductor layer comprises: a first semiconductor layer proximal to the gate; and a second semiconductor layer distal to the gate and in contact with the source / drain electrode. The chemical stability of the second semiconductor layer is higher than that of the first semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a thin film transistor and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] Thin Film Transistor (TFT) is the most critical component of display devices. In related technologies, the semiconductor layer of thin film transistors has different film thicknesses around and within the surface during large-scale film formation processes, such as Figure 1a As shown in the figure, the contour lines around the semiconductor layer are distributed in an irregular shape. Due to the difference in film thickness, the characteristics of some areas around the periphery are offset, and the performance of the semiconductor layer at different locations is different. Therefore, when static electricity or large current passes through, the regional characteristic offset may cause abnormal conditions such as burns or electrostatic breakdown, causing poor display problems and seriously affecting product quality. Figure 1b and Figure 1c The following are optical microscope (OM) and focused ion beam (FIB) images of GOA circuit burns caused by static electricity. In related art, improving the anti-static performance of thin-film transistors is generally achieved by installing anti-static devices. This results in a complex structure, a limited protection area, and the need for multiple devices. If the anti-static device itself malfunctions, it can further cause display defects, increasing product quality risks.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the Invention

[0004] In order to solve the above problems, in the first aspect of the present disclosure, a thin film transistor is provided, comprising a gate, a semiconductor layer and a source and drain electrode, wherein the semiconductor layer comprises: a first semiconductor layer close to the gate; a second semiconductor layer away from the gate and in contact with the source and drain electrode, and the chemical stability of the second semiconductor layer is higher than that of the first semiconductor layer.

[0005] In an exemplary embodiment of the present disclosure, the semiconductor layer further includes at least one intermediate layer located between the first semiconductor layer and the second semiconductor layer, and the electron mobility of the intermediate layer is higher than that of the first semiconductor layer and / or the second semiconductor layer.

[0006] In an exemplary embodiment of the present disclosure, the intermediate layer includes a metal layer, and a material of the metal layer includes one of copper, silver, and tungsten.

[0007] In an exemplary embodiment of the present disclosure, the intermediate layer further includes a third semiconductor layer.

[0008] In an exemplary embodiment of the present disclosure, the total thickness of the first semiconductor layer, the second semiconductor layer, and the at least one intermediate layer ranges from 40 nm to 120 nm.

[0009] In an exemplary embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer both include gallium oxide, zinc oxide, and indium oxide, and the content of zinc oxide in the first semiconductor layer is less than that in the second semiconductor layer.

[0010] In an exemplary embodiment of the present disclosure, the content ratio of gallium oxide, zinc oxide, and indium oxide in the first semiconductor layer is 1:1:1; the content ratio of gallium oxide, zinc oxide, and indium oxide in the second semiconductor layer is 1:(1.1-1.3):1.

[0011] In an exemplary embodiment of the present disclosure, the sum of the thicknesses of the first semiconductor layer and the second semiconductor layer ranges from 62 nm to 95 nm.

[0012] In a second aspect of the present disclosure, a method for manufacturing a thin film transistor is provided, comprising: forming a gate, a semiconductor layer, and a source and drain electrode on a substrate, wherein forming the semiconductor layer comprises: forming a first semiconductor layer on a side of the gate away from the substrate, the first semiconductor layer being close to a side of the gate; forming a second semiconductor layer on a side away from the gate, forming a source and drain electrode on a side of the second semiconductor layer away from the substrate, the source and drain electrode being in contact with the second semiconductor layer, and the chemical stability of the second semiconductor layer being higher than that of the first semiconductor layer.

[0013] In an exemplary embodiment of the present disclosure, the manufacturing method further includes forming at least one intermediate layer between the first semiconductor layer and the second semiconductor layer, wherein the electron mobility of the intermediate layer is higher than the electron mobility of the first semiconductor layer and / or the second semiconductor layer.

[0014] In a third aspect of the present disclosure, a display panel is provided, comprising the thin film transistor described above.

[0015] In a fourth aspect of the present disclosure, a display device is provided, comprising the display panel described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0017] Figure 1a The thickness difference of the semiconductor layer of the thin film transistor in the related art exists;

[0018] Figure 1b This is an optical microscope (OM) image of circuit burn in the related art;

[0019] Figure 1c It is a focused ion beam (FIB) image of circuit burn in the related art;

[0020] Figure 2a is a schematic cross-sectional structural diagram of a thin film transistor according to an embodiment of the present disclosure;

[0021] Figure 2b is a schematic cross-sectional structural diagram of a thin film transistor according to another embodiment of the present disclosure;

[0022] Figure 3 is a graph showing electron transport characteristics of a semiconductor material of a semiconductor layer of a thin film transistor according to an embodiment of the present disclosure;

[0023] Figure 4 The figure is a comparison of the burn conditions of the thin film transistor before and after the improvement according to the embodiment of the present disclosure;

[0024] Figure 5 is a comparison of the local characteristic deviation of the thin film transistor before and after improvement according to the embodiment of the present disclosure;

[0025] Figure 6 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0026] Figure 7 is a flow chart of a method for manufacturing a semiconductor layer of a thin film transistor according to an embodiment of the present disclosure;

[0027] Figure 8 1 is a structural diagram of a thin film transistor in different manufacturing processes according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0030] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0032] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0033] It should be noted that, in this article, the term "chemical stability" refers to a chemical substance that, under certain environmental conditions, clearly does not undergo any chemical changes over time. The chemical stability of one material or substance is greater than that of another material or substance if, under the same environmental conditions, substance A does not undergo chemical changes over time, or undergoes less chemical changes than substance B. In this article, the certain environmental conditions may, for example, be the presence of a relatively high current.

[0034] In this article, regional characteristic offset refers to the phenomenon that when the thickness of the semiconductor layer is consistent, the various properties of different locations are consistent. When the thickness of the semiconductor layer is inconsistent at different locations, the performance exhibited in different regions is different, which in turn affects other properties.

[0035] Figure 2a is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present disclosure. Figure 2b is a schematic cross-sectional structure diagram of a thin film transistor according to another embodiment of the present disclosure.

[0036] like Figure 2a and Figure 2b As shown, the thin film transistor of the present disclosure includes a gate, a semiconductor layer, and a source and drain electrode. Specifically, the thin film transistor includes a substrate 10, a gate 20, a gate protection layer 30, a semiconductor layer 40, a source and drain electrode 50, a source and drain protection layer 60, and an electrode metal layer 70.

[0037] The base substrate 10 may be, for example, a glass backplane. A gate 20 is provided on the base substrate 10, and a gate protection layer 30 is provided on the side of the gate 20 away from the base substrate 10 to protect the gate 10. A semiconductor layer 40 is provided on the side of the gate protection layer 30 away from the base substrate 10. Source and drain electrodes 50 are provided at both ends of the semiconductor layer 40, respectively, and the source and drain electrodes 50 are in contact with both ends of the semiconductor layer 40. A source and drain protection layer 60 is provided on the side of the source and drain electrodes 50 and the semiconductor layer 40 away from the base substrate 10, and the source and drain protection layer 60 covers the semiconductor layer 40 and the source and drain electrodes 50. An electrode metal layer 70 is provided on the side of the source and drain protection layer 60 away from the base substrate 10, and the electrode metal layer 70 is electrically connected to the source and drain electrodes.

[0038] In the embodiment of the present disclosure, the semiconductor layer 40 includes a multi-layer structure. The semiconductor layer 40 may be a stacked structure having two or more layers of semiconductor materials, or a stacked structure consisting of at least two semiconductor layers and a metal layer.

[0039] In one embodiment of the present disclosure, Figure 2a As shown, the semiconductor layer 40 includes two layers, namely a first semiconductor layer 41 close to the gate 20 and a second semiconductor layer 42 away from the gate 20 and in contact with the source and drain 50 . The chemical stability of the second semiconductor layer 42 is higher than that of the first semiconductor layer 41 .

[0040] In this embodiment, the first semiconductor layer 41 and the second semiconductor layer 42 are used to adjust the characteristics of the TFT device. The chemical stability of the second semiconductor layer 42 is higher than that of the first semiconductor layer 41, which can reduce the impact of post-processing on the semiconductor characteristics and improve the chemical stability and structural stability of the entire semiconductor layer. For example, because the second semiconductor layer 42 is located in the upper layer, the impact of post-processing on the semiconductor characteristics can be reduced, thereby reducing or even eliminating regional characteristic deviations caused by differences in semiconductor film thickness during the entire semiconductor layer manufacturing process. Abnormal phenomena such as burns or electrostatic breakdown will not occur when static electricity is generated or a large current passes through.

[0041] According to an embodiment of the present disclosure, by adopting a second semiconductor layer 42 (a semiconductor layer located on the upper layer) with higher chemical stability than the first semiconductor layer 41 (a semiconductor layer located on the lower layer), the regional characteristic deviation of the semiconductor can be effectively reduced or even eliminated, thereby improving the overall anti-static capability of the thin film transistor.

[0042] In this embodiment, the thickness of the first semiconductor layer and the thickness of the second semiconductor layer can be set to be the same, and the sum of the thicknesses of the first semiconductor layer and the second semiconductor layer is in the range of 62 nm to 95 nm, for example, the sum of the thicknesses is 62 nm, 80 nm, or 95 nm. In other optional embodiments, the thickness of the first semiconductor layer and the thickness of the second semiconductor layer can also be different, as long as the sum of the thicknesses of the first semiconductor layer and the second semiconductor layer is within the above range.

[0043] In another embodiment of the present disclosure, Figure 2bAs shown, the semiconductor layer 40' is configured as a three-layer structure, which may include a first semiconductor layer 41', a second semiconductor layer 42', and an intermediate layer 43. The first semiconductor layer 41' is disposed near the gate 20; the second semiconductor layer 42' is disposed away from the gate 20 and in contact with the source and drain electrodes 50; the intermediate layer 43 is located between the first semiconductor layer 41' and the second semiconductor layer 42', and the electron mobility of the intermediate layer 43 is higher than that of the first semiconductor layer 41' and / or the second semiconductor layer 42'. In the embodiment of the present disclosure, the upper layer in contact with the source and drain electrodes is a semiconductor layer, and the layer close to the gate and in contact with the gate protection layer is also a semiconductor layer. The intermediate layer is made of a material with a higher electron mobility than the first semiconductor layer and / or the second semiconductor layer, so that when static electricity is generated or a large current flows, the static electricity or current can be conducted and dissipated as quickly as possible, thereby improving the overall anti-static capability. In this embodiment, the intermediate layer is configured as a single layer, with the lower side of the intermediate layer being the first semiconductor layer and the upper side of the intermediate layer being the second semiconductor layer.

[0044] In this embodiment, the middle layer includes a metal layer. The metal layer is a single metal element. Compared with the semiconductor layers on both sides, it has higher electron mobility, which can ensure the fastest conduction and evacuation of current. The material of the metal layer includes one of copper, silver, and tungsten.

[0045] In other embodiments of the present disclosure, the intermediate layer may also be set as a third semiconductor layer, as long as the electron mobility of the third semiconductor layer is greater than the electron mobility of the first semiconductor layer located at the bottom and / or the second semiconductor layer located at the top.

[0046] In an embodiment of the present disclosure, when the semiconductor layer includes three or more layers, the total thickness of the semiconductor layer ranges from 40 nm to 120 nm. For example, the total thickness can be set to 40 nm, 80 nm, or 120 nm, etc.

[0047] In other optional embodiments, the intermediate layer may be configured as a multilayer structure, for example, 4 layers, 5 layers, or n layers. When the intermediate layer is multilayered, it may be configured as a multilayer metal layer, a mixed stacked structure of a metal layer and a semiconductor layer, or a mixed stacked structure of multiple semiconductor layers. The electron mobility of each layer in the intermediate layer is greater than the electron mobility of the first semiconductor layer and / or the second semiconductor layer.

[0048] In the embodiment of the present disclosure, the semiconductor layer is provided as two layers, for example, an IGZO double-layer structure, namely including a first semiconductor layer and a second semiconductor layer. Figure 2a As shown, the first semiconductor layer 41 is disposed on a side of the thin film transistor close to the base substrate 10 , and the second semiconductor layer 42 is disposed on a side of the thin film transistor away from the base substrate and in contact with the source and drain.

[0049] Figure 3 FIG. 4 is a diagram showing electron transport characteristics of a semiconductor material of a semiconductor layer of a thin film transistor according to an embodiment of the present disclosure.

[0050] The semiconductor layer exhibits different properties due to different element ratios. For example, taking IGZO as the material of the semiconductor layer, IGZO materials mainly include gallium oxide (Ga2O3), zinc oxide (ZnO), and indium oxide (In2O3). Figure 3 As shown, the different elements in IGZO contribute significantly to their performance. For example, in the semiconductor layer material of IGZO, increasing the gallium oxide content can improve the structural stability of the semiconductor layer but reduce electron mobility; increasing the zinc oxide content can improve its chemical stability and electron mobility; and increasing the indium oxide content can improve electron mobility. Therefore, to ensure that the semiconductor layer material has better chemical stability and high electron mobility, increasing the zinc oxide content in the material can improve its chemical stability and electron mobility.

[0051] In the embodiments of the present disclosure, in order to reduce the impact of post-processing on the properties of the upper semiconductor layer, it is necessary to improve the chemical stability of the upper semiconductor layer material. At the same time, in order to ensure that static electricity can be conducted and evacuated as quickly as possible when it occurs, its electron mobility must also be increased. Therefore, by controlling the zinc oxide content of the first semiconductor layer 41 (lower layer) to be less than the zinc oxide content of the second semiconductor layer 42 (upper layer), the second semiconductor layer 42 is ensured to have good chemical stability and high electron mobility, thereby improving the overall antistatic capability of the thin film transistor.

[0052] In the embodiment of the present disclosure, the content ratio of gallium oxide, zinc oxide, and indium oxide in the first semiconductor layer 41 is set to 1:1:1. This ensures that the electrochemical characteristics and structure of the first semiconductor layer 41 are stable, thereby maintaining device stability. The content ratio of gallium oxide, zinc oxide, and indium oxide in the second semiconductor layer 42 is 1:(1.1-1.3):1. By increasing the proportion of zinc oxide in the second semiconductor layer 42, the chemical stability of the second semiconductor layer 42 is increased, and its chemical properties such as corrosion resistance and acid resistance are improved. This effectively reduces the impact of post-processing on the semiconductor properties of the second semiconductor layer, thereby improving the antistatic performance of the thin film transistor.

[0053] Figure 4 The figure compares the burn-in conditions of the thin film transistor before and after improvement according to the embodiment of the present disclosure. Figure 5 This is a comparison of the local characteristic deviation of the thin film transistor before and after improvement according to the embodiment of the present disclosure.

[0054] like Figure 4As shown in the figure, before the improvement (a), i.e., without the semiconductor layer structure of the embodiment of the present disclosure, the semiconductor layer suffers from electrostatic burns. After the improvement (b), i.e., with the semiconductor layer structure of the embodiment of the present disclosure, this electrostatic burn has been eliminated, thereby significantly improving the antistatic performance of the thin film transistor. Figure 5 As shown, before the improvement (a), that is, without the semiconductor layer structure of the embodiment of the present disclosure, the semiconductor layer had local characteristic deviation. After the improvement (b), that is, with the structure of the first semiconductor layer and the second semiconductor layer of the embodiment of the present disclosure, the local characteristic deviation of the semiconductor layer has been eliminated. This improves and enhances the antistatic performance of the thin-film transistor, and increases the device stability and service life of the thin-film transistor.

[0055] Figure 6 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. Figure 7 is a flow chart of a method for manufacturing a semiconductor layer of a thin film transistor according to an embodiment of the present disclosure. Figure 8 1 is a structural diagram of a thin film transistor in different manufacturing processes according to an embodiment of the present disclosure.

[0056] Some embodiments of the present disclosure also provide a method for manufacturing a thin film transistor, such as Figure 6 As shown, the process of the manufacturing method includes operations S1 to S6. Figure 8 and Figure 6 The flow of this manufacturing method will be described in detail.

[0057] In operation S1, a gate is formed on a substrate. Figure 8 As shown in FIG. 1 ( a ), a gate electrode 20 is formed on the upper side of the base substrate 10 .

[0058] In operation S2, a gate protection layer is formed on a side of the gate away from the substrate. Figure 8 As shown in FIG. 5 ( b ), a gate protection layer 30 is formed on the upper side of the base substrate 10 and the gate 20 . The gate protection layer 30 covers the base substrate 10 and the gate 20 .

[0059] In operation S3, a semiconductor layer is formed on a side of the gate protection layer away from the substrate. Figure 8 As shown in (c) of FIG. 3 , a semiconductor layer 40′ formed on the upper side of the gate protection layer 30 partially covers the gate protection layer 30. The semiconductor layer 40′ includes at least two semiconductor layers. In this embodiment, the semiconductor layer 40′ includes a first semiconductor layer 41′, a second semiconductor layer 42′, and an intermediate layer 43 between the first and second semiconductor layers.

[0060] In operation S4, a source and a drain are formed on a side of the semiconductor layer away from the substrate. Figure 8As shown in (d) in FIG. 4 , source and drain electrodes 50 are formed on the upper side of the semiconductor layer 40 ′. The source and drain electrodes 50 are in contact with portions of the semiconductor layer 40 ′. The source and drain electrodes 50 do not completely cover the semiconductor layer 40 ′. That is, the region of the semiconductor layer 40 ′ between the source and drain electrodes 50 is not covered. The semiconductor layer 40 ′ is in contact with the source and drain electrodes 50.

[0061] In operation S5, a source-drain protection layer is formed on the side of the source-drain away from the substrate. Figure 8 As shown in (e) , a source-drain protection layer 60 is formed on the upper side of the source-drain electrode 50 and the semiconductor layer 40 ′. The source-drain protection layer 60 covers a portion of the source-drain electrode 50 and the semiconductor layer 40 ′.

[0062] In operation S6, an electrode metal layer is formed on the side of the source and drain protection layer away from the base substrate. Figure 8 As shown in (f) , an electrode metal layer 70 is formed on the upper side of the source-drain protection layer 60 . A portion of the electrode metal layer penetrates the source-drain protection layer 60 and is electrically connected to the source-drain electrode 50 .

[0063] In this embodiment, the semiconductor layer includes a first semiconductor layer, a second semiconductor layer and an intermediate layer. Figure 7 As shown, the process of forming the semiconductor layer in operation S3 includes operations S31 to S33.

[0064] In operation S31 , a first semiconductor layer is formed on a side of the gate away from the substrate, and the first semiconductor layer is formed on a side close to the gate.

[0065] In operation S32 , at least one intermediate layer 43 is formed between the first semiconductor layer 41 ′ and the second semiconductor layer 42 ′. The electron mobility of the intermediate layer is higher than that of the first semiconductor layer 41 ′ and / or the second semiconductor layer 42 ′.

[0066] In operation S33, a second semiconductor layer 42' is formed on a side away from the gate, and a source-drain electrode 50 is formed on a side of the second semiconductor layer 42' away from the substrate. The source-drain electrode 50 is in contact with the second semiconductor layer 42'. The chemical stability of the second semiconductor layer 42' is higher than that of the first semiconductor layer 41'.

[0067] In other embodiments of the present disclosure, when the semiconductor layer includes only the first semiconductor layer and the second semiconductor layer, the above-mentioned operation S32 may be omitted.

[0068] In an optional embodiment, when the intermediate layer of the semiconductor layer has multiple layers, the above operation S32 may be repeated multiple times to form multiple intermediate layers.

[0069] Some exemplary embodiments of the present disclosure further provide a display panel including the thin film transistors described above. By using the thin film transistors described above, the display effect, device stability, and service life of the entire display panel can be improved.

[0070] In some exemplary embodiments of the present disclosure, a display device is further provided, comprising a display panel as described above. The display device may be any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, an electronic garment, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0071] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A thin film transistor comprising a gate electrode, a semiconductor layer, and a source and drain electrode, wherein: The semiconductor layer includes: a first semiconductor layer close to the gate; a second semiconductor layer away from the gate and in contact with the source and drain electrodes, wherein the chemical stability of the second semiconductor layer is higher than that of the first semiconductor layer, and the content of zinc oxide in the first semiconductor layer is lower than that in the second semiconductor layer; The semiconductor layer further includes at least one intermediate layer located between the first semiconductor layer and the second semiconductor layer. The electron mobility of the intermediate layer is higher than that of the first semiconductor layer and the second semiconductor layer.

2. The thin film transistor according to claim 1, wherein The intermediate layer includes a metal layer, and a material of the metal layer includes one of copper, silver, and tungsten.

3. The thin film transistor according to claim 1, wherein The intermediate layer further includes a third semiconductor layer. The thin film transistor according to claim 1 , wherein: The total thickness of the first semiconductor layer, the second semiconductor layer and the at least one intermediate layer ranges from 40 nm to 120 nm. The thin film transistor according to claim 1 , wherein: The first semiconductor layer and the second semiconductor layer both include gallium oxide, zinc oxide, and indium oxide. The thin film transistor according to claim 5 , wherein: The content ratio of gallium oxide, zinc oxide and indium oxide in the first semiconductor layer is 1:1:1; The content ratio of gallium oxide, zinc oxide, and indium oxide in the second semiconductor layer is 1:(1.1-1.3):

1.

7. The thin film transistor according to claim 1, wherein The total thickness of the first semiconductor layer and the second semiconductor layer ranges from 62 nm to 95 nm.

8. A method for manufacturing a thin film transistor, comprising: A gate, a semiconductor layer, and a source and drain electrode are formed on a substrate, wherein forming the semiconductor layer comprises: forming a first semiconductor layer on a side of the gate away from the substrate, the first semiconductor layer being close to the gate; forming a second semiconductor layer on a side away from the gate, and forming a source and drain electrode on a side of the second semiconductor layer away from the substrate, the source and drain electrode being in contact with the second semiconductor layer, the chemical stability of the second semiconductor layer being higher than that of the first semiconductor layer, and the zinc oxide content in the first semiconductor layer being lower than that in the second semiconductor layer; The method further includes forming at least one intermediate layer between the first semiconductor layer and the second semiconductor layer, wherein the electron mobility of the intermediate layer is higher than the electron mobility of the first semiconductor layer and the second semiconductor layer. 9 . A display panel comprising the thin film transistor according to claim 1 . 10 . A display device comprising the display panel according to claim 9 .

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