A Fractional All-Digital Phase-Locked Loop with Adaptive Adjustment of Algorithm Step Size and Loop Bandwidth

Abstract

The present invention discloses a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth. The fractional all-digital phase-locked loop includes a frequency and phase detector, a time-to-digital converter, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an adaptive step size / bandwidth control algorithm module, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator. The present invention improves the existing circuit structure, and optimizes the performance and innovates the structure of the circuit modules. The adaptive step size / bandwidth control algorithm of the present invention simultaneously adjusts the convergence step size of the LMS algorithm and the bandwidth of the phase-locked loop according to the state of the phase-locked loop, thereby achieving the characteristics of short LMS algorithm convergence time, good fractional spurious performance, short phase-locked loop locking time, and good in-band phase noise of the phase-locked loop.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth. Background Art

[0002] Phase-locked loops are mainly used in transceiver systems and provide local oscillator signals with high resolution, low phase noise, and high spectral purity for the radio frequency front end. In recent years, with the development of digital systems, all-digital phase-locked loops have gradually gained an advantage due to their good portability and characteristics not inferior to analog phase-locked loops. Fractional digital phase-locked loops are widely used because of their high frequency resolution. However, the quantization noise of the time-to-digital converter and Σ-Δ modulator in the fractional digital phase-locked loop has a great impact on the fractional spurs on the output spectrum, thus causing great interference to data reception and transmission in wireless transceivers. To reduce the influence of the quantization noise of the time-to-digital converter and Σ-Δ modulator in the fractional phase-locked loop, when the traditional least mean square (LMS) algorithm is used to reduce the fractional spurs caused by the quantization noise of the Σ-Δ modulator, the LMS algorithm usually takes a long time to converge, and the convergence time usually reaches the sub-millisecond level, thus limiting the application of the phase-locked loop. At the same time, the bandwidth of the fractional digital phase-locked loop is usually set very small to suppress in-band phase noise, but this will also cause the lock-in time of the phase-locked loop to become longer, thus limiting its application in some cases. Summary of the Invention

[0003] The main object of the present invention is to provide a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth. This fractional all-digital phase-locked loop can adaptively and parallelly adjust the step size of the LMS algorithm and the loop bandwidth according to the loop lock state of the phase-locked loop, reducing the convergence time of the LMS algorithm and the loop lock-in time, reducing the spurs caused by the quantization error of the ΣΔ modulator, and suppressing the in-band phase noise.

[0004] To achieve the above object, the present invention provides a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth, including a frequency discriminator / phase discriminator, a time-to-digital converter, an adaptive step size / bandwidth control algorithm module, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator;

[0005] Among them, the two input terminals of the frequency discriminator and phase detector are respectively connected to an external clock signal and the output signal of the multi-mode frequency divider. One output terminal of the frequency discriminator and phase detector is connected to the input terminal of the adaptive step / bandwidth control algorithm module, and the other two output terminals are connected to the input terminals of the time-to-digital converter; the output of the adaptive step / bandwidth control algorithm module is respectively connected to the LMS algorithm module and the digital loop filter; the output of the time-to-digital converter is connected to one input of the first subtractor; one input of the first subtractor is connected to the output of the time-to-digital converter as the minuend, and the other input is connected to the output of the first multiplier as the subtrahend. The output of the first subtractor is connected to the input of the digital loop filter and the input of the LMS algorithm module;

[0006] One input of the second subtractor is connected to the externally input frequency control word FCW as the minuend, and the other input is connected to the output of the ΣΔ modulator as the subtrahend. The output of the second subtractor is connected to the input of the first adder; the two inputs of the first adder are respectively connected to the output of the second subtractor and the output of the first register. The output of the first adder is connected to the input of the first register, the input of the first multiplier, and one of the inputs of the LMS algorithm module; the two inputs of the first multiplier are respectively connected to the output of the first adder and the output of the LMS algorithm module. The output of the first multiplier is used as the other input of the first subtractor after truncation;

[0007] The three inputs of the LMS algorithm module are respectively connected to the output of the adaptive step / bandwidth control algorithm module, the output of the first adder, and the output of the first subtractor. The output of the LMS algorithm module is connected to one of the inputs of the first multiplier; the two inputs of the digital loop filter are respectively connected to the output of the first subtractor and the output of the adaptive step / bandwidth control algorithm module. The output of the digital loop filter is connected to the input of the numerically controlled oscillator; the two inputs of the ΣΔ modulator are respectively connected to the external signal FCW and the output of the multi-mode frequency divider. The output of the ΣΔ modulator is connected to the input of the multi-mode frequency divider and the other input of the second subtractor; the output of the numerically controlled oscillator is connected to the other input of the multi-mode frequency divider; the output of the multi-mode frequency divider is connected to one of the input terminals of the frequency discriminator and phase detector and the clock terminal of the ΣΔ modulator.

[0008] As a further improvement of the present invention, the frequency discriminator and phase detector includes a first D flip-flop, a second D flip-flop, a first NAND gate to a tenth NAND gate, a delay element, an AND gate, a first inverter, and a second inverter;

[0009] Among them, the three inputs of the first D flip-flop are respectively connected to an external reference clock, a power supply voltage, and the output of a delay element. The output of the first D flip-flop is respectively connected to the inputs of a first NAND gate, a fifth NAND gate, an eighth NAND gate, and an AND gate. The three inputs of the second D flip-flop are respectively connected to the output of a multi-mode frequency divider, a power supply voltage, and the output of a delay element. The output of the second D flip-flop is connected to the inputs of a second NAND gate, a sixth NAND gate, a ninth NAND gate, and an AND gate. The inputs of the AND gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop, and the output of the AND gate is connected to the input of the delay element.

[0010] The two inputs of the first NAND gate are respectively connected to the output of the first D flip-flop and the output of the second NAND gate, and the output of the first NAND gate is connected to the input of the third NAND gate. The two inputs of the second NAND gate are respectively connected to the output of the second D flip-flop and the output of the first NAND gate, and the output of the second NAND gate is connected to the input of the fourth NAND gate. The two inputs of the third NAND gate are respectively connected to the outputs of the first NAND gate and the fourth NAND gate, and the output of the third NAND gate is connected to the inputs of the fifth NAND gate and the ninth NAND gate. The two inputs of the fourth NAND gate are respectively connected to the outputs of the second NAND gate and the third NAND gate, and the output of the fourth NAND gate is connected to the inputs of the third NAND gate, the sixth NAND gate, the eighth NAND gate, and the input of a first inverter. The two inputs of the fifth NAND gate are respectively connected to the output of the first D flip-flop and the output of the third NAND gate, and the output of the fifth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the sixth NAND gate are respectively connected to the output of the second D flip-flop and the output of the fourth NAND gate, and the output of the sixth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the seventh NAND gate are respectively connected to the outputs of the fifth NAND gate and the sixth NAND gate, and the output of the seventh NAND gate is connected to Start. The two inputs of the eighth NAND gate are respectively connected to the output of the first D flip-flop and the output of the fourth NAND gate, and the output of the eighth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the ninth NAND gate are respectively connected to the output of the second D flip-flop and the output of the third NAND gate, and the output of the ninth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the tenth NAND gate are respectively connected to the outputs of the eighth NAND gate and the ninth NAND gate, and the output of the tenth NAND gate is connected to Stop. The input of the first inverter is connected to the output of the fourth NAND gate, and the output of the first inverter is connected to the input of the second inverter. The input of the second inverter is connected to the output of the first inverter, and the output of the second inverter is connected to Sign.

[0011] As a further improvement of the present invention, the time-to-digital converter includes a first quantization unit to a sixty-fourth quantization unit and a decoder.

[0012] The two inputs of the first quantization unit are respectively connected to the external signals Start and Stop, and the three outputs of the first quantization unit are respectively connected to the two inputs of the second quantization unit and one input of the decoder; the second quantization unit to the sixty-fourth quantization unit have the same structure and are connected in series with the first quantization unit to form the time-to-digital converter; the outputs of the first quantization unit to the sixty-fourth quantization unit are connected to the input of the decoder, and the output of the decoder is connected to the positive terminal of the first subtractor;

[0013] The first quantization unit includes a first delay unit, a second delay unit and a D flip-flop; the first delay unit is connected to the external input Start, and the output of the first delay unit is connected to one input of the D flip-flop and the first delay unit of the second quantization unit; the second delay unit is connected to the external input Stop, and the output of the second delay unit is connected to the clock input of the D flip-flop and the second delay unit of the second quantization unit; the two inputs of the D flip-flop are respectively connected to the outputs of the first delay unit and the second delay unit, and the output of the D flip-flop is connected to the decoder.

[0014] As a further improvement of the present invention, the adaptive step size / bandwidth control algorithm module includes a second adder, a second register, a frequency divider, a first digital comparator, a second digital comparator, a counter and an OR gate;

[0015] One input of the second adder is connected to the external Sign signal, and the other input is connected to the output of the second register. The output of the second adder is connected to the input of the second register, the negative input of the first comparator and the positive input of the second digital comparator; the two inputs of the second register are respectively connected to the output of the second adder and the output of the OR gate. Another input of the second register is connected to the external clock signal Fref, and the output of the second register is connected to the input of the second adder; the input of the frequency divider is connected to the external clock signal Fref, and the output of the frequency divider is connected to the clock inputs of the first digital comparator and the second digital comparator; the positive input of the first digital comparator is connected to the external input Ntarget1, the negative input of the first digital comparator is connected to the output of the second adder, the clock input of the first digital comparator is connected to the output of the frequency divider, and the output of the first digital comparator is connected to one input of the OR gate; the positive input of the second digital comparator is connected to the output of the second adder, the negative input of the second digital comparator is connected to the external input Ntarget2, the clock input of the second digital comparator is connected to the output of the frequency divider, and the output of the second digital comparator is connected to the other input of the OR gate; the two inputs of the OR gate are respectively connected to the outputs of the first digital comparator and the second digital comparator, and the output of the OR gate is connected to one input of the second register and Sel.

[0016] As a further improvement of the present invention, the LMS algorithm module includes a second multiplier, a third multiplier, a Mux, a third adder and a third register;

[0017] The two inputs of the second multiplier are respectively connected to the external inputs p[k] and e[k], and the output of the second multiplier is connected to one input of the third multiplier; the two inputs of the Mux are respectively connected to the external inputs γ0 and γ1, the selection terminal of the Mux is connected to the external input Sel, and the output of the Mux is connected to the other input of the third multiplier; the two inputs of the third multiplier are respectively connected to the output of the Mux and the output of the second multiplier, and the output of the third multiplier is connected to one input of the third adder; the two inputs of the third adder are respectively connected to the output of the third multiplier and the output of the third register, and the output of the third adder is connected to the input and the output terminal OUT of the third register; the input of the third register is connected to the output of the third adder, and the output of the third register is connected to one input of the third adder.

[0018] As a further improvement of the present invention, the digital loop filter includes a fourth multiplier, a fifth multiplier, a fourth adder, a fifth adder, a fourth register, a fifth register, a first Mux and a second Mux;

[0019] The two inputs of the fourth multiplier are respectively connected to the external digital signal e[k] and the output of the first Mux, and the output of the fourth multiplier is connected to the fifth adder; the two inputs of the fifth multiplier are respectively connected to the external digital signal e[k] and the output of the second Mux, and the output of the fifth multiplier is connected to the fourth adder; the two inputs of the first Mux are respectively connected to the external inputs α0 and α1, the selection terminal of the first Mux is connected to the external input Sel, and the output of the first Mux is connected to the input of the fourth multiplier; the two inputs of the second Mux are respectively connected to the external inputs β0 and β1, the selection terminal of the second Mux is connected to the external input Sel, and the output of the second Mux is connected to the input of the fifth multiplier; the two inputs of the fourth adder are respectively connected to the output of the fifth multiplier and the output of the fourth register, and the output of the fourth adder is connected to the input of the fourth register; the two inputs of the fourth register are respectively connected to the external clock Fref and the output of the fourth adder, and the output of the fourth register is connected to the input of the fourth adder and the input of the fifth adder; the two inputs of the fifth adder are respectively connected to the output of the fourth register and the output of the fourth multiplier; the output of the fifth adder is connected to the input of the fifth register; the two inputs of the fifth register are respectively connected to the output of the fifth adder and the external clock signal Fref, and the output of the fifth register is connected to OUT.

[0020] As a further improvement of the present invention, the numerically controlled oscillator includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a coarse tuning capacitor array, a fine tuning capacitor array and an inductor L1;

[0021] The left and right ends of the inductor L1 are connected to VP and VN respectively, and the center tap of the inductor L1 is connected to VDD; the gate of the first NMOS transistor NM1 is connected to VN and one end of the first capacitor C1, the drain of NM1 is connected to VP, the gate of the second NMOS transistor NM2 and one end of the second capacitor C2, and the source of NM1 is connected to the source of the first PMOS transistor PM1; the gate of the second NMOS transistor NM2 is connected to VP and one end of the second capacitor C2, the drain of NM2 is connected to VN, the gate of the first NMOS transistor NM1 and one end of the first capacitor C1, and the source of NM2 is connected to the source of the second PMOS transistor PM2; the gate of the first PMOS transistor PM1 is connected to the other end of the second capacitor C2 and one end of the first resistor R1, the source of PM1 is connected to the source of the first NMOS transistor NM1, and the drain of PM1 is connected to GND; the gate of the second PMOS transistor PM2 is connected to the other end of the first capacitor C1 and one end of the second resistor R2, the source of PM2 is connected to the source of the second NMOS transistor NM2, and the drain of PM2 is connected to GND; one end of the first resistor R1 is connected to the gate of PM1 and the other end of the second capacitor C2, and the other end of the first resistor R1 is connected to GND; one end of the second resistor R2 is connected to the gate of PM2 and the other end of the first capacitor C1, and the other end of the second resistor R2 is connected to GND; one end of the first capacitor C1 is connected to the gate of NM1 and VN, and the other end of the first capacitor C1 is connected to the gate of PM2 and one end of R2; one end of the second capacitor C2 is connected to the gate of NM2 and VP, and the other end of the second capacitor C2 is connected to the gate of PM1 and one end of R1.

[0022] As a further improvement of the present invention, the fine-tuning capacitor array is composed of the third PMOS transistor and the fourth PMOS transistor in the first group and the second to eighth groups of arrays with the same structure but different sizes. The sources and drains of the third PMOS transistor and the fourth PMOS transistor in the first group are both connected to the external input signal D F [0], the gate of the third PMOS transistor is connected to VP, and the gate of the fourth PMOS transistor is connected to VN; the second to eighth groups of fine-tuning capacitor arrays all adopt the same structure and form an array together with the first group;

[0023] The coarse-tuning capacitor array is composed of the NMOS transistor, the third capacitor, the fourth capacitor, the third resistor, the fourth resistor, the inverter in the first group and the second to fifth groups of coarse-tuning capacitor arrays. One end of the third capacitor is connected to VP, and the other end is connected to one end of the third resistor and the source of the third NMOS transistor; the other end of the third resistor is connected to the output of the first inverter and one end of the fourth resistor; the gate of the third NMOS transistor is connected to the external input D C [0], the drain of the third NMOS transistor is connected to the other end of the fourth resistor and one end of the fourth capacitor; the other end of the fourth capacitor is connected to VN; the input of the first inverter is connected to the external input DC [0]; The second to fifth coarse-tuning capacitor arrays all adopt the same structure and jointly form an array with the first group.

[0024] As a further improvement of the present invention, the multi-mode frequency divider includes a first 2 / 3 frequency divider to a sixth 2 / 3 frequency divider;

[0025] The three inputs of the first 2 / 3 frequency divider are respectively connected to the external input Fin, P0, and the output of the second 2 / 3 frequency divider, and the output of the first 2 / 3 frequency divider is connected to one input of the second 2 / 3 frequency divider; The three inputs of the second 2 / 3 frequency divider are respectively connected to the external input P1, the output of the first 2 / 3 frequency divider, and the output of the third 2 / 3 frequency divider, and the two outputs of the second 2 / 3 frequency divider are respectively connected to the inputs of the first 2 / 3 frequency divider and the third 2 / 3 frequency divider; The three inputs of the third 2 / 3 frequency divider are respectively connected to the external input P2, the output of the second 2 / 3 frequency divider, and the output of the fourth 2 / 3 frequency divider, and the two outputs of the third 2 / 3 frequency divider are respectively connected to the inputs of the second 2 / 3 frequency divider and the fourth 2 / 3 frequency divider; The three inputs of the fourth 2 / 3 frequency divider are respectively connected to the external input P3, the output of the third 2 / 3 frequency divider, and the output of the fifth 2 / 3 frequency divider, and the two outputs of the fourth 2 / 3 frequency divider are respectively connected to the inputs of the third 2 / 3 frequency divider and the fifth 2 / 3 frequency divider; The three inputs of the fifth 2 / 3 frequency divider are respectively connected to the external input P4, the output of the fourth 2 / 3 frequency divider, and the output of the sixth 2 / 3 frequency divider, and the two outputs of the fifth 2 / 3 frequency divider are respectively connected to the inputs of the fourth 2 / 3 frequency divider and the sixth 2 / 3 frequency divider; The three inputs of the sixth 2 / 3 frequency divider are respectively connected to the external input P5, the output of the fifth 2 / 3 frequency divider, and the power supply voltage VDD, and the two outputs of the sixth 2 / 3 frequency divider are respectively connected to the input and the output terminal Fout of the fifth 2 / 3 frequency divider.

[0026] As a further improvement of the present invention, the ΣΔ modulator includes a 19-bit CLA, two 24-bit CLAs, a 5-bit shift module, four 1-bit registers, a 19-bit register, two 24-bit registers, and a noise cancellation circuit;

[0027] The two input terminals of the 19-bit CLA are respectively connected to the 1-bit output terminal of the fourth register and the 19-bit output terminal of the fifth register. The 19-bit output terminal of the 19-bit CLA is connected to the 19-bit input terminal of the 5-bit shift module. The 1-bit output terminal of the 19-bit CLA is respectively connected to the 1-bit input terminals of the first register and the fifth register. The 24-bit output terminal of the 5-bit shift module is connected to the 24-bit input terminal of the first 24-bit CLA. The other two input terminals of the first 24-bit CLA are respectively connected to the 1-bit output terminal of the 19-bit CLA and the 24-bit output terminal of the sixth register. The 1-bit output terminal of the first 24-bit CLA is respectively connected to the 1-bit input terminals of the second register and the second 24-bit CLA. The 24-bit output terminal of the first 24-bit CLA is connected to the 24-bit input terminal of the second 24-bit CLA. The other two input terminals of the second 24-bit CLA are respectively connected to the 1-bit output terminal of the 24-bit CLA and the 24-bit output terminal of the seventh register. The 1-bit output terminal of the second 24-bit CLA is connected to the 1-bit input terminal of the third register. The 24-bit output terminal of the second 24-bit CLA is connected to the 24-bit input terminal of the seventh register. The three input terminals of the noise cancellation circuit are respectively connected to the 1-bit output terminals of the first register, the second register, and the third register. The 4-bit output terminal of the noise cancellation circuit is connected to Y.

[0028] The beneficial effects of the present invention are as follows: The present invention is improved and optimized on the basis of the prior art and circuit structure. By detecting the locked state of the detection loop, the step size of the LMS algorithm and the bandwidth of the digital loop filter are adaptively adjusted in parallel. When the phase-locked loop is not locked, the circuit selects a larger LMS step size and the gain coefficient of the digital loop filter, so as to shorten the convergence time of the LMS algorithm and the locking time of the phase-locked loop. When the phase-locked loop is locked, the circuit selects a smaller LMS step size and the gain coefficient of the digital loop filter, so as to suppress fractional spurs and in-band phase noise. Description of the Drawings

[0029] Figure 1 is the structural block diagram of the fractional all-digital phase-locked loop of the present invention.

[0030] Figure 2 is Figure 1 the circuit diagram of the frequency discriminator and phase detector in

[0031] Figures 3(a) and 3(b) are respectively Figure 1 the circuit diagrams of the time-to-digital converter and quantization unit in

[0032] Figure 4 is Figure 1 the circuit diagram of the adaptive step size / bandwidth control algorithm module in

[0033] Figure 5 is Figure 1 the circuit diagram of the LMS algorithm module in

[0034] Figure 6 is Figure 1 the circuit diagram of the digital loop filter in

[0035] Figure 7 is Figure 1 the circuit diagram of the numerically controlled oscillator in

[0036] Figures 8(a) and 8(b) are respectively Figure 1 the circuit diagrams of the multi-mode frequency divider and the 2 / 3 frequency division unit in

[0037] Figure 9 is Figure 1 the circuit diagram of the ΣΔ modulator in Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] It should be emphasized that during the description of the present invention, various formulas and constraints are distinguished by using consistent labels before and after, but it does not exclude using different labels to denote the same formula and / or constraint. The purpose of such setting is to more clearly illustrate the features of the present invention.

[0040] As Figures 1 to 9 shown, the present invention provides a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth, including a frequency discriminator / phase discriminator, a time-to-digital converter, an adaptive step size / bandwidth control algorithm module, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator.

[0041] Two input ends of the frequency discriminator / phase discriminator are respectively connected to an external clock signal and an output signal of the multi-mode frequency divider. One output end of the frequency discriminator / phase discriminator is connected to an input end of the adaptive step size / bandwidth control algorithm module, and the other two output ends are connected to input ends of the time-to-digital converter. The outputs of the adaptive step size / bandwidth control algorithm module are respectively connected to the LMS algorithm module and the digital loop filter. The output of the time-to-digital converter is connected to one input end of the first subtractor. One input end of the first subtractor is connected to the output of the time-to-digital converter as the minuend, and the other input end is connected to the output of the first multiplier as the subtrahend. The output of the first subtractor is connected to the input of the digital loop filter and the input of the LMS algorithm module.

[0042] One end input of the second subtractor receives the externally input frequency control word FCW as the subtrahend, and the other end input receives the output of the ΣΔ modulator as the minuend. The output of the second subtractor is connected to the input of the first adder. The two inputs of the first adder are respectively connected to the output of the second subtractor and the output of the first register. The output of the first adder is connected to the input of the first register, the input of the first multiplier, and one of the inputs of the LMS algorithm module. The two inputs of the first multiplier are respectively connected to the output of the first adder and the output of the LMS algorithm module. The output of the first multiplier is used as the input of the first subtractor after truncation.

[0043] The three inputs of the LMS algorithm module are respectively connected to the output of the adaptive step / bandwidth control algorithm module, the output of the first adder, and the output of the first subtractor. The output of the LMS algorithm module is connected to one of the inputs of the first multiplier. The two inputs of the digital loop filter are respectively connected to the output of the first subtractor and the output of the adaptive step / bandwidth control algorithm module. The output of the digital loop filter is connected to the input of the numerically controlled oscillator. The two inputs of the ΣΔ modulator are respectively connected to the external signal FCW and the output of the multi-mode frequency divider. The output of the ΣΔ modulator is connected to the input of the multi-mode frequency divider and the input of the second subtractor. The output of the numerically controlled oscillator is connected to the other input of the multi-mode frequency divider. The output of the multi-mode frequency divider is connected to one of the inputs of the frequency discriminator / phase detector and the clock terminal of the ΣΔ modulator.

[0044] The frequency discriminator / phase detector includes a first D flip-flop, a second D flip-flop, a first NAND gate to a tenth NAND gate, a delay element, an AND gate, a first inverter, and a second inverter. Among them, the three inputs of the first D flip-flop are respectively connected to the external reference clock, the power supply voltage, and the output of the delay element. The output of the first D flip-flop is respectively connected to the inputs of the first NAND gate, the fifth NAND gate, the eighth NAND gate, and the input of the AND gate. The three inputs of the second D flip-flop are respectively connected to the output of the multi-mode frequency divider, the power supply voltage, and the output of the delay element. The output of the second D flip-flop is connected to the inputs of the second NAND gate, the sixth NAND gate, the ninth NAND gate, and the input of the AND gate. The inputs of the AND gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop. The output of the AND gate is connected to the input of the delay element.

[0045] The two inputs of the first NAND gate are respectively connected to the output of the first D flip-flop and the output of the second NAND gate, and the output of the first NAND gate is connected to the input of the third NAND gate. The two inputs of the second NAND gate are respectively connected to the output of the second D flip-flop and the output of the first NAND gate, and the output of the second NAND gate is connected to the input of the fourth NAND gate. The two inputs of the third NAND gate are respectively connected to the outputs of the first NAND gate and the fourth NAND gate, and the output of the third NAND gate is connected to the inputs of the fifth NAND gate and the ninth NAND gate. The two inputs of the fourth NAND gate are respectively connected to the outputs of the second NAND gate and the third NAND gate, and the output of the fourth NAND gate is connected to the inputs of the third NAND gate, the sixth NAND gate, the eighth NAND gate and the input of the first inverter. The two inputs of the fifth NAND gate are respectively connected to the output of the first D flip-flop and the output of the third NAND gate, and the output of the fifth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the sixth NAND gate are respectively connected to the output of the second D flip-flop and the output of the fourth NAND gate, and the output of the sixth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the seventh NAND gate are respectively connected to the outputs of the fifth NAND gate and the sixth NAND gate, and the output of the seventh NAND gate is connected to Start; the two inputs of the eighth NAND gate are respectively connected to the output of the first D flip-flop and the output of the fourth NAND gate, and the output of the eighth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the ninth NAND gate are respectively connected to the output of the second D flip-flop and the output of the third NAND gate, and the output of the ninth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the tenth NAND gate are respectively connected to the outputs of the eighth NAND gate and the ninth NAND gate, and the output of the tenth NAND gate is connected to Stop. The input of the first inverter is connected to the output of the fourth NAND gate, and the output of the first inverter is connected to the input of the second inverter; the input of the second inverter is connected to the output of the first inverter, and the output of the second inverter is connected to Sign.

[0046] The time-to-digital converter includes a first quantization unit to a sixty-fourth quantization unit and a decoder; wherein, the two inputs of the first quantization unit are respectively connected to the external signals Start and Stop, and the three outputs of the first quantization unit are respectively connected to the two inputs of the second quantization unit and one input of the decoder; the second quantization unit to the sixty-fourth quantization unit have the same structure and are connected in series with the first quantization unit to form the time-to-digital converter; the outputs of the first quantization unit to the sixty-fourth quantization unit are connected to the input of the decoder, and the output of the decoder is connected to the positive terminal of the first subtractor.

[0047] The first quantization unit includes a first delay unit, a second delay unit, and a D flip-flop; the first delay unit is connected to an external input Start, and the output of the first delay unit is connected to one input of the D flip-flop and the first delay unit of the second quantization unit; the second delay unit is connected to an external input Stop, and the output of the second delay unit is connected to the clock input of the D flip-flop and the second delay unit of the second quantization unit; the two inputs of the D flip-flop are respectively connected to the outputs of the first delay unit and the second delay unit, and the output of the D flip-flop is connected to a decoder.

[0048] The adaptive step / bandwidth control algorithm module includes a second adder, a second register, a frequency divider, a first digital comparator, a second digital comparator, a counter, and an OR gate. Among them, one input of the second adder is connected to an external Sign signal, and the other input is connected to the output of the second register. The output of the second adder is connected to the input of the second register, the negative input of the first comparator, and the positive input of the second digital comparator. The two inputs of the second register are respectively connected to the output of the second adder and the output of the OR gate. Another input of the second register is connected to an external clock signal Fref, and the output of the second register is connected to the input of the second adder. The input of the frequency divider is connected to an external clock signal Fref, and the output of the frequency divider is connected to the clock inputs of the first digital comparator and the second digital comparator. The positive input of the first digital comparator is connected to an external input Ntarget1, the negative input of the first digital comparator is connected to the output of the adder, the clock input of the first digital comparator is connected to the output of the frequency divider, and the output of the first digital comparator is connected to one input of the OR gate. The positive input of the second digital comparator is connected to the output of the second adder, the negative input of the second digital comparator is connected to an external input Ntarget2, the clock input of the second digital comparator is connected to the output of the frequency divider, and the output of the second digital comparator is connected to the other input of the OR gate. The two inputs of the OR gate are respectively connected to the outputs of the first digital comparator and the second digital comparator, and the output of the OR gate is connected to one input of the second register and Sel.

[0049] The LMS algorithm module includes a second multiplier, a third multiplier, a Mux, a third adder, and a third register. Among them, the two inputs of the second multiplier are respectively connected to the external inputs p[k] and e[k], and the output of the second multiplier is connected to one input of the third multiplier; the two inputs of the Mux are respectively connected to the external inputs γ0 and γ1, the selection terminal of the Mux is connected to the external input Sel, and the output of the Mux is connected to the other input of the third multiplier; the two inputs of the third multiplier are respectively connected to the output of the Mux and the output of the second multiplier, and the output of the third multiplier is connected to one input of the third adder; the two inputs of the third adder are respectively connected to the output of the third multiplier and the output of the third register, and the output of the third adder is connected to the input and the output terminal OUT of the third register; the input of the third register is connected to the output of the third adder, and the output of the third register is connected to one input of the third adder.

[0050] The digital loop filter includes a fourth multiplier, a fifth multiplier, a fourth adder, a fifth adder, a fourth register, a fifth register, a first Mux, and a second Mux. Among them, the two inputs of the fourth multiplier are respectively connected to the external digital signal e[k] and the output of the first Mux, and the output of the fourth multiplier is connected to the fifth adder; the two inputs of the fifth multiplier are respectively connected to the external digital signal e[k] and the output of the second Mux, and the output of the fifth multiplier is connected to the fourth adder. The two inputs of the first Mux are respectively connected to the external inputs α0 and α1, the selection terminal of the first Mux is connected to the external input Sel, and the output of the first Mux is connected to the input of the fourth multiplier; the two inputs of the second Mux are respectively connected to the external inputs β0 and β1, the selection terminal of the second Mux is connected to the external input Sel, and the output of the second Mux is connected to the input of the fifth multiplier. The two inputs of the fourth adder are respectively connected to the output of the fifth multiplier and the output of the fourth register, and the output of the fourth adder is connected to the input of the fourth register. The two inputs of the fourth register are respectively connected to the external clock Fref and the output of the fourth adder, and the output of the fourth register is connected to the input of the fourth adder and the input of the fifth adder. The two inputs of the fifth adder are respectively connected to the output of the fourth register and the output of the fourth multiplier; the output of the fifth adder is connected to the input of the fifth register. The two inputs of the fifth register are respectively connected to the output of the fifth adder and the external clock signal Fref, and the output of the fifth register is connected to OUT.

[0051] The digital control oscillator includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a coarse tuning capacitor array, a fine tuning capacitor array, and an inductor L1. Among them, the left and right ends of the inductor L1 are respectively connected to VP and VN, and the center tap of the inductor L1 is connected to VDD; the gate of the first NMOS transistor NM1 is connected to VN and one end of the first capacitor C1, the drain of NM1 is connected to VP, the gate of the second NMOS transistor NM2, and one end of the second capacitor C2, and the source of NM1 is connected to the source of the first PMOS transistor PM1; the gate of the second NMOS transistor NM2 is connected to VP and one end of the second capacitor C2, the drain of NM2 is connected to VN, the gate of the first NMOS transistor NM1, and one end of the first capacitor C1, and the source of NM2 is connected to the source of the second PMOS transistor PM2. The gate of the first PMOS transistor PM1 is connected to the other end of the second capacitor C2 and one end of the first resistor R1, the source of PM1 is connected to the source of the first NMOS transistor NM1, and the drain of PM1 is connected to GND; the gate of the second PMOS transistor PM2 is connected to the other end of the first capacitor C1 and one end of the second resistor R2, the source of PM2 is connected to the source of the second NMOS transistor NM2, and the drain of PM2 is connected to GND. One end of the first resistor R1 is connected to the gate of PM1 and the other end of the second capacitor C2, and the other end of the first resistor R1 is connected to GND; one end of the second resistor R2 is connected to the gate of PM2 and the other end of the first capacitor C1, and the other end of the second resistor R2 is connected to GND. One end of the first capacitor C1 is connected to the gate of NM1 and VN, and the other end of the first capacitor C1 is connected to the gate of PM2 and one end of R2; one end of the second capacitor C2 is connected to the gate of NM2 and VP, and the other end of the second capacitor C2 is connected to the gate of PM1 and one end of R1.

[0052] The fine tuning capacitor array consists of a third PMOS transistor and a fourth PMOS transistor in the first group, and the second to eighth groups of arrays with the same structure but different sizes. The sources and drains of the third PMOS transistor and the fourth PMOS transistor in the first group are both connected to the external input signal D F [0]. The gate of the third PMOS transistor is connected to VP, and the gate of the fourth PMOS transistor is connected to VN; the second to eighth groups of fine tuning capacitor arrays have the same structure and form an array together with the first group.

[0053] The coarse tuning capacitor array consists of an NMOS transistor, a third capacitor, a fourth capacitor, a third resistor, a fourth resistor, an inverter in the first group, and the second to fifth groups of coarse tuning capacitor arrays. One end of the third capacitor is connected to VP, and the other end is connected to one end of the third resistor and the source of the third NMOS transistor; the other end of the third resistor is connected to the output of the first inverter and one end of the fourth resistor; the gate of the third NMOS transistor is connected to the external input DC [0], the drain of the third NMOS transistor is connected to the other end of the fourth resistor and one end of the fourth capacitor; the other end of the fourth capacitor is connected to VN; the input of the first inverter is connected to the external input D C [0]; The second to fifth groups of coarse-tuning capacitor arrays all adopt the same structure and form an array together with the first group.

[0054] The multi-mode frequency divider includes a first 2 / 3 frequency divider to a sixth 2 / 3 frequency divider. Among them, the three inputs of the first 2 / 3 frequency divider are respectively connected to the external input Fin, P0, and the output of the second 2 / 3 frequency divider, and the output of the first 2 / 3 frequency divider is connected to one input of the second 2 / 3 frequency divider; the three inputs of the second 2 / 3 frequency divider are respectively connected to the external input P1, the output of the first 2 / 3 frequency divider, and the output of the third 2 / 3 frequency divider, and the two outputs of the second 2 / 3 frequency divider are respectively connected to the inputs of the first 2 / 3 frequency divider and the third 2 / 3 frequency divider; the three inputs of the third 2 / 3 frequency divider are respectively connected to the external input P2, the output of the second 2 / 3 frequency divider, and the output of the fourth 2 / 3 frequency divider, and the two outputs of the third 2 / 3 frequency divider are respectively connected to the inputs of the second 2 / 3 frequency divider and the fourth 2 / 3 frequency divider; the three inputs of the fourth 2 / 3 frequency divider are respectively connected to the external input P3, the output of the third 2 / 3 frequency divider, and the output of the fifth 2 / 3 frequency divider, and the two outputs of the fourth 2 / 3 frequency divider are respectively connected to the inputs of the third 2 / 3 frequency divider and the fifth 2 / 3 frequency divider; the three inputs of the fifth 2 / 3 frequency divider are respectively connected to the external input P4, the output of the fourth 2 / 3 frequency divider, and the output of the sixth 2 / 3 frequency divider, and the two outputs of the fifth 2 / 3 frequency divider are respectively connected to the inputs of the fourth 2 / 3 frequency divider and the sixth 2 / 3 frequency divider; the three inputs of the sixth 2 / 3 frequency divider are respectively connected to the external input P5, the output of the fifth 2 / 3 frequency divider, and the power supply voltage VDD, and the two outputs of the sixth 2 / 3 frequency divider are respectively connected to the input of the fifth 2 / 3 frequency divider and the output terminal Fout.

[0055] The ΣΔ modulator includes a 19-bit carry look-ahead adder (CLA), two 24-bit CLAs, a 5-bit shift module, four 1-bit registers, a 19-bit register, two 24-bit registers, and a noise cancellation circuit. Among them, the two input terminals of the 19-bit CLA are respectively connected to the 1-bit output terminal of the fourth register 4 and the 19-bit output terminal of the fifth register 5. The 19-bit output terminal of the 19-bit CLA is connected to the 19-bit input terminal of the 5-bit shift module. The 1-bit output terminal of the 19-bit CLA is respectively connected to the 1-bit input terminals of the first register 1 and the fifth register 5. The 24-bit output terminal of the 5-bit shift module is connected to the 24-bit input terminal of the first 24-bit CLA. The other two input terminals of the first 24-bit CLA are respectively connected to the 1-bit output terminal of the 19-bit CLA and the 24-bit output terminal of the sixth register 6. The 1-bit output terminal of the first 24-bit CLA is respectively connected to the 1-bit input terminals of the second register 2 and the second 24-bit CLA. The 24-bit output terminal of the first 24-bit CLA is connected to the 24-bit input terminal of the second 24-bit CLA. The other two input terminals of the second 24-bit CLA are respectively connected to the 1-bit output terminal of the 24-bit CLA and the 24-bit output terminal of the seventh register 7. The 1-bit output terminal of the second 24-bit CLA is connected to the 1-bit input terminal of the third register 3. The 24-bit output terminal of the second 24-bit CLA is connected to the 24-bit input terminal of the seventh register 7. The three input terminals of the noise cancellation circuit are respectively connected to the 1-bit output terminals of the first register 1, the second register 2, and the third register 3. The 4-bit output terminal of the noise cancellation circuit is connected to Y.

[0056] Details will be described below with reference to specific drawings.

[0057] As Figure 1 shown, the phase frequency detector detects the reference signal and the signal output by the frequency divider and generates a signal with two-band phase difference information and a symbol information of frequency advance or lag. Then, the time-to-digital converter converts the phase difference information into a digital signal and tunes it through the loop. The symbol information of frequency advance or lag generated by the phase frequency detector is input to the adaptive step / bandwidth control algorithm module to generate a selection signal Sel. The generated Sel signal performs loop bandwidth control and LMS algorithm step control, so as to achieve the performance of accelerating the loop lock time, reducing the in-band phase noise, and suppressing the fractional spurs.

[0058] The externally input frequency control word FCW is subtracted from the output of the ΣΔ modulator to generate the quantization error of the ΣΔ modulator. The generated quantization error continues to accumulate through the first adder and the first register to generate the digital sequence p[k]. The digital sequence p[k] of the quantization error is used as the input of the LMS algorithm module to fit the transfer function from the multimode frequency divider to the time-to-digital converter. After the output of the LMS algorithm module is multiplied by the digital sequence p[k], it is subtracted from the time-to-digital converter to generate the desired error sequence e[k]. The loop reasonably selects the convergence step size of the LMS through the adaptive step size / bandwidth control algorithm module, so that a smaller desired error sequence e[k] can be achieved to suppress the fractional spurs caused by the ΣΔ modulator, and at the same time, the convergence of the LMS algorithm can be accelerated. At the same time, the selection signal generated by the adaptive step size / bandwidth control algorithm module reasonably selects different gain coefficients of the digital loop filter to achieve different loop bandwidths, thereby accelerating the locking of the phase-locked loop and suppressing the in-band phase noise performance.

[0059] Figure 2 Figure 4 is the circuit diagram of the phase frequency detector, which adopts an edge sampling structure to extract the phase difference between the reference signal and the signal output by the frequency divider. To avoid the reference signal leading or lagging the signal output by the frequency divider so that the time-to-digital converter can normally quantify the phase difference, a latch circuit composed of NAND gates is added behind the phase frequency detector to process the UP / DN signals generated by the traditional phase frequency detector, thereby generating Start, Stop, and Sign signals. Regardless of whether the reference signal leads or lags the signal output by the frequency divider, the pulse width of the Start signal is always greater than that of the Stop signal, which can avoid the time-to-digital converter quantifying incorrectly when the Start and Stop signals are connected to the time-to-digital converter. When the frequency of the reference signal is greater than the frequency of the signal output by the frequency divider, the Sign signal output by the phase frequency detector is always "1"; when the frequency of the reference signal is less than the frequency of the signal output by the frequency divider, the Sign signal output by the phase frequency detector is always "0".

[0060] Figures 3(a) and 3(b) are the circuit diagrams of the time-to-digital converter and the quantization unit respectively, which adopt a vernier caliper structure to achieve better quantization linearity and higher quantization accuracy. In the circuit diagram of the quantization unit, the first delay unit is connected to the Start signal, and the second delay unit is connected to the Stop signal. The delay time of the first delay unit is greater than that of the second delay unit. Therefore, the time-to-digital converter can sample the Start signal through the Stop signal, thereby realizing the quantization of the phase error. The quantization accuracy of the time-to-digital converter is the difference between the delay times of the two different delay units. The higher the quantization accuracy, the better the in-band phase noise. To achieve a higher quantization accuracy, two inverters are used as delay units, and by setting different sizes of the delay units, a resolution at the sub-picosecond level can be achieved.

[0061] Figure 4 It is the circuit diagram of the adaptive step size / bandwidth control algorithm module. The externally input Sign signal is accumulated by the second adder and the second register and then output to the first digital comparator and the second digital comparator. After passing through the frequency divider N, Fref provides the clock Fref_N for the two digital comparators for digital comparison. The relationship between the two thresholds of the first digital comparator and the second digital comparator is N target2 >N target1 , set N target1 to 1, N target2 is N - 1 (N is the division ratio of the frequency divider). When the Sign signal is always "0", the phase-locked loop is not locked, and the output of the accumulator is always "0". At this time, the output Sel of the OR gate is "1"; when the Sign signal is always "1", the phase-locked loop is not locked, and the output of the accumulator is "N". At this time, the output Sel of the OR gate is "1"; when the Sign signal alternates between "0" and "1", the phase-locked loop is locked, and the output of the accumulator is near "N / 2". At this time, the output Sel of the OR gate is "0". Therefore, the Sel signal generated by the circuit can adaptively control the convergence step size of the LMS or the bandwidth of the digital loop filter according to the locked state of the phase-locked loop, thus achieving better performance.

[0062] Figure 5 It is the circuit diagram of the LMS algorithm module. The externally input digital sequence p[k] and the desired error sequence e[k] serve as the two inputs of the second multiplier of the LMS algorithm module. The Sel signal controls the convergence step sizes γ0 and γ1 of the LMS algorithm and performs multiplication and accumulation with the output of the second multiplier, so that the transfer function approximated by the LMS algorithm gradually approaches the transfer function of the original system. The Sel signal controls different convergence step sizes through the locked state of the loop, which can not only accelerate the convergence of the LMS algorithm but also reduce the desired error sequence to suppress fractional spurs.

[0063] Figure 6 It is the circuit diagram of the digital loop filter, which adopts a proportional-integral structure to reduce the circuit complexity. The externally input error sequence e[k] is multiplied by the output of the first Mux through the fourth multiplier to achieve the proportional path; the error sequence e[k] is multiplied by the output of the second Mux through the fifth multiplier and then accumulated through the fourth adder and the fourth register to achieve the integral path. The first Mux and the second Mux select different gain coefficients through the externally input Sel signal to achieve a wide band to accelerate loop locking and a narrow band to suppress in-band phase noise. After passing through the proportional and integral paths, the error sequence e[k] is added by the fifth adder to realize the function of the entire filter. The output of the fifth adder is used as the output through the register, thus avoiding the influence of the glitch caused by the fifth adder on the loop.

[0064] Figure 7It is the circuit diagram of a numerically controlled oscillator, which adopts a noise recycling structure to reduce the noise current injected into the resonator, thereby achieving lower phase noise. NM1, capacitor C2, and PM1 form a noise recycling path. When NM1 generates noise, the noise current will form a loop through NM1, capacitor C2, and PM1, causing a part of the noise current to circulate in NM1 and another part to be injected into the resonator to form phase noise, thus reducing the phase noise caused by NM1; similarly, when PM1 generates a noise current, a part of the noise current will pass through NM1 to reach the resonant circuit, generating phase noise, and the other part will circulate back to PM1 and finally reach the ground. The numerically controlled oscillator consists of a coarse-tuning capacitor array composed of 5-bit switched capacitors and a fine-tuning array composed of 8-bit MOS capacitors. NMOS transistors NM1 and NM2 provide negative resistance for the oscillator to compensate for the energy loss of the resonator. The coarse-tuning capacitor array covers the output frequency range with MIM capacitors, resistors, NMOS transistors, and inverters, and the fine-tuning capacitor array realizes a small capacitance jump by connecting two PMOS capacitors in series.

[0065] Figures 8(a) and 8(b) are respectively the circuit diagrams of the multi-mode frequency divider and the 2 / 3 frequency division unit. The multi-mode frequency divider adopts a 2 / 3 cascaded structure to cover the designed frequency division ratio. The 2 / 3 frequency division unit is composed of a D flip-flop with a TSPC structure and a gate circuit. Within the covered frequency range, the multi-mode frequency divider can not only work normally but also save power.

[0066] Figure 9 It is the circuit diagram of a ΣΔ modulator, which adopts a MASH 1-1-1 structure to generate an output of a digital sequence of [-3,4], can randomize the frequency division ratio of the multi-mode frequency divider, and at the same time push the quantization noise to high frequencies and then filter it out through the low-pass filter of the loop.

[0067] In summary, the present invention has been improved and optimized on the basis of the prior art and circuit structure. By detecting the locked state of the loop, the step size of the adaptive parallel adjustment LMS algorithm and the bandwidth of the digital loop filter are adjusted. When the phase-locked loop is not locked, the circuit selects a larger LMS step size and the gain coefficient of the digital loop filter, thereby shortening the convergence time of the LMS algorithm and the locking time of the phase-locked loop; when the phase-locked loop is locked, the circuit selects a smaller LMS step size and the gain coefficient of the digital loop filter, thereby suppressing fractional spurs and in-band phase noise.

[0068] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth, characterized in that: It includes a frequency discriminator and phase detector, a time-to-digital converter, an adaptive step / bandwidth control algorithm module, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator; Among them, the two input terminals of the frequency discriminator and phase detector are respectively connected to an external clock signal and the output signal of the multi-mode frequency divider. One output terminal of the frequency discriminator and phase detector is connected to the input terminal of the adaptive step / bandwidth control algorithm module, and the other two output terminals are connected to the input terminals of the time-to-digital converter; the outputs of the adaptive step / bandwidth control algorithm module are respectively connected to the LMS algorithm module and the digital loop filter; the output of the time-to-digital converter is connected to one input of the first subtractor; one input of the first subtractor is connected to the output of the time-to-digital converter as the subtrahend, and the other input is connected to the output of the first multiplier as the minuend. The output of the first subtractor is connected to the input of the digital loop filter and the input of the LMS algorithm module; One input of the second subtractor is connected to the externally input frequency control word FCW as the subtrahend, and the other input is connected to the output of the ΣΔ modulator as the minuend. The output of the second subtractor is connected to the input of the first adder; the two inputs of the first adder are respectively connected to the output of the second subtractor and the output of the first register. The output of the first adder is connected to the input of the first register, the input of the first multiplier, and one of the inputs of the LMS algorithm module; the two inputs of the first multiplier are respectively connected to the output of the first adder and the output of the LMS algorithm module. The output of the first multiplier is used as the other input of the first subtractor after being truncated; The three inputs of the LMS algorithm module are respectively connected to the output of the adaptive step / bandwidth control algorithm module, the output of the first adder, and the output of the first subtractor. The output of the LMS algorithm module is connected to one of the inputs of the first multiplier; the two inputs of the digital loop filter are respectively connected to the output of the first subtractor and the output of the adaptive step / bandwidth control algorithm module. The output of the digital loop filter is connected to the input of the numerically controlled oscillator; the two inputs of the ΣΔ modulator are respectively connected to the external signal FCW and the output of the multi-mode frequency divider. The output of the ΣΔ modulator is connected to the input of the multi-mode frequency divider and the other input of the second subtractor; the output of the numerically controlled oscillator is connected to the other input of the multi-mode frequency divider; the output of the multi-mode frequency divider is connected to one of the inputs of the frequency discriminator and phase detector and the clock terminal of the ΣΔ modulator.

2. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The frequency discriminator and phase detector includes a first D flip-flop, a second D flip-flop, a first NAND gate to a tenth NAND gate, a delay element, an AND gate, a first inverter, and a second inverter; Among them, the three inputs of the first D flip-flop are respectively connected to an external reference clock, a power supply voltage, and the output of a delay element. The output of the first D flip-flop is respectively connected to the inputs of a first NAND gate, a fifth NAND gate, an eighth NAND gate, and the input of an AND gate. The three inputs of the second D flip-flop are respectively connected to the output of a multi-mode frequency divider, a power supply voltage, and the output of a delay element. The output of the second D flip-flop is connected to the inputs of a second NAND gate, a sixth NAND gate, a ninth NAND gate, and the input of an AND gate. The inputs of the AND gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop, and the output of the AND gate is connected to the input of the delay element. The two inputs of the first NAND gate are respectively connected to the output of the first D flip-flop and the output of the second NAND gate, and the output of the first NAND gate is connected to the input of the third NAND gate. The two inputs of the second NAND gate are respectively connected to the output of the second D flip-flop and the output of the first NAND gate, and the output of the second NAND gate is connected to the input of the fourth NAND gate. The two inputs of the third NAND gate are respectively connected to the outputs of the first NAND gate and the fourth NAND gate, and the output of the third NAND gate is connected to the inputs of the fifth NAND gate and the ninth NAND gate. The two inputs of the fourth NAND gate are respectively connected to the outputs of the second NAND gate and the third NAND gate, and the output of the fourth NAND gate is connected to the inputs of the third NAND gate, the sixth NAND gate, the eighth NAND gate, and the input of a first inverter. The two inputs of the fifth NAND gate are respectively connected to the output of the first D flip-flop and the output of the third NAND gate, and the output of the fifth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the sixth NAND gate are respectively connected to the output of the second D flip-flop and the output of the fourth NAND gate, and the output of the sixth NAND gate is connected to the input of the seventh NAND gate. The two inputs of the seventh NAND gate are respectively connected to the outputs of the fifth NAND gate and the sixth NAND gate, and the output of the seventh NAND gate is connected to Start. The two inputs of the eighth NAND gate are respectively connected to the output of the first D flip-flop and the output of the fourth NAND gate, and the output of the eighth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the ninth NAND gate are respectively connected to the output of the second D flip-flop and the output of the third NAND gate, and the output of the ninth NAND gate is connected to the input of the tenth NAND gate. The two inputs of the tenth NAND gate are respectively connected to the outputs of the eighth NAND gate and the ninth NAND gate, and the output of the tenth NAND gate is connected to Stop. The input of the first inverter is connected to the output of the fourth NAND gate, and the output of the first inverter is connected to the input of the second inverter. The input of the second inverter is connected to the output of the first inverter, and the output of the second inverter is connected to Sign.

3. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The time-to-digital converter includes a first quantization unit to a sixty-fourth quantization unit and a decoder. The two inputs of the first quantization unit are respectively connected to external signals Start and Stop. The three outputs of the first quantization unit are respectively connected to two inputs of the second quantization unit and one input of the decoder. The second quantization unit to the sixty-fourth quantization unit have the same structure and are connected in series with the first quantization unit to form the time-to-digital converter. The outputs of the first quantization unit to the sixty-fourth quantization unit are connected to the input of the decoder, and the output of the decoder is connected to the positive terminal of a first subtractor. The first quantization unit includes a first delay unit, a second delay unit, and a D flip-flop; the first delay unit is connected to an external input Start, and the output of the first delay unit is connected to one input of the D flip-flop and the first delay unit of the second quantization unit; the second delay unit is connected to an external input Stop, and the output of the second delay unit is connected to the clock input of the D flip-flop and the second delay unit of the second quantization unit; the two inputs of the D flip-flop are respectively connected to the outputs of the first delay unit and the second delay unit, and the output of the D flip-flop is connected to a decoder.

4. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The adaptive step size / bandwidth control algorithm module includes a second adder, a second register, a frequency divider, a first digital comparator, a second digital comparator, a counter, and an OR gate; One input of the second adder is connected to an external Sign signal, and the other input is connected to the output of the second register. The output of the second adder is connected to the input of the second register, the negative input of the first comparator, and the positive input of the second digital comparator; the two inputs of the second register are respectively connected to the output of the second adder and the output of the OR gate. Another input of the second register is connected to an external clock signal Fref, and the output of the second register is connected to the input of the second adder; the input of the frequency divider is connected to an external clock signal Fref, and the output of the frequency divider is connected to the clock inputs of the first digital comparator and the second digital comparator; the positive input of the first digital comparator is connected to an external input Ntarget1, the negative input of the first digital comparator is connected to the output of the second adder, the clock input of the first digital comparator is connected to the output of the frequency divider, and the output of the first digital comparator is connected to one input of the OR gate; the positive input of the second digital comparator is connected to the output of the second adder, the negative input of the second digital comparator is connected to an external input Ntarget2, the clock input of the second digital comparator is connected to the output of the frequency divider, and the output of the second digital comparator is connected to the other input of the OR gate; the two inputs of the OR gate are respectively connected to the outputs of the first digital comparator and the second digital comparator, and the output of the OR gate is connected to one input of the second register and Sel.

5. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The LMS algorithm module includes a second multiplier, a third multiplier, a Mux, a third adder, and a third register; The two inputs of the second multiplier are respectively connected to external inputs p[k] and e[k], and the output of the second multiplier is connected to one input of the third multiplier; the two inputs of the Mux are respectively connected to external inputs γ0 and γ1, the selection terminal of the Mux is connected to an external input Sel, and the output of the Mux is connected to the other input of the third multiplier; the two inputs of the third multiplier are respectively connected to the output of the Mux and the output of the second multiplier, and the output of the third multiplier is connected to one input of the third adder; the two inputs of the third adder are respectively connected to the output of the third multiplier and the output of the third register, and the output of the third adder is connected to the input and the output terminal OUT of the third register; the input of the third register is connected to the output of the third adder, and the output of the third register is connected to one input of the third adder.

6. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The digital loop filter includes a fourth multiplier, a fifth multiplier, a fourth adder, a fifth adder, a fourth register, a fifth register, a first Mux, and a second Mux; Two inputs of the fourth multiplier are respectively connected to an external digital signal e[k] and the output of the first Mux, and the output of the fourth multiplier is connected to the fifth adder; two inputs of the fifth multiplier are respectively connected to the external digital signal e[k] and the output of the second Mux, and the output of the fifth multiplier is connected to the fourth adder; two inputs of the first Mux are respectively connected to external inputs α0 and α1, the selection terminal of the first Mux is connected to an external input Sel, and the output of the first Mux is connected to the input of the fourth multiplier; two inputs of the second Mux are respectively connected to external inputs β0 and β1, the selection terminal of the second Mux is connected to the external input Sel, and the output of the second Mux is connected to the input of the fifth multiplier; two inputs of the fourth adder are respectively connected to the output of the fifth multiplier and the output of the fourth register, and the output of the fourth adder is connected to the input of the fourth register; two inputs of the fourth register are respectively connected to an external clock Fref and the output of the fourth adder, and the output of the fourth register is connected to the input of the fourth adder and the input of the fifth adder; two inputs of the fifth adder are respectively connected to the output of the fourth register and the output of the fourth multiplier; the output of the fifth adder is connected to the input of the fifth register; two inputs of the fifth register are respectively connected to the output of the fifth adder and an external clock signal Fref, and the output of the fifth register is connected to OUT.

7. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The numerically controlled oscillator includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a coarse tuning capacitor array, a fine tuning capacitor array, and an inductor L1; The left and right ends of the inductor L1 are respectively connected to VP and VN, and the center tap of the inductor L1 is connected to VDD; the gate of the first NMOS transistor NM1 is connected to VN and one end of the first capacitor C1, the drain of NM1 is connected to VP, the gate of the second NMOS transistor NM2 and one end of the second capacitor C2, and the source of NM1 is connected to the source of the first PMOS transistor PM1; the gate of the second NMOS transistor NM2 is connected to VP and one end of the second capacitor C2, the drain of NM2 is connected to VN, the gate of the first NMOS transistor NM1 and one end of the first capacitor C1, and the source of NM2 is connected to the source of the second PMOS transistor PM2; the gate of the first PMOS transistor PM1 is connected to the other end of the second capacitor C2 and one end of the first resistor R1, the source of PM1 is connected to the source of the first NMOS transistor NM1, and the drain of PM1 is connected to GND; the gate of the second PMOS transistor PM2 is connected to the other end of the first capacitor C1 and one end of the second resistor R2, the source of PM2 is connected to the source of the second NMOS transistor NM2, and the drain of PM2 is connected to GND; one end of the first resistor R1 is connected to the gate of PM1 and the other end of the second capacitor C2, and the other end of the first resistor R1 is connected to GND; one end of the second resistor R2 is connected to the gate of PM2 and the other end of the first capacitor C1, and the other end of the second resistor R2 is connected to GND; one end of the first capacitor C1 is connected to the gate of NM1 and VN, and the other end of the first capacitor C1 is connected to the gate of PM2 and one end of R2; one end of the second capacitor C2 is connected to the gate of NM2 and VP, and the other end of the second capacitor C2 is connected to the gate of PM1 and one end of R1.

8. The fractional all-digital phase-locked loop according to claim 7, characterized in that: The fine-tuning capacitor array consists of the third PMOS transistor and the fourth PMOS transistor in the first group, and arrays in the second to eighth groups with the same structure but different sizes. The sources and drains of the third PMOS transistor and the fourth PMOS transistor in the first group are both connected to the external input signal D F [0]. The gate of the third PMOS transistor is connected to VP, and the gate of the fourth PMOS transistor is connected to VN. The fine-tuning capacitor arrays in the second to eighth groups all adopt the same structure and form an array together with the first group; The coarse-tuning capacitor array is composed of NMOS transistors in the first group, a third capacitor, a fourth capacitor, a third resistor, a fourth resistor, an inverter, and the second to fifth coarse-tuning capacitor arrays. One end of the third capacitor is connected to VP, and the other end is connected to one end of the third resistor and the source of the third NMOS transistor. The other end of the third resistor is connected to the output of the first inverter and one end of the fourth resistor. The gate of the third NMOS transistor is connected to the external input D C [0], and the drain of the third NMOS transistor is connected to the other end of the fourth resistor and one end of the fourth capacitor. The other end of the fourth capacitor is connected to VN. The input of the first inverter is connected to the external input D C [0]; The second to fifth coarse-tuning capacitor arrays all adopt the same structure and jointly form an array with the first group.

9. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The multi-mode frequency divider includes a first 2 / 3 frequency divider to a sixth 2 / 3 frequency divider; The three inputs of the first 2 / 3 frequency divider are respectively connected to the external input Fin, P0, and the output of the second 2 / 3 frequency divider, and the output of the first 2 / 3 frequency divider is connected to one input of the second 2 / 3 frequency divider; the three inputs of the second 2 / 3 frequency divider are respectively connected to the external input P1, the output of the first 2 / 3 frequency divider, and the output of the third 2 / 3 frequency divider, and the two outputs of the second 2 / 3 frequency divider are respectively connected to the inputs of the first 2 / 3 frequency divider and the third 2 / 3 frequency divider; the three inputs of the third 2 / 3 frequency divider are respectively connected to the external input P2, the output of the second 2 / 3 frequency divider, and the output of the fourth 2 / 3 frequency divider, and the two outputs of the third 2 / 3 frequency divider are respectively connected to the inputs of the second 2 / 3 frequency divider and the fourth 2 / 3 frequency divider; the three inputs of the fourth 2 / 3 frequency divider are respectively connected to the external input P3, the output of the third 2 / 3 frequency divider, and the output of the fifth 2 / 3 frequency divider, and the two outputs of the fourth 2 / 3 frequency divider are respectively connected to the inputs of the third 2 / 3 frequency divider and the fifth 2 / 3 frequency divider; the three inputs of the fifth 2 / 3 frequency divider are respectively connected to the external input P4, the output of the fourth 2 / 3 frequency divider, and the output of the sixth 2 / 3 frequency divider, and the two outputs of the fifth 2 / 3 frequency divider are respectively connected to the inputs of the fourth 2 / 3 frequency divider and the sixth 2 / 3 frequency divider; the three inputs of the sixth 2 / 3 frequency divider are respectively connected to the external input P5, the output of the fifth 2 / 3 frequency divider, and the power supply voltage VDD, and the two outputs of the sixth 2 / 3 frequency divider are respectively connected to the input of the fifth 2 / 3 frequency divider and the output terminal Fout.

10. The fractional all-digital phase-locked loop according to claim 1, characterized in that: The ΣΔ modulator includes a 19-bit CLA, two 24-bit CLAs, a 5-bit shift module, four 1-bit registers, a 19-bit register, two 24-bit registers, and a noise cancellation circuit; The two input terminals of the 19-bit CLA are respectively connected to the 1-bit output terminal of the fourth register and the 19-bit output terminal of the fifth register. The 19-bit output terminal of the 19-bit CLA is connected to the 19-bit input terminal of the 5-bit shift module. The 1-bit output terminal of the 19-bit CLA is respectively connected to the 1-bit input terminals of the first register and the fifth register. The 24-bit output terminal of the 5-bit shift module is connected to the 24-bit input terminal of the first 24-bit CLA. The other two input terminals of the first 24-bit CLA are respectively connected to the 1-bit output terminal of the 19-bit CLA and the 24-bit output terminal of the sixth register. The 1-bit output terminal of the first 24-bit CLA is respectively connected to the 1-bit input terminals of the second register and the second 24-bit CLA. The 24-bit output terminal of the first 24-bit CLA is connected to the 24-bit input terminal of the second 24-bit CLA. The other two input terminals of the second 24-bit CLA are respectively connected to the 1-bit output terminal of the 24-bit CLA and the 24-bit output terminal of the seventh register. The 1-bit output terminal of the second 24-bit CLA is connected to the 1-bit input terminal of the third register. The 24-bit output terminal of the second 24-bit CLA is connected to the 24-bit input terminal of the seventh register. The three input terminals of the noise cancellation circuit are respectively connected to the 1-bit output terminals of the first register, the second register, and the third register. The 4-bit output terminal of the noise cancellation circuit is connected to Y.

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