A high-speed flash-sar hybrid analog-to-digital converter

Abstract

The application provides a high-speed Flash-SAR hybrid analog-digital converter and belongs to the technical field of chips.The application comprises a sampling switch, a Flash ADC, a comparator, a capacitive digital-analog converter, a successive approximation register and a digital error correction circuit.The application adopts a full-differential structure, an input signal is rapidly converted into a 3-digit code through the Flash ADC, meanwhile, the conversion of a high 3-digit capacitor corresponding switch of the capacitive digital-analog converter is controlled, and the conversion of the following digit is completed through the comparator.The capacitive array is divided into two sections, each section of capacitors adopts a capacitive architecture design based on binary error compensation, so that the errors caused by the imbalance of the comparator, the incomplete establishment of the top plate voltage and the thermal noise of the conversion switch itself are reduced;and due to the existence of the encoding circuit in the Flash ADC, the conversion from the thermometer code to the binary code is realized, the area of the chip is saved, and the power consumption is reduced.

Claims

1. A high-speed Flash-SAR hybrid analog-to-digital converter, characterized in that, The analog-to-digital converter includes sampling switch 1, sampling switch 2, a Flash ADC with coarse quantization of the first three bits, comparator Comp, a capacitive digital-to-analog converter, a successive approximation register, and a digital error correction circuit. The input signal is output to the upper plate of the capacitor array of the capacitive digital-to-analog converter through sampling switch 1. The upper plate of the capacitor array is also connected to the input of comparator Comp. The output of comparator Comp is connected to the successive approximation register. The input signal is output to the Flash ADC through sampling switch 2. The 3-bit binary code output by the encoder in the Flash ADC is connected to the successive approximation register. The successive approximation register controls the first three capacitors of the capacitor array. The capacitors after the first three capacitors of the capacitor array are controlled by the result of comparator Comp. The successive approximation register stores the comparison result and outputs it to the digital error correction circuit, finally obtaining the binary output.

2. The high-speed Flash-SAR hybrid analog-to-digital converter according to claim 1, characterized in that, The Flash ADC includes a voltage divider, a switching network A, a switching network B, a DFF, comparators CompA and CompB, and an encoder. When the input signal passes through sampling switch 2 to obtain sampling signals VP and VN, VP is connected to the positive terminal of switching network A and the positive terminal of comparator CompA, and VN is connected to the negative terminal of switching network A and the negative terminal of comparator CompA. Comparator CompA starts working when the input clock signal CLKC1 goes high, comparing the magnitudes of the voltages VP and VN. When the voltage of VP is greater than the voltage of VN, the output VOP is 1 and VON is 0; when the voltage of VP is less than the voltage of VN, the output VOP is 0 and VON is 1. VOP and VON serve as control signals for switching network A, connecting the larger signal of sampling signals VP and VN to the voltage divider and then to switching network B through switching network A, while the smaller signal is directly connected to switching network B through switching network A. The voltage divider consists of eight resistors of equal magnitude. When a larger signal passes through switch network A and reaches the voltage divider, the voltage value decreases by 1 / 8 with each resistor it passes through. There is a path between every two resistors that connects to switch network B, for a total of seven such paths. The control signals for switch network B are also VOP and VON. The output of switch network B is connected to the input of comparator CompB. The function of switch network B is to connect the VP signal to the positive terminal of comparator CompB. The larger signal is divided into seven signals with progressively decreasing voltage values ​​by the voltage divider, and each signal is compared with a smaller signal by comparator CompB. CLKC2 represents the timing parameters of comparator CompB. When CLKC2 goes high, CompB starts working. When the voltage value of VP is greater than VN, the output is 1; when the voltage value of VN is greater than VP, the output is 0. Similarly, there are 7 comparators CompB, with each path corresponding to one such comparator. The output of each comparator CompB is connected to a DFF, which stores the value output by the comparator CompB. CLKC3 is the clock signal for the DFF. When CLKC3 goes high, the output value of the DFF is equal to the input value. The outputs of the 7 DFFs are 7-bit thermometer codes. The outputs of the DFFs are connected to the input of the encoder. The encoder converts the 7-bit thermometer code into a 3-bit binary code and then outputs it.

3. A high-speed Flash-SAR hybrid analog-to-digital converter according to claim 1 or 2, characterized in that, The described capacitive digital-to-analog converter uses a non-binary error-compensated capacitor array, with bridging capacitor C. b The capacitor array is divided into two segments: a low-order capacitor array (LSB) with 4-bit quantization precision and a high-order capacitor array (MSB) with 6-bit quantization precision; the low-order capacitor array includes C LSB1 =8C unit C LSB2 =4C unit C LSB3 =2C unit C LSB3C =2C unit C LSB4 =C unit The high-level capacitor array includes: C MSB1 =16C unit C MSB2 =8C unit C MSB3 =4C unit C MSB3C =4C unit C MSB4 =2C unit C MSB5 =C unit ; where C MSBN For the Nth high-order capacitor, C MSBNC C is the compensation capacitor for the Nth high-order capacitor. unit Unit capacitance; The capacitor array of the capacitive digital-to-analog converter is divided into two sides, namely the P side and the N side. After sampling by sampling switch 1, the signal obtained on the P side is VP1, and the signal obtained on the N side is VN1. Both VP1 and VN1 are connected to the upper plate of the capacitor array. At the same time, VP1 is also connected to the positive terminal of comparator Comp, and VN1 is connected to the negative terminal of comparator Comp.

4. A high-speed Flash-SAR hybrid analog-to-digital converter according to claim 3, characterized in that, The comparator Comp compares VP1 and VN1 when the clock signal CLKC goes high. When the voltage value of VP1 is greater than that of VN1, the output value B is 1; when the voltage value of VP1 is less than that of VN1, the output value B is 0. Each time the comparator Comp performs a comparison, the comparison result generates a VALID signal, which in turn triggers the clock generator to produce a shift clock.

5. A high-speed Flash-SAR hybrid analog-to-digital converter according to claim 4, characterized in that, The clock generator consists of a DFF and an inverter; the input of the first DFF is connected to a high level, and its output is connected to the input of the inverter, while the output of the inverter is connected to the input of the next DFF, and so on, in sequence; the VALID signal is the clock signal of the DFF. Whenever the VALID signal changes from low level to high level, the DFF generates a shift clock, which is then passed to the successive approximation register.

6. A high-speed Flash-SAR hybrid analog-to-digital converter according to claim 5, characterized in that, The successive approximation register consists of a switching switch and a DFF. The switching switch is connected to the bottom plate of the capacitor array of the capacitive digital-to-analog converter. The input signal of the switching switch is the output signal of the comparator Comp, and the clock signal of the switching switch is the shift clock. Each output result of the comparator Comp is transmitted to the switching switch. After the shift clock goes high, the switching switch starts to switch, causing the capacitor array of the capacitive digital-to-analog converter to charge and discharge, thereby achieving the successive approximation of VP1 and VN1. At the same time, the DFF stores B11~B9 outputs of the Flash ADC and B8~B0 outputs of the comparator Comp and transmits them to the digital error correction circuit.

7. A high-speed Flash-SAR hybrid analog-to-digital converter according to claim 6, characterized in that, The digital error correction circuit converts a 12-bit non-binary code number into a 10-bit binary code number; the input of the digital error correction circuit is the number output by the DFF in the successive approximation register, and the output is the overall output of the Flash-SAR hybrid analog-to-digital converter.

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