Fault isolation method and apparatus, switch and storage medium

Abstract

Embodiments of the present application disclose a fault isolation method and device, a switch and a storage medium. The method can be applied to a switch, the switch comprising a CPU and a FPGA, the CPU and the FPGA being in communication connection with a timer; the fault isolation method comprising: sending a signal to the timer by the CPU, and determining whether the switch has a fault according to detected state information of the timer; in the case that it is determined that the CPU has a fault, sending a signal to the timer by the FPGA, and clearing a target configuration of the switch according to a preset protocol file, so that the network connectivity can be ensured and the fault site can be isolated when the CPU in the switch has a fault.

Description

Technical Field

[0001] The present invention relates to the field of Ethernet communication technology, and in particular to a fault isolation method, device, switch and storage medium. Background Technology

[0002] With the continuous development of communication technology, various types of networks have emerged, and network protocols have become increasingly numerous. The network functions of switches have also become more and more complex, leading to a greater possibility of software errors in switches. In particular, some special industries have put forward customized protocol requirements for switches based on the specific application scenarios of their systems. Switch manufacturers often need to design, develop, and conduct on-the-ground testing for these special protocols. Due to the complex environment during actual on-site testing, switch software failures may occur, such as program crashes or infinite loops that cause the central processing unit (CPU) to hang. Simple simulation of the environment cannot reproduce the problem, requiring on-site connection and JTAG localization. The time required for problem localization and analysis is relatively long. Given the importance of the network in the entire system, a failure of the switch protocol may paralyze the network, which is often fatal and unacceptable for the entire system.

[0003] Currently, one approach to addressing the aforementioned issues is to use a watchdog timer to reset and restart the switch, thereby quickly restoring network functionality. However, this method cannot preserve the fault context of the switch, hindering the localization and analysis of switch software problems. Another approach is for switches to use heartbeat messages to detect the availability of the switch's CPU. If a switch does not receive a heartbeat message from the other end, it considers the other end to be faulty and closes the ports connected to the other end to isolate the faulty switch. However, this method prevents normal communication for devices or terminals connected to the faulty switch. Summary of the Invention

[0004] This invention provides a fault isolation method, device, switch, and storage medium to ensure network connectivity and isolation of the fault location when a CPU in the switch fails.

[0005] According to one aspect of the present invention, a fault isolation method is provided, applied to a switch, the switch including a CPU and a Field Programmable Gate Array (FPGA), the CPU and the FPGA being communicatively connected to timers respectively, the method comprising:

[0006] The CPU sends a signal to the timer, and determines whether the switch has malfunctioned based on the detected status information of the timer.

[0007] If a CPU malfunction is detected, a signal is sent to the timer via the FPGA, and the target configuration of the switch is cleared according to a preset protocol file, wherein the target configuration is the configuration related to the CPU.

[0008] According to another aspect of the present invention, a fault isolation device is provided, applied to a switch, the switch including a CPU and an FPGA, the CPU and the FPGA being communicatively connected to a timer respectively, the device comprising:

[0009] The fault detection module is used to send a signal to the timer through the CPU and determine whether the switch has malfunctioned based on the detected status information of the timer.

[0010] The fault clearing module is used to send a signal to the timer through the FPGA when it is determined that the CPU has failed, and to clear the target configuration of the switch according to a preset protocol file, wherein the target configuration is the configuration related to the CPU.

[0011] According to another aspect of the present invention, a switch is provided, the switch comprising:

[0012] At least one processor; and

[0013] A memory communicatively connected to the at least one processor; wherein,

[0014] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the fault isolation method described in any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the fault isolation method described in any embodiment of the present invention.

[0016] The technical solution of this invention can be applied to a switch, which includes a CPU and an FPGA. The CPU and the FPGA are respectively communicatively connected to a timer. Specifically, the CPU can send a signal to the timer, and the switch can be determined to have malfunctioned based on the detected status information of the timer. If the CPU is determined to have malfunctioned, the FPGA can send a signal to the timer, and the target configuration of the switch can be cleared according to a preset protocol file. This ensures that when the CPU in the switch malfunctions, both network connectivity can be maintained and the fault location can be isolated.

[0017] It should be understood that the description in this section is not intended to identify key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the embodiments of the present invention. Other features of the embodiments of the present invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a fault isolation method provided according to Embodiment 1 of the present invention;

[0020] Figure 2 This is a schematic diagram of the structure of a switch according to Embodiment 1 of the present invention;

[0021] Figure 3 This is a flowchart of a fault isolation method provided according to Embodiment 2 of the present invention;

[0022] Figure 4 This is a schematic diagram of switch fault isolation in the prior art according to Embodiment 2 of the present invention;

[0023] Figure 5 This is a flowchart of a fault isolation method provided according to Embodiment 2 of the present invention;

[0024] Figure 6 This is a schematic diagram of a fault isolation device according to Embodiment 3 of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure of a switch that implements the fault isolation method of this invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Example 1

[0029] Figure 1 This is a flowchart of a fault isolation method according to Embodiment 1 of the present invention. This embodiment is applicable to the detection of switch faults and the isolation of detected faults. The method can be executed by a fault isolation device, which can be implemented in hardware and / or software and can be configured in the switch.

[0030] Figure 2 This is a schematic diagram of the structure of a switch according to Embodiment 1 of the present invention, with reference to... Figure 2 The switch 200 involved in this embodiment mainly includes a CPU 210 and an FPGA 220. In this embodiment, the CPU 210 and FPGA 220 are respectively connected to the timer 230. It should be noted that the timer 230 involved in this embodiment can be a hardware watchdog or a software watchdog, and this embodiment does not limit it.

[0031] For details, please refer to Figure 1 The fault isolation method involved in this embodiment mainly includes the following steps:

[0032] Step 110: The CPU sends a signal to the timer, and determines whether the switch has malfunctioned based on the detected status information of the timer.

[0033] In one optional implementation of this embodiment, the CPU can periodically send signals to the timer. For example, the CPU can send a clear signal, a reset signal, or a heartbeat message signal to the timer. This embodiment does not limit the specific implementation of these signals.

[0034] Optionally, in this embodiment, the CPU can send a reset signal to the timer every minute to observe the timer's feedback information in response to the reset signal. For example, the timer can reset its timed information every time it receives a reset signal.

[0035] In one optional implementation of this embodiment, the fault status of the switch can be determined based on the feedback information of the timer's signal to the CPU. For example, in response to a reset signal sent by the CPU, the timer's feedback information is whether to reset the timed information; in response to a clear signal sent by the CPU, the timer's feedback information is whether to clear the timed information. Furthermore, if no feedback information of the timer's signal to the CPU is detected, it can be determined that the CPU of the switch has malfunctioned. For example, a CPU malfunction could be caused by a program crash or an infinite loop leading to CPU hang, etc., which are not limited in this embodiment.

[0036] Step 120: If the CPU is found to be faulty, a signal is sent to the timer through the FPGA, and the target configuration of the switch is cleared according to the preset protocol file.

[0037] The target configuration is a configuration related to the CPU.

[0038] The preset protocol file can contain all the switch's configuration information, which is categorized. For example, the configuration information can be divided into CPU-related configurations and CPU-independent configurations. CPU-related configurations are those that require CPU forwarding, such as unicast enable configuration, multicast enable configuration, Multi-Protocol Label Switching (MPLS) enable configuration, Media Access Control Address (MAC) configuration, and protocol upload to CPU configuration. CPU-independent configurations are those that do not require CPU participation in forwarding, such as port enable configuration, rate configuration, flow control configuration, Maximum Transmission Unit (MTU) configuration, Spanning Tree State configuration, and Virtual Local Area Network (VLAN) configuration. In this embodiment, the target configuration is the CPU-related configuration.

[0039] In an optional implementation of this embodiment, if it is determined that the CPU has failed based on the feedback information of the timer, then signals can continue to be sent to the timer through the FPGA. For example, the FPGA can send a reset signal, a clear signal, or a heartbeat message signal to the timer, and further clear the target configuration of the switch according to the preset protocol file.

[0040] Optionally, in this embodiment, if a CPU malfunction is determined, while sending a signal to the timer via the FPGA, a target configuration can also be determined according to a preset protocol file, and these target configurations can be further cleared.

[0041] Understandably, the target configuration requires CPU forwarding. In the event of a CPU failure, these configurations cannot proceed smoothly. Therefore, clearing these configurations will not affect configurations that do not require CPU forwarding. This ensures the normal operation of the switch while also isolating the switch failure site.

[0042] The technical solution of this embodiment involves the CPU sending a signal to the timer and determining whether the switch has malfunctioned based on the detected status information of the timer. If the CPU is determined to be malfunctioning, the FPGA sends a signal to the timer and clears the target configuration of the switch according to a preset protocol file. This ensures that when the CPU in the switch malfunctions, network connectivity can be maintained and the fault location can be isolated.

[0043] Example 2

[0044] Figure 3 This is a flowchart of a fault isolation method according to Embodiment 2 of the present invention. This embodiment is a further refinement of the above-described technical solutions, and the technical solutions in this embodiment can be combined with the optional solutions in one or more of the above embodiments. Figure 3 As shown, the fault isolation method may include the following steps:

[0045] Step 310: At each set time interval, the CPU sends a timer reset signal to the timer.

[0046] The time interval can be set to 30 seconds, 1 minute, or 5 minutes, etc., and this embodiment does not limit it.

[0047] In an optional implementation of this embodiment, the CPU can send a timer reset signal to the timer every 5 minutes so that the timer can reset the recorded time.

[0048] Step 320: In response to the completion instruction of sending the target timer reset signal, detect the status information of the timer; if the status information of the timer is detected as not being reset within a set time, then determine that the CPU has malfunctioned.

[0049] The status information includes whether the timer is cleared or not; the target timer clearing can be a timer clearing signal sent by the CPU to the timer at any time. The set time can be 1 second, 2 seconds, or 5 seconds after the CPU sends the timer clearing signal, etc., and is not limited to this embodiment.

[0050] In one optional implementation of this embodiment, after the CPU sends a timer reset signal to the timer, the timer's status information can be detected in real time. If it is detected that the timer has not reset its counted data within a set time (e.g., 5 seconds), that is, the timer's status information is always "timer not reset", then it can be determined that the timer reset signal sent by the CPU has not been delivered to the timer, and it can be considered that the CPU has malfunctioned. For example, the CPU program may crash or the CPU may be stuck in an infinite loop, which would also determine that the switch has malfunctioned.

[0051] Step 330: Send a signal to the timer via the FPGA.

[0052] In an optional implementation of this embodiment, after determining that the CPU of the switch has failed, a signal can be sent to the timer through the FPGA, that is, the FPGA takes over the work of the CPU and controls the switch through the FPGA. This can ensure that the switch can continue to complete the switching work even if the CPU fails.

[0053] Step 340: Clear the target configuration of the switch according to the preset protocol file.

[0054] In an optional implementation of this embodiment, after the FPGA sends a signal to the timer, that is, after the FPGA controls the switch, the FPGA can clear the target configuration of the switch according to a preset protocol file.

[0055] In an optional implementation of this embodiment, before clearing the target configuration of the switch according to the preset protocol file, the method may further include: determining the forwarding type of each configuration contained in the switch, and generating the preset protocol file according to the forwarding type.

[0056] The switch configurations include port Layer 2 configurations (e.g., port enable configuration, rate configuration, flow control configuration, MTU configuration, or spanning tree state configuration), VLAN configurations (e.g., VLAN creation, ports included in a VLAN, or VLAN attributes added to a port), unicast enable configurations, multicast enable configurations, MPLS enable configurations, routing MAC configurations, and protocol upload to the CPU configuration, etc., which are not limited in this embodiment.

[0057] In one optional implementation of this embodiment, the forwarding type of each configuration included in the switch can be determined, and the preset protocol file can be generated according to the forwarding type. The forwarding type can be Layer 2 forwarding or Layer 3 forwarding. It can be understood that Layer 2 forwarding is a configuration that does not require CPU participation and is CPU-independent; Layer 3 forwarding is a configuration that requires CPU participation and is CPU-dependent.

[0058] In an optional implementation of this embodiment, generating the preset protocol file according to the forwarding type may include: determining the configuration with the forwarding type of Layer 3 forwarding as the target configuration, extracting the target name of each target configuration, and storing each target name in the first area of ​​the target file; determining the configuration with the forwarding type of Layer 2 forwarding as the reference configuration, extracting the reference name of each reference configuration, and storing each reference name in the second area of ​​the target file; merging the first area and the second area of ​​the target file to obtain the preset protocol file.

[0059] The target file can be any file, such as an XML file, a TXT file, or a DOC file, and this embodiment does not limit it.

[0060] The first region and the second region can be any region of the target file. For example, the first region can be the first page of the target file and the second region can be the second page of the target file; or the first region can be the left side of the target file and the second region can be the right side of the target file. In this embodiment, they are not limited.

[0061] Optionally, in this embodiment, the target configuration may include at least one of the following: unicast enable configuration, multicast enable configuration, MPLS enable configuration, MAC configuration, and protocol upload to CPU configuration; the reference configuration may include at least one of the following: port enable configuration, rate configuration, flow control configuration, MTU configuration, spanning tree state configuration, and VLAN configuration.

[0062] Optionally, in this embodiment, all configurations contained in the switch can be obtained, and the forwarding type of each configuration can be determined. It is understood that in this embodiment, different configurations can be classified according to different forwarding types, and the classified different configurations can be stored in different areas of a file. For example, if the forwarding type of the first configuration is Layer 3 forwarding, the first configuration can be determined as the target configuration, and the configuration name corresponding to the first configuration can be stored in the first area of ​​the target file. If the forwarding type of the second configuration is Layer 2 forwarding, the second configuration can be determined as the reference configuration, and the configuration name corresponding to the second configuration can be stored in the second area of ​​the target file. After all the configurations of the switch are determined, the first area and the second area of ​​the target file can be merged to obtain a complete preset protocol file.

[0063] In an optional implementation of this embodiment, clearing the target configuration of the switch according to a preset protocol file may include: obtaining each target name stored in a first area of ​​the preset file; determining the target configuration corresponding to each target name within the switch; and clearing each target configuration.

[0064] In this embodiment, the names of each target configuration can be determined from a preset protocol file. For example, the names of each target configuration can be found in the first area of ​​the preset protocol file. Furthermore, the target configurations corresponding to these names can be determined in the switch, thereby clearing these target configurations.

[0065] It is understood that the first area of ​​the preset file stores all configurations with the forwarding type of Layer 3 forwarding; in this embodiment, obtaining all the names stored in the first area means obtaining all the target configurations, and further, these target configurations can be quickly cleared.

[0066] The advantage of this setup is that it allows for the rapid identification of CPU-related configurations. Once a CPU malfunction is identified, these configurations can be cleared immediately, thus better preserving the fault scene.

[0067] Optionally, in this embodiment, after clearing the target configuration of the switch according to the preset protocol file, it may further include: obtaining each reference name stored in the second area of ​​the preset protocol file; and forwarding each packet received by the switch according to the reference configuration corresponding to each reference name.

[0068] It is understandable that after isolating and clearing the Layer 3 forwarding configurations (i.e. target configurations) that require CPU participation, the forwarding of each packet data can be achieved by using the retained Layer 2 forwarding configurations (i.e. reference configurations) in conjunction with the FPGA, thus ensuring the normal operation of the switch.

[0069] In one example of this embodiment, after controlling the switch via FPGA, the Layer 2 forwarding configuration of the switching chip can be further retained while other forwarding table configurations are cleared. For example, the Layer 2 forwarding configuration can be retained to ensure network connectivity, the port Layer 2 configuration can be retained to ensure normal physical network connectivity, and the VLAN configuration can be retained to ensure Ethernet Layer 2 connectivity. The unicast enable, multicast enable, MPLS enable, and routing MAC configuration can be cleared to ensure that the switch only performs Layer 2 forwarding and does not perform other forwarding behaviors. The protocol upload to CPU configuration can be cleared to allow protocol packets to be transparently transmitted, thus not affecting the protocol interaction and forwarding table generation of other switches in the network.

[0070] In this embodiment, the CPU sends a timer reset signal to the timer at set time intervals. If the timer reset is not detected within the first time, the CPU is determined to be faulty. By sending a signal to the timer through the FPGA, the FPGA can control the switch. At the same time, by creating a preset protocol file, the CPU-related configurations can be quickly determined and cleared and isolated. When the CPU fails, network connectivity can be guaranteed, and the fault location can be isolated.

[0071] Figure 4 This is a schematic diagram of switch fault isolation in the prior art provided by Embodiment 2 of the present invention, as shown below. Figure 1 As shown, in the prior art, if switch 400 does not receive a heartbeat detection message from peer switch 410, it considers peer switch 410 to be faulty. At this time, it will close the port connecting switch 400 and peer switch 410, thereby isolating the faulty switch. This isolation method prevents devices or terminals connected to peer switch 410 from communicating normally.

[0072] To address the aforementioned issues, this invention implements a watchdog function using an FPGA. The CPU periodically feeds the watchdog. When the CPU is stuck and unable to feed the watchdog, the FPGA takes over the management channel with the switching chip, retains the Layer 2 forwarding configuration of the switching chip, clears other forwarding table configurations, and enables transparent forwarding of packets. The switch does not participate in protocol interaction or other forwarding table generation, thus achieving fault isolation of the switch without affecting the overall network communication, facilitating the location and analysis of faulty switches.

[0073] To better understand the embodiments of the present invention, Figure 5 This is a flowchart of a fault isolation method provided according to Embodiment 2 of the present invention, as follows: Figure 5 As shown, it mainly includes the following steps:

[0074] Step 510: Has the CPU feeding period expired?

[0075] If so, proceed to step 520;

[0076] Otherwise, return to step 510.

[0077] Step 520: Has a fault occurred?

[0078] If so, proceed to step 530;

[0079] Otherwise, proceed to step 540.

[0080] Step 530: The FPGA takes over the control channel of the switching chip, retains the Layer 2 forwarding configuration of the switching chip, and clears the forwarding configuration of the CPU.

[0081] Step 540: Reset the switching chip and reset the CPU.

[0082] This invention, through monitoring the CPU's operating status, clears the protocol-generated forwarding table but retains the Layer 2 forwarding table configuration when the CPU hangs. This ensures the connectivity of the switching network while preserving the fault scene, providing conditions for on-site fault location. It represents a superior method for implementing switch fault isolation.

[0083] In the technical solutions of this invention, the acquisition, storage, and application of user personal information (such as facial information, voice information, etc.) all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0084] Example 3

[0085] Figure 6 This is a schematic diagram of a fault isolation device according to Embodiment 3 of the present invention. This embodiment can execute the fault isolation method involved in any of the above embodiments, such as... Figure 6As shown, the device includes a fault detection module 610 and a fault clearing module 620.

[0086] The fault detection module 610 is used to send a signal from the CPU to the timer and determine whether the CPU has malfunctioned based on the detected status information of the timer.

[0087] The fault clearing module 620 is used to send a signal to the timer through the FPGA when it is determined that the CPU has failed, and to clear the target configuration of the switch according to a preset protocol file, wherein the target configuration is the configuration related to the CPU.

[0088] In this embodiment, the fault detection module enables the CPU to send a signal to the timer, and determines whether the switch has malfunctioned based on the detected status information of the timer. When the fault clearing module determines that the CPU has malfunctioned, it sends a signal to the timer through the FPGA and clears the target configuration of the switch according to a preset protocol file. This ensures that when the CPU in the switch malfunctions, network connectivity can be maintained and the fault location can be isolated.

[0089] In an optional implementation of this embodiment, the fault detection module 610 is specifically used to send a timer reset signal to the timer through the CPU at set time intervals.

[0090] In response to the completion command of sending the target timer reset signal, the status information of the timer is detected; wherein, the status information includes whether the timer is reset or not.

[0091] If the timer's status information is detected as not being cleared within a set time, then the CPU is determined to have malfunctioned. In an optional implementation of this embodiment, the fault isolation device further includes: a preset protocol file determination module, used for...

[0092] Determine the forwarding type of each configuration included in the switch, and generate the preset protocol file according to the forwarding type.

[0093] In one optional implementation of this embodiment, the forwarding type is either Layer 2 forwarding or Layer 3 forwarding;

[0094] The fault clearing module 620 is specifically used to determine the configuration with the forwarding type of Layer 3 forwarding as the target configuration, extract the target name of each target configuration, and store each target name in the first area of ​​the target file;

[0095] The configuration with the forwarding type of Layer 2 forwarding is determined as the reference configuration, and the reference name of each reference configuration is extracted and stored in the second area of ​​the target file;

[0096] The first and second regions of the target file are merged to obtain the preset protocol file.

[0097] In an optional implementation of this embodiment, the fault clearing module 620 is further configured to obtain each of the target names stored in the first region of the preset protocol file;

[0098] Within the switch, determine the target configuration corresponding to each of the target names, and clear each of the target configurations.

[0099] In an optional implementation of this embodiment, the fault isolation device further includes: a forwarding module, configured to obtain reference configurations stored in the second area of ​​the preset protocol file; and forward each packet received by the switch through each of the reference configurations.

[0100] In one optional implementation of this embodiment, the target configuration includes at least one of the following: unicast enable configuration, multicast enable configuration, multiprotocol label switching (MPLS) enable configuration, routing physical address (MAC) configuration, and protocol upload to CPU configuration.

[0101] The reference configuration includes at least one of the following: port enable configuration, rate configuration, flow control configuration, maximum transmission unit (MTU) configuration, spanning tree state configuration, and virtual local area network (VLAN) configuration.

[0102] The fault isolation device provided in this embodiment of the invention can execute the fault isolation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0103] Example 4

[0104] Figure 7 A schematic diagram of a switch 10, which can be used to implement embodiments of the present invention, is shown. The switch is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The switch can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the embodiments of the invention described and / or claimed herein.

[0105] like Figure 7 As shown, the switch 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the switch 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0106] Multiple components in switch 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows switch 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as fault isolation methods.

[0108] In some embodiments, the fault isolation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the switch 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the fault isolation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the fault isolation method by any other suitable means (e.g., by means of firmware).

[0109] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] In the context of embodiments of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0112] To provide user interaction, the systems and techniques described herein can be implemented on a switch having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the switch. Other types of devices can also be used to provide user interaction; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0113] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0114] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0115] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the embodiments of the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of the embodiments of the present invention can be achieved, and this document does not impose any restrictions.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of the embodiments of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the embodiments of the present invention should be included within the scope of protection of the embodiments of the present invention.

Claims

1. A fault isolation method applied in a switch, the switch comprising a central processing unit (CPU) and a programmable array logic (FPGA), wherein the CPU and the FPGA are respectively communicatively connected to a timer, characterized in that, The method includes: The CPU sends a signal to the timer, and determines whether the CPU has malfunctioned based on the detected status information of the timer. If the CPU is found to be faulty, a signal is sent to the timer via the FPGA, and the target configuration of the switch is cleared according to a preset protocol file, wherein the target configuration is the configuration related to the CPU; The preset protocol file contains all the configuration information of the switch and classifies this configuration information; the classification results include configurations related to the CPU and configurations not related to the CPU. Before clearing the target configuration of the switch according to the preset protocol file, the process also includes: Determine the forwarding type of each configuration included in the switch, and generate the preset protocol file according to the forwarding type; The forwarding type is either Layer 2 forwarding or Layer 3 forwarding; The step of generating the preset protocol file according to the forwarding type includes: The configuration with the forwarding type of Layer 3 forwarding is determined as the target configuration, and the target name of each target configuration is extracted and stored in the first area of ​​the target file; The configuration with the forwarding type of Layer 2 forwarding is determined as the reference configuration, and the reference name of each reference configuration is extracted and stored in the second area of ​​the target file; The first and second regions of the target file are merged to obtain the preset protocol file.

2. The method according to claim 1, characterized in that, The step of sending a signal from the CPU to the timer and determining whether the CPU has malfunctioned based on the detected status information of the timer includes: At set intervals, the CPU sends a timer reset signal to the timer. In response to the completion command of sending the target timer reset signal, the status information of the timer is detected; wherein, the status information includes whether the timer is reset or not. If the timer status information is detected as not being cleared within the set time, then the CPU is determined to have malfunctioned.

3. The method according to claim 1, characterized in that, The step of clearing the target configuration of the switch according to the preset protocol file includes: Retrieve the target names stored in the first region of the preset protocol file; Within the switch, determine the target configuration corresponding to each of the target names, and clear each of the target configurations.

4. The method according to claim 3, characterized in that, After clearing the target configuration of the switch according to the preset protocol file, the process also includes: Retrieve the reference names stored in the second region of the preset protocol file; Each packet received by the switch is forwarded according to the reference configuration corresponding to each of the reference names.

5. The method according to any one of claims 1-4, characterized in that, The target configuration includes at least one of the following: unicast enable configuration, multicast enable configuration, multiprotocol label switching (MPLS) enable configuration, routing physical address (MAC) configuration, and protocol upload to CPU configuration; The reference configuration includes at least one of the following: port enable configuration, rate configuration, flow control configuration, maximum transmission unit (MTU) configuration, spanning tree state configuration, and virtual local area network (VLAN) configuration.

6. A fault isolation device applied in a switch, the switch comprising a CPU and an FPGA, the CPU and the FPGA being communicatively connected to a timer, characterized in that, The device includes: The fault detection module is used to send a signal from the CPU to the timer and determine whether the CPU has malfunctioned based on the detected status information of the timer. The fault clearing module is used to send a signal to the timer through the FPGA when it is determined that the CPU has failed, and to clear the target configuration of the switch according to a preset protocol file, wherein the target configuration is the configuration related to the CPU; The preset protocol file contains all the configuration information of the switch and classifies this configuration information; the classification results include configurations related to the CPU and configurations not related to the CPU. It also includes: a preset protocol file determination module, used to determine the forwarding type of each configuration included in the switch, and generate the preset protocol file according to the forwarding type; The forwarding type is either Layer 2 forwarding or Layer 3 forwarding; The fault clearing module is specifically used to determine the configuration with the forwarding type of Layer 3 forwarding as the target configuration, extract the target name of each target configuration, and store each target name in the first area of ​​the target file; The configuration with the forwarding type of Layer 2 forwarding is determined as the reference configuration, and the reference name of each reference configuration is extracted and stored in the second area of ​​the target file; The first and second regions of the target file are merged to obtain the preset protocol file.

7. A switch, characterized in that, The switch includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the fault isolation method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the fault isolation method according to any one of claims 1-5.

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