Antifuse array structure and memory

Abstract

The embodiment of the present application relates to the field of semiconductor circuit design, in particular to a kind of anti-fuse array structure and memory, comprising: a plurality of anti-fuse integrated structure, in bit line extension direction and word line extension direction arrangement into anti-fuse matrix;Each anti-fuse integrated structure is arranged in the same active region, and the extension direction of active region is same with the extension direction of bit line;Anti-fuse integrated structure includes: first anti-fuse storage MOS tube, first switch tube, second switch tube and second anti-fuse storage MOS tube;First switch tube and second switch tube are controlled by two adjacent word lines respectively, and first anti-fuse storage MOS tube and second anti-fuse storage MOS tube are controlled by two adjacent programming wires respectively, and programming wire is also used to control adjacent anti-fuse integrated structure.To realize that the layout area of the same capacity storage array only needs to occupy smaller, thereby increasing the spacing between anti-fuse storage unit on the basis of original layout area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor circuit design, in particular to a structure of anti-fuse array and a memory. BACKGROUND

[0002] Semiconductor devices are essential for many modern applications. In semiconductor devices, memory devices for storing data play an important role. With the progress of technology, the capacity of memory devices is constantly increasing, in other words, the density of the storage array arranged on the substrate is increasing.

[0003] For anti-fuse memory, the density of the storage array is increasing, and the spacing between anti-fuse storage units is decreasing, making it difficult to ensure the electrical isolation effect of the electrical elements between the anti-fuse storage units.

[0004] Therefore, it is urgent to improve the layout of the anti-fuse array structure to ensure the electrical isolation effect of the electrical elements between the anti-fuse storage units. SUMMARY

[0005] The embodiments of the present application provide a structure of anti-fuse array and a memory, and provide a new layout of anti-fuse array to realize that the same capacity of storage array only needs to occupy a smaller layout area, thereby increasing the spacing between the anti-fuse storage units on the basis of the original layout area, and ensuring the electrical isolation effect of the electrical elements between the anti-fuse storage units.

[0006] The embodiments of the present application provide a structure of anti-fuse array, comprising: a plurality of anti-fuse integrated structures arranged into an anti-fuse matrix in a bit line extension direction and a word line extension direction, the bit line extension direction and the word line extension direction being perpendicular to each other; each anti-fuse integrated structure is arranged in a same active region, and the extension direction of the active region is the same as the bit line extension direction; each anti-fuse integrated structure comprises: a first anti-fuse storage MOS transistor, a first switch tube, a second switch tube and a second anti-fuse storage MOS transistor arranged in sequence in the extension direction of the bit line; the first switch tube and the second switch tube are controlled by two adjacent word lines respectively, the common end of the first switch tube and the second switch tube is connected with the bit line, the first anti-fuse storage MOS transistor and the second anti-fuse storage MOS transistor are controlled by two adjacent programming wires respectively, and in the bit line extension direction, the programming wires are also used to control adjacent anti-fuse integrated structures.

[0007] The antifuse integrated structure includes a first antifuse storage MOS transistor, a second antifuse storage MOS transistor, a first switch transistor and a second switch transistor, wherein the first antifuse storage MOS transistor and the second antifuse storage MOS transistor are controlled by adjacent programming wires, that is, two antifuse storage cells are controlled by adjacent programming wires, and the first switch transistor and the second switch transistor serve as switch transistors of the antifuse storage cell and are controlled by adjacent word lines, that is, the antifuse integrated structure 100 includes two antifuse storage cells and two switch units; It is known to those skilled in the art that in the antifuse array, the extension direction of the programming wire is the same as the extension direction of the word line, that is, the direction in which the programming wire extends is the same as the direction in which the word line extends. and perpendicular to the extension direction of the bit line; wherein, in the extension direction of the bit line, the programming conductor is also used to control two adjacent anti-fuse integrated structures arranged along the extension direction of the bit line, and the same programming conductor is used to control an anti-fuse memory cell in two adjacent anti-fuse integrated structures connected on the same bit line, and the two anti-fuse memory cells respectively belong to two adjacent anti-fuse integrated structures, thereby reducing the layout length of the anti-fuse memory array in the extension direction of the bit line; on the basis of the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the anti-fuse memory cell located in the same active area is increased to ensure the electrical isolation effect of the electrical components of the anti-fuse memory array.

[0008] In addition, the active area includes an active area body, the length direction of the active area body is the extension direction of the active area, and in the extension direction of the active area, the width of the active area body is the same at all locations to ensure that the spacing between the active devices in the antifuse matrix is ​​the same, further ensuring the electrical isolation effect of the active devices in the antifuse matrix.

[0009] The active area also includes a raised portion disposed on at least one side of the main active area body. In the direction in which the active area extends, the raised portion is shorter than the main active area body. In the direction in which the word lines extend, the width of the central portion of the active area is greater than the width of the ends of the active area. The provision of the raised portion increases the width-to-length ratio of the active area where the first and second switching transistors are located, thereby improving the conductivity of the first and second switching transistors and preventing data read errors in the anti-fuse memory cell caused by poor conductivity between the first and second switching transistors.

[0010] In addition, the protrusion is arranged on one side of the main body of the active region, and in the extending direction of the bit line, the protrusions of two adjacent active regions are arranged opposite to each other.

[0011] In addition, in the bit line extension direction, the gate of the second anti-fuse storage MOS transistor of each anti-fuse integrated structure and the gate of the first anti-fuse storage MOS transistor of the adjacent anti-fuse integrated structure are connected to the same programming wire.

[0012] In addition, the gate of the first antifuse storage MOS transistor is connected to the first programming wire; the gate of the first switch transistor is connected to the first word line, the source is connected to the first antifuse storage MOS transistor, and the drain is connected to the bit line; the gate of the second switch transistor is connected to the second word line, the source is connected to the second antifuse storage MOS transistor, and the drain is connected to the bit line; and the gate of the second antifuse storage MOS transistor is connected to the second programming wire.

[0013] In addition, the active region comprises: a first doped region, a second doped region, a third doped region, a fourth doped region, and a fifth doped region arranged in sequence along the extension direction of the active region; the first doped region is the idle terminal of the first antifuse MOS transistor, the second doped region is the common terminal of the first antifuse storage MOS transistor and the first switch transistor, the third doped region is the common terminal of the first switch transistor and the second switch transistor, the fourth doped region is the common terminal of the second switch transistor and the second antifuse storage MOS transistor, and the fifth doped region is the idle terminal of the second antifuse MOS transistor; and the bit line is electrically connected to the third doped region.

[0014] In addition, the antifuse array structure further comprises: an insulating layer covering the active region, wherein the bit line is arranged on the insulating layer; the insulating layer further has a conductive via hole exposing the top surface of the third doped region; and a conductive layer filling the conductive via hole, one end of which is in contact with the third doped region and the other end is in contact with the bit line, so that the bit line is electrically connected to the third doped region. By connecting the bit line and the conductive layer through the bit line extension layer, the stability of the electrical contact between the bit line and the conductive layer is ensured, and the formed antifuse matrix is prevented from having a conductive defect.

[0015] In addition, the conductive via hole is arranged on one side of the connected bit line, and the conductive via holes of the adjacent two antifuse integrated structures are arranged on both sides of the connected bit line in the extension direction of the bit line, and the connected bit line is in contact with the conductive layer through the bit line extension layer. By connecting the bit line and the conductive layer through the bit line extension layer, the stability of the electrical contact between the bit line and the conductive layer is ensured, and the formed antifuse matrix is prevented from having a conductive defect.

[0016] In addition, the gate of the first antifuse storage MOS transistor is arranged on the top surface of the active region between the first doped region and the second doped region, the gate of the first switch transistor is arranged on the top surface of the active region between the second doped region and the third doped region, the gate of the second switch transistor is arranged on the top surface of the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is arranged on the top surface of the active region between the fourth doped region and the fifth doped region.

[0017] In addition, the gate of the first antifuse storage MOS transistor is embedded in the active region between the first doped region and the second doped region, the gate of the first switch transistor is embedded in the active region between the second doped region and the third doped region, the gate of the second switch transistor is embedded in the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is embedded in the active region between the fourth doped region and the fifth doped region.

[0018] In addition, the antifuse matrix includes a plurality of columns of antifuse integrated structures arranged along the direction of extension of the word lines, wherein the bit line connected to the first column of antifuse integrated structures is a first dummy bit line, and the bit line connected to the last column of antifuse integrated structures is a second dummy bit line. By arranging the dummy bit lines at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures at the edges of the antifuse matrix is made consistent with that of the antifuse integrated structures in the interior of the matrix, so that defects in the antifuse storage units at the edges of the antifuse matrix are prevented and the antifuse storage units can work normally.

[0019] In addition, the antifuse matrix includes a plurality of rows of antifuse integrated structures arranged along the direction of extension of the bit lines, wherein the gate of the first antifuse MOS transistor in the first row of antifuse integrated structures is connected to a first dummy programming conductor, and the gate of the second antifuse MOS transistor in the last row of antifuse integrated structures is connected to a second dummy programming conductor. By arranging the dummy programming conductors at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures at the edges of the antifuse matrix is made consistent with that of the antifuse integrated structures in the interior of the matrix, so that defects in the antifuse storage units at the edges of the antifuse matrix are prevented and the antifuse storage units can work normally.

[0020] In addition, the gate of the first switch transistor in the first row of antifuse integrated structures is connected to a first dummy word line, and the gate of the second switch transistor in the last row of antifuse integrated structures is connected to a second dummy word line; wherein the first dummy programming conductor and the second dummy programming conductor are located at the outermost side of the antifuse matrix, and the first dummy word line and the second dummy word line are located at the next outer side of the antifuse matrix. By arranging the dummy word lines at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures at the edges of the antifuse matrix is made consistent with that of the antifuse integrated structures in the interior of the matrix, so that defects in the antifuse storage units at the edges of the antifuse matrix are prevented and the antifuse storage units can work normally.

[0021] The embodiment of the present application also provides a memory including a storage array adopting the antifuse array structure.

[0022] In the direction of extension of the bit lines, the layout length of the antifuse storage array is reduced, so that, on the basis of the original layout area and the same capacity of the storage array, the spacing between the switch units and the antifuse storage units in the same active region is increased to ensure the electrical isolation effect of the electrical elements in the storage array formed by the antifuse integrated structures. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A circuit schematic diagram of an anti-fuse integrated structure according to an embodiment of the present application;

[0024] Figure 2 A circuit schematic diagram of an anti-fuse matrix according to an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a connection of the same programming wire of an anti-fuse storage unit in adjacent anti-fuse integrated structures according to an embodiment of the present application;

[0026] Figure 4 and Figure 5 A top view schematic diagram of a layout structure of an anti-fuse integrated structure according to an embodiment of the present application;

[0027] Figure 6 A cross-sectional view schematic diagram of a layout structure of an anti-fuse integrated structure according to an embodiment of the present application;

[0028] Figure 7 A cross-sectional view schematic diagram of a layout structure of another anti-fuse integrated structure according to an embodiment of the present application;

[0029] Figure 8 and Figure 9 A layout structure schematic diagram of an anti-fuse matrix according to an embodiment of the present application;

[0030] Figure 10 and Figure 11 A layout structure schematic diagram of a bit line in an anti-fuse matrix according to an embodiment of the present application;

[0031] Figure 12 A virtual structure schematic diagram of a memory according to another embodiment of the present application;

[0032] Figure 13 A timing schematic diagram of a programming stage and a readout stage of a memory according to another embodiment of the present application. DETAILED DESCRIPTION

[0033] For an anti-fuse memory, the density of the storage array is increased, the spacing between the anti-fuse storage units is reduced, and it is difficult to ensure the electrical isolation effect of the electrical elements between the anti-fuse storage units.

[0034] An anti-fuse array structure according to an embodiment of the present application provides a new layout mode of the anti-fuse array, so as to realize that the storage array with the same capacity only occupies a smaller layout area, thereby increasing the spacing between the anti-fuse storage units on the basis of the original layout area and ensuring the electrical isolation effect of the electrical elements between the anti-fuse storage units.

[0035] Those skilled in the art will appreciate that, in the various embodiments of this application, many technical details are provided to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0036] Figure 1 A circuit diagram of the antifuse integrated structure provided in this embodiment, Figure 2 A circuit diagram of the antifuse matrix provided in this embodiment, Figure 3 The schematic diagram of connecting an antifuse memory cell to the same programming wire in adjacent antifuse integrated structures provided in this embodiment is as follows: Figure 4 and Figure 5 A schematic top view of the layout structure of the antifuse integrated structure provided in this embodiment, Figure 6 A schematic cross-sectional view of the layout structure of an antifuse integrated structure provided in this embodiment is shown in FIG. Figure 7 A schematic cross-sectional view of the layout structure of another antifuse integrated structure provided in this embodiment, Figure 8 and Figure 9 A schematic diagram of a layout structure of an antifuse matrix provided in this embodiment, Figure 10 and Figure 11 This is a schematic diagram of the layout structure of the bit lines in the antifuse matrix provided in this embodiment. The antifuse array structure provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0037] refer to Figure 1 and Figure 2 , an antifuse array structure, comprising:

[0038] Multiple antifuse integrated structures 100 (refer to Figure 1 ), arranged in an antifuse matrix in the extending direction of the bit line BL and the word line WL (reference Figure 2 ), the extending direction of the bit line BL and the extending direction of the word line WL are perpendicular to each other.

[0039] Each antifuse integrated structure 100 includes a first antifuse storage MOS transistor 101, a first switch transistor 111, a second switch transistor 112, and a second antifuse storage MOS transistor 102, which are sequentially arranged along the extending direction of the bit line BL. The first switch transistor 111 and the second switch transistor 112 are each controlled by two adjacent word lines WL. A common terminal of the first switch transistor 111 and the second switch transistor 112 is connected to the bit line BL. The first antifuse storage MOS transistor 101 and the second antifuse storage MOS transistor are each controlled by a programming conductor PGM. In the extending direction of the bit line BL, the programming conductor PGM is also used to control adjacent antifuse integrated structures 100.

[0040] In addition, each anti-fuse integrated structure 100 is arranged in the same active region, and the extension direction of the active region is the same as the extension direction of the bit line BL.

[0041] It should be noted that, Figure 2 The diagram is only a part of the formed anti-fuse matrix, and is only used to embody the arrangement mode of the anti-fuse matrix in the embodiment of the application, and does not constitute a limitation on the number of the bit line BL, the word line WL and the programming conductor PGM. In specific use, the number of the bit line BL, the word line WL and the programming conductor PGM can be selected according to the capacity of the required storage array. In addition, the values in the "<>" are only used to distinguish different bit lines BL, word lines WL or programming conductors PGM, and do not constitute a limitation on the embodiment.

[0042] The anti-fuse integrated structure 100 includes a first anti-fuse storage MOS transistor 101, a second anti-fuse storage MOS transistor 102, a first switch transistor 111 and a second switch transistor 112, that is, the anti-fuse integrated structure 100 includes two anti-fuse storage units and two switch units. The first anti-fuse storage MOS transistor 101 and the second anti-fuse storage MOS transistor 102 are controlled by the adjacent programming conductor PGM, that is, the two anti-fuse storage units are controlled by the adjacent programming conductor PGM, and the first switch transistor 111 and the second switch transistor 112 are switch transistors of the anti-fuse storage unit and are controlled by the adjacent word line WL. It is known to those skilled in the art that in the anti-fuse array, the extension direction of the programming conductor PGM is the same as the extension direction of the word line WL, that is, the extension direction of the programming conductor PGM is perpendicular to the extension direction of the bit line BL. In the extension direction of the bit line BL, the programming conductor PGM is also used to control two adjacent anti-fuse integrated structures 100 arranged in the extension direction of the bit line BL. The same programming conductor PGM is used to control one anti-fuse storage unit in the adjacent two anti-fuse integrated structures 100 connected on the same bit line BL, that is, the same programming conductor PGM is used to control two anti-fuse storage units located in different anti-fuse integrated structures 100, so that in the extension direction of the bit line BL, the layout length of the anti-fuse storage array is reduced. On the basis of the original layout area and the same capacity of the storage array, the distance between the switch unit and the anti-fuse storage unit in the same active region is increased to ensure the electrical isolation effect of the electrical elements of the anti-fuse storage array.

[0043] Specifically, the gate of the first antifuse memory MOS transistor 101 is connected to the first program wire PGM<1>, the gate of the first switch transistor 111 is connected to the first word line WL<1>, one end of the source or drain of the first antifuse memory MOS transistor 101 is connected to the first switch transistor 111, and the other end is connected to the bit line BL, the gate of the second switch transistor 112 is connected to the second word line WL<2>, one end of the source or drain of the second antifuse memory MOS transistor 102 is connected to the second switch transistor 112, and the other end is connected to the bit line BL, and the gate of the second antifuse memory MOS transistor 102 is connected to the second program wire PGM<2>.

[0044] In addition, with reference to Figure 3 In the direction of extension of the bit line BL, for any two adjacent antifuse integrated structures 100, the gate of the second switch transistor 112 of one of the antifuse integrated structures 100 is connected to the word line WL <n-2>, the gate of the second antifuse memory MOS transistor 102 is connected to the program wire PGM <m>; another anti-fuse integrated structure 100 first anti-fuse storage MOS tube 101 gate connection programming wire PGM <m>, the gate of the first switch tube 111 is connected with the word line WL <n-1>; In the extension direction of the bit line BL, the first switch tube 111 and the second switch tube 112 in any two adjacent antifuse integrated structures 100 are connected to the bit line BL <n>Up.

[0045] That is, in the direction of the extension of the bit line BL, the gate of the second antifuse storage MOS transistor 102 of each antifuse integrated structure 100 is connected to the same programming conductor PGM as the gate of the first antifuse storage MOS transistor 101 of the adjacent antifuse integrated structure 100 <m>, where n, m are positive integers greater than or equal to 1.

[0046] It should be noted that in other examples, it can also be set as follows: in the bit line extension direction, the gate of the first anti-fuse storage MOS tube of each anti-fuse integrated structure is connected to the same programming wire as the gate of the second anti-fuse storage MOS tube of the adjacent anti-fuse integrated structure.

[0047] refer to Figure 4 and Figure 5 For the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 arranged in the same active area, in one example, the active area 200 includes an active area body, the length direction of the active area body is the extension direction of the active area 200, and the width of the active area body is the same at all locations in the extension direction of the active area 200 to ensure that the spacing between the active devices in the antifuse matrix is ​​the same, further ensuring the electrical isolation effect of the active devices in the antifuse matrix.

[0048] Furthermore, the active region also includes a raised portion, which is disposed on at least one side of the active region body, specifically, on at least one side along the length of the active region. In the extension direction of the active region 200, the raised portion is shorter than the length of the active region body; in the extension direction of the word line WL, the width of the central portion of the active region 200 is greater than the width of the active region 200 at both ends. The raised portion and the active region body are used to form the first switching transistor 111 and the second switching transistor 112. The channel width of the first switching transistor 111 and the second switching transistor 112 is the sum of the width of the raised portion and the active region body. The first antifuse storage MOS transistor 101 and the second antifuse storage MOS transistor 102 are disposed in the active region body, and the channel width of the first antifuse storage MOS transistor 101 and the second antifuse storage MOS transistor 102 is the width of the active region. The protrusion is provided to increase the width-to-length ratio of the active region where the first switch transistor 111 and the second switch transistor 112 are located, thereby improving the conductivity of the first switch transistor 111 and the second switch transistor 112. This ensures that sufficient fuse voltage flows through the first anti-fuse storage MOS transistor 101 and the second anti-fuse storage MOS transistor 102, thereby avoiding data read and write errors in the anti-fuse storage unit caused by poor conductivity of the first switch transistor 111 and the second switch transistor 112. In addition, the increase in the width of the central portion of the active region 200 also facilitates the preparation of the first switch transistor 111 and the second switch transistor 112.

[0049] In one example, the active region 200 consists only of the active region body; in one example, referring to Figure 5 The protruding part is arranged on one side of the active region body, and in the extension direction of the bit line BL, the protruding parts of two adjacent active regions are oppositely arranged, that is, for two adjacent rows of active regions 200, the protruding part of one row of active regions 200 is arranged on one side of the active region body, and the protruding part of the other row of active regions 200 is arranged on the other side of the active region protruding part; so that the active regions of two adjacent rows can be closely arranged while the area of the active region is increased, and the area of the anti-fuse array structure is reduced.

[0050] In another example, with reference to Figure 6 The protruding part is arranged on one side of the active region body, and in the extension direction of the bit line BL, the protruding parts of two adjacent active regions are oppositely arranged, that is, for two adjacent rows of active regions 200, the protruding part of one row of active regions 200 is arranged on one side of the active region body, and the protruding part of the other row of active regions 200 is arranged on the other side of the active region protruding part; so that the active regions of two adjacent rows can be closely arranged while the area of the active region is increased, and the area of the anti-fuse array structure is reduced.

[0051] In some embodiments, in the extension direction of the bit line BL, the active region bodies of two adjacent anti-fuse integrated structures 100 at least partially overlap in the orthogonal projection on a preset plane, so as to further reduce the area of the anti-fuse array structure. The preset plane is parallel to the extension direction of the bit line BL and perpendicular to the extension direction of the word line.

[0052] Specifically, with reference to Figure 6 and Figure 7 The active region 200 comprises:

[0053] The first doped region 212, the second doped region 222, the third doped region 232, the fourth doped region 242 and the fifth doped region 252 are sequentially arranged in the extension direction of the active region 200.

[0054] The active region 200 is surrounded by the isolation region 201, the first doped region 212 is the idle terminal of the first anti-fuse storage MOS tube 101, the second doped region 222 is the common terminal of the first anti-fuse storage MOS tube 101 and the first switch tube 111, the third doped region 232 is the common terminal of the first switch tube 111 and the second switch tube 112, the fourth doped region 242 is the common terminal of the second switch tube 112 and the second anti-fuse storage MOS tube 102, and the fifth doped region 252 is the idle terminal of the second anti-fuse storage MOS tube 102.

[0055] That is, the source electrode of the first anti-fuse storage MOS tube 101 is idle, the drain electrode is connected with the drain electrode of the first switch tube 111, and the source electrode of the first switch tube 111 is connected with the bit line BL, so as to realize the electrical conduction between the first anti-fuse storage MOS tube 101 and the bit line BL after the first switch tube 111 is turned on. The source electrode of the second anti-fuse storage MOS tube 102 is idle, the drain electrode is connected with the drain electrode of the second switch tube 112, and the source electrode of the second switch tube 112 is connected with the bit line BL, so as to realize the electrical conduction between the second anti-fuse storage MOS tube 102 and the bit line BL after the second switch tube 112 is turned on.

[0056] Since the first switch 111 and the second switch 112 have the same source connection relationship, the layout area of ​​the antifuse integrated structure 100 can be reduced by sharing the source, that is, by sharing the same doping region.

[0057] For the anti-fuse memory cell, the anti-fuse MOS tube is controlled by the programming line PGM to form a memory cell. The word line WL controls the switch tube to facilitate the writing of storage data on the bit line BL. When the corresponding word line WL is selected, the anti-fuse memory cell is electrically connected to the bit line BL. The discharge speed of the anti-fuse memory cell on the bit line BL (after a preset time, by comparing the bit line BL voltage with the standard voltage) can be used to determine whether the anti-fuse memory cell is broken down, thereby obtaining the 1-bit binary data stored in the anti-fuse memory cell.

[0058] In a specific example, refer to Figure 6 The gate of the first antifuse storage MOS transistor 101 is arranged on the top surface of the active region 200 between the first doping region 212 and the second doping region 222. The gate of the first switch transistor 111 is arranged on the top surface of the active region 200 between the second doping region 222 and the third doping region 232. The gate of the second switch transistor 112 is arranged on the top surface of the active region 200 between the third doping region 232 and the fourth doping region 242. The gate of the second antifuse storage MOS transistor 102 is arranged on the top surface of the active region 200 between the fourth doping region 242 and the fifth doping region 252. That is, the active regions of the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are arranged in a top-gate manner.

[0059] In a specific example, refer to Figure 7 The gate of the first antifuse storage MOS transistor 101 is buried in the active region 200 between the first doping region 212 and the second doping region 222. The gate of the first switch transistor 111 is buried in the active region 200 between the second doping region 222 and the third doping region 232. The gate of the second switch transistor 112 is buried in the active region 200 between the third doping region 232 and the fourth doping region 242. The gate of the second antifuse storage MOS transistor 102 is buried in the active region 200 between the fourth doping region 242 and the fifth doping region 252. That is, the active regions of the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are arranged in a buried gate manner.

[0060] Combine Figure 6 and Figure 7 The anti-fuse integrated structure 100 further comprises an insulating layer 203 covering the active region 200, and a bit line BL (205) disposed on the insulating layer 203 and electrically connected to the third doped region 232.

[0061] Specifically, the insulating layer 200 has a conductive via (not shown) exposing a top surface of the third doped region 232 and a conductive layer 204 filling the conductive via (not shown) and contacting the third doped region 232 at one end and the BL (205) at the other end to electrically connect the bit line to the third doped region 232.

[0062] For the layout of the anti-fuse matrix, refer to Figure 8 and Figure 10 The anti-fuse matrix comprises a plurality of rows of anti-fuse integrated structures 100 arranged along the extension direction of the word line WL and a plurality of columns of anti-fuse integrated structures 100 arranged along the extension direction of the bit line BL. The plurality of anti-fuse integrated structures 100 in each row of anti-fuse integrated structures 100 are arranged at intervals along the extension direction of the WL, and the plurality of anti-fuse integrated structures 100 in each column of anti-fuse integrated structures 100 are arranged at intervals along the extension direction of the BL. In the extension direction of the bit line BL, the adjacent two anti-fuse integrated structures 100 are arranged alternately in the adjacent two columns.

[0063] For the layout of the anti-fuse matrix, refer to Figure 9 , Figure 9 For the layout of the anti-fuse matrix, refer to Figure 8 , the conductive vias of the anti-fuse integrated structures 100 in the same column are arranged on the same straight line, and the bit lines BL (205) are arranged along the straight line, so that the bit lines BL (205) can cover the conductive vias on the same straight line to simplify the forming process of the bit lines BL (205).

[0064] For the layout of the anti-fuse matrix, refer to Figure 11 , Figure 11 For the layout of the anti-fuse matrix, refer to Figure 10 , the conductive vias are disposed on one side of the connected bit line BL (205), and the conductive vias of the adjacent anti-fuse integrated structures 100 are disposed on both sides of the connected bit line BL (205) in the extension direction of the bit line BL (205), and the bit line BL is in contact with the conductive layer 204 (refer to Figure 6 and Figure 7 ) through a bit line extension layer 300. The connection of the bit line BL and the conductive layer through the bit line extension layer 300 ensures the stability of the electrical contact between the bit line and the conductive layer and prevents the formed anti-fuse matrix from having a conductive defect.

[0065] In one example, the antifuse integrated structures 100 connected by the same word line WL are arranged at equal intervals. That is, in the extending direction of the word line WL, the spacing between adjacent antifuse integrated structures 100 is equal, to avoid the situation where the spacing between adjacent antifuse integrated structures 100 is too small to damage the overall electrical isolation effect of the antifuse memory array.

[0066] In one example, the antifuse integrated structures 100 connected by the same bit line BL are arranged at equal intervals. That is, in the extending direction of the bit line BL, the spacing between adjacent antifuse integrated structures 100 is equal to avoid the situation where the spacing between adjacent antifuse integrated structures 100 is too small to damage the overall electrical isolation effect of the antifuse memory array.

[0067] In one example, the bit line BL connected to the first column of antifuse integrated structures 100 is the first dummy bit line Dummy1, and the bit line BL connected to the last column of antifuse integrated structures 100 is the second dummy bit line Dummy2. By providing dummy bit lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures within the matrix, thereby preventing defects in the antifuse memory cells at the edge from causing malfunction.

[0068] In one example, the gate of the first storage MOS transistor 101 in the first row of antifuse integrated structures 100 is connected to a first dummy programming wire Dummy3, and the gate of the second storage MOS transistor in the last row of antifuse integrated structures 100 is connected to a second dummy programming wire Dummy4. By providing dummy programming wires at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures within the matrix, preventing defects in the antifuse storage cells at the edge from causing malfunction.

[0069] Furthermore, the gate of the first switch tube 111 in the first row of antifuse integrated structures 100 is connected to the first virtual word line Dummy5, ​​and the gate of the second switch tube 112 in the last row of antifuse integrated structures 100 is connected to the second virtual word line Dummy6. The first dotted programming wire Dummy3 and the second virtual programming wire Dummy4 are located at the outermost side of the antifuse matrix, and the first virtual word line Dummy5 and the second virtual word line Dummy6 are located at the second outermost side of the antifuse matrix. By setting up virtual word lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​guaranteed to be consistent with that of the antifuse integrated structures within the matrix, thereby preventing defects in the antifuse storage cells at the edge from malfunctioning.

[0070] The embodiment of the present application reduces the layout length of the antifuse memory array in the bit line extension direction. Therefore, based on the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0071] It should be noted that the specific connection method of the "source" and "drain" defined above does not constitute a limitation on the embodiments of this application. In other embodiments, the connection method of "drain" replacing "source" and vice versa can be adopted. In addition, in order to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that other units do not exist in this embodiment.

[0072] Another embodiment of the present application also provides a memory, wherein the memory array of the memory applies the antifuse array structure provided in the above embodiment. By applying the antifuse array structure provided in the above embodiment as the memory array, on the basis of the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0073] Figure 12 A schematic diagram of the virtual structure of the memory provided in this embodiment, Figure 13 The following is a timing diagram of the programming phase and the reading phase of the memory provided by this embodiment. The memory provided by this embodiment is further described in detail with reference to the accompanying drawings, as follows:

[0074] refer to Figure 12 The memory includes: a memory array 403, which adopts the antifuse array structure provided by the above embodiment; a control unit 401, which is used to receive a row address signal Row_ADD, a programming enable signal PGM_En and a word line enable signal WL_En; a row selection control unit 402, which is connected to the memory array 403 and the control unit 401, and is used to generate a programming selection signal PGM according to the row address signal Row_ADD and the programming enable signal PGM_En. <n 2:0>, generates a word line selection signal WL according to the row address signal Row_ADD and the word line enable signal WL_En <n:0>; column selection control unit 404, connected to the memory array 403, for turning on the corresponding bit line WL of the memory array 403 according to the bit line selection signal (not shown).

[0075] wherein the program enable signal PGM_En is used to indicate that the program wire is turned on, and the word line enable signal WL_En is used to indicate that the bit line is turned on; the program selection signal PGM <n 2:0>for turning on a program lead line PGM in the corresponding memory array 403; a word line selection signal WL <n:0>for turning on a word line WL in the corresponding memory array 403.

[0076] With specific reference now to Figure 13 In the programming phase, a program enable signal PGM_En and a row address signal Row_ADD are provided to generate a program strobe signal PGM <n 2:0>to form an anti-fuse memory cell by blowing the corresponding anti-fuse MOS transistor, and to select the anti-fuse memory cell by a word line enable signal WL <n:0>The control switch is turned on to write data into the anti-fuse memory cell through the corresponding bit line BL. In the readout stage, the word line enable signal WL_En and the row address signal Row_ADD are provided to generate the word line selection signal WL <n:0>, so as to select the corresponding anti-fuse memory cell and electrically connect it to the bit line BL.

[0077] Through the common control of the bit line BL and the word line WL, when the corresponding word line WL is selected, the anti-fuse memory unit is electrically connected to the bit line BL, and the discharge speed of the charge on the bit line BL is controlled by the anti-fuse memory unit (after a preset time, the voltage of the bit line BL is adjusted by comparing it with the standard voltage V REF Comparison), it can be determined whether the anti-fuse memory cell is broken down, thereby obtaining 1 bit of binary data stored in the anti-fuse memory cell.

[0078] It should be noted that, since the programming conductor PGM in this embodiment is connected to two anti-fuse memory cells controlled by different word lines WL, the programming selection signal PGM <n 2:0>The required high level duration needs to cover twice the word line strobe signal WL <n:0>The time for the high level to complete the programming of the data.

[0079] It is worth mentioning that each unit involved in the embodiment is a logical unit. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment. However, this does not mean that there are no other units in the embodiment.

[0080] It should be noted that, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment. Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / m>

Claims

1. An antifuse array structure, characterized in that: include: A plurality of antifuse integrated structures are arranged in an antifuse matrix in a bit line extension direction and a word line extension direction, wherein the bit line extension direction and the word line extension direction are perpendicular to each other; Each antifuse integrated structure is disposed in the same active region, wherein the extension direction of the active region is the same as the extension direction of the bit line; the active region comprises an active region body and a protruding portion, wherein the active region body is the portion of the active region excluding the protruding portion, the length direction of the active region body is the extension direction of the active region, and the width of the active region body is the same at all locations along the extension direction of the active region; In the word line extension direction, the width of the middle portion of the active area is greater than the width of both ends of the active area; Each antifuse integrated structure includes: A first anti-fuse storage MOS transistor, a first switch transistor, a second switch transistor and a second anti-fuse storage MOS transistor are sequentially arranged along the extending direction of the bit line; The first switch tube and the second switch tube are respectively controlled by two adjacent word lines, and the common end of the first switch tube and the second switch tube is connected to the bit line. The first anti-fuse storage MOS tube and the second anti-fuse storage MOS tube are respectively controlled by two adjacent programming wires, and in the extension direction of the bit line, the programming wires are also used to control adjacent anti-fuse integrated structures.

2. The antifuse array structure according to claim 1, wherein: The active area further includes a protrusion, which is provided on at least one side of the main body of the active area. In the extending direction of the active area, the length of the protrusion is smaller than the length of the main body of the active area.

3. The antifuse array structure according to claim 2, wherein: The protrusion is arranged on one side of the main body of the active region, and in the extending direction of the bit line, the protrusions of two adjacent active regions are arranged opposite to each other.

4. The antifuse array structure according to claim 1, wherein: In the extending direction of the bit line, the gate of the second anti-fuse storage MOS transistor of each anti-fuse integrated structure is connected to the same programming wire as the gate of the first anti-fuse storage MOS transistor of the adjacent anti-fuse integrated structure.

5. The antifuse array structure according to claim 1, wherein: include: The gate of the first anti-fuse storage MOS tube is connected to a first programming wire; The gate of the first switch tube is connected to the first word line, the source is connected to the first anti-fuse storage MOS tube, and the drain is connected to the bit line; The gate of the second switch tube is connected to the second word line, the source is connected to the second anti-fuse storage MOS tube, and the drain is connected to the bit line; The gate of the second anti-fuse storage MOS tube is connected to the second programming wire.

6. The antifuse array structure according to claim 1, wherein: The active region includes: a first doping region, a second doping region, a third doping region, a fourth doping region and a fifth doping region sequentially arranged along an extension direction of the active region; The first doped region is an idle end of the first anti-fuse storage MOS transistor, the second doped region is a common end of the first anti-fuse storage MOS transistor and the first switch transistor, the third doped region is a common end of the first switch transistor and the second switch transistor, the fourth doped region is a common end of the second switch transistor and the second anti-fuse storage MOS transistor, and the fifth doped region is an idle end of the second anti-fuse storage MOS transistor; The bit line is electrically connected to the third doping region.

7. The antifuse array structure according to claim 6, wherein: Also includes: an insulating layer covering the active area, wherein the bit line is arranged on the insulating layer; The insulating layer further comprises a conductive through hole, wherein the conductive through hole exposes the top surface of the third doping region; A conductive layer fills the conductive through hole, one end of the conductive layer contacts the third doping region, and the other end contacts the bit line, so that the bit line is electrically connected to the third doping region.

8. The antifuse array structure according to claim 7, wherein: The conductive through hole is arranged on one side of the connected bit line. In the bit line extension direction, the conductive through holes of two adjacent antifuse integrated structures are arranged on both sides of the connected bit line. The connected bit line is in contact with the conductive layer through the bit line extension layer.

9. The antifuse array structure according to claim 6, wherein: The gate of the first anti-fuse storage MOS tube is set on the top surface of the active area between the first doping area and the second doping area, the gate of the first switching tube is set on the top surface of the active area between the second doping area and the third doping area, the gate of the second switching tube is set on the top surface of the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is set on the top surface of the active area between the fourth doping area and the fifth doping area.

10. The antifuse array structure according to claim 6, wherein: The gate of the first anti-fuse storage MOS tube is buried in the active area between the first doping area and the second doping area, the gate of the first switch tube is buried in the active area between the second doping area and the third doping area, the gate of the second switch tube is buried in the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is buried in the active area between the fourth doping area and the fifth doping area.

11. The antifuse array structure according to claim 1, wherein: The antifuse matrix includes multiple columns of antifuse integrated structures arranged along the word line extension direction, wherein the bit lines connected to the antifuse integrated structures in the first column are first virtual bit lines, and the bit lines connected to the antifuse integrated structures in the last column are second virtual bit lines.

12. The antifuse array structure according to claim 1, wherein: The antifuse matrix includes multiple rows of antifuse integrated structures arranged along the bit line extension direction, wherein the gate of the first antifuse storage MOS tube in the first row of the antifuse integrated structure is connected to the first virtual programming wire, and the gate of the second antifuse storage MOS tube in the last row of the antifuse integrated structure is connected to the second virtual programming wire.

13. The antifuse array structure according to claim 12, wherein: The gate of the first switch tube in the anti-fuse integrated structure in the first row is connected to the first virtual word line, and the gate of the second switch tube in the anti-fuse integrated structure in the last row is connected to the second virtual word line; wherein, the first virtual programming wire and the second virtual programming wire are located at the outermost side of the anti-fuse matrix, and the first virtual word line and the second virtual word line are located at the second outer side of the anti-fuse matrix.

14. A memory comprising a memory array, characterized in that: The storage array adopts the antifuse array structure according to any one of claims 1 to 13.

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