A flash memory device

Abstract

This invention provides a flash memory storage device, including a substrate and a gate stack disposed on the substrate. The substrate includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The gate stack is disposed on the channel region and, from top to bottom, comprises a control gate, a barrier oxide layer, a charge trapping layer, and a tunneling oxide layer. The source region is connected to a source voltage (VS) module, the drain region is connected to a drain voltage (VD) module, and the control gate is connected to a gate voltage (VG) module. This flash memory storage device can remove trapped charges in shallow energy levels in advance, thereby significantly optimizing the retention and high-temperature characteristics of the flash memory storage device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a flash memory storage device. Background Technology

[0002] Memory chips, also known as semiconductor memories, are the main components used for storage in electronic digital devices and hold a very important position in the entire integrated circuit market. Memory can store program code to process various types of data, as well as intermediate data and final results generated during data processing. It is currently the most widely used basic general-purpose integrated circuit product.

[0003] Based on their function, data retrieval method, and data storage principle, memory chips can be broadly classified into volatile memory and non-volatile memory. Non-volatile memory retains its stored content even after external power is cut off; it has a slower read speed but a larger storage capacity. It mainly includes EEPROM, Flash Memory, PROM (Programmable Read-Only Memory), and EPROM (Erasable Programmable Read-Only Memory). Volatile memory is divided into DRAM and SRAM. As the mainstream technology for non-volatile memory, Flash memory mainly falls into two categories: floating-gate based and trap-based.

[0004] Charge-trapped memory (CTM) is a non-volatile semiconductor memory that uses trap or quantum well materials as charge storage media. With the improvement of the performance of materials such as trapping layers and the entry of memory cell size into the nanoscale, the advantages of CTM are becoming increasingly obvious. It has received widespread attention and will become the mainstream development direction of non-volatile memory technology compatible with CMOS front-end processes below 32nm.

[0005] However, the charges in the charge traps of charge-trapped memory have a certain energy level distribution, from shallow energy level to deep energy level. The trapped charges in the shallow energy level are prone to escape and be lost at high temperatures or when data is retained for a long time, which can cause the characteristics of flash memory cells to drift and the storage data to be damaged.

[0006] To address the aforementioned issues, it is necessary to improve existing charge trapping memories. Summary of the Invention

[0007] Technical problems to be solved

[0008] In view of the above-mentioned shortcomings of the prior art, the present invention provides a flash memory storage device that can remove the trapped charge in the shallow energy level in advance, thereby significantly optimizing the retention characteristics and high temperature characteristics of the flash memory storage device.

[0009] Technical solution

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] The present invention provides a flash memory storage device, including a substrate and a gate stack disposed on the substrate. The substrate includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The gate stack is disposed on the channel region. The gate stack consists of a control gate, a barrier oxide layer, a charge trapping layer, and a tunneling oxide layer from top to bottom. The source region is connected to a source voltage VS module, the drain region is connected to a drain voltage VD module, and the control gate is connected to a gate voltage VG module.

[0012] Furthermore, the source voltage VS module, the drain voltage VD module, and the gate voltage VG module each output voltage, and the pulse width and amplitude of the output voltage can be adjusted respectively.

[0013] Furthermore, the gate voltage VG output voltage is low, while the source voltage VS module and the drain voltage VD module output voltage is high.

[0014] Furthermore, the material of the control gate includes at least one of the following: platinum, gold, titanium aluminide alloy, palladium, aluminum, metal nitride, metal boron nitride, metal silicon nitride, metal silicide, and metal aluminum nitride.

[0015] Furthermore, the material of the charge trapping layer includes at least one of the following: tantalum oxide, titanium dioxide, barium titanate, strontium titanate, zirconium dioxide, lead zirconate titanate, hafnium dioxide, aluminum oxide, yttrium oxide, lanthanum oxide, oxygen-rich silicon oxynitride, nitrogen-rich silicon oxynitride, aluminum nitride, silicon nitride, silicon-rich nitride, hafnium oxide, titanium oxide, hafnium oxynitride, and hafnium silicate.

[0016] Furthermore, the material of the barrier oxide layer is a dielectric material with a dielectric constant greater than that of silicon dioxide, including at least one of the following: silicon oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum oxide, hafnium oxynitride compound, hafnium aluminate compound, titanium dioxide, tantalum pentoxide, aluminum oxide, cerium dioxide, tungsten trioxide, and yttrium oxide.

[0017] Furthermore, the charge trapping layer comprises multiple layers.

[0018] Furthermore, the charge trapping layer includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer disposed on the first nitride layer, wherein the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer, and the second nitride layer comprises a trap-dense oxygen-depleted nitride layer, and an anti-tunneling layer comprising oxides is arranged to separate the first nitride layer and the second nitride layer.

[0019] Furthermore, the first nitride layer is deuterated, and the deuterium concentration in the first nitride layer is lower than the deuterium concentration in the first deuterated layer.

[0020] Furthermore, it also includes a second deuterated layer placed above the second nitride layer.

[0021] Beneficial effects

[0022] This invention designs a flash memory storage device, mainly addressing the issue that the charges in charge traps in charge-trapped memory have a certain energy level distribution, ranging from shallow to deep energy levels. Trapped charges in the shallow energy levels are prone to escape and loss at high temperatures or during long-term data retention, thereby causing drift in the characteristics of the flash memory storage cell and damage to the stored data. The soft erase operation of this flash memory storage device removes the trapped charges in the shallow energy levels in advance, thus significantly optimizing the reliability issues such as the retention characteristics and high-temperature characteristics of the flash memory storage cell. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0024] Figure 1 This is a schematic diagram of a flash memory storage device provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the voltage module output in a flash memory storage device according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a flash memory storage device provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] See Figure 1 An embodiment of the present invention provides a flash memory storage device, including a substrate and a gate stack disposed on the substrate. The substrate includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The gate stack is disposed on the channel region, and the gate stack consists of a control gate, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer from top to bottom. The source region is connected to a source voltage (VS) module, the drain region is connected to a drain voltage (VD) module, and the control gate is connected to a gate voltage (VG) module. The present invention removes trapped charges in shallow energy levels in advance by adjusting the outputs of the source voltage (VS) module, the drain voltage (VD) module, and the gate voltage (VG) module respectively. Figure 3 As shown.

[0029] In this embodiment, as Figure 2 As shown, the source voltage VS module, the drain voltage VD module, and the gate voltage VG module each output voltage, and the pulse width and amplitude of the output voltage can be adjusted respectively. Furthermore, the gate voltage VG output voltage is low, while the source voltage VS module and the drain voltage VD module output voltage is high, which causes some shallow-level electrons in the stored electrons of the charge trapping layer to recombine. In addition, this setting can improve the high-temperature characteristics and data retention capability of the flash memory storage device by about 30%.

[0030] In this embodiment, the material of the control gate generally includes at least one of the following: platinum, gold, titanium aluminide alloy, palladium, aluminum, metal nitride, metal boron nitride, metal silicon nitride, metal silicide, and metal aluminum nitride.

[0031] In this embodiment, the charge trapping layer material includes at least one of the following: tantalum oxide, titanium dioxide, barium titanate, strontium titanate, zirconium dioxide, lead zirconate titanate, hafnium dioxide, aluminum oxide, yttrium oxide, lanthanum oxide, oxygen-rich silicon oxynitride, nitrogen-rich silicon oxynitride, aluminum nitride, silicon nitride, silicon-rich nitride, hafnium oxide, titanium oxide, hafnium oxynitride, and hafnium silicate. Industry focus is primarily on hafnium dioxide (HfO2) and zirconium dioxide (ZrO2), with HfO2 or hafnium compounds being preferred due to their high dielectric constant, volatility, and thermal stability, offering advantages in terms of good balance and reasonable bandgap width during deposition. Compared to HfO2, a suitable ZrO2 morphology exhibits better dielectric constant performance, but its bandgap is slightly narrower, leading to leakage issues. However, this leakage problem can be addressed by forming a zirconium dioxide / aluminum oxide / zirconium dioxide (collectively referred to as ZAZ) layer structure.

[0032] In this embodiment, the material of the barrier oxide layer is a dielectric material with a dielectric constant greater than that of silicon dioxide. The dielectric constant of silicon dioxide is 3.9, and the dielectric constant of the barrier oxide layer is at least 7. It includes at least one of the following high-dielectric materials: silicon oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum oxide, hafnium oxynitride, hafnium oxynitride, hafnium aluminate, titanium dioxide, tantalum pentoxide, aluminum oxide, cerium dioxide, tungsten trioxide, and yttrium oxide. Furthermore, when the barrier oxide layer is formed of hafnium oxide, the transition metal doped in the barrier layer is at least one of the following transition metals: tantalum, vanadium, ruthenium, and niobium. If the barrier oxide layer is formed of zirconium oxide, the transition metal doped in the barrier layer is at least one of the following transition metals: tungsten, ruthenium, molybdenum, nickel, niobium, vanadium, titanium, and zinc.

[0033] In this embodiment, the charge trapping layer is generally multilayered, and the multilayered charge trapping layer generally includes at least two layers having different compositions of silicon, oxygen, and nitrogen. In one embodiment, the multilayered charge trapping layer includes a first nitride layer containing a substantially trap-free, silicon-rich, oxygen-rich nitride and a second nitride layer containing a trap-dense, silicon-rich, nitrogen-rich, and oxygen-depleted nitride. It has been found that the silicon-rich, oxygen-rich first nitride layer reduces the charge loss rate after programming and erasing, manifested in small voltage offsets in hold mode. The silicon-rich, nitrogen-rich, and oxygen-depleted second nitride layer improves speed and increases the initial difference between programming and erasing voltages without affecting the charge loss rate of memory devices fabricated using embodiments with a silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the device's operating lifetime.

[0034] In addition to the first and second nitride layers, the multilayer charge trapping layer also includes one or more deuterated layers. In this embodiment, the multilayer charge trapping region includes a first deuterated layer separating the first nitride layer and the tunnel dielectric layer, and a second deuterated layer separating the second nitride layer and the barrier dielectric layer. The first and second deuterated layers may be composed of deuterated derivatives of the same material used to form the first and second nitride layers. For example, in one embodiment, where the first and second nitride layers comprise silicon nitride and / or silicon oxynitride, the first and second deuterated layers may be composed of deuterated derivatives of silicon oxynitride.

[0035] In this embodiment, the first nitride layer is deuterated, and the deuterium concentration in the first nitride layer is lower than the deuterium concentration in the first deuterated layer. Furthermore, a second deuterated layer is included, positioned above the second nitride layer.

[0036] The advantage of this invention lies in the fact that the charges in the charge traps of the charge trap memory have a certain energy level distribution, ranging from shallow to deep energy levels. The trapped charges in the shallow energy levels are prone to escape and loss at high temperatures or during long-term data retention, which can cause drift in the characteristics of the flash memory cell and damage to the stored data. The soft erase operation of this flash memory device removes the trapped charges in the shallow energy levels in advance, thereby significantly optimizing the reliability issues such as the retention characteristics and high-temperature characteristics of the flash memory cell.

[0037] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory storage device, characterized in that, The system includes a substrate and a gate stack disposed on the substrate. The substrate includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The gate stack is disposed on the channel region and, from top to bottom, comprises a control gate, a barrier oxide layer, a charge trapping layer, and a tunneling oxide layer. The source region is connected to a source voltage (VS) module, the drain region is connected to a drain voltage (VD) module, and the control gate is connected to a gate voltage (VG) module. The source voltage (VS) module, the drain voltage (VD) module, and the gate voltage (VG) module each output voltage, and the pulse width and amplitude of the output voltage can be adjusted independently. The gate voltage (VG) output voltage is low, and the source voltage (VS) module and the drain voltage (VD) module output voltage are high.

2. The flash memory storage device according to claim 1, characterized in that, The material of the control gate includes at least one of the following: platinum, gold, titanium aluminide alloy, palladium, aluminum, metal nitride, metal boron nitride, metal silicon nitride, metal silicide, and metal aluminum nitride.

3. The flash memory storage device according to claim 1, characterized in that, The charge trapping layer is made of at least one of the following materials: tantalum oxide, titanium dioxide, barium titanate, strontium titanate, zirconium dioxide, lead zirconate titanate, hafnium dioxide, aluminum oxide, yttrium oxide, lanthanum oxide, oxygen-rich silicon oxynitride, nitrogen-rich silicon oxynitride, aluminum nitride, silicon nitride, silicon-rich nitride, hafnium oxide, titanium oxide, hafnium oxynitride, and hafnium silicate.

4. The flash memory storage device according to claim 1, characterized in that, The material of the barrier oxide layer is a dielectric material with a dielectric constant greater than that of silicon dioxide, including at least one of the following: silicon oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum oxide, hafnium oxynitride compound, hafnium aluminate compound, titanium dioxide, tantalum pentoxide, aluminum oxide, cerium dioxide, tungsten trioxide, and yttrium oxide.

5. The flash memory storage device according to claim 1, characterized in that, The charge trapping layer comprises multiple layers.

6. The flash memory storage device according to claim 5, characterized in that, The charge trapping layer includes a first deuterated layer disposed on the tunneling oxide layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer disposed on the first nitride layer, wherein the first nitride layer comprises a substantially trap-free, oxygen-rich nitride layer, and the second nitride layer comprises a trap-dense, oxygen-depleted nitride layer, and an anti-tunneling layer comprising oxides is arranged to separate the first nitride layer and the second nitride layer.

7. The flash memory storage device according to claim 6, characterized in that, The first nitride layer is deuterated, and the deuterium concentration in the first nitride layer is lower than the deuterium concentration in the first deuterated layer.

8. The flash memory storage device according to claim 7, characterized in that, It also includes a second deuterated layer placed above the second nitride layer.

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