A memory suitable for cross array crosstalk prevention and a manufacturing method thereof

Abstract

The application provides a memory suitable for cross array anti-crosstalk and a manufacturing method thereof, which comprises, from bottom to top, a substrate, a bottom electrode, a hafnium-zirconium-based oxide, a metal, a hafnium-zirconium-based oxide and an upper electrode. The substrate serves as a hard support layer of the device; the bottom electrode and the upper electrode serve as read-write ends of the device signal; and the sandwich structure of the hafnium-zirconium-based oxide, the metal and the hafnium-zirconium-based oxide is used for information storage and realization of the anti-crosstalk function. The hafnium-based oxide is used to replace the perovskite material, which is beneficial to obtaining ferroelectric function in a high-density integrated ultrathin medium and realizing anti-crosstalk of a high-density cross array.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronic devices, and particularly relates to a memory suitable for cross array anti-crosstalk and a manufacturing method thereof. BACKGROUND

[0002] It is the eternal pursuit of memory to continuously reduce the device size to meet high-density integration and improve storage capacity. The traditional ferroelectric memory uses perovskite structure material as the storage medium, but its ferroelectric performance deteriorates with the film thickness thinning, which poses a serious challenge to high-density integration. In addition, there is a crosstalk problem in the cross array used for high-density storage, which seriously affects the reliability of reading storage information. It is a realistic demand for high-density ferroelectric storage to have good ferroelectric performance under ultra-thin film thickness and the device has good nonlinearity to suppress crosstalk. SUMMARY

[0003] In view of the defects and deficiencies of the prior art, the purpose of the present application is to provide a memory suitable for cross array anti-crosstalk and a manufacturing method thereof. Since hafnium-zirconium-based oxide still has good ferroelectric characteristics at low dimension, it can be used as a storage medium to meet reliable storage under high-density integration. Integrating complementary switching function in the device is beneficial to suppress the crosstalk encountered in the cross storage array and improve the reliability of device reading.

[0004] The present application uses hafnium-zirconium-based oxide as a storage medium and integrates complementary resistance switching characteristics into the device, which improves the nonlinearity of the device while ensuring the ferroelectric performance, and is beneficial to the high-density integration of ferroelectric storage and the suppression of crosstalk.

[0005] It comprises, from bottom to top, a substrate, a bottom electrode, a hafnium-zirconium-based oxide, a metal, a hafnium-zirconium-based oxide and an upper electrode. The substrate serves as a hard support layer of the device; the bottom electrode and the upper electrode serve as the read-write end of the device signal; the sandwich structure composed of the hafnium-zirconium-based oxide, the metal and the hafnium-zirconium-based oxide is used for information storage and the realization of anti-crosstalk function. The present application uses hafnium-based oxide instead of perovskite material, which is beneficial to obtaining ferroelectric function in ultra-thin medium of high-density integration and realizing anti-crosstalk of high-density cross array.

[0006] The present application specifically adopts the following technical solutions:

[0007] A memory suitable for cross array anti-crosstalk, characterized in that it comprises, from bottom to top, a substrate, a bottom electrode, a hafnium-zirconium-based oxide, a metal, a hafnium-zirconium-based oxide and an upper electrode;

[0008] The substrate serves as a device support layer;

[0009] The bottom electrode and the upper electrode serve as the read-write end of the device signal;

[0010] The hafnium-zirconium-based oxide / metal / hafnium-zirconium-based oxide sandwich structure is sandwiched between the bottom electrode and the upper electrode, and is used for information storage and realization of anti-crosstalk function.

[0011] Further, the bottom electrode and the upper electrode are metal, metal alloy, conductive metal compound or semiconductor.

[0012] Further, the metal is one or more of Au, Pt, Pd and Ru, and is sandwiched between the hafnium-zirconium-based oxide layers.

[0013] Further, the chemical formula of the hafnium-zirconium-based oxide is Hf 1-x Zr x O2, wherein 0≤x≤1.

[0014] Further, the material of the electrode is Pt or TiN.

[0015] Further, the thickness of the hafnium-zirconium-based oxide is 0.5-20 nm, and the thickness of the metal layer is 0.5-30 nm.

[0016] The manufacturing method of the above memory suitable for cross array anti-crosstalk includes the following steps:

[0017] Step S1: a bottom electrode is manufactured on a substrate by sputtering, PECVD, MOCVD, ALD or evaporation;

[0018] Step S2: a hafnium-zirconium-based oxide, a metal and a hafnium-zirconium-based oxide are sequentially manufactured on the bottom electrode by sputtering, PECVD, MOCVD, ALD or evaporation, to form a sandwich structure;

[0019] Step S3: the sandwich structure is heat treated at 450-850 °C for 10-3000 s;

[0020] Step S4: an upper electrode is manufactured on the sandwich structure by sputtering, PECVD, MOCVD, ALD or evaporation;

[0021] Step S5: a device unit is etched by etching process, and the memory preparation is completed.

[0022] Compared with the prior art, the hafnium-zirconium-based oxide is used as the storage medium in the application and the preferred scheme, the reliability of ferroelectric storage under ultra-thin film thickness is improved, and high-density integration is served. By designing a laminated sandwich structure as a storage medium, complementary switching characteristics are realized in the hafnium-zirconium-based oxide, and the reliability of device signal reading is improved. This scheme provides a new choice for improving the reliability of high-density integrated cross array ferroelectric storage. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structural schematic diagram of the present application;

[0024] Figure 2 is a hysteresis loop diagram of a device in an embodiment of the present application;

[0025] Figure 3 is a I-V characteristic curve diagram of a device in an embodiment of the present application.

[0026] Figure 1 In the figure, 01 - upper electrode; 02 - hafnium-zirconium-based oxide; 03 - metal; 04 - hafnium-zirconium-based oxide; 05 - bottom electrode; 06 - substrate. DETAILED DESCRIPTION

[0027] In order to make the features and advantages of the patent more obvious and easy to understand, the following specific examples are described in detail as follows:

[0028] In order to make the features and advantages of the patent more obvious and easy to understand, the following specific examples are described in detail as follows:

[0029] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise indicated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application pertains.

[0030] It should be noted that the terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form, and in addition, it should be understood that when the terms "comprise" and / or "include" are used in the specification, there is a feature, step, operation, device, component and / or combination thereof.

[0031] Please refer to Figure 1 The present application provides a memory, comprising a substrate 06, a bottom electrode 05, a hafnium-zirconium-based oxide 04, a metal 03, a hafnium-zirconium-based oxide 02 and an upper electrode 01. The substrate 06 is a hard support layer for the device. The bottom electrode 05 is placed above the substrate as a read-write terminal for the device signal. The hafnium-zirconium-based oxide 04 / metal 03 / hafnium-zirconium-based oxide 02 forms a laminated sandwich structure as the main functional layer of the device. The upper electrode 01 is above the sandwich structure.

[0032] In an embodiment of the present application, the substrate is a silicon wafer.

[0033] In an embodiment of the present application, the bottom electrode and the upper electrode are each independently selected from a metal, a metal alloy, a conductive metal compound or a well-conductive semiconductor. The metal is Pt, TiN, W or Pd; the metal alloy is Pt / Ti or Ti / W; the conductive metal compound is TiN, TiW, TaN or WSi; and the well-conductive semiconductor is heavily doped silicon, AZO, ITO or FTO.

[0034] In an embodiment of the present application, the metal is a noble metal such as Au, Pt, Pd, Ru and the like, and is sandwiched between the hafnium-zirconium-based oxide layers, and the thickness of the metal is 0.5-30 nm.

[0035] In an embodiment of the present application, the hafnium-zirconium-based oxide has a chemical formula of Hf 1-x Zr x O2, wherein 0≤x≤1. The thickness of the hafnium-zirconium-based oxide is 0.5-20 nm.

[0036] In an embodiment of the present application, the electrode is Pt or TiN.

[0037] In an embodiment of the present application, the method for manufacturing the memory device comprises the following steps:

[0038] Step S1: a bottom electrode 05 is formed on a substrate 06 by sputtering, PECVD, MOCVD, ALD or evaporation;

[0039] Step S2: a hafnium-zirconium-based oxide 04, a metal 03 and a hafnium-zirconium-based oxide 02 are sequentially formed on the bottom electrode 05 by sputtering, PECVD, MOCVD, ALD or evaporation, to form a sandwich structure;

[0040] Step S3: the sandwich structure is heat-treated at 450-850 °C for 10-3000 s;

[0041] Step S4: an upper electrode 01 is formed on the sandwich structure by sputtering, PECVD, MOCVD, ALD or evaporation;

[0042] Step S5: a device unit is etched by an etching process, and the memory device is completed.

[0043] The present application is further demonstrated and explained below in combination with actual cases.

[0044] Embodiment 1:

[0045] An electronic synapse device is provided, which has a structure as shown in Figure 1 The device comprises a silicon substrate 06, a TiN layer 05 with a thickness of 100 nm, a hafnium-zirconium-based oxide layer 04 with a thickness of 6 nm, a metal layer 03 with a thickness of 2 nm, a hafnium-zirconium-based oxide layer 02 with a thickness of 6 nm and an upper electrode 01. 0.5 Zr 0.5O2 layer 04, a Pt layer 03 with a thickness of 20 nm, an Hf 0.5 Zr 0.5 O2 layer 02 and a TiN layer 01 with a thickness of 100 nm are formed. The silicon substrate 06 is a silicon wafer, serving as a hard support layer of the device. The 100 nm TiN layer 05 is formed on the silicon substrate, serving as a signal read-write end. Hf 0.5 Zr 0.5 O2 layer 04 / Pt layer 03 / Hf 0.5 Zr 0.5 O2 layer 02 forms a laminated sandwich structure, serving as the main functional layer of the device. The 100 nm TiN layer 01 serves as another terminal for reading and writing of the device.

[0046] The method for manufacturing the memory as above specifically comprises the following steps:

[0047] Step S1: a TiN bottom electrode 05 is prepared on a silicon substrate 06 by sputtering;

[0048] Step S2: on the TiN bottom electrode 05, an Hf 0.5 Zr 0.5 O2 layer 04 is first prepared by atomic layer deposition (ALD) with a thickness of 6 nm, and then a Pt layer 03 with a thickness of 20 nm is deposited thereon by sputtering, followed by preparation of an Hf 0.5 Zr 0.5 O2 layer 02 by ALD with a thickness of 6 nm, thereby forming a sandwich structure;

[0049] Step S3: the sandwich structure is placed in a N2 atmosphere and subjected to rapid thermal treatment at 500 °C for 30 s;

[0050] Step S4: a 100 nm thick TiN top electrode 01 is prepared on the sandwich structure after the heat treatment by sputtering;

[0051] Step S5: a device unit with a unit area of 50 μm × 50 μm is etched by an etching process, and the memory is completed.

[0052] To prove that the Hf 0.5 Zr 0.5 O2 layer in the device has ferroelectric properties, a comparative sample with a structure of “100 nm TiN / 6 nm Hf 0.5 Zr 0.5 O2 / 100 nm Pt” is prepared in this embodiment, and a ferroelectric tester is used to test the curve (i.e., the hysteresis loop) of the polarization intensity of the comparative sample versus the applied voltage. Figure 2is the hysteresis loop diagram of the device, and the curve well illustrates the change of the remanent polarization of the device with the applied voltage, and the device has the ferroelectric storage effect. Figure 3 is the current-voltage characteristic curve of the device prepared in the embodiment. It can be obviously seen from the figure that the nonlinearity of the curve is improved, and the device has obvious complementary resistance switching characteristics. This not only has the storage effect but also improves the reliability of reading of the device.

[0053] Based on the design idea of the present application, the method for reducing the light intensity of the blue sub-pixel can be realized from the perspectives of structure design, process and circuit, including but not limited to the above adjustment methods.

[0054] The above embodiments are only used to help understand the method of the present application and its core idea. Meanwhile, the above are only the preferred embodiments of the present application, and are not intended to limit the present application in other forms. Any skilled person in the art can modify or change the above disclosed technical contents into equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments without departing from the technical scheme of the present application, and according to the technical essence of the present application, still belong to the protection scope of the technical scheme of the present application.

Claims

1. A memory suitable for cross array crosstalk immunity, characterized by: From bottom to top, sequentially include: substrate, bottom electrode, hafnium-zirconium-based oxide, metal, hafnium-zirconium-based oxide and upper electrode; The substrate serves as a device support layer; The bottom electrode and the upper electrode serve as read-write ends of device signals; The hafnium-zirconium-based oxide / metal / hafnium-zirconium-based oxide forms a sandwich structure and is sandwiched between the bottom electrode and the upper electrode, for information storage and realization of anti-crosstalk function.

2. The memory of claim 1, wherein: The bottom electrode and the upper electrode are metal, conductive metal compound or semiconductor.

3. The memory of claim 1, wherein: the memory is suitable for use in a cross-point array. The metal is one or more of Au, Pt, Pd and Ru, and is sandwiched between the hafnium-zirconium-based oxide layers.

4. The memory of claim 1, wherein: The chemical formula of the hafnium zirconium-based oxide is Hf 1-x Zr x O2, wherein 0 < x < 1.

5. The memory of claim 1, wherein: the memory is suitable for use in a cross-point array. The material of the bottom electrode and the upper electrode is Pt or TiN.

6. The memory of claim 1 suitable for cross array crosstalk immunity, wherein: The thickness of the hafnium-zirconium-based oxide is 0.5-20 nm, and the thickness of the metal is 0.5-30 nm.

7. The method of claim 1-6, wherein: The method comprises the following steps: Step S1: fabricating a bottom electrode on a substrate by sputtering, PECVD, MOCVD, ALD or evaporation; Step S2: fabricating a hafnium-zirconium-based oxide, a metal and a hafnium-zirconium-based oxide in sequence on the bottom electrode by sputtering, PECVD, MOCVD, ALD or evaporation, to form a sandwich structure; Step S3: heat treating the sandwich structure at 450-850 °C for 10-3000 s; Step S4: fabricating an upper electrode on the sandwich structure by sputtering, PECVD, MOCVD, ALD or evaporation; Step S5: etching a device unit by etching process to complete the preparation of the memory.

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