Method and apparatus for checking data content integrity

Abstract

The present disclosure relates to methods and apparatuses for data processing, such as a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI). When at least a portion of the data corresponds to priority data, the apparatus may further detect an amount of adjustment of the received data, and the data is displayed or stored based on the detected amount of adjustment.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 051,663, entitled "METHODS AND APPARATUS FOR DATA CONTENT INTEGRITY", filed on Jul. 14, 2020, and U.S. Patent Application No. 17 / 092,165, entitled "METHODS AND APPARATUS FOR DATA CONTENT INTEGRITY", filed on Nov. 6, 2020, the entire contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present disclosure generally relates to processing systems, and more particularly, to one or more techniques for data or display processing. Background Art

[0004] Computing devices typically utilize a graphics processing unit (GPU) to accelerate the rendering of graphics data for display. Such computing devices can include, for example, computer workstations, mobile phones such as so - called smart phones, embedded systems, personal computers, tablet computers, and video game consoles. The GPU executes a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. A central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of concurrently executing multiple applications, and each of the multiple applications may need to utilize the GPU during execution. Devices that provide content for visual presentation on a display typically include a GPU.

[0005] Generally, the GPU of a device is configured to perform processes in the graphics processing pipeline. However, with the advent of wireless communication and smaller handheld devices, the need for improved graphics processing has been continuously increasing. Summary of the Invention

[0006] A brief overview of one or more aspects is given below to provide a basic understanding of such aspects. This overview is not an extensive review of all contemplated aspects and is not intended to identify key elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device can be a display processor, a display processing unit (DPU), a GPU, a CPU, a display, a compositor, and / or a frame processor. The device can receive data including a plurality of data bits, the data being associated with at least one data source. The device can also determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI). When at least a portion of the data corresponds to priority data, the device can also detect an adjustment amount of the received data, and the data is displayed or stored based on the detected adjustment amount. Additionally, the device can generate a data signature for the received data based on the adjustment amount of the received data. The device can also determine whether the adjustment amount is less than or equal to a data adjustment threshold. The device can also communicate the data based on the detected adjustment amount.

[0008] Details of one or more examples of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of the present disclosure.

[0010] Figure 2 illustrates an example GPU in accordance with one or more techniques of the present disclosure.

[0011] Figure 3 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0012] Figure 4 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0013] Figure 5 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0014] Figure 6 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0015] Figure 7 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0016] Figure 8 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0017] Figure 9 illustrates an example diagram of data processing in accordance with one or more techniques of the present disclosure.

[0018] Figure 10 An example diagram showing an image according to one or more techniques of the present disclosure.

[0019] Figure 11 An example diagram showing data processing according to one or more techniques of the present disclosure.

[0020] Figure 12 An example communication flow diagram showing data processing according to one or more techniques of the present disclosure.

[0021] Figure 13 An example flow diagram showing an example method according to one or more techniques of the present disclosure. Detailed Description

[0022] The display subsystem is used in safety applications, where the image data on the display can be used for several driver assistance functions and / or for the instrument cluster. Failure to display correct or accurate data can lead to violations of the defined safety goals for automotive applications (e.g., rearview camera systems, forward collision warning systems, traffic sign recognition, parking assistance systems, and instrument cluster displays providing sign information). For example, a frozen display during a rearview camera application or an autonomous driving function can result in life - threatening injuries. Additionally, a multi - input signature register (MISR) can be implemented for regions of interest (ROI) as a key automotive safety mechanism within the display subsystem. The ability to ensure data content integrity of the image data is an important feature. MISR has not been well - studied in the context of safety applications, while cyclic redundancy check (CRC) has a rich usage history in safety applications in many industries, including aviation. Supporting CRC instead of MISR can allow for higher design coverage. In some cases, the CRC polynomial selection can be a highly specialized domain. Moreover, the selection of an appropriate polynomial can leverage knowledge of application and polynomial characteristics. Programmable CRC can provide the influence to remove existing competing solutions by removing significant migration barriers. Aspects of the present disclosure can include a display subsystem capable of simultaneously processing safety and non - safety display image content for different applications (e.g., automotive applications). The present disclosure relates to the use of a display subsystem in functional - safety automotive applications. Specifically, the present disclosure relates to ADAS and instrument clusters in safety automotive applications that include the use of a display subsystem. The present disclosure also relates to a system method for ensuring data content integrity of displays (e.g., instrument clusters, rearview camera applications, surround - view systems, and autonomous driving applications). Additionally, the present disclosure includes a system method for performing concurrent online CRC calculations on user - configurable selected regions of interest within a display image. The software - configurable CRC polynomial can be static per customer or changed on a frame - by - frame or use - case basis.

[0023] Aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should appreciate that the scope of the present disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other aspects of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the present disclosure is intended to cover such apparatus or methods practiced using other structures, functions, or combinations of structures and functions in addition to or different from the aspects of the present disclosure set forth herein. Any aspect of the present disclosure may be embodied by one or more elements of a claim.

[0024] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of the aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses, or objectives. Rather, the aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and the figures are merely illustrative of the present disclosure and not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0025] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the following detailed description and illustrated in the figures by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0026] For example, an element, or any portion of an element, or any combination of elements can be implemented as a "processing system" that includes one or more processors (which may also be referred to as processing units). Examples of processors include: microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SOCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in the processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise, software can be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc. The term application can refer to software. As described herein, one or more techniques can refer to an application (i.e., software) configured to perform one or more functions. In such an example, the application can be stored in a memory, such as on-chip memory of a processor, system memory, or any other memory. The hardware described herein (such as a processor) can be configured to execute the application. For example, the application can be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware can access the code from the memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, a component can be hardware, software, or a combination thereof. A component can be a separate component or a sub-component of a single component.

[0027] Accordingly, in one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored on or encoded as one or more instructions or code on a computer-readable medium. A computer-readable medium includes computer storage media. A storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other media that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0028] In general, the present disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on a processing unit (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a GPU). For example, the present disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout the present disclosure.

[0029] As used herein, instances of the term "content" can refer to "graphics content", "image", and vice versa. This is true regardless of whether the term is used as an adjective, a noun, or other part of speech. In some examples, as used herein, the term "graphics content" can refer to content generated by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" can refer to content generated by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" can refer to content generated by a graphics processing unit.

[0030] In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" can refer to content generated by a display processing unit. Graphics content can be processed to become display content. For example, a graphics processing unit can output graphics content such as a frame to a buffer (which can be referred to as a frame buffer). A display processing unit can read the graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques on it to generate display content. For example, a display processing unit can be configured to perform composition on one or more render layers to generate a frame. As another example, a display processing unit can be configured to synthesize, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling on a frame (e.g., magnifying or reducing). In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form a frame, i.e., a frame includes two or more layers, and a frame including two or more layers can subsequently be blended.

[0031] Figure 1FIG. 0 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of the device 104 may be components of a system-on-a-chip (SOC). The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120 and a system memory 124. In some aspects, the device 104 may include a number of optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frames for presentation thereon. In further examples, the results of graphics processing may not be displayed on the device, e.g., the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or the results of graphics processing may be transmitted to another device. In some aspects, this may be referred to as split rendering.

[0032] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. In some examples, the device 104 may include a display processor (such as the display processor 127) to perform one or more display processing techniques on one or more frames generated by the processing unit 120 prior to presentation by one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. One or more displays 131 may be configured to display or otherwise present the frames processed by the display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light-emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0033] Memory external to processing unit 120, such as system memory 124, may be accessible to processing unit 120. For example, processing unit 120 may be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 may be communicatively coupled to system memory 124 via a bus. In some examples, processing units 120 may be communicatively coupled to each other via a bus or different connections.

[0034] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0035] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagated signal. However, the term "non-transitory" should not be construed to mean that internal memory 121 or system memory 124 is immovable or that its contents are static. As an example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may be non-removable from device 104.

[0036] The processing unit 120 can be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 can be integrated into the motherboard of the device 104. In some examples, the processing unit 120 can be present on a graphics card installed in a port in the motherboard of the device 104, or can otherwise be incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 can include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is implemented partially in software, the processing unit 120 can store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., the internal memory 121), and can execute the instructions in hardware using one or more processors to perform the techniques of the present disclosure. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., can be considered one or more processors.

[0037] In some aspects, the content generation system 100 can include an optional communication interface 126. The communication interface 126 can include a receiver 128 and a transmitter 130. The receiver 128 can be configured to perform any of the receiving functions described herein with respect to the device 104. Additionally, the receiver 128 can be configured to receive information (e.g., eye or head position information, rendering commands, or location information) from another device. The transmitter 130 can be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 can be configured to send information (which can include a request for content) to another device. The receiver 128 and the transmitter 130 can be combined into a transceiver 132. In such an example, the transceiver 132 can be configured to perform any of the receiving functions and / or transmitting functions described herein with respect to the device 104.

[0038] Refer again to Figure 1, in some aspects, the graphics processing pipeline 107 can include a determination component 198 configured to receive data including a plurality of data bits, the data being associated with at least one data source. The determination component 198 can also be configured to determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI). The determination component 198 can also be configured to detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, and the data is displayed or stored based on the detected adjustment amount. The determination component 198 can also be configured to generate a data signature of the received data based on the adjustment amount of the received data. The determination component 198 can also be configured to determine whether the adjustment amount is less than or equal to a data adjustment threshold. The determination component 198 can also be configured to communicate the data based on the detected adjustment amount.

[0039] As described herein, a device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, the device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, a device, a telephone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device, or a virtual reality device), a non-wearable device, a display or display device, a television, a set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. Processes herein can be described as being performed by a particular component (e.g., a GPU), but in further embodiments, can be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.

[0040] The GPU can process multiple types of data or data groups in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data groups, such as context register groups and draw call data. A context register group can be a set of global state information that can manage how a graphics context will be processed, such as information about global registers, shader programs, or constant data. For example, a context register group can include information about the color format. In some aspects of the context register group, there can be bits indicating which workload belongs to the context register. Additionally, there can be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a specific operation, such as a color mode or color format. Thus, the context register can define multiple states of the GPU.

[0041] The context state can be used to determine how a single processing unit (e.g., vertex fetcher (VFD), vertex shader (VS), shader processor, or geometry processor) operates and / or in which mode the processing unit operates. For this purpose, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads, such as vertex or pixel workloads, in the pipeline based on the context register definitions of the mode or state. Certain processing units (e.g., VFD) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may change the corresponding context. Additionally, the workloads corresponding to the mode or state can follow the changing mode or state.

[0042] Figure 2 FIG. 200 shows an example GPU 200 in accordance with one or more techniques of the present disclosure. As Figure 2 shown, the GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z - process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, an L2 cache (UCHE) 238, and a system memory 240. Although Figure 2 shown that the GPU 200 includes processing units 220 - 238, the GPU 200 can include multiple additional processing units. Additionally, the processing units 220 - 238 are merely examples, and according to the present disclosure, the GPU can use any combination or order of processing units. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0043] As Figure 2As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to parse a command buffer into context register groups (e.g., context register group 260) and / or draw call data groups (e.g., draw call group 212). Then, CP 210 can send the context register group 260 or the draw call data group 212 to a processing unit or block in the GPU via separate paths. Additionally, the command buffer 250 can alternate different states of context registers and draw calls. For example, the command buffer can be constructed in such a way as: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0044] Aspects of a mobile device or smartphone can utilize a buffer mechanism to distribute or coordinate buffers between the application rendering side (e.g., GPU or CPU) of the device and the display or composition side (e.g., display engine) of the device. For example, some mobile devices can utilize a buffer queue mechanism to distribute or coordinate buffers between the application rendering side and the display or composition side, which can include a buffer composer or a hardware composer (HWC). In some aspects, the application rendering side can be referred to as the producer, while the display or composition side can be referred to as the consumer. Additionally, a synchronization divider or a fence can be used to synchronize the content between the application rendering side and the display or composition side. Thus, a fence can be referred to as a synchronization divider and vice versa.

[0045] Some systems (such as advanced driver assistance systems (ADAS)) may need to meet functional safety specifications (e.g., as indicated by the International Organization for Standardization (ISO) 26262) and functional safety standards for vehicles. ISO 26262 poses challenges to the entire automotive supply chain. Each party (e.g., semiconductor suppliers, Tier 1, and original equipment manufacturers (OEMs)) can work together to achieve compliance. A key functional safety specification can be to ensure the data content integrity of selected portions of the image data sent to the display.

[0046] In some aspects, a display subsystem can be used in automotive applications. For these systems, the image data on the display can be used for several driver assistance functions and / or for the instrument cluster. Failure to display correct or accurate data can lead to violations of the defined safety goals for automotive applications (e.g., rearview camera systems, forward collision warning systems, traffic sign recognition, parking assistance systems, and instrument cluster displays providing sign information). For example, a frozen display during a rearview camera application or an autonomous driving function can result in life-threatening injuries.

[0047] Additionally, a multi-input signature register (MISR) can be implemented for regions of interest (ROI) in a display as a key automotive safety mechanism within the display subsystem. As described herein, the ability to ensure data content integrity of image data is an important feature. MISR has not been well studied in the context of safety applications, while cyclic redundancy check (CRC) has a rich usage history in safety applications in many industries including aerospace. Supporting CRC instead of MISR can allow for higher design coverage required in ISO 26262 analysis, thus contributing to automotive safety integrity level (ASIL) certification.

[0048] In some cases, CRC polynomial selection can be a highly specialized domain. Additionally, the selection of an appropriate polynomial may require knowledge of the application and polynomial characteristics. A poor choice during the polynomial selection process can lead to an unexpectedly high rate of undetected errors in CRC applications. Programmable CRC can shift the burden of polynomial selection to the OEM. A specific polynomial can be assumed to build existing safety applications. Programmable CRC can provide the influence to remove existing competing solutions by removing significant migration barriers. This can provide the OEM with the ability to mix different safety applications with different polynomials. This can also provide a market advantage.

[0049] Figure 3 FIG. 300 showing data processing. More specifically, FIG. 300 is a display processing unit (DPU) area decomposition. As Figure 3 shown, FIG. 300 includes a control unit 302, a bus interface 310, video graphics (VIG) components 311 - 314, direct memory access (DMA) components 316 - 319, a crossbar switch 320, layer mixer (LM) components 321 - 326, a destination surface processor pipeline (DSPP) components 331 - 334, a scaling / sharpening component 340, an ROI MISR / CRC 350, a panel compression component 360, a crossbar switch 370, a display serial interface (DSI) components 381 - 386, and a write-back (WB) component 391. Figure 3 The use of a region of interest (ROI) multi-input signature register (MISR) as well as CRC (e.g., ROI MISR / CRC 350) in a display subsystem for automotive applications. As Figure 3 depicted, a large percentage of the DPU design can be upstream of the CRC 350 such that it can receive protection.

[0050] Compared to other solutions such as error checking and correction (ECC) codes, certain data processing designs (e.g., FIG. 300) can provide high design coverage with low area cost. However, it may be beneficial for a display subsystem to be able to simultaneously process secure and non-secure display image content for different applications (e.g., automotive applications).

[0051] Aspects of the present disclosure can include a display subsystem capable of simultaneously processing secure and non-secure display image content for different applications (e.g., automotive applications). Aspects of the present disclosure relate to the use of the display subsystem in functional automotive applications. Specifically, aspects of the present disclosure relate to ADAS and instrument clusters in automotive applications that incorporate the use of the display subsystem. Aspects of the present disclosure also relate to a system method for ensuring data content integrity of displays (e.g., instrument clusters, rearview camera applications, surround view systems, and autonomous driving applications). Additionally, aspects of the present disclosure include a system method for performing concurrent online CRC calculations on user-configurable selected regions of interest (ROIs) within a display image. Aspects of the present disclosure also relate to software-configurable CRC polynomials, which can be static per customer or changed on a per-frame or per-use-case basis. Additionally, aspects of the present disclosure allow different polynomials to be selected for different regions of interest within a display image.

[0052] Aspects of the present disclosure relate to a system method for performing concurrent offline data integrity security analysis on a user-configurable selected region of interest (ROI), which can include a safety-critical display image. Aspects of the present disclosure also relate to a system method for performing a user-configurable selection of pixels within an ROI, which can include a safety-critical display image. Additionally, aspects of the present disclosure relate to a system method for performing concurrent online CRC calculations on a user-configurable selection of pixels within an ROI, which can include a safety-critical display image. Thus, aspects of the present disclosure can include multiple different ROI shapes. For example, the ROI can be a rectangular shape, a circular shape, and completely arbitrary shapes. Additionally, aspects of the present disclosure relate to a selectively, software-configurable ROI in its entirety or for a subset of pixels from a safety-critical display image deemed suitable for offline safety analysis, which can be changed on a per-frame basis.

[0053] Aspects of the present disclosure include general configurable hardware blocks (i.e., parallel CRC blocks) that can process multiple data bits input per clock cycle, e.g., N-bit data. The block can include an N-bit data input and M-bit flip-flop storage for the CRC value. For each CRC flip-flop bit, there can be an associated exclusive OR (XOR) structure in which each of the N bits of the input data and the M bits of the current CRC state can act as controlled by a separate enable. Additionally, aspects of the present disclosure can be highly pipelined such that the maximum clock frequency (FMAX) is a function of the polynomial degree rather than based on the number of bits processed per clock cycle. Some deployments can support certain sizes of CRCs, e.g., 32-bit CRC. In some aspects, once the hardware supports the maximum size of CRC (e.g., 32-bit CRC), the hardware can also support any size of CRC up to that size, e.g., 16-bit CRC or 24-bit CRC.

[0054] Figure 4 FIG. 400 illustrates data processing in accordance with one or more techniques of the present disclosure. More specifically, FIG. 400 illustrates a conventional CRC circuit with an M-bit polynomial capable of processing 1 bit of data per clock cycle. As Figure 4 shown, FIG. 400 includes CRC 410, CRC 411, CRC(M-1), P 420, P 421, P(N-1), and a serial input. FIG. 400 can be a 1-bit-per-operation algorithm. Additionally, FIG. 400 can be a polynomial controlled by respective enable bits (e.g., Pn).

[0055] In some instances, aspects of the present disclosure can include a parallel CRC circuit that can be generalized to allow processing of M bits per clock cycle. Using CRC for high data rate signals such as display pixel data can take advantage of the ability to process many bits of data during each clock cycle. Each CRC and data bit can contribute to each updated CRC bit. Additionally, there can be subordinate polynomials, as well as polynomials controlled by respective enable bits, e.g., EN_CRC(j,i) and EN_D(k,i). As indicated herein, the decomposition process can help generate these individual enable bits.

[0056] Figure 5 FIG. 500 illustrates data processing in accordance with one or more techniques of the present disclosure. As Figure 5 shown, FIG. 500 includes CRC 511, CRC(i), D(k), EN_CRC(j,i), and EN_D(j,k). FIG. 500 shows a 32-bit CRC capable of processing 60 bits per clock cycle. As Figure 5As indicated, in some instances, the CRC implementation can process two 30-bit pixels per clock cycle. This may require a certain number of configuration bits to control, e.g., (60 + 32) * 32 = 2944 bits.

[0057] Figure 6 FIG. 600 showing data processing in accordance with one or more techniques of the present disclosure. FIG. 600 includes CRC 611, CRC(i), D(k), EN_CRC(j,i), and EN_D(j,k). As Figure 6 shown, the computed data components can be pipelined to reduce the number of combinatorial terms. Additionally, the pipeline of the computed data components can be increased as needed. Additionally, the maximum operating frequency can be independent of the number of data bits processed per clock cycle.

[0058] Aspects of the present disclosure can also include parallel CRC blocks that can be shared by N regions of interest (ROIs). In a gauge cluster application, independent CRC signatures can be collected in different parts of the display. Multiple different groups can be assumed, e.g., four (4) separate groups. Additionally, the number of ROIs utilized by an OEM may be increasing, which would increase the hardware cost of CRC hardware without using hardware sharing.

[0059] Figure 7 FIG. 700 showing data processing in accordance with one or more techniques of the present disclosure. FIG. 700 includes CRC 711, CRC 712, CRC(i), D(k), and EN_D(j,k). As Figure 7 shown, aspects of the present disclosure can also include sharing hardware between ROIs. In some aspects, taking advantage of the fact that gauge cluster icons may not physically overlap, one CRC signature can be updated at a time. This can result in each ROI having its own CRC signature storage while the signature calculation circuitry can be shared, which can result in significant area savings.

[0060] Aspects of the present disclosure can also include many polynomial implementation variations. For example, the polynomial factorization of a common polynomial can be shared between each ROI. As described above, the factorization process can help generate individual enable bits. By doing so, aspects of the present disclosure can maximize area savings. Alternatively, multiple polynomials can be factored and stored. For example, there can be 16 ROIs that actively use two unique polynomials. The correct set of enables can be multiplexed into the shared CRC hardware based on the particular ROI being processed.

[0061] In some aspects of the present disclosure, there may be many available CRC context switching options. For example, the figures herein illustrate a multiplexer for selecting between multiple ROIs. Extending this multiplexing to a large number of ROIs may create timing paths. This can be avoided by preloading the CRC into a local CRC holding register. Additionally, multiple sets of registers can hold the current CRC context, such as CRC-A and CRC-B. This can avoid directly connecting N ROIs to an XOR structure. When working in one CRC (e.g., CRC-A), aspects of the present disclosure can preload another CRC (e.g., CRC-B) for the next ROI (and vice versa). This can be a cost-effective implementation that avoids affecting FMAX.

[0062] Figure 8 FIG. 800 showing data processing in accordance with one or more techniques of the present disclosure. FIG. 800 includes CRC 811, CRC(i), D(k), EN_CRC(j,i), EN_D(j,k), CRC 820, CRC 821, CRC(m-1), P 830, P 831, P(n-1), and a serial input. As Figure 8 shown, aspects of the present disclosure may also include polynomial decomposition via parallel CRC block reconfiguration. As Figure 8 depicted, polynomial enable terms can be calculated by feeding a pulse of length (N+M) into a serial CRC configured with the desired polynomial and recording the M-bit CRC value at each step. The resulting set of bits (e.g., M*(N+M) bits) can form the polynomial enable for a parallel CRC hardware block. For example, the pulse can be: "1" followed by (N+M-1) "0"s. The parallel CRC block can also be used to perform its own decomposition to avoid the software burden of directly managing individual enable terms, or to avoid having dedicated decomposition hardware. This can be achieved by configuring the enable to use a single data bit and setting the enable to match the serial CRC polynomial.

[0063] Aspects of the present disclosure may also include a serial configuration of the aforementioned blocks. For example, the hardware can program the parallel CRC block as if it were a serial CRC block for the decomposition process.

[0064] Aspects of the present disclosure may also include MISR decomposition via reconfiguration of hardware blocks. In some cases, a parallel CRC block with appropriate settings enabled can be used to compute the MISR signature. Additionally, the MISR signature can be computed N bits at a time. For example, in a DPU, the MISR can be computed on 30-bit pixels, but the data path can be wider, e.g., processing two pixels per clock. Polynomial terms can be computed by feeding a pulse of length (N+M) into a basic MISR implementation (i.e., a 30-bit implementation). For example, the pulse can be: '1' followed by (N+M-1) '0' terms. The parallel CRC block can be used to perform its own MISR decomposition. No additional hardware may be used. This can be achieved by configuring the enable to use a single data bit and setting the enable to match the basic MISR implementation. Support for other XOR algorithms can be provided by allowing software to have the ability to directly program the enable bits or by providing a similar decomposition strategy in hardware.

[0065] Aspects of the present disclosure may also include parallel CRC hardware capable of processing less than N bits per clock cycle. The parallel CRC block can be configured to process N bits per clock cycle. For example, it can be configured to process two 30-bit pixels per clock cycle. The same hardware can also be used to process less data. For example, an ROI may contain an odd number of pixels, which may result in processing a certain number of bits (e.g., 30 bits) in some cases, while typically processing another number of bits (e.g., 60 bits). In these cases, the enable is a subset of the larger case. The desired computation can be achieved by masking out the unwanted enable terms without utilizing a new decomposition of the polynomial. This is useful for other applications that process a variable number of pixels per clock cycle or have specifications with variable processing word lengths.

[0066] Additionally, aspects of the present disclosure may include real-time configurability. The flexibility of the hardware can allow it to be reconfigured to meet customer specifications, such as supporting any polynomial degree up to M, where M is the maximum size provided in the hardware. Further, the hardware can allow support for any arbitrary polynomial, support CRC, MISR, or other XOR-based signature algorithms, and support any order of bits within a pixel, e.g., the position of the mixed red / green / blue (RGB) and whether the pixel is processed least significant bit (LSB) or most significant bit (MSB) first.

[0067] The parallel CRC block can be reconfigured in real time, which can be accomplished in a certain number of clock cycles (e.g., N+M clock cycles) for decomposition. For example, to support 32-bit CRC processing at 60 bits per clock cycle, multiple clock cycles (e.g., 92 clock cycles) can be used for configuration. This can allow for multiple reconfiguration options. Aspects of the present disclosure can also include two independent security applications, where unique polynomials are used on the combination meter. One option can be to enable the decomposition and storage of two polynomials. For example, multiple ROIs (e.g., ROI A, ROI B, and / or ROI C) can belong to one security application, while another ROI (e.g., ROI D) can belong to a separate rearview camera security application.

[0068] Assuming fast decomposition, the polynomial can be decomposed by hardware on the fly. In this way, each ROI can use a unique polynomial without increasing the enable storage. In practice, this may result in the polynomial having to be decomposed multiple times while raster scanning pixels, leading to significant complexity. Many simplifications can be possible, for example, if the dashboard is configured such that the rearview camera application is at the bottom of the screen and the indicator icons are at the top of the screen, a single switch of the polynomial can be utilized.

[0069] Aspects of the present disclosure can also time-multiplex a single polynomial over different frame times. For example, during one frame time, the present disclosure can use polynomial P0 to collect the CRC signature of the ROI, and during the next frame time, the present disclosure can use polynomial P1 to collect the CRC signature of the ROI. The method selection can depend on the Fault Tolerant Time Interval (FTTI). In practice, this method may be sufficient for most applications.

[0070] Additionally, the present disclosure can include ensuring data content integrity in the absence of ECC on the display subsystem memory. This can be performed during normal system operation without entering a dedicated test mode. Aspects of the present disclosure can also provide the flexibility to support different security applications with different polynomial specifications. Furthermore, aspects of the present disclosure are capable of having a minimal die area impact on the System-on-Chip (SoC) via hardware resource sharing. Aspects of the present disclosure can also include the ability to perform in-field high-speed operation testing (i.e., concurrent online testing). Aspects of the present disclosure can also include the ability to detect permanent and intermittent faults in the display subsystem logic and memory.

[0071] Aspects of the present disclosure may include many advantages, such as increasing the claimed design coverage of a display in a cost-effective manner. This can increase customer confidence in safety applications, such as in the advanced driver assistance system (ADAS) space and the instrument cluster space. In some cases, using a display subsystem without such a mechanism for safety applications may be challenging. This can also provide more flexibility for OEMs in integrating different safety applications on the SoC. Moreover, this can allow for flexibility in polynomial selection. Additionally, this can help meet the functional safety specifications of the display subsystem as specified in the ISO 26262 functional safety standard. Further, this can help meet customer-specific ASIL compliance, e.g., as specified in the ISO 26262 functional safety standard. Additionally, aspects of the present disclosure can enhance the MISR characteristics of existing display subsystems for safety ADAS applications through targeted design changes.

[0072] In some aspects, the ability to ensure data content integrity of a secure display image, performed by a customized offline solution, may be important. Aspects of the present disclosure may utilize procedures that take a long period of time to purify their solutions from a security analysis perspective in order to drive impact. If the process utilizes a CRC mechanism to ensure data integrity, this can minimize the reconstruction of the customer database. Aspects of the present disclosure may also utilize alternative methods to the CRC mechanism to ensure data integrity, such as those that may reduce false positives from a security analysis perspective. Aspects of the present disclosure may also implement more offline security mechanisms to ensure that secure content is not visually compromised compared to bit-exact data integrity verification, which can minimize false positives that may not be visually dangerous. Additionally, aspects of the present disclosure may utilize visibility checks of secure materials when combined with non-secure materials. Aspects of the present disclosure may also enable industrial designers to have a wider range of visually appealing content to combine secure elements with non-secure elements.

[0073] Some aspects of the present disclosure may also minimize the total system bandwidth (BW) and processor utilization, which in turn can bring the KPI to a level that complies with the fault tolerance time interval (FTTI). This can eliminate the burden of certifying hardware and software (e.g., ASIL certification), which can minimize engineering costs and accelerate time to market. Aspects of the present disclosure may also bring greater flexibility and reusability to customers. In some cases, aspects of the present disclosure may allow customers to have a wide range of flexibility in the geometry of the pixels where CRC values can be collected for safety diagnostics. For customers specifying higher ASIL capabilities, aspects of the present disclosure may provide independent and redundant diagnostic paths for safety-critical content. For example, aspects of the present disclosure may implement ASIL decomposition, such as a strategy that can utilize independence and redundancy to achieve functional safety specifications.

[0074] Aspects of the present disclosure may include multiple component diagrams, e.g., diagrams including components for data processing when using CRC. For example, the diagrams of the present disclosure may include data capture components, software, hardware, memory, a display processing unit (DPU), and a display. Each of these components may communicate with each other during data processing (such as when using CRC).

[0075] Figure 9 Diagram 900 showing data processing according to one or more techniques of the present disclosure. As Figure 9 shown, diagram 900 includes multiple components for data processing. More specifically, diagram 900 includes multiple hardware blocks for configuring a specific ROI. As Figure 9 shown, block 902 includes an extraction and separation of static random access memory (SRAM). Block 902 may be connected to block 904 including a source pipeline processing block. Block 904 may be connected to block 906 including a layer mixing processing block. Block 906 may be connected to block 908 including a write-back engine. Block 908 may be connected to block 910 including user ROI configuration and block 912 including user per-pixel configuration. Finally, block 908 may be connected to block 914 where aspects of the present disclosure generate an ROI display output.

[0076] As Figure 9 shown, aspects of the present disclosure may include configurable hardware blocks that allow a user to configure a specific region of interest (ROI) in memory write-back and selected pixels that are of interest to an offline security analysis mechanism. Additionally, aspects of the present disclosure may include configurable hardware blocks that allow a user to configure a set of pixels within a configurable ROI. If the ROI is less than or equal to the full image or screen, this may effectively reduce pixel throughput.

[0077] Figure 10 Diagram 1000 showing an image according to one or more techniques of the present disclosure. As Figure 10 shown, diagram 1000 includes image 1010, and image 1010 includes a region of interest (ROI) 1020. Image 1010 includes an image width and an image height. Similarly, ROI 1020 includes an ROI width and an ROI height. Although ROI 1020 is shown in the bottom corner of image 1010, ROI 1020 may be located anywhere within image 1010. In some cases, ROI 1020 may be stored in memory or a buffer.

[0078] Figure 11 Diagram 1100 showing data processing according to one or more techniques of the present disclosure. As Figure 11As shown, Figure 1100 includes multiple steps or processes for data processing according to the present disclosure. At 1102, multiple synthetic pixels can be input from a mixer. At 1104, aspects of the present disclosure can perform ROI bypass. At 1106, aspects of the present disclosure can perform full-plane processing, such as tone mapping, color management, and / or sharpening processing. At 1108, aspects of the present disclosure can determine whether a pixel is within an ROI. At 1110, aspects of the present disclosure can determine an ROI with MISR or CRC. At 1112, aspects of the present disclosure can output to a display. Figure 1100 is also a bypass mechanism that can be used with an ROI of any shape. For example, the multiplexing controlled by 1108 can select the pixels for panel processing unless the pixel is within a rectangular ROI and the pixels within the ROI are marked as secure pixels. This can allow the ROI to have a non-rectangular shape.

[0079] As Figure 11 depicted, the pixels can be on the topmost layer fed into the layer mixer. These pixels can be associated with alpha information, where the foreground alpha is set to a certain value, such as 1.0, and the background alpha is set to a certain value, such as 0. Additionally, these pixels can be fully opaque upper-layer pixels. For example, aspects of the present disclosure can define a fully opaque pipeline with a foreground alpha of 1.0 and a background alpha of 0.0. This may be the case for security icons of any shape. Additionally, aspects of the present disclosure can blend the secure content with the background. Although the present disclosure can run CRC on fully opaque pixels, the present disclosure can allow for soft blending with the background material around the edges to obtain a visually appealing result while still maintaining security. In some aspects, different pipelines (e.g., VIG / DMA pipelines) can be used to obtain different security layer icons as long as each of these areas is displayed on the topmost layer of the display at the panel location. In some aspects, the pixel output from the mixer can bypass any pixel processing to ensure that there can be no tampering with data integrity. The bypass data path can be configured with an ROI as large as or larger than the ROI configured for the write-back engine. This can also be used in conjunction with online CRC calculation.

[0080] Additionally, per-pixel alpha information can be propagated to the write-back engine and used in conjunction with online CRC calculation. For example, any alpha with a pixel value of 1.0 can be written out to memory without tampering, while all other pixels can be written as black. This introduced mechanism can allow for collecting CRC signatures on non-rectangular, arbitrarily sized secure content. Any pixels with non-opaque alpha values can be excluded from the signature generation. This can allow the OEM to smoothly blend the security icon with the background display canvas material while also having a deterministic security signature, such as an indication on a map, etc.

[0081] In some aspects, if the ROI also includes pixels that specify a security implementation, the secure display image write-back can come into play. Some aspects of the security implementation may prohibit the write-back memory from being accessible by a non-privileged processor, which may compromise the security use case as it may specify general processor access for security analysis via software algorithms. In some instances, if the pipeline is configured to be secure, the security protection bits can propagate to the write-back engine. Additionally, the write-back engine can observe each pixel, such as whether it is security-critical, secure, or both, and then decide to write back the original pixel or black out the pixel if the memory write-back is not to a protected memory. For example, if a pixel is considered security-critical and secure, the write-back engine can write back the secure pixel as it is opaque and does not lose confidentiality from a security robustness perspective. Aspects of the present disclosure can also include the ability to run security applications outside of standard memory (e.g., rather than outside of secure memory). Thus, aspects of the present disclosure can include the ability to black out secure content, i.e., including the ability to move the playback.

[0082] Additionally, aspects of the present disclosure can include the real-time configurability of writing back the ROI, writing back secure pixels, or writing back all the ROI pixels. The mapping of secure pixels within the ROI can also be real-time configurable as it can be a function of the alpha channel of that particular pixel and the z-order of that particular secure image at the top. In some cases, these configurations can be double-buffered and / or programmable on a per-frame basis. Aspects of the present disclosure can also achieve certain hardware architecture metrics via improved design coverage, e.g., according to the ISO 26262 functional safety standard, such as the single-point fault metric (SPFM) and the latent point fault metric (LPFM). Aspects of the present disclosure can also allow customers to utilize offline security mechanisms to ensure visual security and minimize false alarms when it is not visually dangerous. Aspects of the present disclosure can also allow customers to have a wider array visually, which can attract a combination of content of security elements and non-security elements.

[0083] Figure 12 A communication flowchart 1200 of data processing according to one or more techniques of the present disclosure is shown. As Figure 12 shown, FIG. 1200 includes a data capture component 1202, a DPU 1204, a memory 1206, and a display 1208.

[0084] At 1210, the DPU 1204 can receive data including a plurality of data bits, such as data 1212, which is associated with at least one data source. As Figure 12As shown, data capture component 1202 can send data 1212 to DPU 1204. In some aspects, at least one data source can correspond to a region of interest (ROI), such as ROI 1020.

[0085] At 1220, DPU 1204 can determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI) (e.g., ROI 1020).

[0086] In some aspects, the priority data can be security data. The security data can be displayed on top of a display (e.g., display 1208), where the security data can be displayed as one or more security pixels, and where the ROI (e.g., ROI 1020) can be part of the display (e.g., display 1208). One or more security pixels can correspond to one or more opaque pixels. Additionally, each of the one or more security pixels can be associated with alpha information that includes at least one of a foreground alpha value or a background alpha value.

[0087] At 1230, when at least a portion of the data corresponds to priority data, DPU 1204 can detect an amount of adjustment of the received data (e.g., data 1212), where the data can be displayed or stored based on the detected amount of adjustment. In some cases, the amount of adjustment can be detected based on at least one detection algorithm that corresponds to at least one cyclic redundancy check (CRC) (e.g., the CRC at step 1110 in Figure 11 ). Additionally, at least one CRC can include at least one polynomial that is programmable or configurable. The amount of adjustment can be detected based on at least one detection algorithm. The amount of adjustment can also be detected by a display processing unit (DPU) (e.g., DPU 1204). Additionally, the amount of adjustment can be detected based on at least one detection algorithm that corresponds to at least one multiple input signature register (MISR) (e.g., the MISR at step 1110 in Figure 11 ) or at least one exclusive or (XOR) algorithm.

[0088] At 1240, DPU 1204 can generate a data signature for the received data (e.g., data 1212) based on the amount of adjustment of the received data. The data signature of the received data can be compared with the data signature of the processed data. Additionally, the data signature of the received data can be a cyclic redundancy check (CRC) signature.

[0089] At 1250, the DPU 1204 may determine whether the adjustment amount is less than or equal to a data adjustment threshold. In some aspects, when the adjustment amount is less than or equal to the data adjustment threshold, data (e.g., data 1212) may be displayed, where the data may be displayed at a display (e.g., display 1208). Additionally, when the adjustment amount is greater than the data adjustment threshold, data (e.g., data 1212) may be stored, where the data may be stored in at least one of a memory or a buffer (e.g., memory 1206).

[0090] At 1260, the DPU 1204 may communicate data, such as data 1262, based on the detected adjustment amount. For example, data (e.g., data 1262) may be communicated to be stored (e.g., stored at memory 1206) or displayed (e.g., displayed at display 1208).

[0091] Figure 13 Example flowchart 1000 illustrating an example method in accordance with one or more techniques of the present invention. The method may be performed by a device (e.g., a DPU, GPU, CPU, synthesizer, frame processor, display processor, data processor, or a device for data processing).

[0092] At 1302, the device may receive data including a plurality of data bits, the data being associated with at least one data source, as described in the examples in conjunction with Figures 3 - 12 In some aspects, at least one data source may correspond to a region of interest (ROI), as described in the examples in conjunction with Figures 3 - 12 the examples in

[0093] At 1304, the device may determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI), as described in the examples in conjunction with Figures 3 - 12 the examples in

[0094] In some aspects, the priority data may be security data, as described in the examples in conjunction with Figures 3 - 12 the examples in. The security data may be displayed on top of a display, where the security data may be displayed as one or more security pixels, where the ROI may be a portion of the display, as described in the examples in conjunction with Figures 3 - 12 the examples in. One or more security pixels may correspond to one or more opaque pixels, as described in the examples in conjunction with Figures 3 - 12 the examples in. Additionally, each of the one or more security pixels may be associated with alpha information including at least one of a foreground alpha value or a background alpha value, as described in the examples in conjunction with Figures 3 - 12 the examples in

[0095] At 1306, when at least a portion of the data corresponds to priority data, the apparatus may detect an amount of adjustment of the received data and display or store the data based on the detected amount of adjustment, as described in the example in conjunction with Figures 3 - 12 In some cases, the amount of adjustment may be detected based on at least one detection algorithm, where the at least one detection algorithm corresponds to at least one cyclic redundancy check (CRC), as described in the example in conjunction with Figures 3 - 12 In addition, the at least one CRC may include at least one polynomial, where the at least one polynomial is programmable or configurable, as described in the example in conjunction with Figures 3 - 12 The amount of adjustment may be detected based on at least one detection algorithm, as described in the example in conjunction with Figures 3 - 12 The amount of adjustment may also be detected by a display processing unit (DPU), as described in the example in conjunction with Figures 3 - 12 In addition, the amount of adjustment may be detected based on at least one detection algorithm, where the at least one detection algorithm corresponds to at least one multiple input signature register (MISR) or at least one exclusive OR (XOR) algorithm, as described in the example in conjunction with Figures 3 - 12

[0096] At 1308, the apparatus may generate a data signature of the received data based on the amount of adjustment of the received data, as described in the example in conjunction with Figures 3 - 12 The data signature of the received data may be compared with the data signature of the processed data, as described in the example in conjunction with Figures 3 - 12 In addition, the data signature of the received data may be a cyclic redundancy check (CRC) signature, as described in the example in conjunction with Figures 3 - 12

[0097] At 1310, the apparatus may determine whether the amount of adjustment is less than or equal to a data adjustment threshold, as described in the example in conjunction with Figures 3 - 12 In some aspects, when the amount of adjustment is less than or equal to the data adjustment threshold, the data may be displayed, and the data is displayed at a display, as described in the example in conjunction with Figures 3 - 12 In addition, when the amount of adjustment is greater than the data adjustment threshold, the data may be stored, and the data is stored in at least one of a memory or a buffer, as described in the example in conjunction with Figures 3 - 12

[0098] At 1312, the apparatus may communicate the data based on the detected amount of adjustment. For example, the data may be communicated for storage or display, as described in the example in conjunction with Figures 3 - 12

[0099] ​​​​In one configuration, a method or apparatus for graphics processing is provided. The apparatus can be a DPU, GPU, CPU, synthesizer, frame synthesizer, frame processor, display processor, data processor, or an apparatus for data processing. In one aspect, the apparatus can be the processing unit 120 within the device 104, or can be some other hardware within the device 104 or another device. The apparatus can include: components for receiving data including a plurality of data bits, the data being associated with at least one data source. The apparatus can further include: components for determining whether at least a portion of the data corresponds to priority data within a region of interest (ROI). The apparatus can further include: components for detecting an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount. The apparatus can further include: components for determining whether the adjustment amount is less than or equal to a data adjustment threshold. The apparatus can further include: components for communicating the data based on the detected adjustment amount. The apparatus can further include: components for generating a data signature of the received data based on the adjustment amount of the received data.

[0100] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described display processing techniques can be used by a DPU, GPU, CPU, synthesizer, frame synthesizer, frame processor, display processor, or other data processor to implement the above methods and processes. This can also be implemented at low cost compared to other data and frame processing techniques. Additionally, the data processing techniques herein can improve or accelerate data processing or execution. Further, the data processing techniques herein can increase the data utilization and / or resource efficiency of a DPU or GPU. Additionally, the data processing techniques herein can include methods that can improve the reliability of data transmission and / or the integrity of data content.

[0101] According to the present disclosure, unless the context dictates otherwise, the term "or" can be interpreted as "and / or". Additionally, although phrases such as "one or more" or "at least one" may have been used for some features disclosed herein and not for others, features for which such language is not used can be interpreted to have such an implied meaning unless the context dictates otherwise.

[0102] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" has been used throughout this disclosure, such a processing unit can be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module can be stored on or transmitted via a computer-readable medium as one or more instructions or code. A computer-readable medium can include a computer data storage medium or a communication medium, where the communication medium includes any medium that facilitates communication of a computer program from one place to another. In this way, a computer-readable medium generally can correspond to: (1) a tangible computer-readable storage medium that is non-transitory; or (2) a communication medium such as a signal or a carrier wave. A data storage medium can be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage, or other magnetic storage devices. As used herein, disk and optical disks include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks utilize lasers to optically reproduce data. Combinations of the foregoing should also be included within the scope of computer-readable media. A computer program product can include a computer-readable medium.

[0103] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, as used herein, the term "processor" can refer to any one of the foregoing structures or any other structure suitable for implementing the techniques described herein. Additionally, the techniques can be fully implemented in one or more circuits or logic elements.

[0104] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of the devices configured to perform the disclosed techniques, but they do not necessarily need to be implemented by different hardware units. Rather, as described above, the various units may be combined in any hardware unit or provided by a batch of interoperable hardware units (including one or more processors as described above) in combination with suitable software and / or firmware.

[0105] Various examples have been described. These examples and other examples are within the scope of the appended claims. The following aspects are merely illustrative and may be combined with other aspects or teachings described herein, without limitation thereto.

[0106] Aspect 1 is a data processing method. The method includes: receiving data including a plurality of data bits, the data being associated with at least one data source. The method further includes: determining whether at least a portion of the data corresponds to priority data within a region of interest (ROI). The method further includes: detecting an adjustment amount of the received data when at least a portion of the data corresponds to priority data, and the data is displayed or stored based on the detected adjustment amount.

[0107] Aspect 2 is the method according to aspect 1, wherein the priority data is security data.

[0108] Aspect 3 is the method according to any one of aspects 1 and 2, wherein the security data is displayed on an upper layer of a display, the security data is displayed as one or more security pixels, and the ROI is a part of the display.

[0109] Aspect 4 is the method according to any one of aspects 1 to 3, wherein the one or more security pixels correspond to one or more opaque pixels.

[0110] Aspect 5 is the method according to any one of aspects 1 to 4, wherein each of the one or more security pixels is associated with alpha information, and the alpha information includes at least one of a foreground alpha value or a background alpha value.

[0111] Aspect 6 is the method according to any one of aspects 1 to 5, wherein the adjustment amount is detected based on at least one detection algorithm, and the at least one detection algorithm corresponds to at least one cyclic redundancy check (CRC).

[0112] Aspect 7 is the method according to any one of aspects 1 to 6, wherein the at least one CRC includes at least one polynomial, and the at least one polynomial is programmable or configurable.

[0113] Aspect 8 is the method according to any one of Aspects 1 to 7, further comprising: determining whether the adjustment amount is less than or equal to a data adjustment threshold.

[0114] Aspect 9 is the method according to any one of Aspects 1 to 8, wherein when the adjustment amount is less than or equal to the data adjustment threshold, the data is displayed, and the data is displayed at a display.

[0115] Aspect 10 is the method according to any one of Aspects 1 to 9, wherein when the adjustment amount is greater than the data adjustment threshold, the data is stored, and the data is stored in at least one of a memory or a buffer.

[0116] Aspect 11 is the method according to any one of Aspects 1 to 10, wherein the adjustment amount is detected based on at least one detection algorithm.

[0117] Aspect 12 is the method according to any one of Aspects 1 to 11, further comprising: communicating data based on the detected adjustment amount.

[0118] Aspect 13 is the method according to any one of Aspects 1 to 12, further comprising: generating a data signature of the received data based on the adjustment amount of the received data.

[0119] Aspect 14 is the method according to any one of Aspects 1 to 13, wherein the data signature of the received data is compared with the data signature of the processed data.

[0120] Aspect 15 is the method according to any one of Aspects 1 to 14, wherein the data signature of the received data is a cyclic redundancy check (CRC) signature.

[0121] Aspect 16 is the method according to any one of Aspects 1 to 15, wherein at least one data source corresponds to a region of interest (ROI).

[0122] Aspect 17 is the method according to any one of Aspects 1 to 16, wherein the adjustment amount is detected by a display processing unit (DPU).

[0123] Aspect 18 is the method according to any one of Aspects 1 to 17, wherein the adjustment amount is detected based on at least one detection algorithm, and the at least one detection algorithm corresponds to at least one multi-input signature register (MISR) or at least one exclusive OR (XOR) algorithm.

[0124] Aspect 19 is a device for data processing, comprising components for implementing the method according to any one of Aspects 1 to 18.

[0125] Aspect 20 is a device for data processing, comprising at least one processor coupled to a memory and configured to implement the method according to any one of Aspects 1 to 18.

[0126] Aspect 21 is a computer-readable medium storing computer-executable code which, when executed by a processor, causes the processor to implement the method according to any one of aspects 1 to 18.

Claims

1. A data processing method, comprising: Receiving data including a plurality of data bits, the data being associated with at least one data source; Determining whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI); When the at least a portion of the data corresponds to the priority data, detecting an adjustment amount of the received data, the data being displayed or stored based on the detected adjustment amount; And Determining whether the adjustment amount of the received data is less than or equal to a data adjustment threshold, wherein when the adjustment amount is less than or equal to the data adjustment threshold, the data is displayed, or when the adjustment amount is greater than the data adjustment threshold, the data is stored.

2. The method according to claim 1, wherein The priority data is security data.

3. The method according to claim 2, wherein, The security data is displayed on an upper layer of a display, the security data being displayed as one or more security pixels, and the ROI being a part of the display.

4. The method according to claim 3, wherein The one or more security pixels correspond to one or more opaque pixels.

5. The method according to claim 3, wherein Each of the one or more security pixels is associated with alpha information, the alpha information including at least one of a foreground alpha value or a background alpha value.

6. The method according to claim 1, wherein, Detecting the adjustment amount based on at least one detection algorithm, the at least one detection algorithm corresponding to at least one cyclic redundancy check (CRC).

7. The method according to claim 6, wherein, The at least one CRC includes at least one polynomial, the at least one polynomial being programmable or configurable.

8. The method according to claim 1, wherein, The data is displayed at a display.

9. The method according to claim 1, wherein, The data is stored in at least one of a memory or a buffer.

10. The method according to claim 1, wherein Detecting the adjustment amount based on at least one detection algorithm.

11. The method according to claim 1, further comprising: Communicating the data based on the detected adjustment amount.

12. The method according to claim 1, further comprising: Generating a data signature of the received data based on the adjustment amount of the received data.

13. The method according to claim 12, wherein, Comparing the data signature of the received data with the data signature of the processed data.

14. The method according to claim 12, wherein, The data signature of the received data is a cyclic redundancy check (CRC) signature.

15. The method according to claim 1, wherein The at least one data source corresponds to the ROI.

16. The method according to claim 1, wherein Detecting the adjustment amount by a display processing unit (DPU).

17. The method according to claim 1, wherein, Detecting the adjustment amount based on at least one detection algorithm, the at least one detection algorithm corresponding to at least one multi-input signature register (MISR) or at least one exclusive OR (XOR) algorithm.

18. An apparatus for data processing, comprising: A memory; And At least one processor coupled to the memory and configured to: Receive data including a plurality of data bits, the data being associated with at least one data source; Determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI); When the at least a portion of the data corresponds to the priority data, detect an adjustment amount of the received data, the data being displayed or stored based on the detected adjustment amount; And Determine whether the adjustment amount of the received data is less than or equal to a data adjustment threshold, wherein when the adjustment amount is less than or equal to the data adjustment threshold, the data is displayed, or when the adjustment amount is greater than the data adjustment threshold, the data is stored.

19. The apparatus according to claim 18, wherein, The priority data is security data.

20. The apparatus according to claim 19, wherein, The security data is displayed on the upper layer of the display, the security data is displayed as one or more security pixels, and the ROI is a part of the display.

21. The apparatus according to claim 20, wherein, The one or more security pixels correspond to one or more opaque pixels.

22. The apparatus according to claim 20, wherein, Each of the one or more security pixels is associated with alpha information, and the alpha information includes at least one of a foreground alpha value or a background alpha value.

23. The apparatus according to claim 18, wherein, Detect the adjustment amount based on at least one detection algorithm, and the at least one detection algorithm corresponds to at least one cyclic redundancy check CRC.

24. The device according to claim 23, wherein, The at least one CRC includes at least one polynomial, and the at least one polynomial is programmable or configurable.

25. The apparatus according to claim 18, wherein, The data is displayed at the display.

26. The device according to claim 18, wherein The data is stored in at least one of a memory or a buffer.

27. The apparatus according to claim 18, wherein, Detect the adjustment amount based on at least one detection algorithm.

28. The device according to claim 18, wherein, The at least one processor is further configured to: Communicate the data based on the detected adjustment amount.

29. The device according to claim 18, wherein, The at least one processor is further configured to: Generate a data signature of the received data based on the adjustment amount of the received data.

30. The apparatus according to claim 29, wherein, Compare the data signature of the received data with the data signature of the processed data.

31. The device according to claim 29, wherein, The data signature of the received data is a cyclic redundancy check CRC signature.

32. The apparatus according to claim 18, wherein The at least one data source corresponds to the ROI.

33. The apparatus according to claim 18, wherein, The adjustment amount is detected by a display processing unit DPU.

34. The apparatus according to claim 18, wherein, Detect the adjustment amount based on at least one detection algorithm, and the at least one detection algorithm corresponds to at least one multi-input signature register MISR or at least one exclusive OR XOR algorithm.

35. A device for data processing, comprising: Components for receiving data including a plurality of data bits, the data being associated with at least one data source; Components for determining whether at least a part of the data corresponds to priority data, the priority data being within a region of interest ROI; Components for detecting an adjustment amount of the received data when at least a part of the data corresponds to the priority data, and the data is displayed or stored based on the detected adjustment amount; And Components for determining whether the adjustment amount is less than or equal to a data adjustment threshold, wherein when the adjustment amount is less than or equal to the data adjustment threshold, the data is displayed, or when the adjustment amount is greater than the data adjustment threshold, the data is stored.

36. The device according to claim 35, further comprising: Components for communicating the data based on the detected adjustment amount.

37. The device according to claim 35, further comprising: Components for generating a data signature of the received data based on the adjustment amount of the received data.

38. A non-transitory computer-readable medium storing computer-executable code for data processing, and the code, when executed by a processor, causes the processor to: Receive data including a plurality of data bits, the data being associated with at least one data source; Determine whether at least a portion of the data corresponds to priority data within a region of interest (ROI); When at least the portion of the data corresponds to the priority data, detect an adjustment amount of the received data, and the data is displayed or stored based on the detected adjustment amount; And Determine whether the adjustment amount of the received data is less than or equal to a data adjustment threshold, wherein when the adjustment amount is less than or equal to the data adjustment threshold, the data is displayed, or when the adjustment amount is greater than the data adjustment threshold, the data is stored.

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