Display panel and display device

Abstract

Display panels and display devices, relating to the field of display technology. The display panel has multiple sub-pixels (20) on a substrate (10). Each sub-pixel (20) includes a compensation transistor (T1), a driving transistor (T2), a storage capacitor (Cst), and a first initialization signal line (252). The first active pattern (211) of the compensation transistor (T1) includes a first active part (2111), a second active part (2112), and a third active part (2113) connected in sequence. The second active part (2112) extends along a first direction, and the extension directions of the first active part (2111) and the third active part (2113) intersect with the first direction. The first initialization signal line (252) extends along the first direction, and the orthographic projection of the first initialization signal line (252) on the substrate (10) overlaps with the orthographic projection of the second active part (2112) on the substrate (10). The first initialization signal line (252) and the first active pattern (211) directly overlap to form a coupling capacitor.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, people have higher and higher requirements for display devices. While pursuing a larger and higher resolution visual experience, people also pay attention to issues such as the stability and uniformity of display brightness during display.

[0003] Overview

[0004] This disclosure provides the following technical solutions through some embodiments:

[0005] In a first aspect, a display panel is provided, comprising: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a compensation transistor, a driving transistor, a storage capacitor and a first initialization signal line; a first electrode of the compensation transistor is connected to a second electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the gate of the driving transistor and a first plate of the storage capacitor, respectively.

[0006] The first active pattern of the compensation transistor includes a first active portion, a second active portion and a third active portion connected in sequence. The second active portion extends along a first direction, and the extension directions of the first active portion and the third active portion both intersect with the first direction.

[0007] The first initialization signal line extends along the first direction, and the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the second active part on the substrate.

[0008] Secondly, a display device is provided, including the aforementioned display panel.

[0009] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are listed below. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram illustrating the structure of a display panel in the related art is shown.

[0012] Figure 2 A schematic diagram of the structure of a display panel according to an embodiment of this application is shown.

[0013] Figure 3 schematically shown Figure 2 The diagram shows a sectional view of the display panel along section A-A'.

[0014] Figure 4 A schematic diagram of the structure of the active layer in the display panel of an embodiment of this application is shown.

[0015] Figure 5 A schematic diagram illustrating the structure of the active layer and the first gate layer in a display panel according to an embodiment of this application is shown.

[0016] Figure 6 The schematic diagram illustrates the structure of the active layer, the first gate layer, and the second gate layer in the display panel of an embodiment of this application.

[0017] Figure 7 The schematic diagram illustrates the structure of the active layer, the first gate layer, the second gate layer, and the through-holes in the display panel of an embodiment of this application.

[0018] Figure 8 A schematic diagram of the source / drain electrode layer in a display panel according to an embodiment of this application is shown.

[0019] Figure 9 The equivalent circuit diagram corresponding to each sub-pixel in the display panel of the present application embodiment is shown schematically.

[0020] Figure 10 schematically shown Figure 9 The circuit shown corresponds to the driving timing diagram. Specific Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In related technologies, such as Figure 1As shown, each sub-pixel in the display panel includes a compensation transistor T1, a first initialization signal line 12, a second initialization signal line 13, a reset signal line 14, a gate line 15, a light emission control signal line 16, a first power supply signal line 17, and a data line 18. The active pattern of the compensation transistor T1 includes a first active portion arranged along the row direction and a second active portion arranged along the column direction, i.e., the active pattern of the compensation transistor T1 is distributed in an "L" shape. A connection portion 11 is also provided on the same layer as the second gate layer where the first initialization signal line 12 is located. The first power supply signal line 17 is connected to the connection portion 11 through a via penetrating the interlayer dielectric layer. The corner positions of the first and second active portions of the compensation transistor T1 overlap with the connection portion 11 to form a coupling capacitor.

[0023] However, since an additional connection portion 11 needs to be provided on the second gate layer to connect to the first power signal line 17, so that the connection portion 11 and the active pattern of the compensation transistor T1 overlap to form a coupling capacitor, the circuit space layout of each sub-pixel will be more complex, resulting in a larger space occupied by the circuit layout of each sub-pixel, thus reducing the aperture ratio of each sub-pixel.

[0024] In this embodiment, the first active pattern of the compensation transistor is changed so that the first active pattern includes a first active part, a second active part, and a third active part connected in sequence. The second active part extends along the first direction, and the extension directions of the first active part and the third active part intersect with the first direction. The orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second active part on the substrate have an overlapping area. The coupling capacitor is directly formed by the overlap of the first initialization signal line and the first active pattern of the compensation transistor. At this time, there is no need to set the connection part 11. By optimizing the circuit design of the sub-pixel, the circuit space arrangement of each sub-pixel is simpler. Correspondingly, the space occupied by the circuit arrangement of each sub-pixel is saved, thereby improving the aperture ratio of each sub-pixel.

[0025] Reference Figure 2 This diagram illustrates a structural schematic of a display panel according to an embodiment of this application. Figure 3 It shows Figure 2 The diagram shows a sectional view of the display panel along section A-A'. Figure 4 A schematic diagram of the structure of the active layer in the display panel of an embodiment of this application is shown.

[0026] This application discloses a display panel, including: a substrate 10 and a plurality of sub-pixels 20 disposed on the substrate 10. Each sub-pixel 20 includes: a compensation transistor T1, a driving transistor T2, a storage capacitor Cst and a first initialization signal line 252. The first terminal of the compensation transistor T1 is connected to the second terminal of the driving transistor T2, and the second terminal of the compensation transistor T1 is connected to the gate of the driving transistor T2 and the first plate of the storage capacitor Cst, respectively.

[0027] The first active pattern 211 of the compensation transistor T1 includes a first active portion 2111, a second active portion 2112, and a third active portion 2113 connected in sequence. The second active portion 2112 extends along a first direction, and the extension directions of the first active portion 2111 and the third active portion 2113 both intersect with the first direction. The first initialization signal line 252 extends along the first direction, and the orthographic projection of the first initialization signal line 252 on the substrate 10 overlaps with the orthographic projection of the second active portion 2112 on the substrate 10.

[0028] In actual products, the substrate 10 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a PI (Polyimide) substrate. Multiple sub-pixels 20 are distributed on the substrate 10, and each sub-pixel 20 is arranged in an array.

[0029] Each sub-pixel 20 includes a compensation transistor T1, a driving transistor T2, and a storage capacitor Cst. The driving transistor T2 is the transistor that drives the light-emitting device to emit light; the compensation transistor T1 is the transistor that compensates for the threshold voltage of the driving transistor T2. The compensation transistor T1 is connected between the gate and the second terminal of the driving transistor T2. The compensation transistor T1 is a dual-gate transistor to reduce the leakage current of the compensation transistor T1, thereby improving the stability of the gate voltage of the driving transistor T2; and the first plate of the storage capacitor Cst is connected to the gate of the driving transistor T2 and the second terminal of the compensation transistor T1 to store the written voltage. During the process of the driving transistor T2 driving the light-emitting device to emit light, the driving transistor T2 is kept in the conducting state by discharging.

[0030] like Figure 4 As shown, the first active pattern 211 of the compensation transistor T1 includes a first active portion 2111, a second active portion 2112 and a third active portion 2113 connected in sequence. The second active portion 2112 extends along a first direction, and the extension directions of the first active portion 2111 and the third active portion 2113 both intersect with the first direction, so that the first active pattern 211 is distributed in a "U" shape.

[0031] Furthermore, the first initialization signal line 252 extends along the first direction, that is, the first initialization signal line 252 is parallel to the second active part 2112 in the first active pattern 211. The first direction actually refers to the row direction of the display panel. The orthographic projection of the first initialization signal line 252 on the substrate 10 and the orthographic projection of the second active part 2112 on the substrate 10 have an overlapping area, so that the first initialization signal line 252 and the second active part 2112 in the first active pattern 211 overlap to form a coupling capacitor.

[0032] By changing the first active pattern 211 of the compensation transistor T1, the first active pattern 211 includes a first active part 2111, a second active part 2112 and a third active part 2113 connected in sequence, and directly forms a coupling capacitor by overlapping with the first active pattern 211 of the compensation transistor T1 through the first initialization signal line 252. At this time, there is no need to set up an additional connection part 11. By optimizing the circuit design of the sub-pixel 20, the circuit space arrangement of each sub-pixel 20 is simpler, and correspondingly, the space occupied by the circuit arrangement of each sub-pixel 20 is saved, thereby improving the aperture ratio of each sub-pixel 20.

[0033] Optionally, the orthographic projection of the first initialization signal line 252 on the substrate 10 covers the orthographic projection of the second active part 2112 on the substrate 10.

[0034] exist Figure 1 In the related technology shown, the corner positions of the first and second active portions of the compensation transistor T1 overlap with the connecting portion 11, resulting in a small overlap area between the active pattern of the compensation transistor T1 and the connecting portion 11, and consequently, a small capacitance value of the resulting coupling capacitor. When the capacitance value of the coupling capacitor is small, at low refresh rates, the voltage of the active pattern of the compensation transistor T1 cannot be stabilized for a long time, causing the voltage supplied by the storage capacitor to the driving transistor to be unstable, thereby resulting in poor stability and uniformity of the luminous intensity of each sub-pixel.

[0035] In this embodiment, when the orthographic projection of the first initialization signal line 252 on the substrate 10 overlaps the orthographic projection of the second active portion 2112 on the substrate 10, the overlap area between the first initialization signal line 252 and the first active pattern 211 of the compensation transistor T1 increases, resulting in a larger capacitance value of the coupling capacitor. Since the voltage of the first initialization signal input to the first initialization signal line 252 is constant and always the first initialization voltage, the voltage on the first active pattern 211 is also constant. The voltage on the first active pattern 211 is not affected by the signal jumps in the display panel. At low refresh rates, the duration of each frame is long. When the capacitance value of the coupling capacitor formed by the first initialization signal line 252 and the first active pattern 211 of the compensation transistor T1 is large, the voltage of the first active pattern 211 of the compensation transistor T1 can be stably maintained over a long period of time. This makes the voltage provided by the storage capacitor Cst to the driving transistor T2 more stable, thereby improving the stability and uniformity of the luminous brightness of each sub-pixel 20.

[0036] Of course, the display panel of this application embodiment can also be applied to high refresh rate scenarios. At high refresh rates, the stability and uniformity of the light emission brightness of each sub-pixel 20 can also be improved.

[0037] In some embodiments, the first initialization signal line 252 overlaps only with the second active portion 2112 to form a coupling capacitor, while the first initialization signal line 252 does not overlap with the first active portion 2111 and the third active portion 2113. That is, the orthographic projection of the first initialization signal line 252 on the substrate 10 only overlaps with the orthographic projection of the second active portion 2112 on the substrate 10. In this case, along the second direction, the width of the first initialization signal line 252 is less than or equal to the width of the second active portion 2112.

[0038] It should be noted that when the orthographic projection of the first initialization signal line 252 on the substrate 10 only covers the orthographic projection of the second active part 2112 on the substrate 10, the width of the first initialization signal line 252 is equal to the width of the second active part 2112; while when the orthographic projection of the first initialization signal line 252 on the substrate 10 only overlaps with a portion of the orthographic projection of the second active part 2112 on the substrate 10, the width of the first initialization signal line 252 is less than the width of the second active part 2112.

[0039] In some other embodiments, the orthographic projection of the first initialization signal line 252 on the substrate 10 also overlaps with the orthographic projections of the first active portion 2111 and the third active portion 2113 on the substrate 10.

[0040] Optionally, in addition to overlapping with the second active portion 2112, the first initialization signal line 252 also overlaps with a portion of the first active portion 2111 and a portion of the third active portion 2113. This increases the overlap area between the first initialization signal line 252 and the first active pattern 211 of the compensation transistor T1, thereby increasing the capacitance value of the formed coupling capacitor and further improving the stability and uniformity of the light emission brightness of each sub-pixel 20. In this case, along the second direction, the width of the first initialization signal line 252 is greater than the width of the second active portion 2112.

[0041] In one optional embodiment of this application, such as Figure 4 As shown, the extension directions of the first active part 2111 and the third active part 2113 are parallel to each other.

[0042] The first direction is the row direction of the display panel, and the extension directions of the first active part 2111 and the third active part 2113 are both the second direction, which intersects with the first direction.

[0043] Specifically, the second direction can be perpendicular to the first direction. In this case, the second direction is the column direction of the display panel. The first active part 2111 and the third active part 2113 both extend along the column direction of the display panel. At this time, the position where the first active part 2111 and the second active part 2112 meet is at a right angle, and the position where the third active part 2113 and the second active part 2112 meet is also at a right angle. Furthermore, the first active part 2111 and the third active part 2113 are both located on the same side of the second active part 2112.

[0044] It should be noted that the second direction is perpendicular to the first direction, which can be understood as the angle between the second direction and the first direction being within a preset angle range, such as a preset angle range of 85° to 95°, or optionally, a preset angle range of 90°.

[0045] Of course, the second direction may not be perpendicular to the first direction. In this case, the angle between the second direction and the first direction is greater than the first preset angle or less than the second preset angle. For example, the first preset angle is 95° and the second preset angle is 85°.

[0046] In addition, the third active portion 2113 also has a third protrusion on the side opposite to the first active portion 2111. This third protrusion facilitates the connection of the third connection portion provided on the source / drain electrode layer to the third active portion 2113 in the first active pattern 211 through a seventh via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24 and the first gate insulating layer 22.

[0047] In another optional embodiment of this application, the extension direction of the first active part 2111 is a third direction, and the extension direction of the third active part 2113 is a fourth direction, and the third direction and the fourth direction intersect.

[0048] Wherein, the extension direction of the second active part 2112 is the first direction, which is the row direction of the display panel. The extension direction of the first active part 2111 is not parallel to the extension direction of the third active part 2113, and the extension directions of the first active part 2111 and the third active part 2113 both intersect with the first direction. At this time, the position where the first active part 2111 and the second active part 2112 meet is an acute angle or an obtuse angle, and the position where the third active part 2113 and the second active part 2112 meet is also an acute angle or an obtuse angle.

[0049] For example, at the position where the first active part 2111 and the second active part 2112 are connected, the included angle between the first active part 2111 and the second active part 2112 is 100°, and at the position where the third active part 2113 and the second active part 2112 are connected, the included angle between the third active part 2113 and the second active part 2112 is also 100°.

[0050] In this embodiment, each sub-pixel 20 further includes a gate line 232, a reset signal line 231, a second initialization signal line 251, a light emission control signal line 233, a first power supply signal line 271, and a data line 272; the gate line 232, the reset signal line 231, the second initialization signal line 251, and the light emission control signal line 233 all extend along a first direction, and the first power supply signal line 271 and the data line 272 all extend along a second direction, and the second direction intersects with the first direction.

[0051] The second direction can be perpendicular to the first direction. In this case, the first direction is the row direction of the display panel, and the second direction is the column direction of the display panel. The gate line 232, the reset signal line 231, the second initialization signal line 251, and the light emission control signal line 233 all extend along the row direction, and the orthographic projections of the first initialization signal line 252, the gate line 232, the reset signal line 231, the second initialization signal line 251, and the light emission control signal line 233 on the substrate 10 do not overlap. The first power signal line 271 and the data line 272 both extend along the column direction, and the orthographic projections of the first power signal line 271 and the data line 272 on the substrate 10 also do not overlap.

[0052] It should be noted that the second direction is perpendicular to the first direction, which can be understood as the angle between the second direction and the first direction being within a preset angle range, such as a preset angle range of 85° to 95°.

[0053] like Figure 2As shown, in each sub-pixel 20, the reset signal line 231 is located between the first initialization signal line 252 and the second initialization signal line 251, the first initialization signal line 252 is located between the reset signal line 231 and the gate line 232, and the gate line 232 is located between the first initialization signal line 252 and the light emission control signal line 233.

[0054] The first initialization signal line 252 and the second initialization signal line 251 in each sub-pixel 20 are arranged separately and separated by a reset signal line 231, so that the first initialization signal line 252 can more easily overlap with the first active pattern 211 of the compensation transistor T1 to form a coupling capacitor.

[0055] In the actual product, the gate of the compensation transistor T1 is controlled by the gate line 232, and the gate of the compensation transistor T1 is the part of the gate line 232 that overlaps with the first active part 2111 and the third active part 2113.

[0056] In this case, the gate line 232 can be directly used as the gate of the compensation transistor T1, making the circuit layout of the sub-pixel 20 simpler; of course, the gate of the compensation transistor T1 can also be set separately and connected to the gate line 232.

[0057] Furthermore, at the location where the first active portion 2111 and the second active portion 2112 meet, the first initialization signal line 252 has a first protrusion toward the gate line 232 and a second protrusion away from the gate line 232; and, at other locations except the location where the first active portion 2111 and the second active portion 2112 meet, the width of the first initialization signal line 252 along the second direction is equal.

[0058] Since the first initialization signal line 252 is also connected to the first electrode of the second reset transistor T7, in order to facilitate the connection of the second connection portion 274 provided on the source-drain electrode layer to the first initialization signal line 252 through the sixth via penetrating the interlayer dielectric layer 26, so as to realize the connection of the first initialization signal line 252 to the first electrode of the second reset transistor T7 at the position where the first active portion 2111 and the second active portion 2112 are connected, the first initialization signal line 252 needs to be configured to have a first protrusion facing the gate line 232 and a second protrusion away from the gate line 232; while other positions of the first initialization signal line 252 do not need to be connected to other structures, so the width of the first initialization signal line 252 along the column direction is set to be equal at other positions except the position where the first active portion 2111 and the second active portion 2112 are connected.

[0059] like Figure 2As shown, each sub-pixel 20 also includes a first reset transistor T3; the gate of the first reset transistor T3 is controlled by a reset signal line 231, the first terminal of the first reset transistor T3 is connected to the second initialization signal line 251, and the second terminal of the first reset transistor T3 is connected to the second terminal of the compensation transistor T1.

[0060] At this time, the second terminal of the first reset transistor T3 is also connected to the first plate of the storage capacitor Cst and the gate of the driving transistor T2. The first reset transistor T3 is used to turn on under the control of the reset signal input by the reset signal line 231, and transmit the second initialization signal provided by the second initialization signal line 251 to the first plate of the storage capacitor Cst and the gate of the driving transistor T2, so as to reset the storage capacitor Cst and the gate of the driving transistor T2.

[0061] Among them, the first reset crystal T3 is a dual-gate transistor; as Figure 4 As shown, the second active pattern 213 of the first reset transistor T3 includes a fourth active portion 2131, a fifth active portion 2132, and a sixth active portion 2133 connected in sequence. The fifth active portion 2132 extends along a first direction, and the extension directions of the fourth active portion 2131 and the sixth active portion 2133 both intersect with the first direction. The gate of the first reset transistor T3 is the portion of the reset signal line 231 that overlaps with the fourth active portion 2131 and the sixth active portion 2133.

[0062] When the first reset crystal T3 is a dual-gate transistor, the leakage current of the first reset crystal T3 can be reduced, thereby improving the stability of the gate voltage of the driving transistor T2.

[0063] Furthermore, the second active pattern 213 of the first reset transistor T3 includes a fourth active portion 2131, a fifth active portion 2132 and a sixth active portion 2133 connected in sequence. The fifth active portion 2132 extends along a first direction, which is the row direction of the display panel. The extension directions of the fourth active portion 2131 and the sixth active portion 2133 both intersect with the first direction, so that the second active pattern 213 is also distributed in a "U" shape.

[0064] Optionally, the extension directions of the fourth active portion 2131 and the sixth active portion 2133 are parallel to each other, and the extension directions of the fourth active portion 2131 and the sixth active portion 2133 are both in the column direction of the display panel, so that the position where the fourth active portion 2131 and the fifth active portion 2132 meet is at a right angle, and the position where the sixth active portion 2133 and the fifth active portion 2132 meet is also at a right angle; and the fourth active portion 2131 and the sixth active portion 2133 are both located on the side of the fifth active portion 2132 facing the first initialization signal line 252.

[0065] Specifically, the fourth active portion 2131 also has a fourth protrusion facing the first power signal line 271. The fourth protrusion facilitates the connection of the third connection portion provided on the source / drain electrode layer to the fourth active portion 2131 in the second active pattern 213 through a third via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22. The sixth active portion 2133 has a fifth protrusion facing the fourth active portion 2131 and a sixth protrusion away from the fourth active portion 2131. The fifth and sixth protrusions facilitate the connection of the first connection portion provided on the source / drain electrode layer to the sixth active portion 2133 in the second active pattern 213 through a fourth via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22.

[0066] Furthermore, the gate of the first reset transistor T3 is the part of the reset signal line 231 that overlaps with the fourth active part 2131 and the sixth active part 2133. That is, the reset signal line 231 is used as the gate of the first reset transistor T3, which makes the circuit layout of the sub-pixel 20 simpler.

[0067] Of course, the gate of the first reset transistor T3 can also be additionally set, and the gate of the first reset transistor T3 can be connected to the reset signal line 231.

[0068] In this embodiment, the orthographic projection of the second active pattern 213 on the substrate 10 and the orthographic projection of the first power signal line 271 on the substrate 10 do not overlap.

[0069] In related technologies, the first power signal line 17 needs to be connected to the connector 11. Due to circuit space layout requirements, this will make... Figure 1 The active pattern of the first reset transistor T3 overlaps with the first power signal line 271; however, in this embodiment, the connection part 11 is not required, and the first power signal line 17 does not need to be connected to the connection part 11, thereby reducing the load on the first power signal line 17, improving the display effect of the display panel, and, based on the circuit spatial arrangement, it is possible to control that the orthographic projection of the second active pattern 213 on the substrate 10 and the orthographic projection of the first power signal line 271 on the substrate 10 do not overlap.

[0070] like Figure 2 As shown, each sub-pixel 20 also includes a first light-emitting control transistor T4; the gate of the first light-emitting control transistor T4 is controlled by the light-emitting control signal line 233, the first terminal of the first light-emitting control transistor T4 is connected to the first power supply signal line 271, and the second terminal of the first light-emitting control transistor T4 is connected to the first terminal of the driving transistor T2; the first power supply signal line 271 is also connected to the second plate of the storage capacitor Cst.

[0071] like Figure 4As shown, the active pattern 214 of the first light-emitting control transistor T4 has a first main body and a seventh protrusion connected to each other. The first main body extends along the column direction and overlaps with the light-emitting control signal line 233. The gate of the first light-emitting control transistor T4 is the part of the light-emitting control signal line 233 that overlaps with the first main body of the active pattern 214. Along the row direction of the display panel, the seventh protrusion in the active pattern 214 is located on the side of the first main body of the active pattern 214 facing the first active pattern 211. The setting of the seventh protrusion in the active pattern 214 facilitates the connection of the first power signal line 271 set on the source and drain electrode layers to the seventh protrusion in the active pattern 214 through the eleventh via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24 and the first gate insulating layer 22.

[0072] like Figure 2 As shown, each sub-pixel 20 also includes a data writing transistor T5; the gate of the data writing transistor T5 is controlled by the gate line 232, the first terminal of the data writing transistor T5 is connected to the data line 272, and the second terminal of the data writing transistor T5 is connected to the first terminal of the driving transistor T2.

[0073] like Figure 4 As shown, the active pattern 215 of the data writing transistor T5 extends along the column direction of the display panel. The gate of the data writing transistor T5 is the part of the gate line 232 that overlaps with the active pattern 215. Furthermore, the active pattern 215 of the data writing transistor T5 is connected to the first main body portion of the active pattern 214 of the first light-emitting control transistor T4.

[0074] like Figure 2 As shown, each sub-pixel 20 also includes a second light-emitting control transistor T6 and a light-emitting device; the gate of the second light-emitting control transistor T6 is controlled by the light-emitting control signal line 233, the first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T2, and the second terminal of the second light-emitting control transistor T6 is connected to the first terminal of the light-emitting device.

[0075] like Figure 4As shown, the active pattern 216 of the second light-emitting control transistor T6 has a second main body and an eighth protrusion connected to each other. The second main body extends along the column direction and overlaps with the light-emitting control signal line 233. The gate of the second light-emitting control transistor T6 is the part of the light-emitting control signal line 233 that overlaps with the second main body of the active pattern 216. Along the row direction of the display panel, the eighth protrusion in the active pattern 216 is located on the side of the second main body of the active pattern 216 facing the first power signal line 271. The arrangement of the eighth protrusion in the active pattern 216 facilitates the connection of the fourth connection portion provided on the source and drain electrode layers to the eighth protrusion in the active pattern 216 through the tenth via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22.

[0076] In this configuration, the second main body portion of the active pattern 216 of the second light-emitting control transistor T6 is connected to the first active portion 2111 of the first active pattern 211; while the active pattern 212 of the driving transistor T2 is located between the active pattern 216 of the second light-emitting control transistor T6 and the active pattern 215 of the data writing transistor T5, and the active pattern 212 of the driving transistor T2 is connected to the active pattern 216 of the second light-emitting control transistor T6 and the active pattern 215 of the data writing transistor T5 respectively.

[0077] like Figure 2 As shown, each sub-pixel 20 also includes a second reset transistor T7; the gate of the second reset transistor T7 is controlled by the reset signal line 231, the first terminal of the second reset transistor T7 is connected to the first initialization signal line 252, and the second terminal of the second reset transistor T7 is connected to the first terminal of the light-emitting device.

[0078] like Figure 4 As shown, the active pattern 217 of the second reset transistor T7 extends along the column direction of the display panel. In each sub-pixel 20, the active pattern 217 of the second reset transistor T7 is located on the side of the active pattern 216 of the second light-emitting control transistor T6 away from the first active pattern 211, and the active pattern 217 of the second reset transistor T7 is connected to the active pattern 216 of the second light-emitting control transistor T6. The gate of the second reset transistor T7 is the part of the reset signal line 231 that overlaps with the active pattern 217.

[0079] Furthermore, the active pattern 217 of the second reset transistor T7 has a ninth protrusion facing the first power signal line 271 and a tenth protrusion away from the first power signal line 271. The arrangement of the ninth and tenth protrusions facilitates the connection of the second connection portion 274 provided on the source and drain electrode layers to the active pattern 217 of the second reset transistor T7 through a second via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24 and the first gate insulating layer 22.

[0080] In the actual product, in the nth row of sub-pixels 20, the reset signal line 231 connected to the first reset transistor T3 is the reset signal line 231 in the nth row of sub-pixels 20, the reset signal line 231 connected to the second reset transistor T7 is the reset signal line 231 in the (n+1)th row of sub-pixels, and the reset signal line 231 connected to the second reset transistor T7 is connected to the gate line 232 in the nth row of sub-pixels 20; n is a positive integer greater than 0.

[0081] Figure 2 The diagram shows the structure of any two adjacent columns of sub-pixels 20 in the nth row. It can be seen that the second reset transistor T7 in the (n-1)th row of sub-pixels 20, namely T7(n-1), is connected to the reset signal line 231 in the nth row of sub-pixels 20, and the second reset transistor T7 in the nth row of sub-pixels 20, namely T7(n), is connected to the reset signal line 231 in the (n+1)th row of sub-pixels 20; and the gate line 232 in the nth row of sub-pixels 20 is connected to the reset signal line 231 in the (n+1)th row of sub-pixels.

[0082] It is worth noting that the second active pattern 213 of the first reset transistor T3 is disconnected from the first active pattern 211 of the compensation transistor T1, the active pattern 212 of the driving transistor T2, the active pattern 214 of the first light-emitting control transistor T4, the active pattern 215 of the data writing transistor T5, the active pattern 216 of the second light-emitting control transistor T6, and the active pattern 217 of the second reset transistor T7.

[0083] In this embodiment, the first active pattern 211 is located in the active layer, the gate line 232, the reset signal line 231, the light emission control signal line 233, and the first electrode 234 of the storage capacitor Cst are all located in the first gate layer, the first initialization signal line 252, the second initialization signal line 251, and the second electrode 253 of the storage capacitor Cst are located in the second gate layer, and the first power signal line 271 and the data line 272 are located in the source-drain electrode layer; a first gate insulating layer 22 is disposed between the first gate layer and the active layer, a second gate insulating layer 24 is disposed between the second gate layer and the first gate layer, and an interlayer dielectric layer 26 is disposed between the source-drain electrode layer and the second gate layer, and the source-drain electrode layer is located on the side of the interlayer dielectric layer 26 away from the substrate 10.

[0084] Among them, such as Figure 4As shown, the first active pattern 211 of the compensation transistor T1, the active pattern 212 of the driving transistor T2, the second active pattern 213 of the first reset transistor T3, the active pattern 214 of the first light-emitting control transistor T4, the active pattern 215 of the data writing transistor T5, the active pattern 216 of the second light-emitting control transistor T6, and the active pattern 217 of the second reset transistor T7 are all located on the same active layer.

[0085] like Figure 5 As shown, along the column direction of the display panel, the width of each region of the gate line 232 is equal, the width of each region of the reset signal line 231 is equal, and the width of each region of the light emission control signal line 233 is equal. In each sub-pixel 20, the gate line 232 is located between the first initialization signal line 252 and the light emission control signal line 233, and a first electrode 234 of the storage capacitor Cst is disposed between the gate line 232 and the light emission control signal line 233. The orthographic projection shape of the first electrode 234 on the substrate 10 is rectangular. Furthermore, the gate line 232, the reset signal line 231, the light emission control signal line 233, and the first electrode 234 of the storage capacitor Cst are all located on the same layer of the first gate layer.

[0086] Furthermore, the reset signal line 231 overlaps with the fourth active portion 2131 and the sixth active portion 2133 in the second active pattern 213 of the first reset transistor T3, and also overlaps with the active pattern 217 of the second reset transistor T7; the gate line 232 overlaps with the first active portion 2111 and the third active portion 2113 in the first active pattern 211 of the compensation transistor T1, and also overlaps with the active pattern 215 of the data writing transistor T5; the first plate 234 of the storage capacitor Cst overlaps with the active pattern 212 of the driving transistor T2; and the light emission control signal line 233 overlaps with the active pattern 216 of the second light emission control transistor T6 and the active pattern 214 of the first light emission control transistor T4.

[0087] like Figure 6 As shown, in each sub-pixel 20, the reset signal line 231 is located between the second initialization signal line 251 and the first initialization signal line 252, and the second electrode 253 of the storage capacitor Cst is located on the side of the first initialization signal line 252 away from the second initialization signal line 251. The first initialization signal line 252, the second initialization signal line 251 and the second electrode 253 of the storage capacitor Cst are all located on the same layer in the second gate layer.

[0088] In the second active pattern 213, at the position where the fifth active part 2132 and the sixth active part 2133 are connected, the second initialization signal line 251 has an eleventh protrusion facing the first initialization signal line 252 and a twelfth protrusion away from the first initialization signal line 252, so that the first connection part can be connected to the second initialization signal line 251 through the first via penetrating the interlayer dielectric layer 26. At other positions except the position where the fifth active part 2132 and the sixth active part 2133 are connected, the width of the second initialization signal line 251 along the second direction is equal.

[0089] The second electrode plate 253 of the storage capacitor Cst has a through opening. The orthographic projection of this opening onto the substrate 10 overlaps with the orthographic projection of the first electrode plate 234 of the storage capacitor Cst onto the substrate 10. This allows the third connection portion provided on the source / drain electrode layer to be connected to the first electrode plate 234 of the storage capacitor Cst through the eighth via penetrating the interlayer dielectric layer 26 and the second gate insulating layer 24 at the opening of the second electrode plate 253. The orthographic projection of the other parts of the second electrode plate 253 onto the substrate 10 also overlaps with the orthographic projection of the first electrode plate 234 onto the substrate 10, so that the storage capacitor Cst is formed through the first electrode plate 234 and the second electrode plate 253.

[0090] like Figure 7As shown, 260 represents a first via penetrating the interlayer dielectric layer 26, which exposes the second initialization signal line 251; 261 represents a second via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22, which exposes the active pattern 217 of the second reset transistor T7; 262 represents a third via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22, which exposes the second active pattern 217 of the first reset transistor T3. In pattern 213, the fourth active portion 2131; 263 represents a fourth via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22, which exposes the sixth active portion 2133 in the second active pattern 213 of the first reset transistor T3; 264 represents a fifth via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22, which exposes the active pattern 215 of the data writing transistor T5; 265 represents a via penetrating the interlayer dielectric layer 26; The sixth via 265 of dielectric layer 26 exposes the first initialization signal line 252; 266 represents the seventh via 265 penetrating the interlayer dielectric layer 26, the second gate insulating layer 24, and the first gate insulating layer 22, exposing the third active portion 2113 in the first active pattern 211; 267 represents the eighth via 267 penetrating the interlayer dielectric layer 26 and the second gate insulating layer 24, exposing the first electrode 234 of the storage capacitor Cst; 268 represents the via 265 penetrating the interlayer dielectric layer 26. The ninth via 268 of 6 exposes the second plate 253 of the storage capacitor Cst; 269 represents the tenth via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24 and the first gate insulating layer 22, and the tenth via 269 exposes the active pattern 216 of the second light-emitting control transistor T6; 270 represents the eleventh via penetrating the interlayer dielectric layer 26, the second gate insulating layer 24 and the first gate insulating layer 22, and the eleventh via 270 exposes the active pattern 214 of the first light-emitting control transistor T4.

[0091] like Figure 8 As shown, the first power signal line 271, data line 272, first connection portion 273, second connection portion 274, third connection portion 275 and fourth connection portion 276 are all located in the same layer of the source and drain electrode layer, and the orthographic projections of the first power signal line 271, data line 272, first connection portion 273, second connection portion 274, third connection portion 275 and fourth connection portion 276 on the substrate 10 do not overlap.

[0092] Specifically, the first power signal line 271 is connected to the second plate 253 of the storage capacitor Cst through the ninth via 268, and is also connected to the active pattern 214 of the first light-emitting control transistor T4 through the eleventh via 270; the data line 272 is connected to the active pattern 215 of the data writing transistor T5 through the fifth via 264; the first connection part 273 is connected to the second initialization signal line 251 through the first via 260, and is also connected to the sixth active part 2133 in the second active pattern 213 of the first reset transistor T3 through the fourth via 263; the second connection part 274 is connected to the second reset transistor T3 through the second via 261. The active pattern 217 of the bit transistor T7 is connected, and the second connection part 274 is also connected to the first initialization signal line 252 through the sixth via 265; the third connection part 275 is connected to the fourth active part 2131 in the second active pattern 213 of the first reset transistor T3 through the third via 262, the third connection part 275 is connected to the third active part 2113 in the first active pattern 211 of the compensation transistor T1 through the seventh via 266, and the third connection part 275 is also connected to the first plate 234 of the storage capacitor Cst through the eighth via 267; the fourth connection part 276 is connected to the active pattern 216 of the second light-emitting control transistor T6 through the tenth via 269.

[0093] Will Figure 8 The source / drain electrode layer shown is set in Figure 7 The structure shown can be used to obtain, as follows: Figure 2 The display panel shown is based on the connection relationship of each film layer. Figure 2 The equivalent circuit diagram corresponding to each sub-pixel 20 in the display panel shown is as follows: Figure 9 As shown.

[0094] In this configuration, the gate of compensation transistor T1 is controlled by gate line 232. The first terminal of compensation transistor T1 is connected to the second terminal of driving transistor T2. The second terminal of compensation transistor T1 is connected to the gate of driving transistor T2 and the first plate 234 of storage capacitor Cst. The second plate 253 of storage capacitor Cst is connected to the first power supply signal line 271. The gate of first reset transistor T3 is controlled by reset signal line 231. The first terminal of first reset transistor T3 is connected to the second initialization signal line 251. The second terminal of first reset transistor T3 is connected to the second terminal of compensation transistor T1. The gate of first light-emitting control transistor T4 is controlled by light-emitting control signal line 233. The first terminal of first light-emitting control transistor T4 is connected to the first power supply signal line 271. The second terminal of first light-emitting control transistor T4 is connected to the driving transistor T2 and the first plate 234 of storage capacitor Cst. The first terminal of the driving transistor T2 is connected; the gate of the data writing transistor T5 is controlled by the gate line 232, the first terminal of the data writing transistor T5 is connected to the data line 272, and the second terminal of the data writing transistor T5 is connected to the first terminal of the driving transistor T2; the gate of the second light-emitting control transistor T6 is controlled by the light-emitting control signal line 233, the first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T2, and the second terminal of the second light-emitting control transistor T6 is connected to the first terminal of the light-emitting device EL; the gate of the second reset transistor T7 is controlled by the reset signal line 231, the first terminal of the second reset transistor T7 is connected to the first initialization signal line 252, and the second terminal of the second reset transistor T7 is connected to the first terminal of the light-emitting device EL; while the second terminal of the light-emitting device EL is connected to the second power supply signal line.

[0095] It should be noted that, upon obtaining such... Figure 2 Following the display panel shown, structures such as the anode, pixel boundary layer, light-emitting layer, and cathode need to be formed sequentially. Figure 9 The light-emitting device (EL) in the image includes an anode, a light-emitting layer, and a cathode stacked together. The first electrode of the light-emitting device (EL) is the anode, and the second electrode of the light-emitting device (EL) is the cathode.

[0096] like Figure 10 As shown, for the nth row sub-pixel 20, in the first stage t11, the reset signal Reset input to the nth row reset signal line 231 is a low-level signal, which turns on the first reset transistor T3. Then, the second initialization signal Vinit2 input to the second initialization signal line 251 resets the storage capacitor Cst and the gate of the driving transistor T2. At this time, the driving transistor T2 is in the on state. Since the gate signal Gate input to the gate line 232 and the light emission control signal EM input to the light emission control signal line 233 are both high-level signals, the compensation transistor T1, the first light emission control transistor T4, the data writing transistor T5 and the second light emission control transistor T6 are all turned off.

[0097] In the second stage t12, the gate signal Gate input to gate line 232 is a low-level signal, causing the compensation transistor T1 and the data writing transistor T5 to conduct. Since the driving transistor T2 is also in the conducting state, the data signal Data provided by data line 272 charges the storage capacitor Cst through the data writing transistor T5, the driving transistor T2, and the compensation transistor T1, making the gate voltage of the driving transistor T2 Vdata + Vth, where Vth refers to the threshold voltage of the driving transistor T2, and Vdata refers to the voltage of the data signal Data. Since the reset signal Reset input to the nth row reset signal line 231 and the light emission control signal EM input to the light emission control signal line 233 are both high-level signals, the first reset transistor T3, the first light emission control transistor T4, and the second light emission control transistor T6 are all turned off.

[0098] At this time, in the nth row of sub-pixels 20, since the reset signal line 231 connected to the second reset transistor T7 is the reset signal line 231 in the (n+1)th row of sub-pixels 20, and the reset signal line 231 connected to the second reset transistor T7 is connected to the gate line 232 in the nth row of sub-pixels 20, therefore, in the second stage t12, the reset signal Reset input to the reset signal line 231 in the (n+1)th row of sub-pixels 20 is also a low-level signal, which makes the second reset transistor T7 turn on, and then the first initialization signal Vinit1 input through the first initialization signal line 252 resets the first electrode of the light-emitting device EL.

[0099] In the third stage t13, the light-emitting control signal EM input to the light-emitting control signal line 233 is a low-level signal, causing the first light-emitting control transistor T4 and the second light-emitting control transistor T6 to turn on. This provides a driving current to the first electrode of the light-emitting device EL through the first light-emitting control transistor T4, the driving transistor T2, and the second light-emitting control transistor T6, driving the light-emitting device EL to emit light. The magnitude of the driving current is related to the voltage of the high-level voltage signal VDD provided by the first power supply signal line 271 and the voltage of the data signal Vdata. At this time, since the reset signal Reset input to the nth row reset signal line 231 and the gate signal Gate input to the gate line 232 are both high-level signals, the first reset transistor T3, the compensation transistor T1, the data writing transistor T5, and the second reset transistor T7 are all turned off.

[0100] It should be noted that the second power signal line is used to provide a low-level voltage signal VSS to the cathode of the light-emitting device EL. The above driving process is illustrated using the example where the compensation transistor T1, driving transistor T2, first reset transistor T3, first light-emitting control transistor T4, data writing transistor T5, second light-emitting control transistor T6, and second reset transistor T7 are all P-type transistors, which conduct when the gate is low and turn off when the gate is high. Of course, the compensation transistor T1, driving transistor T2, first reset transistor T3, first light-emitting control transistor T4, data writing transistor T5, second light-emitting control transistor T6, and second reset transistor T7 can also be N-type transistors, which conduct when the gate is high and turn off when the gate is low. Furthermore, to distinguish the two terminals of the transistor other than the gate, the source is called the first terminal and the drain is called the second terminal.

[0101] In this embodiment, the gate lines 232 in the sub-pixels 20 located in the same row are interconnected, the reset signal lines 231 in the sub-pixels 20 located in the same row are interconnected, the light emission control signal lines 233 in the sub-pixels 20 located in the same row are interconnected, the first initialization signal lines 252 in the sub-pixels 20 located in the same row are interconnected, and the second initialization signal lines 251 in the sub-pixels 20 located in the same row are interconnected; the data lines 272 in the sub-pixels 20 located in the same column are interconnected, and the first power signal lines 271 in the sub-pixels 20 located in the same column are interconnected.

[0102] By connecting the same type of traces extending along the row direction in the same row of sub-pixels 20 together, and connecting the same type of traces extending along the column direction in the same column of sub-pixels 20 together, the number of leads in the fan-out area of ​​the display panel is reduced, thereby making the area occupied by the fan-out area smaller.

[0103] If it is necessary to form such Figure 2 The display panel shown requires that each sub-pixel 20 has a corresponding compensation transistor T1, driving transistor T2, storage capacitor Cst, first initialization signal line 252, first reset transistor T3, first light-emitting control transistor T4, data writing transistor T5, second light-emitting control transistor T6 and second reset transistor T7, as well as a second initialization signal line 251, reset signal line 231, gate line 232, light-emitting control signal line 233, first power signal line 271 and data line 272 formed on the substrate 10.

[0104] Specifically, a patterning process is first used on substrate 10 to form, such as Figure 4 The active layer shown includes active patterns of various transistors. Then, a first gate insulating layer 22 is formed covering the active layer and the substrate 10. A first gate layer is formed on the gate insulating layer 22 using a patterning process, resulting in the desired structure. Figure 5 The structure shown includes a first gate layer comprising a reset signal line 231, a gate line 232, a first electrode 234 of a storage capacitor Cst, and a light-emitting control signal line 233. Next, a second gate insulating layer 24 is formed covering the first gate layer and the first gate insulating layer 22. A second gate layer is then formed on the second gate insulating layer 24 using a patterning process, resulting in the structure shown. Figure 6 The structure shown includes a second gate layer comprising a first initialization signal line 252, a second initialization signal line 251, and a second electrode 253 of a storage capacitor Cst; then, an interlayer dielectric layer 26 is formed covering the second gate layer and the second gate insulating layer 24, and a through via is formed, such as... Figure 7 The vias shown are: first via 260, second via 261, third via 262, fourth via 263, fifth via 264, sixth via 265, seventh via 266, eighth via 267, ninth via 268, tenth via 269, and eleventh via 270; finally, a patterning process is used to form the vias shown in the diagram on the interlayer dielectric layer 26. Figure 8 The source and drain electrode layers shown are thus obtained as follows. Figure 2 The display panel shown includes a source / drain electrode layer comprising a first power signal line 271, a data line 272, a first connection portion 273, a second connection portion 274, a third connection portion 275, and a fourth connection portion 276.

[0105] In the formation of such Figure 2 Following the display panel shown, a passivation layer covering the source / drain electrode layer and the interlayer dielectric layer 26 needs to be formed, as well as a planarization layer located on the side of the passivation layer away from the source / drain electrode layer. Next, an anode layer and a pixel defining layer are formed on the planarization layer. The pixel defining layer has pixel openings that expose the anode layer. An organic functional layer is formed within the pixel openings. Then, a cathode layer covering the pixel defining layer and the organic functional layer is formed. Finally, an encapsulation layer covering the cathode layer is formed, thereby obtaining the completed display panel. This encapsulation layer can be an organic encapsulation layer, an inorganic encapsulation layer, or a stacked structure of organic encapsulation layers.

[0106] In this embodiment, by changing the first active pattern of the compensation transistor, the first active pattern includes a first active portion, a second active portion, and a third active portion connected in sequence. The second active portion extends along a first direction, and the extension directions of the first and third active portions intersect with the first direction. Furthermore, the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the second active portion on the substrate. A coupling capacitor is directly formed by the overlap of the first initialization signal line and the first active pattern of the compensation transistor. At this time, there is no need to set up additional connection portions. By optimizing the circuit design of the sub-pixel, the circuit space arrangement of each sub-pixel is simplified, thereby saving the space occupied by the circuit arrangement of each sub-pixel and improving the aperture ratio of each sub-pixel.

[0107] This application also discloses a display device, including the display panel described above.

[0108] In addition, the display device also includes a driver chip that is bound to the wiring in the display panel, and a TCON (Timer Control Register) connected to the driver chip.

[0109] In practical applications, the display device can be any product or component with display function, such as a mobile phone, tablet computer, monitor, laptop computer, or navigator.

[0110] Furthermore, the specific structure of the display panel in the display device can be referred to the description of the display panel above, and the effect is similar to that achieved by the display panel above. To avoid repetition, it will not be described again here.

[0111] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0112] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0113] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, comprising: Base; as well as Multiple sub-pixels are disposed on the substrate, each sub-pixel comprising: Compensating transistor; Drive transistors; Storage capacitors; and First initialization signal line; The first terminal of the compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the compensation transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor, respectively. The first active pattern of the compensation transistor includes a first active portion, a second active portion and a third active portion connected in sequence. The second active portion extends along a first direction, and the extension directions of the first active portion and the third active portion both intersect with the first direction. The first initialization signal line extends along the first direction, and the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the second active part on the substrate.

2. The display panel according to claim 1, wherein, The orthographic projection of the first initialization signal line on the substrate overlaps the orthographic projection of the second active part on the substrate.

3. The display panel according to claim 1, wherein, The orthographic projection of the first initialization signal line on the substrate also overlaps with the orthographic projections of the first active part and the third active part on the substrate.

4. The display panel according to claim 1, wherein, Each of the sub-pixels further includes a gate line, a reset signal line, a second initialization signal line, a light emission control signal line, a first power supply signal line, and a data line; The gate line, the reset signal line, the second initialization signal line, and the light emission control signal line all extend along the first direction, and the first power signal line and the data line all extend along the second direction, which intersects with the first direction.

5. The display panel according to claim 4, wherein, The reset signal line is located between the first initialization signal line and the second initialization signal line, the first initialization signal line is located between the reset signal line and the gate line, and the gate line is located between the first initialization signal line and the light emission control signal line.

6. The display panel according to claim 4, wherein, The gate of the compensation transistor is controlled by the gate line, and the gate of the compensation transistor is the portion of the gate line that overlaps with the first active portion and the third active portion.

7. The display panel according to claim 4, wherein, At the location where the first active portion and the second active portion meet, the first initialization signal line has a first protrusion facing the gate line and a second protrusion away from the gate line; Furthermore, at all locations except where the first active part and the second active part are connected, the width of the first initialization signal line along the second direction is equal.

8. The display panel according to claim 4, wherein, Each of the sub-pixels also includes: First reset transistor; The gate of the first reset transistor is controlled by the reset signal line, the first terminal of the first reset transistor is connected to the second initialization signal line, and the second terminal of the first reset transistor is connected to the second terminal of the compensation transistor.

9. The display panel according to claim 8, wherein, The first reset transistor is a dual-gate transistor; The second active pattern of the first reset transistor includes a fourth active portion, a fifth active portion, and a sixth active portion connected in sequence. The fifth active portion extends along the first direction, and the extension directions of the fourth active portion and the sixth active portion both intersect with the first direction. The gate of the first reset transistor is a portion of the reset signal line that overlaps with the fourth active portion and the sixth active portion.

10. The display panel according to claim 9, wherein, The orthographic projection of the second active pattern on the substrate and the orthographic projection of the first power signal line on the substrate do not overlap.

11. The display panel according to claim 1, wherein, The extension directions of the first active portion and the third active portion are parallel to each other; or, The first active part extends in a third direction, and the third active part extends in a fourth direction, with the third direction intersecting the fourth direction.

12. The display panel according to claim 4, wherein, Each of the sub-pixels also includes: First light-emitting control transistor; Wherein, the gate of the first light-emitting control transistor is controlled by the light-emitting control signal line, the first terminal of the first light-emitting control transistor is connected to the first power supply signal line, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor; The first power signal line is also connected to the second plate of the storage capacitor.

13. The display panel according to claim 4, wherein, Each of the sub-pixels also includes: Data is written to the transistor; The gate of the data writing transistor is controlled by the gate line, the first terminal of the data writing transistor is connected to the data line, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor.

14. The display panel according to claim 8, wherein, Each of the sub-pixels also includes: Second light-emitting control transistor and light-emitting device; The gate of the second light-emitting control transistor is controlled by the light-emitting control signal line, the first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the light-emitting device.

15. The display panel according to claim 14, wherein, Each of the sub-pixels also includes: Second reset transistor; The gate of the second reset transistor is controlled by the reset signal line, the first terminal of the second reset transistor is connected to the first initialization signal line, and the second terminal of the second reset transistor is connected to the first terminal of the light-emitting device.

16. The display panel according to claim 15, wherein, In the sub-pixel of the nth row, the reset signal line connected to the first reset transistor is the reset signal line in the sub-pixel of the nth row, the reset signal line connected to the second reset transistor is the reset signal line in the sub-pixel of the (n+1)th row, and the reset signal line connected to the second reset transistor is connected to the gate line in the sub-pixel of the nth row; where n is a positive integer greater than 0.

17. The display panel according to claim 4, wherein, The first active pattern is located in the active layer, the gate line, the reset signal line, the light emission control signal line and the first electrode of the storage capacitor are all located in the first gate layer, the first initialization signal line, the second initialization signal line and the second electrode of the storage capacitor are located in the second gate layer, and the first power signal line and the data line are located in the source and drain electrode layers. A first gate insulating layer is disposed between the first gate layer and the active layer, a second gate insulating layer is disposed between the second gate layer and the first gate layer, an interlayer dielectric layer is disposed between the source / drain electrode layer and the second gate layer, and the source / drain electrode layer is located on the side of the interlayer dielectric layer away from the substrate.

18. The display panel according to claim 4, wherein, The gate lines in the sub-pixels located in the same row are interconnected, the reset signal lines in the sub-pixels located in the same row are interconnected, the light emission control signal lines in the sub-pixels located in the same row are interconnected, the first initialization signal lines in the sub-pixels located in the same row are interconnected, and the second initialization signal lines in the sub-pixels located in the same row are interconnected. The data lines in the sub-pixels located in the same column are interconnected, and the first power signal lines in the sub-pixels located in the same column are interconnected.

19. A display device comprising a display panel as claimed in any one of claims 1 to 18.

Images