Semiconductor memory device and method of controlling the same

Abstract

The present application provides a semiconductor storage device with a long life and a control method thereof. The semiconductor storage device of an embodiment includes a memory transistor, a transistor electrically connected to a gate electrode of the memory transistor, a voltage supply line electrically connected to the gate electrode of the memory transistor via the transistor, a signal supply line connected to a gate electrode of the transistor, a capacitor electrically connected to the gate electrode of the memory transistor without the transistor, and a wiring connected to a current path between the gate electrode of the memory transistor and the transistor via the capacitor. At a first timing of a write operation to the memory transistor, a voltage of the voltage supply line is a first voltage, a voltage of the signal supply line is a second voltage, and a voltage of the wiring is a third voltage. At a second timing, the voltage of the signal supply line is lowered to a fourth voltage. At a third timing, the voltage of the wiring is raised to a fifth voltage.

Description

[0001] Reference of Related Application

[0002] This application claims priority to Japanese Patent Application No. 2021-153609 (Filing date: September 21, 2021). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0003] The present embodiment relates to a semiconductor storage device and a control method thereof. BACKGROUND

[0004] A semiconductor storage device provided with a plurality of memory transistors is known. SUMMARY

[0005] The present application relates to a semiconductor storage device and a control method thereof.

[0006] A semiconductor storage device of one embodiment includes a first memory transistor, a first transistor, a first voltage supply line, a first signal supply line, a first capacitor, and a first wiring. The first transistor is electrically connected to a gate electrode of the first memory transistor. The first voltage supply line is electrically connected to the gate electrode of the first memory transistor through the first transistor. The first signal supply line is electrically connected to a gate electrode of the first transistor. The first capacitor is electrically connected to the gate electrode of the first memory transistor without passing through the first transistor. The first wiring is connected to a current path between the gate electrode of the first memory transistor and the first transistor through the first capacitor. In a first timing for a write operation to the first memory transistor, a voltage of the first voltage supply line is a first voltage, a voltage of the first signal supply line is a second voltage, and a voltage of the first wiring is a third voltage. In a second timing later than the first timing, the voltage of the first signal supply line is decreased from the second voltage to a fourth voltage smaller than the second voltage. In a third timing later than the second timing, the voltage of the first wiring is increased from the third voltage to a fifth voltage larger than the third voltage. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic block diagram illustrating a configuration of a semiconductor storage device of the first embodiment.

[0008] Figure 2 FIG. 2 is a schematic circuit diagram illustrating a configuration of a part of the semiconductor storage device of the first embodiment.

[0009] Figure 3 FIG. 3 is a schematic circuit diagram illustrating a configuration of a part of the semiconductor storage device of the first embodiment.

[0010] Figure 4is a schematic circuit diagram showing a configuration of a part of the semiconductor storage device of the first embodiment.

[0011] Figure 5 is a schematic plan view showing a configuration of a part of the semiconductor storage device of the first embodiment.

[0012] Figure 6 is a schematic perspective view showing a configuration of a part of the semiconductor storage device of the first embodiment.

[0013] Figure 7 is a schematic enlarged view of a part shown by A of Figure 5

[0014] Figure 8 is a schematic enlarged view of a part shown by B of Figure 6

[0015] Figure 9 is a schematic sectional view for explaining a readout operation.

[0016] Figure 10 is a schematic sectional view for explaining a write operation.

[0017] Figure 11 is a schematic sectional view for explaining an erase operation.

[0018] Figure 12 is a schematic circuit diagram for explaining a write operation of the semiconductor storage device of the present embodiment.

[0019] Figure 13 is a schematic waveform chart for explaining a write operation of the semiconductor storage device of the present embodiment.

[0020] Figure 14 is a schematic waveform chart for explaining a write operation of the semiconductor storage device of the second embodiment.

[0021] Figure 15 is a schematic sectional view showing a configuration of a part of the semiconductor storage device of the third embodiment.

[0022] Figure 16 is a schematic sectional view showing a configuration of a part of the semiconductor storage device of the fourth embodiment.

[0023] Figure 17 is a schematic sectional view showing a configuration of a part of the semiconductor storage device of the fourth embodiment.

[0024] Figure 18 ​​is a schematic cross-sectional view for explaining a write operation of the semiconductor storage device of the fifth embodiment.

[0025] Figure 19 is a schematic cross-sectional view showing a configuration of the transistor T BL0 of the first comparative example.

[0026] Figure 20 is a schematic cross-sectional view showing a configuration of the transistor T BL1 of the second comparative example.

[0027] Figure 21 is a schematic cross-sectional view showing a configuration of the transistor T BL2 of the fifth embodiment.

[0028] Figure 22 is a schematic cross-sectional view showing a configuration of the transistor T BL3 of the sixth embodiment.

[0029] Explanation of Reference Numerals

[0030] MC... memory cell (memory transistor), BL... bit line, WLa, WLb... word line, Ta, Tb, T BL ... transistor, Lwla, Lwlb... voltage supply line, Lg1, Lg2... signal supply line, Cba, Cbb... capacitor, Lb... wiring. DETAILED DESCRIPTION

[0031] Next, the semiconductor storage device of the embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples, and are not intended to limit the present application. In addition, the following drawings are schematic, and part of the configuration or the like is omitted for convenience of explanation. In addition, for the portions common to the plurality of embodiments, the same reference numerals are attached, and the explanation is sometimes omitted.

[0032] In addition, in the present specification, when it is said "semiconductor storage device", it sometimes means a memory die, and sometimes means a memory chip, a memory card, an SSD (Solid State Drive), or the like including a controller die. Furthermore, it sometimes means a smart phone, a tablet terminal, a personal computer, or the like including a host computer.

[0033] In addition, in the present specification, when it is said "control circuit", it sometimes means a peripheral circuit such as a sequencer provided in a memory die, and sometimes means a controller die or a controller chip connected to the memory die, or the like, and sometimes means a configuration including both of them.

[0034] In addition, in the case where it is said in this specification that a first configuration is electrically connected to a second configuration, the first configuration can be directly connected to the second configuration, or the first configuration can be connected to the second configuration via a wiring, a semiconductor element, or a transistor, or the like. For example, in the case where three transistors are connected in series, even if the second transistor is in an off state, the first transistor is electrically connected to the third transistor.

[0035] In addition, in the case where it is said in this specification that a first configuration is connected between a second configuration and a third configuration, it sometimes means that the first configuration, the second configuration, and the third configuration are connected in series and the second configuration is connected to the third configuration via the first configuration.

[0036] In addition, in the case where it is said in this specification that a circuit or the like makes two wirings or the like conductive, for example, it sometimes means that the circuit or the like includes a transistor or the like and the transistor or the like is provided in a current path between the two wirings and the transistor or the like is in an on state.

[0037] In addition, in this specification, a predetermined direction parallel to the upper surface of a substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0038] In addition, in this specification, a direction along a predetermined surface is sometimes referred to as a first direction, a direction intersecting the first direction along the predetermined surface is sometimes referred to as a second direction, and a direction intersecting the predetermined surface is sometimes referred to as a third direction. These first direction, second direction, and third direction can or can not correspond to any one of the X direction, the Y direction, and the Z direction.

[0039] In addition, in this specification, "upper", "lower", and the like are described with the substrate as a reference. For example, a direction away from the substrate along the Z direction described above is referred to as upper, and a direction approaching the substrate along the Z direction is referred to as lower. In addition, in the case where a lower surface or a lower end is described with respect to a certain configuration, it means a surface or an end portion on the substrate side of the configuration, and in the case where an upper surface or an upper end is described, it means a surface or an end portion on the side opposite to the substrate of the configuration. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0040] [First Embodiment]

[0041] [Circuit Configuration]

[0042] Figure 1 is a schematic block diagram illustrating a configuration of a semiconductor storage device of the first embodiment. Figures 2-4 is a schematic circuit diagram illustrating a configuration of a part of the semiconductor storage device.

[0043] In addition, in the case where it is said in this specification that a first configuration is electrically connected to a second configuration, the first configuration can be directly connected to the second configuration, or the first configuration can be connected to the second configuration via a wiring, a semiconductor element, or a transistor, or the like. For example, in the case where three transistors are connected in series, even if the second transistor is in an off state, the first transistor is electrically connected to the third transistor. Figure 1The diagram illustrates multiple control terminals. These control terminals are sometimes represented as control terminals corresponding to a high-level activation signal (positive logic signal). Additionally, they are sometimes represented as control terminals corresponding to a low-level activation signal (negative logic signal). Furthermore, they are sometimes represented as control terminals corresponding to both high-level and low-level activation signals. Figure 1 In the diagram, the reference numerals for the control terminals corresponding to the low-level activation signal include an overline (horizontal bar). In this specification, the reference numerals for the control terminals corresponding to the low-level activation signal include a forward slash (" / "). Furthermore, Figure 1 The description is for illustrative purposes only, and the specific scheme can be adjusted accordingly. For example, some or all of the high-level activation signals can be set as low-level activation signals, or some or all of the low-level activation signals can be set as high-level activation signals.

[0044] like Figure 1 As shown, the semiconductor memory device includes a memory cell array (MCA) and peripheral circuitry (PC). The PC includes a voltage generation circuit (VG), a line decoder (RD), a sense amplifier module (SAM), and a sequencer (SQC). Additionally, the PC includes a cache memory (CM), an address register (ADR), a command register (CMR), and a status register (STR). Furthermore, the PC includes input / output (I / O) control circuitry and logic circuitry (CTR).

[0045] [Circuit configuration of a memory cell array (MCA)]

[0046] like Figure 2 As shown, the memory cell array MCA has multiple memory blocks BLK. Each memory block BLK includes multiple string cells SU. Each string cell SU has multiple memory strings MS. One end of each memory string MS is connected to the peripheral circuit PC via a bit line BL. The other end of each memory string MS is connected to the peripheral circuit PC via a common source line SL.

[0047] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the STD, STS, and STSb are sometimes simply referred to as the select transistors (STD, STS, STSb).

[0048] A memory cell (MC) is a field-effect transistor. The memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. Furthermore, the gate electrodes of multiple memory cell MCs corresponding to a memory string (MS) are each implemented using a portion of a word line (WL). These word lines (WL) function as the gate electrodes of all the memory cell MCs contained in all the memory strings (MS) within a memory block (BLK).

[0049] Select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. The gate electrode of each select transistor (STD, STS, STSb) is implemented as a portion of a select gate line (SGD, SGS, SGSb). One drain-side select gate line SGD functions as the gate electrode of all drain-side select transistors STD contained in all memory strings MS within a single string unit SU. One source-side select gate line SGS functions as the gate electrode of all source-side select transistors STS contained in all memory strings MS within a single memory block BLK. One source-side select gate line SGSb functions as the gate electrode of all source-side select transistors STSb contained in all memory strings MS within a single memory block BLK.

[0050] [Circuit configuration of voltage generation circuit VG]

[0051] For example, Figure 3 As shown, the voltage generation circuit VG( Figure 1 It has multiple voltage generation units vg1 to vg3. During read, write, and erase operations, voltage generation units vg1 to vg3 generate a predetermined voltage, which is then transmitted via voltage supply line L. VG1 L VG2 L VG3 The output voltages from each voltage generation unit (vg1-vg3) are adjusted appropriately according to control signals from the sequencer (SQC).

[0052] The voltage generation unit VG1 is a boost circuit, such as a charge pump circuit. During the write operation, the voltage generation unit VG1 converts the power supply voltage V... CC Boost, the output voltage supplied to the select word line (V, described later) PGM -α( Figure 13 Additionally, the voltage generation unit vg1 can also generate the power supply voltage V during the erase operation. CC Boost voltage, outputting the erase voltage V (described later) ERAThe output terminal of the voltage generation unit VG1 is connected to the voltage supply line L. VG1 Voltage supply line L VG1 It is electrically connected to the voltage generation unit vg2.

[0053] The voltage generation unit Vg2 is, for example, a step-down circuit such as a voltage regulator. During the readout operation, the voltage generation unit Vg2 outputs the readout voltage V (described later). READ Additionally, during the write operation, the voltage generation unit vg2 outputs the write voltage V (described later). PASS .

[0054] The voltage generation unit VG3 is, for example, a step-down circuit such as a voltage regulator. During the read operation, the voltage generation unit VG3 outputs the read voltage, described later. Additionally, during the write operation, the voltage generation unit VG3 outputs the verification voltage, described later.

[0055] [Circuit configuration of the line decoder RD]

[0056] For example, Figure 3 As shown, the line decoder RD includes a block decoder BLKD, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0057] The block decoder BLKD has multiple block decoding units (blkd). These multiple block decoding units (blkd) correspond to multiple memory blocks (BLK) in the memory cell array (MCA). Each block decoding unit (blkd) has multiple transistors (T). BLK Multiple transistors T BLK Corresponding to multiple word lines WL in the memory block BLK. Transistor T BLK For example, an NMOS transistor based on the field-effect transistor. Transistor T BLK The drain electrode of transistor T is connected to word line WL. BLK The source electrode is connected to the voltage supply line CG. The voltage supply line CG is connected to all the block decoding units (blkd) in the block decoder BLKD. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided corresponding to all block decoding units (blkd). Furthermore, the signal supply lines BLKSEL are connected to all transistors T in the block decoding unit (blkd). BLK .

[0058] In read and write operations, for example, with the address register ADR ( Figure 1 Address data D in ) ADDThe voltage of one of the signal supply lines BLKSEL corresponding to the block address included in the address data D included in the address register ADR becomes an "H (high level)" state, and the voltage of the other signal supply lines BLKSEL becomes an "L (low level)" state. For example, a predetermined drive voltage having a positive magnitude is supplied to one of the signal supply lines BLKSEL, and a ground voltage V SS and so on. Thus, all of the word lines WL in one of the memory blocks BLK corresponding to the block address and all of the voltage supply lines CG are turned on. In addition, all of the word lines WL in the other memory blocks BLK become a floating state.

[0059] The word line decoder WLD has a plurality of word line decoding units wld. The plurality of word line decoding units wld correspond to the plurality of memory cells MC in the memory string MS. In the illustrated example, the word line decoding unit wld has two transistors T WLS , T WLU . The drain electrode of the transistor T WLS , T WLU is connected to the voltage supply line CG. The source electrode of the transistor T WLS is connected to the voltage supply line CG WLU . The source electrode of the transistor T WLS is connected to the voltage supply line CG S . The gate electrode of the transistor T WLU is connected to the signal supply line WLSEL U . The gate electrode of the transistor T WLS is connected to the signal supply line WLSEL S . The signal supply line WLSEL WLU is provided a plurality of times in correspondence with one of the transistors T U included in all of the word line decoding units wld. The signal supply line WLSEL S is provided a plurality of times in correspondence with the other of the transistors T WLS included in all of the word line decoding units wld.

[0060] In the readout operation, the write operation, and so on, for example, the voltage of the signal supply line WLSEL corresponding to one of the word line decoding units wld corresponding to the page address included in the address data D included in the address register ADR becomes an "H" state, and the voltage of the WLSEL corresponding thereto becomes an "L" state. In addition, the voltage of the signal supply line WLSEL corresponding to the word line decoding units wld other than this becomes an "H" state, and the voltage of the WLSEL corresponding thereto becomes an "L" state. U WLU Figure 1 ADD S U S ​​​​​​The voltage becomes the "L" state, corresponding to the WLSEL. U The voltage becomes "H". Additionally, the voltage supply line CG is... S Supply and Selection Word Line WL S The corresponding voltage. Additionally, the voltage supply line CG... U Supply and non-selective word line WL U The corresponding voltage. Therefore, a word line WL corresponding to the aforementioned page address is supplied with and selected by the word line WL. S The corresponding voltage. Additionally, supply voltage to other word lines WL and to the non-selected word lines WL. U The corresponding voltage.

[0061] The drive circuit DRV, for example, has 4 transistors T DRV1 ~T DRV4 Transistor T DRV1 ~T DRV4 For example, an NMOS transistor based on the field-effect transistor. Transistor T DRV1 ~T DRV3 The drain electrode is connected to the voltage supply line CG. S Transistor T DRV4 The drain electrode is connected to the voltage supply line CG. U Transistor T DRV1 The source electrode is supplied via voltage line L VG1 And connected to the output terminal of the voltage generation unit vg1. Transistor T DRV2 T DRV4 The source electrode is supplied via voltage line L VG2 And connected to the output terminal of the voltage generation unit vg2. Transistor T DRV3 The source electrode is supplied via voltage line L VG3 And connected to the output terminal of the voltage generation unit vg3. In transistor T DRV1 ~T DRV4 The gate electrodes are connected to the signal supply lines VSEL1 to VSEL4 respectively.

[0062] In read operations, write operations, etc., for example, with the voltage supply line CG S The voltage of one of the corresponding signal supply lines VSEL1 to VSEL3 is in the "H" state, and the others are in the "L" state. Additionally, the voltage supply line CG... U The voltage of the corresponding signal supply line VSEL4 becomes "H".

[0063] Address decoders not shown, for example, follow the sequencer SQC ( Figure 1 The control signals are referenced sequentially to the address register ADR ( Figure 1 Address data D in ) ADDThe row address RA is included. The row address RA includes the block address and page address mentioned above. The address decoder supplies the above signals to lines BLKSEL and WLSEL. S WLSEL U The voltage is controlled to either "H" or "L" state.

[0064] In addition, Figure 3 In the example, the row decoder RD sets one block decoding unit (blkd) for each storage block (BLK). However, this configuration can be changed appropriately. For example, one block decoding unit (blkd) can also be set for each of two or more storage blocks (BLK).

[0065] [Circuit configuration of the Sensing Amplifier Module (SAM)]

[0066] For example, Figure 4 As shown, the sense amplifier module SAM includes multiple sense amplifiers SA. These multiple sense amplifiers SA are electrically connected to multiple bit lines BL. Furthermore, multiple transistors T are respectively arranged in the current paths between the multiple sense amplifiers SA and the multiple bit lines BL. BL These multiple transistors T BL The gate electrode of each transistor is connected to a common signal supply line, BLS. Additionally, these multiple transistors T... BL In addition to the bit line BL, the drain electrode is also connected to the erase voltage V (described later). ERA The composition (e.g., Figure 3 The voltage generation unit vg1 is electrically connected.

[0067] [Circuit configuration of the cache memory CM]

[0068] Cache memory CM ( Figure 1 It has multiple latching circuits. These multiple latching circuits are connected to the sense amplifier module (SAM) via a DBUS wiring system. The data DAT contained in these multiple latching circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0069] Additionally, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit converts the address data D in the address register ADR. ADD The column address CA is included in the decoding. The switching circuit, based on the output signal of the decoding circuit, causes the latch circuit corresponding to the column address CA to connect to the bus DB. Figure 1 ) Conduction.

[0070] [Circuit configuration of the sequencer SQC]

[0071] Sequencer SQC ( Figure 1 According to the command data D held in the command register CMR CMD, outputs internal control signals to a row decoder RD, a sense amplifier module SAM, and a voltage generation circuit VG. In addition, the sequencer SQC outputs state data D ST to a state register STR.

[0072] In addition, the sequencer SQC generates a ready / busy signal and outputs it to a terminal RY / / BY. During a period in which the voltage of the terminal RY / / BY is in the "L" state, access to the semiconductor storage device is substantially prohibited. In addition, during a period in which the voltage of the terminal RY / / BY is in the "H" state, access to the semiconductor storage device is permitted.

[0073] [Circuit configuration of the input / output control circuit I / O]

[0074] The input / output control circuit I / O has data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS, / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which a power supply voltage V CCQ and a ground voltage V SS are supplied, respectively.

[0075] Data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in accordance with internal control signals from the logic circuit CTR. In addition, data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the state register STR to the buffer circuit in accordance with internal control signals from the logic circuit CTR.

[0076] The plurality of input circuits include, for example, a comparator connected to either one of the data signal input / output terminals DQ0 to DQ7 or both of the trigger signal input / output terminals DQS, / DQS. The plurality of output circuits include, for example, an OCD (Off Chip Driver) circuit connected to either one of the data signal input / output terminals DQ0 to DQ7 or either one of the trigger signal input / output terminals DQS, / DQS.

[0077] [Circuit configuration of the logic circuit CTR]

[0078] The logic circuit CTR Figure 1 receives external control signals via external control terminals / CEn, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O in accordance with the same.

[0079] [Configuration of the semiconductor storage device]

[0080] Figure 5 is a schematic plan view showing a configuration of a part of a semiconductor storage device. Figure 6 is a schematic perspective view showing a configuration of a part of a semiconductor storage device. Further, Figure 6 is a diagram for explaining a schematic configuration of a semiconductor storage device, and does not show the number, shape, arrangement, and the like of a specific configuration. Figure 7 is Figure 5 is a schematic enlarged view of a part shown by A of Figure 8 is Figure 6 is a schematic enlarged view of a part shown by B of

[0081] As shown in Figure 5 , for example, a semiconductor storage device is provided with a semiconductor substrate 100. In the illustrated example, four memory cell array regions R MCA are arranged in the X direction and the Y direction are provided on the semiconductor substrate 100.

[0082] As shown in Figure 6 , for example, a semiconductor storage device is provided with a semiconductor substrate 100, a transistor layer L TR provided on the semiconductor substrate 100, a memory cell array layer L TR provided above the transistor layer L MCA , and a wiring layer M0 provided above the memory cell array layer L MCA .

[0083] [Configuration of Semiconductor Substrate 100]

[0084] The semiconductor substrate 100 is, for example, a semiconductor substrate composed of P-type silicon (Si) containing a P-type impurity such as boron (B). On the surface of the semiconductor substrate 100, an N-type well region containing an N-type impurity such as phosphorus (P), a P-type well region containing a P-type impurity such as boron (B), a semiconductor substrate region in which neither the N-type well region nor the P-type well region is provided, and an insulating region 100I are provided.

[0085] [Configuration of Transistor Layer L TR ]

[0086] As shown in Figure 6As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 100 through an insulating layer. The wiring layer GC includes a plurality of electrodes gc opposite to the surface of the semiconductor substrate 100. These plurality of electrodes gc function as gate electrodes of a plurality of transistors Tr constituting a peripheral circuit PC and electrodes of a plurality of capacitors, respectively. These plurality of electrodes gc are respectively connected to contact electrodes CS. The contact electrodes CS may, for example, be a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, these plurality of contact electrodes CS are connected to a plurality of wirings contained in wiring layers D0, D1, and D2. These plurality of wirings may, for example, be a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0087] [Storage cell array layer L] MCA [Construction]

[0088] For example, Figure 5 As shown, in the storage cell array layer L MCA Storage cell array region R MCA Multiple storage blocks (BLKs) are configured and arranged in the Y direction. For example, Figure 7 As shown, a memory block BLK has multiple string cells SU arranged in the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is disposed between two adjacent memory blocks BLK in the Y direction. For example... Figure 7 As shown, an inter-string insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string units SU in the Y direction.

[0089] For example, Figure 6 As shown, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0090] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction. Furthermore, a contact electrode CC extending in the Z direction is provided at one end of the conductive layer 110 in the X direction.

[0091] For example, Figure 6As shown, a conductive layer 111 is disposed below the conductive layer 110. The conductive layer 111 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 is disposed between the conductive layer 111 and the conductive layer 110.

[0092] A conductive layer 112 is disposed below the conductive layer 111. The conductive layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Alternatively, the conductive layer 112 may also contain a conductive layer of metals such as tungsten (W), tungsten silicide, or other conductive layers. Furthermore, an insulating layer 101 is disposed between the conductive layer 112 and the conductive layer 111.

[0093] Conductive layer 112 serves as the source line SL ( Figure 2 ) to perform its function. Conductive layer 112, for example, with respect to the memory cell array region R MCA ( Figure 5 All storage blocks (BLK) contained in the ) are shared by the BLK.

[0094] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 2 The gate electrodes of the multiple source-side selection transistors STSb connected thereto function as well. The conductive layer 111 is electrically independent for each memory block BLK.

[0095] Additionally, one or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 serve as the source-side selected gate line (SGS). Figure 2 The gate electrodes of the multiple source-side selection transistors (STS) connected thereto function as a plurality of conductive layers 110. These multiple conductive layers 110 are electrically independent for each memory block (BLK).

[0096] Additionally, multiple conductive layers 110 located above this serve as word lines WL ( Figure 2 ) and multiple storage units MC connected to it Figure 2 The gate electrode functions. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0097] Additionally, one or more conductive layers 110 located above this serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 2 The gate electrode of the device performs its function. For example, as... Figure 7 As illustrated, the width Y in the Y direction of these plurality of conductive layers 110 SGD The width Y in the Y direction of the other conductive layers 110 WL Small. Also, for example, Figure 7As illustrated, the aforementioned inter-string unit insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. These multiple conductive layers 110 are electrically independent for each string unit SU.

[0098] For example, Figure 7 As shown, the semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor pillars 120 serve as a memory string (MS). Figure 2 The channel region of the multiple memory cells MC and selection transistors (STD, STS, STSb) contained in the semiconductor pillar 120 functions as such. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). Figure 6 As shown, the semiconductor pillar 120 has a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central part.

[0099] The outer peripheral surface of the semiconductor pillar 120 is surrounded by a plurality of conductive layers 110 and 111, respectively, and is opposite to these conductive layers 110 and 111. The lower end of the semiconductor pillar 120 is connected to the conductive layer 112. The upper end of the semiconductor pillar 120 is connected to the bit line BL via an impurity region 121 containing N-type impurities such as phosphorus (P), contact electrodes Ch and Vy. The bit line BL extends in the Y direction and is arranged in the X direction.

[0100] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. For example, Figure 8 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the conductive layer 112.

[0101] In addition, Figure 8 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0102] [Read the action]

[0103] Next, the read operation of the semiconductor memory device in this embodiment will be described. Figure 9 It is a schematic cross-sectional view used to illustrate the readout action.

[0104] Furthermore, in the following explanation, the word line WL that sometimes becomes the object of the action is referred to as the selection word line WL. S The word lines other than these are called non-selection word lines WL. U Additionally, in the following explanation, the connection to the select word line WL in the multiple storage units MC contained in the string unit SU, which has become the object of the action, is discussed. S The following explanation illustrates an example of a read operation performed by a memory cell MC (hereinafter sometimes referred to as a "selection memory cell MC"). Furthermore, in the following explanation, a configuration including multiple such selection memory cell MCs may sometimes be referred to as a selection page PG.

[0105] In the readout operation, for example, a voltage V is supplied to the bit line BL. DD Additionally, a voltage V is supplied to the source line SL. SRC Voltage V SRC It can be compared to the ground voltage V SS Large, or can be related to ground voltage V SS Equal. Voltage V DD Specific voltage V SRC big.

[0106] Additionally, during the readout operation, a voltage V is supplied to the gate line SGD on the drain side. SG Voltage V SG Specific voltage V DD Large. Additionally, the voltage V SG With voltage V DD The voltage difference is greater than the threshold voltage at which the drain-side selective transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side selective transistor STD, transferring voltage V. DD .

[0107] Additionally, during the readout operation, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG Specific voltage V SRC Large. Additionally, the voltage V SG With voltage V SRC The voltage difference is greater than the threshold voltage required for the source-side select transistors STS and STSb to function as NMOS transistors. Therefore, an electron channel is formed in the channel region of the source-side select transistors STS and STSb, transferring voltage V. SRC .

[0108] Additionally, during the readout action, the non-selected word line WL is... U Supply readout voltage V READ Read the voltage V. READ Specific voltage V DD VSRC In addition, the read-through voltage V READ is larger than the threshold voltage of the storage unit MC when the storage unit MC functions as an NMOS transistor regardless of the data recorded in the storage unit MC. Therefore, a channel of electrons is formed in the channel region of the non-selected storage unit MC, and the voltage V DD , V SRC is transmitted to the selected storage unit MC. DD SRC

[0109] In addition, in the read operation, the read voltage V S is supplied to the selected word line WL CGR . The read voltage V CGR is smaller than the read-through voltage V READ . The voltage difference between the read voltage V CGR and V SRC is larger than the threshold voltage of the storage unit MC in which a part of the data is recorded. Therefore, the storage unit MC in which a part of the data is recorded becomes an ON state. Therefore, a current flows in the bit line BL connected to such a storage unit MC. On the other hand, the voltage difference between the read voltage V CGR and V SRC is smaller than the threshold voltage of the storage unit MC in which a part of the data is recorded. Therefore, the storage unit MC in which a part of the data is recorded becomes an OFF state. Therefore, no current flows in the bit line BL connected to such a storage unit MC.

[0110] In addition, in the read operation, whether a current flows in the bit line BL is detected by the sense amplifier module SAM Figure 1 , and thereby the ON state / OFF state of the storage unit MC is detected, and thereby the data indicating the state of the storage unit MC is acquired.

[0111] In addition, in the read operation, an AND, OR, or the like operation process is performed on the data indicating the state of the storage unit MC as necessary, and thereby the data recorded in the storage unit MC is calculated.

[0112] [Write Operation]

[0113] Next, the write operation of the semiconductor storage device of the present embodiment will be described. Figure 10 is a schematic cross-sectional view for describing the write operation.

[0114] Further, in the following description, an example in which the write operation is performed on a plurality of selected storage units MC corresponding to a selected page PG will be described.

[0115] ​​In the write operation, for example, a voltage V W is supplied to the bit line BL connected to the selected memory cell MC in which the adjustment of the threshold voltage is performed SRC . In addition, a voltage V P is supplied to the bit line BL connected to the selected memory cell MC in which the adjustment of the threshold voltage is not performed DD . Hereinafter, the selected memory cell MC in which the adjustment of the threshold voltage is performed among the plurality of selected memory cells MC is sometimes referred to as a "write memory cell MC", and the selected memory cell MC in which the adjustment of the threshold voltage is not performed is sometimes referred to as a "prohibit memory cell MC".

[0116] In addition, in the write operation, a voltage V SGD is supplied to the drain side selection gate line SGD.

[0117] The voltage V SGD is larger than the voltage V SRC . In addition, the voltage V SGD is larger than the voltage V SRC . Therefore, the channel region of the drain side selection transistor STD connected to the bit line BL W forms a channel of electrons, and the voltage V SRC is transferred.

[0118] On the other hand, the voltage V SGD is smaller than the voltage V DD . Therefore, the drain side selection transistor STD connected to the bit line BL P becomes in an off state.

[0119] In addition, in the write operation, a voltage V SRC is supplied to the source line SL, and a ground voltage V SS is supplied to the source side selection gate lines SGS, SGSb. Thereby, the source side selection transistors STS, STSb become in an off state.

[0120] In addition, in the write operation, a write pass voltage V U is supplied to the non-selected word line WL PASS . The write pass voltage V PASS is larger than the read pass voltage V READ . In addition, the write pass voltage V PASS is larger than the voltage V SRCRegardless of the data recorded in the memory cell MC, the voltage difference is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, delivering a voltage V to the written memory cell MC. SRC .

[0121] Additionally, during the write operation, select the word line WL. S Supply programming voltage V PGM Programming voltage V PGM Write voltage V PASS big.

[0122] Here, for example, Figure 10 As shown, the path is connected to the bit line BL W The channel of the semiconductor pillar 120 is supplied with voltage V SRC In such a semiconductor pillar 120 with select word line WL S A relatively large electric field is generated between them. As a result, electrons in the channel of semiconductor pillar 120 pass through tunnel insulating film 131 ( Figure 8 And towards the charge storage film 132 ( Figure 8 This tunneling occurs within the memory cell (MC). Consequently, the threshold voltage for writing to the memory cell increases.

[0123] Additionally, connected to bit line BL P The channel of the semiconductor pillar 120 becomes electrically floating, and the potential of the channel is transmitted through the non-select word line WL. U The voltage rises to the write voltage V due to capacitive coupling. PASS Left and right. In such a semiconductor pillar 120 and select word line WL S Only a smaller electric field than the one described above is generated between them. Therefore, electrons in the channel of semiconductor pillar 120 do not accumulate in charge storage film 132. Figure 8 Tunneling occurs within the memory cell (MC). Therefore, the threshold voltage of the memory cell (MC) is prevented from increasing.

[0124] [Erase action]

[0125] Next, the erasure operation of the semiconductor memory device in this embodiment will be described. Figure 11 It is a schematic cross-sectional view used to illustrate the erasing action.

[0126] Furthermore, the following description provides an example of performing an erase operation on the storage block BLK that has become the object of the action.

[0127] During the erase operation, an erase voltage V is supplied to the bit line BL and the source line SL. ERA Erasure voltage V ERA For example, it can be compared to the programming voltage V. PGMLarge, and can also be related to the programming voltage V PGM equal.

[0128] Additionally, during the erase operation, a voltage V is supplied to the gate line SGD on the drain side. SG Voltage V SG ′Ratio of erase voltage V ERA Small. Therefore, GIDL (Gate Induced Drain Leakage) is generated in the drain-side select transistor STD, producing electron-hole pairs. Additionally, electrons move towards the bit line BL, and holes move towards the memory cell MC.

[0129] Additionally, during the erase operation, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG "Comparison of erase voltage V" ERA Small. Therefore, GIDL is generated in the source-side selective transistors STS and STSb, producing electron-hole pairs. Furthermore, electrons move towards the source line SL, and holes move towards the memory cell MC.

[0130] Additionally, during the erase operation, a ground voltage V is supplied to the word line WL. SS Therefore, holes in the channel of semiconductor pillar 120 pass through tunnel insulating film 131 ( Figure 8 And towards the charge storage film 132 ( Figure 8 The memory cell (MC) tunnels through the storage medium. As a result, the threshold voltage of the storage cell (MC) decreases.

[0131] In addition, during the erasing action, refer to Figure 4 The transistor T described BL It becomes disconnected. Therefore, during the erase operation, the sense amplifier module SAM is electrically disconnected from the bit line BL.

[0132] Programming voltage V PGM [Generation method]

[0133] For reference Figure 10 As explained, in the semiconductor memory device of the first embodiment, the select word line WL is... S Supply programming voltage V PGM Here, the programming voltage V PGM This is a relatively high voltage among the voltages used in semiconductor memory devices. Therefore, the control programming voltage V in the peripheral circuit PC is sometimes relevant. PGM Concerns arise regarding the pressure resistance, reliability, and lifespan of the components.

[0134] Therefore, in the semiconductor memory device of the first embodiment, the programming voltage V is generated by the following method. PGMThis suppresses concerns related to the aforementioned pressure resistance, reliability, and lifespan.

[0135] Figure 12 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device of this embodiment. Figure 13 It is a schematic waveform diagram used to illustrate the write operation.

[0136] exist Figure 12 The example shows one memory cell (MC). Additionally, in... Figure 12 The diagram illustrates word lines WLa and WLb connected to the memory cell MC. These two word lines, WLa and WLb, are connected to other components in the peripheral circuit PC via transistors Ta and Tb and voltage supply lines Lwla and Lwlb, respectively. Furthermore, a common signal supply line Lg1 is connected to the gate electrodes of transistors Ta and Tb. Additionally, the memory cell MC is connected via bit line BL and transistor Tb. BL And connected to the peripheral circuit PC. Additionally, in transistor T... BL The gate electrode is connected to the signal supply line Lg2.

[0137] Furthermore, transistors Ta and Tb can be, for example, references. Figure 3 The transistor T described BLK Additionally, signal supply line Lg1 can be a reference. Figure 3 The signal supply line BLKSEL is described. Additionally, the voltage supply lines Lwla and Lwlb can be referenced, for example. Figure 3 The voltage supply line CG is described above. Additionally, the signal supply line Lg2 can be used as a reference. Figure 4 The signal supply line BLS is described.

[0138] In addition, such as Figure 12 As shown, the semiconductor memory device of this embodiment includes capacitors Cba and Cbb connected to word lines WLa and WLb, and wiring Lb connected to these capacitors Cba and Cbb.

[0139] like Figure 13 As shown, during the timing t101 of the write operation in this embodiment, a write pass voltage V is supplied to the voltage supply lines Lw1a and Lwlb. PASS Supply voltage V to signal supply line Lg1 PGMH Supply ground voltage V to wiring Lb SS BL to the bit line W Supply voltage V SRC Supply voltage V to signal supply line Lg2 DD Voltage V PGMH For example, the voltage V described later. PGM-α. The voltage V PASS .

[0140] At timing t102, the voltage V PGM -α is supplied to the voltage supply line Lwla. The voltage V PGM -α is smaller than the program voltage V PGM . Thus, the voltage V PGM -α is transmitted to the word line WLa.

[0141] At timing t103, the ground voltage V SS is supplied to the signal supply lines Lgl, Lg2. Thus, the word lines WLa, WLb and the bit line BL become in a floating state. Further, the voltage of the signal supply line Lgl can not be the ground voltage V SS .

[0142] At timing t104, the voltage of the wiring Lb is raised from the ground voltage V SS to the voltage α.

[0143] Here, as explained with reference to Figure 12 , the capacitors Cba, Cbb are provided between the wiring Lb and the word lines WLa, WLb. Thus, if the voltage of the wiring Lb is raised from the ground voltage V SS to the voltage α, the voltages of the word lines WLa, WLb also increase by the voltage α. Thus, the voltage of the word line WLa rises to the program voltage V PGM . In addition, in the illustrated example, the voltage of the word line WLb increases to the voltage V PASS larger than the write pass voltage V PASS + α.

[0144] Further, if the voltages of the word lines WLa, WLb increase by the voltage α, the potential of the channel of the electrons formed on the outer peripheral surface of the semiconductor pillar 120 by the capacitive coupling between the word line WL and the semiconductor pillar 120 also increases by the voltage α or so. Thus, the voltage of the bit line BL also increases by the voltage α or so. In the illustrated example, the voltage of the bit line BL increases to the voltage V SRC + α.

[0145] Further, in the illustrated example, at timing t104, the ground voltage V SS is supplied to the voltage supply lines Lwla, Lwlb.

[0146] At timing t105, the voltage V DD is supplied to the signal supply line Lg2. Thus, the voltage V SRCTherefore, a reference is provided to each cabling section. Figure 10 The voltage is explained.

[0147] Under timer t106, the voltage of wiring Lb is reduced from voltage α to ground voltage V. SS Additionally, voltage V is supplied to signal supply line Lg1. PGMH As a result, the charge in the word lines WLa and WLb is discharged, dropping to the ground voltage V. SS .

[0148] At timer t107, the voltage of signal supply lines Lg1 and Lg2 is reduced to the ground voltage V. SS .

[0149] Here, for example, in transistors Ta and Tb are references Figure 3 The transistor T described BLK Furthermore, the voltage supply lines Lwla and Lwlb are references. Figure 3 In the case of the voltage supply line CG, during the write operation, the voltage is supplied from the output terminal of the voltage generation unit vg1 to the transistor T. BLK The maximum voltage in the current path up to the source terminal is greater than the programming voltage V. PGM Small voltage V PGM -α.

[0150] According to this method, since the transmitted voltage is reduced, it is possible to suppress the transistor T located in the aforementioned current path. WLS T WLU T DRV1 T DRV3 This addresses concerns regarding the voltage withstand capability, reliability, and lifespan of the voltage generation unit Vg1. Furthermore, transistors with smaller circuit areas can be used. Additionally, the amount of material supplied to the aforementioned transistor T can be reduced. BLK The maximum voltage V supplied by the gate electrode of the same type PGMH Therefore, it is possible to suppress transistor T BLK The generation of leakage current between them.

[0151] [Second Implementation]

[0152] Next, refer to Figure 14 The semiconductor memory device of the second embodiment will now be described. Figure 14 This is a schematic waveform diagram used to illustrate the write operation of the semiconductor memory device in this embodiment.

[0153] The semiconductor memory device of the second embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. However, a portion of the write operation in the semiconductor memory device of the second embodiment differs from a portion of the write operation in the semiconductor memory device of the first embodiment.

[0154] As Figure 14 shown, the operation at timings t201, t202 of the write operation of the present embodiment is the same as the operation at timings t101, t102 of the write operation of the first embodiment.

[0155] At timing t203, the voltage V1 is supplied to the signal supply line Lgl, and the ground voltage V SS is supplied to the signal supply line Lg2. At this time, the voltage V1 is larger than the write pass voltage V PASS . In addition, the voltage difference between the voltage V1 and the write pass voltage V PASS is larger than the threshold voltage of the transistor Tb. Therefore, the transistor Tb is maintained in the on state. On the other hand, the voltage difference between the voltage V1 and the voltage V PGM - α is smaller than the threshold voltage of the transistor Ta. Therefore, the transistor Ta becomes in the off state. Thus, the word line WLa is selectively brought into the floating state.

[0156] At timing t204, the voltage of the wiring Lb is raised from the ground voltage V SS to the voltage α. At this time, the voltage of the word line WLa is raised to the program voltage V PGM in the same manner as in the first embodiment. On the other hand, the voltage of the word line WLb is maintained at the write pass voltage V PASS . Further, in the illustrated example, at timing t204, the voltage of the voltage supply line Lwla is maintained at the voltage V PGM - α. This is to maintain the transistor Ta in the off state. In addition, the voltage of the voltage supply line Lwlb is maintained at the write pass voltage V PASS . This is because the transistor Tb is in the on state.

[0157] The operations at timings t205 to t207 are basically the same as the operations at timings t105 to t107 of the write operation of the first embodiment. However, at timing t206, the ground voltage V SS is supplied to the voltage supply lines Lwla, Lwlb.

[0158] According to such a method, it is possible to maintain the voltage of the non-selected word line WL U at the write pass voltage V PASS .

[0159] [3rd Embodiment]

[0160] Next, the semiconductor storage device of the third embodiment will be described with reference to Figure 15 . Figure 15 is a schematic cross-sectional view for describing the write operation of the semiconductor storage device of the present embodiment.

[0161] The semiconductor memory device of the third embodiment is configured essentially the same as that of the semiconductor memory device of the first or second embodiment. However, in the semiconductor memory device of the third embodiment, the source line SL is electrically independent for each string cell SU. Figure 15 The conductive layer 312, which functions as the source line SL, is illustrated in the diagram. The conductive layer 312 is constructed in essentially the same way as the conductive layer 112. However, the conductive layer 312 is electrically independent for each string cell SU.

[0162] In the semiconductor memory device of the third embodiment, during the write operation, the configuration of the string cell SU, excluding the select page PG, is used as capacitors Cba and Cbb. Figure 12 For example, when the serial cell SUa includes the selection page PG, the semiconductor pillar 120 corresponding to the serial cells SUb to SUe functions as an electrode of one of the capacitors Cba and Cbb. Additionally, multiple conductive layers 110 function as electrodes of the other of the capacitors Cba and Cbb. Furthermore, the conductive layer 312 (source line SL) corresponding to the serial cells SUb to SUe functions as wiring Lb.

[0163] The write operation in the third embodiment is performed essentially the same as the write operation in the first or second embodiment. However, in the write operation of the semiconductor memory device in the third embodiment, for example, the voltage of the conductive layer 312 corresponding to the serial cell SUa is set to a voltage greater than the voltage of the conductive layers 312 corresponding to the serial cells SUb to SUe. Furthermore, the voltage of the source-side select gate lines SGS and SGSb is adjusted to a level that makes the source-side select transistors STS and STSb corresponding to the serial cell SUa in the off state and the source-side select transistors STS and STSb corresponding to the serial cells SUb to SUe in the on state. Additionally, in Figure 13 The timer t104 or Figure 14 At timing t204, the voltage α of the conductive layer 312 corresponding to the serial cells SUB~SUe is increased. Simultaneously, the potential of the channel on the outer peripheral surface of the semiconductor pillar 120 formed in the serial cells SUB~SUe increases by α. Furthermore, through the capacitive coupling between the semiconductor pillar 120 and the conductive layer 110, the voltage α of the conductive layer 110 increases.

[0164] Furthermore, when using this method, if the voltage of the conductive layer 312 corresponding to the serial units SUB~SUe is voltage V SRC If the voltage varies, the threshold voltage of the memory cell MC in the serial cells SUB to SUBe may change. Therefore, the voltage of the conductive layer 312 corresponding to the serial cells SUB to SUBe is preferably at least greater than the voltage V. SRC big.

[0165] Furthermore, when using this method, if the voltage of the conductive layer 312 corresponding to the serial cells SUB~SUe is the write pass voltage V PASS If the voltage is too low, an electron channel may not form on the outer peripheral surface of the semiconductor pillar 120. Therefore, the voltage of the conductive layer 312 corresponding to the string cells SUB~SUe is preferably, for example, proportional to the write pass voltage V. PASS With readout voltage V READ The voltage difference of the same degree V PASS -V READ Small.

[0166] [Fourth Implementation]

[0167] Next, refer to Figure 16 and Figure 17 The semiconductor memory device of the fourth embodiment will now be described. Figure 16 and Figure 17 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to this embodiment. Furthermore, with... Figure 16 The position of the XZ section in the Y direction and its relation to Figure 17 The XZ sections correspond to different positions in the Y direction.

[0168] The semiconductor memory device of the fourth embodiment is configured essentially the same as the semiconductor memory device of the first or second embodiment. However, as Figure 17 As shown, the semiconductor memory device of the fourth embodiment includes an insulating layer 401 and a conductive layer 410 covering the ends of a plurality of conductive layers 110 in the X direction. The conductive layer 410 is used as a reference. Figure 12 The electrodes of capacitors Cba and Cbb, and wiring Lb, are described to perform their functions.

[0169] exist Figure 16 and Figure 17 The diagram illustrates the ends of multiple conductive layers 110 arranged in the Z direction in the X direction. Additionally, in... Figure 16 The diagram illustrates multiple contact electrodes CC arranged in the X direction. Figure 17 The diagram illustrates a conductive layer 410 and an insulating layer 401. The conductive layer 410 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W). The conductive layer 410 has multiple opposing regions 411 and multiple connecting regions 412. The multiple opposing regions 411 extend in the X direction and are respectively opposite to the upper surfaces of the multiple conductive layers 110 arranged in the Z direction. The connecting regions 412 extend in the Z direction and connect two opposing regions at different heights. The insulating layer 401 includes, for example, silicon oxide (SiO2).

[0170] [Fifth Implementation]

[0171] Next, the semiconductor memory device of the fifth embodiment will be described.

[0172] In embodiments 1 to 4, with the word line WL electrically disconnected from the peripheral circuit PC, the programming voltage V is generated using capacitive coupling. PGM This suppresses concerns related to the withstand voltage, reliability, and lifespan of the components in the peripheral circuit PC.

[0173] However, this method is merely illustrative. For example, if a negative voltage is supplied to the bit line BL during a write operation, the negative voltage supplied to the select word line WL during the write operation can be reduced. S The supplied voltage.

[0174] Figure 18 This is a schematic cross-sectional view used to explain the write operation of the semiconductor memory device according to the fifth embodiment. The write operation of the fifth embodiment is basically the same as that described in the reference diagram. Figure 10 The write operation described is performed in the same way. However, in the write operation of the fifth embodiment, as... Figure 18 As shown, the voltage supplied to the bit line BL, word line WL, and drain-side gate select line SGD is compared with the reference voltage. Figure 10 The voltage β is explained for each voltage.

[0175] Furthermore, when writing operations are performed in such a way, for example to the bit line BL... W The voltage V supplied with negative polarity SRC -β. In this case, as a reference Figure 4 The transistor T described BL It is preferable to use a configuration that can supply a negative voltage. This will be explained below.

[0176] Figure 19 The transistor T shown is from the first comparative example. BL A schematic cross-sectional view of its composition. Figure 19 In, as transistor T BL The example illustrates the structure of a transistor T. BL0 Transistor T BL0 The semiconductor substrate 100 is disposed on a P-type semiconductor substrate. The source electrode CS of the semiconductor substrate 100 is... S The contact portion is provided with an impurity region R containing N-type impurities. n+ In the semiconductor substrate 100, with the drain electrode CS D The contact portion is provided with an impurity region R containing N-type impurities. n+ A portion of the semiconductor substrate 100 serves as transistor T. BL0function. A diffusion region R containing an N-type impurity is provided between the channel region and the drain electrode CS D n- In addition, the semiconductor substrate 100 is provided with an electrode CS Sub that supplies a substrate voltage to the semiconductor substrate 100. A ground voltage V Sub is supplied to the electrode CS SS .

[0177] In such a configuration, for example, if a voltage of a negative polarity is supplied to the source electrode CS BL0 of the transistor T S , the electrode CS Sub and the source electrode CS S become a forward-biased relationship, and a large current sometimes flows to the semiconductor substrate 100. In addition, as a result, the entire device sometimes is destroyed.

[0178] Figure 20 is a schematic cross-sectional view showing the configuration of the transistor T BL of the second comparative example. In Figure 20 , the transistor T BL is exemplified as a configuration example of the transistor T BL1 . In the example of Figure 20 , an N-type well W n containing an N-type impurity is provided in the P-type semiconductor substrate 100. In addition, a P-type well W n containing a P-type impurity is provided in the N-type well W p . The transistor T BL1 is basically configured similarly to the transistor T BL0 . However, the transistor T BL1 is provided in the P-type well W p . Further, in the example of Figure 20 , an electrode CS n is provided in the N-type well W Wn . In addition, an electrode CS p is provided in the P-type well W Wp . In addition, a voltage V Wn is supplied to the electrode CS DD , and a voltage V Wp ' is supplied to the electrode CS SS .

[0179] In such a configuration, for example, when a voltage of a negative polarity is supplied to the source electrode CS BL1 of the transistor T S , by also setting the voltage V Wp ' of the electrode CS SS to a voltage of a negative polarity, a voltage of a negative polarity can be appropriately transmitted. ​

[0180] However, in such a configuration, it is necessary to provide the N-type well W n and the P-type well W p in the semiconductor substrate 100. Thus, the circuit area can sometimes increase.

[0181] Therefore, in the present embodiment, as the transistor T BL , a transistor that can both suppress an increase in the circuit area and appropriately transmit a voltage of a negative polarity is employed.

[0182] Figure 21 is a schematic cross-sectional view showing a configuration of the transistor T BL of the fifth embodiment. In Figure 21 , as a configuration example of the transistor T BL , the transistor T BL2 is exemplified. That is, in Figure 21 , the semiconductor substrate 100, the semiconductor layer 510 opposed to the upper surface of the semiconductor substrate 100, and the gate insulating film 501 of silicon oxide (SiO2) or the like provided between the semiconductor substrate 100 and the semiconductor layer 510 are exemplified.

[0183] In the illustrated example, the impurity region R n+ containing an impurity of the N-type is provided on the upper surface of the semiconductor substrate 100. This impurity region R n+ functions as a gate electrode of the transistor T BL2 . This impurity region R n+ is connected to a contact electrode not shown. This impurity region R n+ is connected to the signal supply line BLS Figure 4 via the contact electrode.

[0184] The semiconductor layer 510 is, for example, a semiconductor layer of polysilicon (Si) or the like. The semiconductor layer 510 has the source region 511 and the drain region 512 and the gate region 513 provided therebetween.

[0185] The source region 511 is provided on the upper surface of the insulating region 100I. The upper surface of the source region 511 is connected to the source electrode CS S . The impurity region R n+ containing an impurity of the N-type is provided in the source region 511.

[0186] The drain region 512 is provided on the upper surface of the insulating region 100I. The upper surface of the drain region 512 is connected to the drain electrode CS D . The impurity region R D containing an impurity of the N-type is provided in the contact portion of the drain region 512 with the drain electrode CS n+Additionally, a diffusion region R containing N-type impurities is provided in the region outside the drain region 512. n- Diffusion region R n- The concentration of N-type impurities in the impurity region R is higher than that in the impurity region R. n+ The concentration of N-type impurities in the sample is low.

[0187] Gate region 513 is disposed on the upper surface of gate insulating film 501. An impurity region R containing P-type impurities is disposed within gate region 513. p The lower surface of the gate region 513 is separated from the impurity region R of the semiconductor substrate 100 by the gate insulating film 501. n+ relatively.

[0188] In such a configuration, for example, even if the transistor T BL2 Source electrode CS S Supplying a negative voltage will not generate the current problem described above. Therefore, a negative voltage can be transmitted appropriately.

[0189] Furthermore, in this configuration, it is not necessary to provide an N-type well W on the semiconductor substrate 100. n and P-type trap W p Therefore, compared with the reference Figure 20 The transistor T described BL1 In comparison, it can be implemented with a smaller circuit area.

[0190] [Sixth Implementation]

[0191] Next, refer to Figure 22 The semiconductor memory device of the sixth embodiment will now be described. Figure 22 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to this embodiment.

[0192] The semiconductor memory device of the sixth embodiment is configured in essentially the same way as the semiconductor memory device of the fifth embodiment. However, in the sixth embodiment, an N-type well W containing N-type impurities is provided on the semiconductor substrate 100. n Furthermore, in the sixth embodiment, the semiconductor memory device replaces the transistor T. BL2 And possessing transistor T BL3 .

[0193] transistor T BL3 Basically related to transistor T BL2 The same configuration is used. However, in the sixth embodiment, in the N-type trap W... n The upper surface is provided with an impurity region R containing P-type impurities. p+ The impurity region R p+ As transistor T BL3functions as the gate electrode of the transistor T

[0194] In the transistor T BL3 , either a positive voltage or a negative voltage can be used as the gate voltage of the transistor T BL3 .

[0195] [Other Embodiments]

[0196] The semiconductor storage devices of Embodiments 1 to 6 have been described above. However, the above description is merely an example, and the specific configuration, operation method, and the like can be appropriately adjusted.

[0197] For example, the operation method described with reference to Figure 13 and Figure 14 is merely an example. In Figure 13 and Figure 14 , the magnitude of the voltage supplied to each wiring, the timing of supplying the voltage, and the like can be appropriately adjusted. For example, the voltage transmitted to the voltage supply lines Lwla and Lwlb at the timing t101 of Figure 13 may also be a voltage V PASS - α smaller than the write-through voltage V PASS - α.

[0198] Further, the capacitors Cba and Cbb in Figure 12 can be implemented by any configuration. For example, the capacitors Cba and Cbb can also be implemented by the semiconductor substrate 100 ( Figure 6 ) and the electrode gc ( Figure 6 ). Further, the capacitors can also be implemented by a configuration using a contact electrode CC or the like. Further, as described with reference to Figure 15 , the capacitors can also be implemented by the conductive layer 110 and the semiconductor pillar 120. Further, as described with reference to Figure 17 , the capacitors can also be implemented by the conductive layer 110 and the conductive layer 410. Further, the capacitors can also be implemented by a configuration other than the above.

[0199] Further, the semiconductor storage devices of Embodiments 1 to 4 can have any one of the transistor T BL0 ( Figure 19 ), the transistor T BL1 ( Figure 20 ), the transistor T BL2 ( Figure 21 ), and the transistor T BL3 ( Figure 22 ) as the transistor T BL ( Figure 4 ). Further, in the semiconductor storage devices of Embodiments 1 to 4, the transistor T BL( Figure 4 ).

[0200] [Other]

[0201] While some embodiments of the application have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. The novel embodiments can be implemented in other various manners, and various omissions, substitutions, and changes can be made without departing from the scope of the application. The embodiments and modifications thereof contain in the scope, spirit of the application, and are included in the scope of the application recited in the claims and the equivalent thereof.

Claims

1. A semiconductor memory device comprising: a semiconductor substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the semiconductor substrate; a first semiconductor pillar extending in the first direction and opposing the plurality of first conductive layers; a first charge accumulation film provided between the plurality of first conductive layers and the first semiconductor pillar; a first memory transistor in which one of the plurality of first conductive layers is provided as a gate electrode and the first semiconductor pillar is provided as a channel region; a first transistor electrically connected to the gate electrode of the first memory transistor; a first voltage supply line electrically connected to the gate electrode of the first memory transistor via the first transistor; a first signal supply line electrically connected to the gate electrode of the first transistor; a first capacitor electrically connected to the gate electrode of the first memory transistor without passing through the first transistor; and a first wiring connected to a current path between the gate electrode of the first memory transistor and the first transistor via the first capacitor, wherein the plurality of first conductive layers include a portion functioning as one electrode of the first capacitor, wherein at a first timing of a write operation for the first memory transistor, a voltage of the first voltage supply line is a first voltage, a voltage of the first signal supply line is a second voltage, and a voltage of the first wiring is a third voltage, wherein at a second timing later than the first timing of the write operation for the first memory transistor, the voltage of the first signal supply line is decreased from the second voltage to a fourth voltage smaller than the second voltage, and wherein at a third timing later than the second timing of the write operation for the first memory transistor, the voltage of the first wiring is increased from the third voltage to a fifth voltage greater than the third voltage.

2. The semiconductor memory device according to claim 1, comprising: a memory string including the first memory transistor and a second memory transistor; a second transistor electrically connected to a gate electrode of the second memory transistor; a second voltage supply line electrically connected to the gate electrode of the second memory transistor via the second transistor; and a second capacitor electrically connected to the gate electrode of the second memory transistor without passing through the second transistor.

3. The semiconductor memory device according to claim 2, wherein a voltage of the second voltage supply line is maintained at a sixth voltage smaller than the first voltage from the first timing to the third timing of the write operation for the first memory transistor.

4. The semiconductor memory device according to claim 1, comprising: a second semiconductor pillar extending in the first direction and opposing the plurality of first conductive layers; and a second charge accumulation film provided between the plurality of first conductive layers and the second semiconductor pillar, wherein the second semiconductor pillar includes a portion functioning as the other electrode of the first capacitor.

5. The semiconductor memory device according to claim 1, comprising: a first region and a second region arranged in a second direction intersecting the first direction, wherein the first region includes: the first semiconductor pillar; and the first capacitor, and wherein the second region includes: the second semiconductor pillar; and the second capacitor. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first charge accumulation film, The second region includes: A plurality of contact electrodes extending in the first direction and connected to the plurality of first conductive layers, respectively; and A second conductive layer opposite to the plurality of first conductive layers, The second conductive layer includes a portion functioning as an electrode of the other party of the first capacitor.

6. A control method of a semiconductor storage device, the semiconductor storage device including: a semiconductor substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the semiconductor substrate; a first semiconductor pillar extending in the first direction and opposite to the plurality of first conductive layers; a first charge accumulation film provided between the plurality of first conductive layers and the first semiconductor pillar; a first storage transistor in which one of the plurality of first conductive layers is provided as a gate electrode and the first semiconductor pillar is provided as a channel region; a first transistor electrically connected to the gate electrode of the first storage transistor; a first voltage supply line electrically connected to the gate electrode of the first storage transistor via the first transistor; a first signal supply line electrically connected to the gate electrode of the first transistor; a first capacitor electrically connected to the gate electrode of the first storage transistor without passing through the first transistor; and a first wiring connected to a current path between the gate electrode of the first storage transistor and the first transistor via the first capacitor, the plurality of first conductive layers include a portion functioning as an electrode of one party of the first capacitor, in the control method, at a first timing of a write operation to the first storage transistor, a voltage of the first voltage supply line is a first voltage, a voltage of the first signal supply line is a second voltage, and a voltage of the first wiring is a third voltage, at a second timing later than the first timing of the write operation to the first storage transistor, the voltage of the first signal supply line is decreased from the second voltage to a fourth voltage smaller than the second voltage, at a third timing later than the second timing of the write operation to the first storage transistor, the voltage of the first wiring is increased from the third voltage to a fifth voltage larger than the third voltage.

7. The control method of a semiconductor storage device according to claim 6, the semiconductor storage device including: a memory string including the first storage transistor and a second storage transistor; a second transistor electrically connected to a gate electrode of the second storage transistor; a second voltage supply line electrically connected to the gate electrode of the second storage transistor via the second transistor; and a second capacitor electrically connected to the gate electrode of the second storage transistor without passing through the second transistor.

8. The control method of a semiconductor storage device according to claim 7, from the first timing to the third timing of the write operation to the first storage transistor, a voltage of the second voltage supply line is maintained at a sixth voltage smaller than the first voltage.

9. The control method of a semiconductor storage device according to claim 6, the semiconductor storage device including: ​ a second semiconductor pillar extending in the first direction opposite to the plurality of first conductive layers; and a second charge accumulation film provided between the plurality of first conductive layers and the second semiconductor pillar, the second semiconductor pillar includes a portion functioning as an electrode on the other side of the first capacitor.

10. The control method of a semiconductor storage device according to claim 6, the semiconductor storage device has a first region and a second region arranged in a second direction intersecting the first direction, the first region includes: the first semiconductor pillar; and the first charge accumulation film, the second region includes: a plurality of contact electrodes extending in the first direction and connected to the plurality of first conductive layers, respectively; and a second conductive layer opposite to the plurality of first conductive layers, the second conductive layer includes a portion functioning as an electrode on the other side of the first capacitor.

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