A semiconductor structure and a method of fabricating the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The application adds a plasma elimination component composed of a diode and a capacitor in parallel, and the plasma elimination component is electrically connected to a device to be protected and a corresponding pad. Before plasma passes through the corresponding pad to reach the device to be protected during the film layer preparation process of each metal layer and each insulating layer in the later stage of the semiconductor structure, the capacitor stores the electric charge, and the diode releases the electric charge, so that the damage of the plasma to the device to be protected can be effectively prevented, and the measurement error caused by the damage of the plasma is eliminated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] During wafer fabrication, the device structure in the front-end process can be damaged by plasma in the back-end process, affecting its performance and causing inaccurate measurements.

[0003] like Figure 1 As shown, during the wafer fabrication process, after the front-end process of fabricating the high-resistivity polysilicon (HR Poly) structure 11 used as a resistor on the substrate 10, during the subsequent fabrication processes of the first metal layer 121, second metal layer 122, ..., top metal layer 12m, and first insulating layer 131, second insulating layer 132, ..., top insulating layer 13n, plasma can damage the high-resistivity polysilicon structure 11, affecting its performance and causing inaccurate measurements. To clearly illustrate this invention, the following defines some technical terms. Specifically, an opening on the insulating layer between a metal layer and the active region or polysilicon is defined as a contact hole (CT), used to form a contact between the metal layer and the active region or polysilicon; an opening on the insulating layer between metal layers is defined as a through-hole (VIA), used to connect the corresponding metal layers.

[0004] The equivalent circuit diagram of the existing high-resistivity polysilicon structure is as follows: Figure 2 As shown, its territory is as follows Figure 3 As shown. The two ends of the existing high-resistivity polysilicon structure 21 are connected to different pads Pad1 and Pad2 via metal lines 22 and contact holes 23, respectively. For illustrative purposes, Figure 3 The metal line 22 is shown in a transparent effect to illustrate the contact hole 23 and the high-resistivity polysilicon structure 21 below it. Due to the influence of plasma in the subsequent process, the high-resistivity polysilicon structure 21 is damaged by plasma introduction, and the resistance distribution of a large number of samples exceeds the specification limit, thus making the measurement inaccurate.

[0005] Therefore, how to prevent high-resistivity polycrystalline silicon structures from being damaged by plasma, thereby eliminating measurement errors caused by plasma-induced damage, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor structure and its preparation method that can effectively prevent high-resistivity polycrystalline silicon structures from being damaged by plasma, thereby eliminating measurement errors caused by plasma-induced damage.

[0007] To solve the above problems, one embodiment of the present application provides a semiconductor structure, comprising: a device to be protected, two ends of the device to be protected being electrically connected to corresponding pads respectively; and at least one plasma elimination component, the plasma elimination component being electrically connected to the device to be protected and the corresponding pads; wherein before plasma reaches the device to be protected through the corresponding pads, charges are stored by the plasma elimination component and then released, so as to prevent the device to be protected from being damaged by the plasma.

[0008] In some embodiments, the plasma elimination component comprises: a diode, a cathode of the diode being electrically connected to the device to be protected and the corresponding pads; and a capacitor, a first plate of the capacitor being electrically connected to the device to be protected and the corresponding pads; an anode of the diode being electrically connected to a second plate of the capacitor, so that the diode and the capacitor form a parallel structure, so as to store charges by the capacitor before plasma reaches the device to be protected through the corresponding pads, and then release the charges through the diode, so as to prevent the device to be protected from being damaged by the plasma.

[0009] To solve the above problems, one embodiment of the present application further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate being provided with a P-well region; forming a device to be protected and at least one plasma elimination component on the P-well region; electrically connecting two ends of the device to be protected to corresponding pads respectively, and electrically connecting the plasma elimination component to the device to be protected and the corresponding pads, so as to store charges by the plasma elimination component before plasma reaches the device to be protected through the corresponding pads, and then release the charges, so as to prevent the device to be protected from being damaged by the plasma.

[0010] The present application adds the plasma elimination component composed of the diode and the capacitor in parallel, and electrically connects the plasma elimination component to the device to be protected and the corresponding pads, so as to store charges by the capacitor before plasma reaches the device to be protected through the corresponding pads, and then release the charges through the diode, so as to prevent the device to be protected from being damaged by the plasma, and eliminate the measurement error caused by the plasma-induced damage. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0012] Figure 1 Figure 2 is a cross-sectional view of a wafer portion of a semiconductor structure according to an embodiment of the present application;

[0013] Figure 2 Figure 3 is an equivalent circuit diagram of a prior high resistance polysilicon structure;

[0014] Figure 3 Figure 4 is a layout of the high resistance polysilicon structure shown in Figure 3; Figure 2

[0015] Figure 5 is an equivalent circuit diagram of a semiconductor structure according to an embodiment of the present application; Figure 4

[0016] Figure 6 is a layout of a semiconductor structure according to an embodiment of the present application; Figure 5

[0017] Figure 7 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application; Figure 6

[0018] Figure 8 is a schematic diagram of a device structure formed by the main steps of the method of fabricating a semiconductor structure according to an embodiment of the present application. Figures 7A-7D DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments of the present application, any other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present application.

[0020] The present application provides a semiconductor structure, comprising: a device to be protected and at least one plasma elimination component; two ends of the device to be protected are respectively electrically connected to corresponding pads; and the plasma elimination component is electrically connected to the device to be protected and the corresponding pads. Before plasma reaches the device to be protected through the corresponding pads, the plasma elimination component stores and releases electric charges to prevent the plasma from damaging the device to be protected.

[0021] In some embodiments, one plasma elimination component is arranged at each end of the device to be protected, so as to prevent the plasma from damaging the device to be protected at both ends of the device to be protected.

[0022] ​In some embodiments, the plasma elimination component comprises a diode and a capacitor; a cathode of the diode is electrically connected to the device to be protected and the corresponding pad; a first plate of the capacitor is electrically connected to the device to be protected and the corresponding pad; an anode of the diode is electrically connected to a second plate of the capacitor, so that the diode and the capacitor form a parallel structure, to store the charge through the capacitor before the plasma reaches the device to be protected through the corresponding pad, and to release the charge through the diode, so as to prevent the damage of the plasma to the device to be protected. The material, form, size and specification of the diode and the capacitor are not limited in the embodiment.

[0023] Referring to Figure 4 , which is an equivalent circuit diagram of the semiconductor structure provided by the embodiment of the present application. As shown in Figure 4 , the semiconductor structure 40 comprises a device to be protected 41 and a first plasma elimination component 421 and a second plasma elimination component 422. A first end of the device to be protected 41 is electrically connected to a first pad Pad1 through a metal wire 49, and a second end of the device to be protected 41 is electrically connected to a second pad Pad2 through a metal wire 49. The first plasma elimination component 421 is electrically connected to the first end of the device to be protected 41 and the first pad Pad1 through a metal wire 49, and the second plasma elimination component 422 is electrically connected to the second end of the device to be protected 41 and the second pad Pad2 through a metal wire 49. The first plasma elimination component 421 stores and releases the charge before the plasma reaches the device to be protected 41 through the first pad Pad1, and the second plasma elimination component 422 stores and releases the charge before the plasma reaches the device to be protected 41 through the second pad Pad2, so as to effectively prevent the damage of the plasma to the device to be protected.

[0024] Specifically, the first plasma elimination component 421 comprises a first diode D1 and a first capacitor C1. A cathode of the first diode D1 is electrically connected to the first end of the device to be protected 41 and the first pad Pad1, a first plate of the first capacitor C1 is electrically connected to the first end of the device to be protected 41 and the first pad Pad1, and an anode of the first diode D1 is electrically connected to a second plate of the first capacitor C1, so that the first diode D1 and the first capacitor C1 form a parallel structure, to store the charge through the first capacitor C1 before the plasma reaches the device to be protected 41 through the first pad Pad1, and to release the charge through the first diode D1, so as to prevent the damage of the plasma to the device to be protected 41.

[0025] Specifically, the second plasma elimination component 422 comprises a second diode D2 and a second capacitor C2. The cathode of the second diode D2 is electrically connected to the second end of the device to be protected 41 and the second pad Pad2; the first plate of the second capacitor C2 is electrically connected to the second end of the device to be protected 41 and the second pad Pad2; the anode of the second diode D2 is electrically connected to the second plate of the second capacitor C2, so that the second diode D2 and the second capacitor C2 form a parallel structure, to prevent the damage of the device to be protected 41 by plasma, by storing the charge through the second capacitor C2 before the plasma reaches the device to be protected 41 through the second pad Pad2, and releasing the charge through the second diode D2.

[0026] For the convenience of illustration, Figure 4 In the embodiment, the anode of the first diode D1 and the second plate of the first capacitor C1 are both electrically connected to a common point A; the anode of the second diode D2 and the second plate of the second capacitor C2 are both electrically connected to the common point A. In the semiconductor structure 40, the common point A can be the substrate of the wafer, specifically, a P-well region on the substrate. That is, the anode of the first diode D1 and the second plate of the first capacitor C1 are both electrically connected to the P-well region, thereby forming a parallel structure.

[0027] Please refer to Figure 5 which is a layout of a semiconductor structure provided by an embodiment of the present application. As shown in Figure 5 , the semiconductor structure 50 comprises a device to be protected 51, a first plasma elimination component and a second plasma elimination component.

[0028] In the embodiment, the semiconductor structure 50 comprises a substrate, and a P-well region 500 is formed on the substrate; the device to be protected 51 is a high resistance poly (HR Poly) structure formed on the P-well region 500 of the substrate. Since the plasma will damage the high resistance poly structure during the film preparation process of the back-end-of-line of the semiconductor structure, affect the performance of the high resistance poly structure, and cause inaccurate measurement, the present application adds a plasma elimination component to complete plasma elimination before the plasma reaches the device to be protected through the corresponding pad, so as to prevent the damage of the device to be protected by the plasma.

[0029] In the embodiment, the first end of the device to be protected 51 is electrically connected to the first pad Pad1, and the second end of the device to be protected 51 is electrically connected to the second pad Pad2. The first pad Pad1 and the second pad Pad2 are both multi-layer metal laminated structures, and the two ends of the device to be protected 51 are respectively electrically connected to the corresponding pads through metal wires, and the metal wires are in the same layer as any metal layer of the multi-layer metal laminated structure. That is, the metal wires in any layer can be used for wiring at the two ends of the device to be protected 51.

[0030] In the embodiment, the P-well region 500 is formed with two first active regions (AA) 501 and two second active regions 502. The first active region 501 is formed with a first N-type doped region 503 in the corresponding region, the second active region 502 is formed with a second N-type doped region 504 in the corresponding region, the second active region 502 is formed with an insulating layer 505 (shown in Figure 7B the middle), and the insulating layer 505 is formed with a conductive material layer 506. The P-well region 500, the first N-type doped region 503, and the region adjacent to the first N-type doped region 503 of the P-well region 500 are respectively a P region, an N region, and a PN junction, forming diodes D1, D2. The second N-type doped region 504, the insulating layer 505, and the conductive material layer 506 are respectively a first plate, a dielectric layer, and a second plate, forming capacitors C1, C2. The first active region 501 is electrically connected to the device to be protected 51 and the corresponding pad through a first contact hole CT1 and a metal wire 509, and the conductive material layer 506 is electrically connected to the device to be protected 51 and the corresponding pad through a second contact hole CT2 and a metal wire 509; since the P region of the diode and the first plate of the capacitor are both formed in the P-well region 500, they are conducted through the P-well region 500; thus, the diode D1 and the capacitor C1 form a parallel structure, and the diode D2 and the capacitor C2 form a parallel structure. Before the plasma reaches the device to be protected 51 through the first pad Pad1, the charge is stored by the capacitor C1 and released after passing through the diode D1, and before the plasma reaches the device to be protected 51 through the second pad Pad2, the charge is stored by the capacitor C2 and released after passing through the diode D2, thereby effectively preventing the damage of the plasma to the device to be protected 51. For convenience, Figure 5 in the middle, the metal wire 509 is shown in perspective to show the contact hole and other film layer structures thereunder.

[0031] In the embodiment, the first N-type doped region 503 is located between the device 51 to be protected and the corresponding pad, and the orthogonal projection of the first N-type doped region 503 on the P-well region 500 completely covers the first active region 501. The second N-type doped region 504 is located at the end of the device 51 to be protected and adjacent to the first N-type doped region 503, and the orthogonal projection of the second N-type doped region 504 on the P-well region 500 completely covers the second active region 502.

[0032] In some embodiments, the material of the conductive material layer 506 is the same as that of the device 51 to be protected, for example, both are polysilicon.

[0033] Based on the same inventive concept, the present application also provides a method for preparing a semiconductor structure, which can prepare the semiconductor structure as described in the above embodiments of the present application, and can effectively prevent plasma damage and eliminate the measurement error caused by plasma-induced damage.

[0034] Please refer to Figures 6-7D 、 Figure 5 , wherein, Figure 6 is a step schematic diagram of the method for preparing a semiconductor structure provided by an embodiment of the present application, Figures 7A-7D is a device structure schematic diagram formed by the main steps of the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0035] As Figure 6 shown, in the embodiment, the method comprises the following steps: S1, providing a substrate, wherein the substrate is formed with a P-well region; S2, forming a device to be protected and at least one plasma elimination component on the P-well region; and S3, electrically connecting the two ends of the device to be protected to the corresponding pads respectively, and electrically connecting the plasma elimination component to the device to be protected and the corresponding pads, so that before the plasma reaches the device to be protected through the corresponding pad, the electric charge is stored and then released by the plasma elimination component, to prevent the damage of the plasma to the device to be protected.

[0036] In the embodiment, the step S2 further comprises: 1) forming at least one first active region and at least one second active region on the P-well region; 2) forming a first N-type doped region as the N region of a diode on the region corresponding to the first active region, and forming the P-well region as the P region of the diode, so as to form the diode of the plasma elimination component; 3) forming a second N-type doped region as the first plate of a capacitor on the region corresponding to the second active region, forming an insulating layer as the dielectric layer of the capacitor on the second active region, and forming a conductive material layer as the second plate of the capacitor on the insulating layer, so as to form the capacitor of the plasma elimination component; and 4) forming the device to be protected on the P-well region.

[0037] Please refer to step S2 and Figures 7A-7C The device to be protected and at least one plasma elimination component are formed on the P-well region 500. In this embodiment, step S2 further includes: 1) forming two first active regions 501 and two second active regions 502 on the P-well region 500, such as... Figure 7A As shown; 2) A first N-type doped region 503 is formed in the region corresponding to the first active region 501, a second N-type doped region 504 is formed in the region corresponding to the second active region 502, and an insulating layer 505 is formed on the second active region 502, as shown. Figure 7B As shown; 3) A conductive material layer 506 is formed on the insulating layer 505, and the device to be protected 51 is formed on the P-well region 500, as shown. Figure 7C As shown. The first N-type doped region 503 serves as the N-region of the diode, and the P-well region 500 serves as the P-region of the diode, thereby forming the diode of the plasma elimination component; the second N-type doped region 504 serves as the first plate of the capacitor, the insulating layer 505 serves as the dielectric layer of the capacitor, and the conductive material layer 506 serves as the second plate of the capacitor, thereby forming the capacitor of the plasma elimination component.

[0038] In this embodiment, the first N-type doped region 503 is located between the device to be protected 51 and the corresponding pad, and the orthographic projection of the first N-type doped region 503 onto the P-well region 500 completely covers the first active region 501. The second N-type doped region 504 is located at the end of the device to be protected 51 and adjacent to the first N-type doped region 503, and the orthographic projection of the second N-type doped region 504 onto the P-well region 500 completely covers the second active region 502.

[0039] In some embodiments, the material of the conductive material layer 506 is the same as the material of the device to be protected 51, for example, both are polycrystalline silicon.

[0040] In some embodiments, an N-type doped region is formed by doping the active region with pentavalent atoms, such as phosphorus.

[0041] Please refer to step S3 and Figure 7D , Figure 5 The two ends of the device to be protected are electrically connected to the corresponding pads, and the plasma elimination assembly is electrically connected to the device to be protected and the corresponding pads. In this embodiment, step S3 further includes: 1) forming reference contact holes CT0 at both ends of the device to be protected 51, forming a first contact hole CT1 in the first active region 501, and forming a second contact hole CT2 in the second active region 502; as shown Figure 7DAs shown in the figure; 2) the two ends of the device to be protected 51 are respectively electrically connected to the corresponding pads through the reference contact hole CT0 and the metal line 509; and the first active region is electrically connected to the device to be protected and the corresponding pad through the first contact hole CT1 and the metal line 509, and the conductive material layer is electrically connected to the device to be protected and the corresponding pad through the second contact hole CT2 and the metal line 509; the device structure formed is as shown in the figure. Figure 5 Thus, the diode and the capacitor form a parallel structure, so that before the plasma reaches the device to be protected through the corresponding pad, the charge is stored through the capacitor and released through the diode, so as to prevent the damage of the plasma to the device to be protected.

[0042] In some embodiments, the first end of the device to be protected 51 is electrically connected to the first pad Pad1, and the second end of the device to be protected 51 is electrically connected to the second pad Pad2. The first pad Pad1 and the second pad Pad2 are both multilayer metal laminated structures, and the two ends of the device to be protected 51 are respectively electrically connected to the corresponding pads through the metal lines, and the metal lines are in the same layer as any metal layer of the multilayer metal laminated structure. That is, the metal lines on both ends of the device to be protected 51 can be laid in any layer of metal layer.

[0043] In some embodiments, the metal lines electrically connecting the diode and the device to be protected 51, the metal lines electrically connecting the capacitor and the device to be protected 51, and the metal lines electrically connecting the device to be protected 51 and the corresponding pad are laid in the same metal layer.

[0044] From the above, it can be seen that the semiconductor structure and the preparation method thereof provided by the above-mentioned embodiments of the present application add the plasma elimination assembly composed of the parallel diode and capacitor, and electrically connect it to the device to be protected and the corresponding pad. In the film layer preparation process of each metal layer and each insulating layer in the later stage of the semiconductor structure, before the plasma reaches the device to be protected through the corresponding pad, the charge is stored through the capacitor and released through the diode, which can effectively prevent the damage of the plasma to the device to be protected, thereby eliminating the measurement error caused by the plasma-induced damage.

[0045] It should be noted that the terms "comprise" and "have" and their conjugates, as used in the specification and claims of the present application, are intended to encompass the presence of stated features, structures, components, elements, or objects, but do not preclude the presence or addition of one or more other features, structures, components, elements, or objects. The terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, unless otherwise indicated by context. The use of the terms "a" and "an" and "the" and "said" and "at least one" and "one or more" to refer to an element or object also is taken to cover "one or more" unless otherwise indicated by context. The term "based on" can be taken to mean "based at least in part on," that is, not necessarily based exclusively on the matter following the term. In addition, the embodiments and features discussed above can be combined with each other, as much as is physically possible. Furthermore, in the following description of various embodiments, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, various embodiments can be practiced without these specific details. In other instances, well-known components have not been described in detail in order to avoid unnecessarily obscuring the embodiments. Unless otherwise noted, the use of the ordinal adjectives (i.e., "first," "second," etc.) to describe a common but distinct member of a generic set is to be understood as indicating a number of the features. The use of the terms "at least one" and "one or more" is to be taken as synonymous with each other.

[0046] The above description is merely of the preferred embodiments of the application and various modifications and improvements can be made by those skilled in the art without departing from the principles of the application. Such modifications and improvements are intended to fall within the scope of the application.

Claims

1. A semiconductor structure, characterized by The semiconductor structure comprises a substrate, a P well region is formed on the substrate, the P well region is formed with two first active regions and two second active regions, a first N type doped region is formed in the corresponding region of the first active region, a second N type doped region is formed in the corresponding region of the second active region, an insulating layer is formed on the second active region, and a conductive material layer is formed on the insulating layer; the plasma elimination assembly comprises a diode and a capacitor, the P well region, the first N type doped region and the region adjacent to the first N type doped region of the P well region are respectively used as the P region, the N region and the PN junction of the diode, and the second N type doped region, the insulating layer and the conductive material layer are respectively used as the first plate, the dielectric layer and the second plate of the capacitor; the first active region is electrically connected to the to-be-protected device and the corresponding pad through a first contact hole and a metal wire, and the conductive material layer is electrically connected to the to-be-protected device and the corresponding pad through a second contact hole and a metal wire, so that the diode and the capacitor form a parallel structure; wherein before plasma reaches the to-be-protected device through the corresponding pad, the capacitor of the plasma elimination assembly stores the electric charge and releases the electric charge after the diode, so as to prevent the damage of the plasma to the to-be-protected device. The pad is a multilayer metal laminated structure, and the two ends of the to-be-protected device are respectively electrically connected to the corresponding pad through a metal wire, and the metal wire is in the same layer as any metal layer of the multilayer metal laminated structure. The first N type doped region is located between the to-be-protected device and the corresponding pad, and the orthographic projection of the first N type doped region on the P well region completely covers the first active region; the second N type doped region is located at the end of the to-be-protected device and adjacent to the first N type doped region, and the orthographic projection of the second N type doped region on the P well region completely covers the second active region. The semiconductor structure comprises a substrate, a P well region is formed on the substrate, the P well region is formed with two first active regions and two second active regions, a first N type doped region is formed in the corresponding region of the first active region, a second N type doped region is formed in the corresponding region of the second active region, an insulating layer is formed on the second active region, and a conductive material layer is formed on the insulating layer; the plasma elimination assembly comprises a diode and a capacitor, the P well region, the first N type doped region and the region adjacent to the first N type doped region of the P well region are respectively used as the P region, the N region and the PN junction of the diode, and the second N type doped region, the insulating layer and the conductive material layer are respectively used as the first plate, the dielectric layer and the second plate of the capacitor; the first active region is electrically connected to the to-be-protected device and the corresponding pad through a first contact hole and a metal wire, and the conductive material layer is electrically connected to the to-be-protected device and the corresponding pad through a second contact hole and a metal wire, so that the diode and the capacitor form a parallel structure; wherein before plasma reaches the to-be-protected device through the corresponding pad, the capacitor of the plasma elimination assembly stores the electric charge and releases the electric charge after the diode, so as to prevent the damage of the plasma to the to-be-protected device.

2. The semiconductor structure of claim 1, wherein, The pad is a multilayer metal laminated structure, and the two ends of the to-be-protected device are respectively electrically connected to the corresponding pad through a metal wire, and the metal wire is in the same layer as any metal layer of the multilayer metal laminated structure.

3. The semiconductor structure of claim 1, wherein, The first N type doped region is located between the to-be-protected device and the corresponding pad, and the orthographic projection of the first N type doped region on the P well region completely covers the first active region; the second N type doped region is located at the end of the to-be-protected device and adjacent to the first N type doped region, and the orthographic projection of the second N type doped region on the P well region completely covers the second active region.

4. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure comprises a substrate, a P well region is formed on the substrate, the P well region is formed with two first active regions and two second active regions, a first N type doped region is formed in the corresponding region of the first active region, a second N type doped region is formed in the corresponding region of the second active region, an insulating layer is formed on the second active region, and a conductive material layer is formed on the insulating layer; the plasma elimination assembly comprises a diode and a capacitor, the P well region, the first N type doped region and the region adjacent to the first N type doped region of the P well region are respectively used as the P region, the N region and the PN junction of the diode, and the second N type doped region, the insulating layer and the conductive material layer are respectively used as the first plate, the dielectric layer and the second plate of the capacitor; the first active region is electrically connected to the to-be-protected device and the corresponding pad through a first contact hole and a metal wire, and the conductive material layer is electrically connected to the to-be-protected device and the corresponding pad through a second contact hole and a metal wire, so that the diode and the capacitor form a parallel structure; wherein before plasma reaches the to-be-protected device through the corresponding pad, the capacitor of the plasma elimination assembly stores the electric charge and releases the electric charge after the diode, so as to prevent the damage of the plasma to the to-be-protected device. The application provides a substrate with a P well region formed thereon; a device to be protected and plasma elimination components arranged at two ends of the device to be protected are formed on the P well region, the plasma elimination components include a diode and a capacitor; the step of forming the device to be protected and the plasma elimination components arranged at two ends of the device to be protected on the P well region further includes: forming two first active regions and two second active regions on the P well region; forming a first N-type doped region as an N region of the diode on a corresponding region of the first active region, the P well region as a P region of the diode, and a region adjacent to the first N-type doped region as a PN junction of the diode, so as to form the diode of the plasma elimination components; forming a second N-type doped region as a first plate of the capacitor on a corresponding region of the second active region, forming an insulating layer as a dielectric layer of the capacitor on the second active region, and forming a conductive material layer as a second plate of the capacitor on the insulating layer, so as to form the capacitor of the plasma elimination components; and forming a high-resistance polysilicon structure as the device to be protected on the P well region; the two ends of the device to be protected are electrically connected to corresponding pads respectively, and the plasma elimination components are electrically connected to the device to be protected and the corresponding pads; the step of electrically connecting the two ends of the device to be protected to the corresponding pads respectively and electrically connecting the plasma elimination components to the device to be protected and the corresponding pads further includes: forming reference contact holes at the two ends of the device to be protected respectively, forming a first contact hole on the first active region, and forming a second contact hole on the second active region; the two ends of the device to be protected are electrically connected to the corresponding pads through the reference contact holes and metal wires; the first active region is electrically connected to the device to be protected and the corresponding pads through the first contact hole and metal wires, and the conductive material layer is electrically connected to the device to be protected and the corresponding pads through the second contact hole and metal wires, so that the diode and the capacitor form a parallel structure; before plasma passes through the corresponding pads to reach the device to be protected, the capacitor of the plasma elimination components stores charges and releases the charges after passing through the diode, so as to prevent the device to be protected from being damaged by the plasma.

5. The method of claim 4, wherein, The first N-type doped region is located between the device to be protected and the corresponding pad, and the orthographic projection of the first N-type doped region on the P well region completely covers the first active region; the second N-type doped region is located at the end of the device to be protected and adjacent to the first N-type doped region, and the orthographic projection of the second N-type doped region on the P well region completely covers the second active region.

6. The method of claim 4, wherein, The pad is a multilayer metal laminated structure, and the metal wire is in the same layer as any metal layer of the multilayer metal laminated structure.

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