Display panel, preparation method thereof and display device

Abstract

The application provides a display panel and a preparation method thereof and a display device, relates to the technical field of display, and is used for balancing via hole density at each position in the display panel and improving the performance of a TFT. A display area includes a plurality of pixel circuits; a non-display area includes a gate-on circuit area in which a plurality of gate-on circuit groups are arranged and a gate driving circuit area in which a plurality of gate driving circuit units are arranged; the pixel circuit, the gate-on circuit group and the gate driving circuit unit each include a plurality of transistors, the transistor includes a first inorganic insulating layer between an active structure and a second electrode, the first inorganic insulating layer includes a first sub-via hole, a second sub-via hole and a second via hole penetrating through the first inorganic insulating layer; the second electrode and a third electrode are electrically connected with the active structure through the first sub-via hole and the second sub-via hole respectively; the second via hole does not overlap with the active structure in the orthogonal projection of a plane in which the display panel is located; and the gate-on circuit area and / or the gate driving circuit area include the second via hole.

Description

[0001] This application is a divisional application of the application with the application date of April 27, 2020, the application number of 202010344142.5, and the title of "Display panel, preparation method thereof, and display device". TECHNICAL FIELD

[0002] The present application relates to the technical field of display, and in particular to a display panel, a preparation method thereof, and a display device. BACKGROUND

[0003] A thin film transistor (hereinafter referred to as TFT) is an important component of a display panel. Currently, TFT devices are arranged in the display area and the non-display area of the display panel. For example, TFT devices are arranged in the display area to construct pixel circuits. TFT devices are arranged in the non-display area to construct peripheral circuits. The performance of TFT devices has an important influence on the display effect of the display panel. How to reasonably design the structure of TFT devices in different areas of the display panel to ensure the display effect of the display panel has become the research focus of researchers. SUMMARY

[0004] Embodiments of the present application provide a display panel, a preparation method thereof, and a display device, to reasonably design the structure of TFT devices in different areas of the display panel to ensure the display effect of the display panel.

[0005] In one aspect, the present application provides a display panel, comprising a display area and a non-display area.

[0006] The display area comprises a plurality of pixel circuits.

[0007] The non-display area comprises a gate-on circuit area and a gate drive circuit area, the gate-on circuit area comprises a plurality of gate-on circuit groups, and the gate drive circuit area comprises a plurality of gate drive circuit units.

[0008] The pixel circuit, the gate-on circuit group, and the gate drive circuit unit each include a plurality of transistors, the transistors include an active structure, a first electrode, a second electrode, and a third electrode, a first inorganic insulating layer is included between the active structure and the second electrode, the first inorganic insulating layer includes a via hole penetrating through the first inorganic insulating layer, the via hole includes a first via hole and a second via hole, the first via hole includes a first sub-via hole and a second sub-via hole; a normal projection of the first sub-via hole on a plane where the display panel is located and a normal projection of the second sub-via hole on the plane where the display panel is located each at least partially overlap a normal projection of the active structure on the plane where the display panel is located, a normal projection of the second via hole on the plane where the display panel is located does not overlap the normal projection of the active structure on the plane where the display panel is located, the second electrode is electrically connected with the active structure through the first sub-via hole, and the third electrode is electrically connected with the active structure through the second sub-via hole;

[0009] The gate-on circuit region includes the second via hole;

[0010] And / or,

[0011] The gate drive circuit region includes the second via hole.

[0012] In another aspect, an embodiment of the present application provides a preparation method of a display panel, the display panel including a display region and a non-display region, the non-display region including a gate-on circuit region and a gate drive circuit region, the preparation method including:

[0013] Providing a substrate base plate;

[0014] Forming a pixel circuit, a gate-on circuit group, and a gate drive circuit unit on one side of the substrate base plate; the pixel circuit is located in the display region, the gate-on circuit group is located in the gate-on circuit region, and the gate drive circuit unit is located in the gate drive circuit region; the pixel circuit, the gate-on circuit group, and the gate drive circuit unit each include a plurality of transistors, the transistors include an active structure, a first electrode, a second electrode, and a third electrode;

[0015] The method of forming the pixel circuit, the gate-on circuit group, and the gate drive circuit unit includes:

[0016] Forming the active structure, the first electrode, and a first inorganic insulating layer on one side of the substrate base plate; the first inorganic insulating layer is located on a side of the active structure away from the substrate base plate;

[0017] forming a via hole penetrating the first inorganic insulating layer in the first inorganic insulating layer, the via hole comprising a first via hole and a second via hole, the first via hole comprising a first sub-via hole and a second sub-via hole, the orthographic projection of the first sub-via hole on the plane where the substrate is located and the orthographic projection of the second sub-via hole on the plane where the substrate is located both at least partially overlap with the orthographic projection of the active structure on the plane where the substrate is located; and the orthographic projection of the second via hole on the plane where the substrate is located does not overlap with the orthographic projection of the active structure on the plane where the substrate is located;

[0018] performing a hydrogenation treatment on the first inorganic insulating layer;

[0019] forming a second electrode and a third electrode on a side of the hydrogenated first inorganic insulating layer away from the base substrate, wherein the second electrode is electrically connected to the active structure through the first sub-via hole, and the third electrode is electrically connected to the active structure through the second sub-via hole;

[0020] The gating circuit area includes the second via hole;

[0021] and / or,

[0022] The gate driving circuit area includes the second via hole.

[0023] In another aspect, an embodiment of the present invention provides a display device, which includes the above-mentioned display panel.

[0024] The display panel, preparation method thereof, and display device provided by the embodiments of the present invention can balance the via density of the gate drive circuit area and / or the gate circuit area, which originally has uneven via density, by setting a second via that does not serve as an electrical connection in the gate drive circuit area and / or the gate circuit area. Furthermore, when the first inorganic insulating layer and the active structure are hydrogenated, the hydrogen content of the first inorganic insulating layer and the active structure at different positions in the gate drive circuit area and / or the gate circuit area can be balanced, thereby making the characteristics of the TFT devices at different positions in the gate drive circuit area and / or the gate circuit area tend to be consistent. Therefore, when the peripheral circuit composed of these TFTs in the gate drive circuit area and / or the gate circuit area drives the display of the sub-pixels located in the display area, the brightness of the sub-pixels at different positions can be made consistent, thereby avoiding the uneven display phenomenon of some positions being too dark or too bright, which is beneficial to improving the display uniformity of the display panel.

Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 is a schematic cross-sectional view of a TFT device in the prior art;

[0027] Figure 2 A schematic top view of a display panel provided by an embodiment of the present invention;

[0028] Figure 3 A schematic top view of a liquid crystal display panel provided by an embodiment of the present invention;

[0029] Figure 4 for Figure 3 Schematic diagram of the wiring of a single sub-pixel;

[0030] Figure 5 for Figure 4 A schematic cross-sectional view of

[0031] Figure 6 A schematic diagram of a pixel circuit included in an organic light emitting display panel provided by an embodiment of the present invention;

[0032] Figure 7 for Figure 6 A wiring diagram of a pixel circuit shown;

[0033] Figure 8 A schematic cross-sectional view of a portion of an organic light emitting display panel provided by an embodiment of the present invention;

[0034] Figure 9 A circuit diagram of a gate drive circuit unit provided by an embodiment of the present invention;

[0035] Figure 10 for Figure 9 The wiring diagram of the gate drive circuit unit shown;

[0036] Figure 11 A circuit diagram of a gating circuit group provided by an embodiment of the present invention;

[0037] Figure 12 for Figure 11 The wiring diagram of the gating circuit group shown;

[0038] Figure 13 A schematic cross-sectional view of a portion of a display panel provided by an embodiment of the present invention;

[0039] Figure 14 A via distribution schematic diagram of a gate drive circuit region provided for an embodiment of the present application is shown in FIG. 1.

[0040] Figure 15 A via distribution schematic diagram of a gate drive circuit region provided for an embodiment of the present application is shown in FIG. 1.

[0041] Figure 16 An enlarged schematic diagram of a partial position of a gate drive circuit region provided for an embodiment of the present application is shown in FIG. 2.

[0042] Figure 17 An enlarged schematic diagram of a partial position of a gate drive circuit region provided for an embodiment of the present application is shown in FIG. 2.

[0043] Figure 18 A top view schematic diagram of yet another display panel provided for an embodiment of the present application is shown in FIG. 3.

[0044] Figure 19 A top view schematic diagram of yet another display panel provided for an embodiment of the present application is shown in FIG. 3.

[0045] Figure 20 An enlarged schematic diagram of a middle region Q is shown in FIG. 4. Figure 19 An enlarged schematic diagram of a middle region Q is shown in FIG. 4.

[0046] Figure 21 A flowchart of a preparation method of a display panel provided for an embodiment of the present application is shown in FIG. 5.

[0047] Figure 22 A schematic diagram of a display device provided for an embodiment of the present application is shown in FIG. 6.

DETAILED DESCRIPTION

[0048] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0049] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0050] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0051] It should be understood that the term "and / or" as used herein merely describes an associated relationship, which means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0052] It should be understood that although the terms first, second, etc. are used in the embodiments of the present application to describe the via holes, the via holes should not be limited to these terms. These terms are only used to distinguish the via holes with different functions from each other. For example, the first via hole can also be referred to as the second via hole, and similarly, the second via hole can also be referred to as the first via hole without departing from the scope of the embodiments of the present application.

[0053] At present, for a display panel using an active driving mode, a pixel circuit for controlling independent display of a pixel is arranged in a display area, and a peripheral circuit electrically connected with the pixel circuit is arranged in a non-display area. The pixel circuit and the peripheral circuit both include a TFT device. As shown in Figure 1 Figure 1 is a cross-sectional view of a TFT device in the prior art, in which a semiconductor layer 2', a first insulating layer 31', a gate 4', a second insulating layer 32', a source 51' and a drain 52', and a third insulating layer 33' are formed on the same side of a substrate 1'. The source 51' and the drain 52' are respectively electrically connected with the semiconductor layer 2' through a via hole penetrating the first insulating layer 31' and the second insulating layer 32'. The first insulating layer 31' and the second insulating layer 32' are inorganic insulating layers made of inorganic materials.

[0054] In the preparation of a TFT device with a structure as shown in Figure 1 After the second insulating layer 32' is prepared, a via hole penetrating the first insulating layer 31' and the second insulating layer 32' needs to be prepared. After the via hole is prepared, the first insulating layer 31', the second insulating layer 32' and the semiconductor layer 2' need to be subjected to a hydrogenation treatment to eliminate interface state defects in the first insulating layer 31', the second insulating layer 32' and the semiconductor layer 2', and then a metal layer forming the source 51' and the drain 52' is prepared. In the hydrogenation treatment process, hydrogenated amorphous silicon (a-Si:H) containing a large number of silicon-hydrogen bonds Si:H is formed in the semiconductor layer 2', which can improve the conductivity of the semiconductor layer 2'.

[0055] ​In the process of implementing the present application, the inventors have found that the display panel has the problem of display unevenness in different positions due to different display brightness. The inventors have found that the TFT device of the peripheral circuit connected to the pixel in the position with smaller brightness has the problem of positive shift of threshold voltage Vth and larger leakage current. Moreover, the inventors have found that the TFT device characteristics are related to the hydrogen content in the inorganic insulating layer and the semiconductor layer.

[0056] Specifically, due to the large number of electronic components and various wirings included in the peripheral circuit in the non-display area and the complex arrangement, the distribution of the TFT included in the peripheral circuit in the non-display area is relatively uneven compared with the distribution of the TFT in the display area. In the non-display area, the distribution of the TFT in some positions is relatively sparse.

[0057] Due to the uneven distribution of the TFT device, the distribution of the via hole included in the inorganic insulating layer in different positions in the non-display area is also relatively uneven. Since the hydrogenation treatment in the process of preparing the TFT device is performed after the punching operation on the inorganic insulating layer, the via hole density will affect the hydrogenation degree in different positions in the first insulating layer 31', the second insulating layer 32' and the semiconductor layer 2', resulting in a large difference in the hydrogen content in different positions in the first insulating layer 31', the second insulating layer 32' and the semiconductor layer 2', and further resulting in inconsistent characteristics of the TFT device in different positions.

[0058] Specifically, the inventors have found in the research process that in the place with smaller via hole density, after the hydrogenation treatment, the hydrogen content in the first insulating layer 31', the second insulating layer 32' and the semiconductor layer 2' is relatively large, the threshold voltage Vth of the TFT device is positively biased, the leakage current is increased, the brightness of the pixel electrically connected to the TFT device in this position is reduced, and a dark spot appears at this pixel during display.

[0059] Therefore, the embodiment of the present application provides a display panel as shown in Figure 2 Figure 2 A top view schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure, wherein the display panel includes a display area AA and a non-display area NA. The display area AA includes a plurality of sub-pixels 1, and a scan line 2 and a data line 3 electrically connected to the sub-pixel 1. The scan line 2 extends along a first direction x, and a plurality of scan lines 2 are arranged along a second direction y. The data line 3 extends along the second direction y, and a plurality of data lines 3 are arranged along the first direction x. The scan line 2 and the data line 3 cross to define the position of the sub-pixel 1. The sub-pixel 1 includes a pixel circuit (not shown). The pixel circuit includes a transistor. For example, the transistor included in the pixel circuit can be a TFT.

[0060] ​It should be noted that the pixel circuit can have different structures according to different display types. For example, taking a liquid crystal display panel as an example, as shown in Figure 3 、 Figure 4 and Figure 5 , Figure 3 is a top view schematic diagram of a display area of a liquid crystal display panel provided by an embodiment of the present application, Figure 4 is Figure 3 an enlarged schematic diagram of a single sub-pixel in Figure 5 is Figure 4 a cross-sectional schematic diagram of Figure 3 and Figure 4 not shown) and liquid crystal molecules 103 Figure 3 and Figure 4 not shown), the pixel circuit can include a TFT connecting the pixel electrode 101 with the scan line 2 and the data line 3, wherein the control electrode of the TFT is connected with the scan line 2, and the source electrode and the drain electrode are respectively connected with the pixel electrode 101 and the data line 3.

[0061] Taking an organic light emitting display panel as an example, the pixel circuit included in the sub-pixel 1 can include a storage capacitor C and a plurality of TFTs. Optionally, in the organic light emitting display panel, the scan line can be provided as a plurality of wires including a first scan line 21, a second scan line 22, and an emission signal line E. The organic light emitting display panel further includes a reference signal line VREF providing a reference voltage signal, and a first power voltage signal line PVDD providing a first power voltage and a second power voltage signal line PVEE providing a second power voltage. In combination with Figure 6 、 Figure 7 and Figure 8 , Figure 6 is a schematic diagram of a pixel circuit included in an organic light emitting display panel provided by an embodiment of the present application, Figure 7 is Figure 6 a wiring schematic diagram of the pixel circuit shown in Figure 8 is a cross-sectional schematic diagram of a partial position of an organic light emitting display panel provided by an embodiment of the present application, wherein the pixel circuit is a 7T1C structure including seven transistors T11, T12, …, T16, T17 and one storage capacitor C1. As shown in Figure 6 , the sub-pixel 1 further includes an organic light emitting device 8 electrically connected with the pixel circuit, the organic light emitting device 8 includes an anode 81, a light emitting layer 83 and a cathode 82 which are stacked. The anode 81 can be connected with the source electrode or the drain electrode of the sixth transistor T16 and the seventh transistor T17.

[0062] Referring to Figure 2The non-display area NA includes a gate drive circuit area NA1 and a gate circuit area NA2. The gate drive circuit area NA1 includes multiple gate drive circuit units 4 electrically connected to the scan lines 2. The gate circuit area NA2 includes multiple gate circuit groups 5 electrically connected to the data lines 3. The gate drive circuit units 4 and the gate circuit groups 5 also include multiple transistors. The transistors included in the gate drive circuit units 4 and the gate circuit groups 5 can also be TFTs.

[0063] For example, Figure 9 and Figure 10 As shown, Figure 9 A circuit diagram of a gate drive circuit unit provided by an embodiment of the present invention, Figure 10 for Figure 9 Schematic diagram of the wiring of the gate drive circuit unit shown, wherein the gate drive circuit unit 4 includes 10 transistors T21, T22, T23, ..., T28, T29, T30 and three storage capacitors C21, C22, C33. Optionally, the multiple gate drive circuit units 4 included in the gate drive circuit area NA1 are cascaded with each other. For the gate drive circuit units 4 of two adjacent levels, the output signal OUT of one of them is not only provided to the scan line 2 electrically connected thereto, but also provided to the other gate drive circuit unit 4 as the input signal IN of the gate drive circuit unit 4. Among them, the input signal of the first-level gate drive circuit unit 4 can be provided by the frame start signal STV. When the display panel is working, the multi-level gate drive circuit unit 4 successively outputs the valid level signal to be transmitted to the sub-pixels of the corresponding row through the multiple rows of scan lines 2, so that the sub-pixels of the corresponding row are turned on.

[0064] Combine Figure 2 、 Figure 11 and Figure 12 As shown, Figure 11 A circuit diagram of a gating circuit group provided by an embodiment of the present invention, Figure 12 for Figure 11 The wiring diagram of the gating circuit group shown in FIG. Figure 11 and Figure 12 The gating circuit group 5 includes 6 transistors M1, M2, ..., M5, and M6 as an example. Of course, the number of transistors included in the gating circuit group 5 can be other, and the embodiments of the present invention will not be described in detail here. Figure 2 As shown, the non-display area NA further includes a data driver 6. The data driver 6 includes a plurality of data output terminals. Figure 11 and Figure 12As shown, a data output terminal is electrically connected to M data lines via a gating circuit group 5; where M is an integer greater than 1. Specifically, the sources of multiple transistors belonging to the same gating circuit group 5 are connected one-to-one to multiple data lines 3, and their drains are connected to the same data output terminal. The gating circuit area NA2 also includes a switch control signal line CKH correspondingly connected to the control electrodes of the transistors in the gating circuit group 5. For example, when the gating circuit group 5 includes six transistors, M1, M2, ..., M5, and M6, the gating circuit area NA2 also includes six switch control signal lines, CKH1, CKH2, ..., CKH5, and CKH6, to control the time-sharing conduction of transistors M1, M2, ..., M5, and M6. The data signal input to the data output terminal B1 can be provided to the six data lines 3 connected to the gating circuit group 5 in a time-sharing manner. This configuration can reduce the number of terminals providing the data output terminal of the data driver 6.

[0065] like Figure 13 As shown, Figure 13 A cross-sectional schematic diagram of a partial position of a display panel provided for an embodiment of the present invention, wherein the transistor TFT includes an active structure 60, a first electrode 61, a second electrode 62 and a third electrode 63, a first inorganic insulating layer 641 is included between the active structure 60 and the second electrode 62, the first inorganic insulating layer 641 includes a via hole passing through the first inorganic insulating layer 641, the via hole includes a first via hole 71 and a second via hole 72, and the first via hole 71 includes a first sub-via hole 711 and a second sub-via hole 712.

[0066] In the embodiment of the present invention, the orthographic projection of the first sub-via 711 on the plane where the display panel is located and the orthographic projection of the second sub-via 712 on the plane where the display panel is located both at least partially overlap with the orthographic projection of the active structure 60 on the plane where the display panel is located. The second electrode 62 is electrically connected to the active structure 60 through the first sub-via 711, and the third electrode 63 is electrically connected to the active structure 60 through the second sub-via 712. That is, the first via 71 serves to electrically connect the structures above and below it. Specifically, as shown in FIG. Figure 4 、 Figure 5 、 Figure 7 、 Figure 8 、 Figure 10 、 Figure 12 As shown, the TFTs included in the pixel circuit, the gate driving circuit unit 4, and the gate circuit group 5 all include a plurality of the above-mentioned first via holes 71 for electrical connection.

[0067] like Figure 13 As shown, the orthographic projection of the second via 72 on the plane where the display panel is located does not overlap with the orthographic projection of the active structure 60 on the plane where the display panel is located. That is, in this embodiment of the present invention, the second via 72 is arranged away from the active structure 60, making the second via 72 a dummy via that is not used for electrical connection.

[0068] Optionally, in embodiments of the present application, the second via hole 72 can be arranged in the gate drive circuit region NA1. As shown in Figure 14 Figure 14 A via hole distribution diagram of a gate drive circuit region provided in embodiments of the present application is shown in the figure, wherein the gate drive circuit region NA1 includes both the first via hole 71 for electrical connection and the second via hole 72 not for electrical connection. The first via hole 71 and the second via hole 72 are distinguished by different filling patterns.

[0069] Alternatively, as shown in Figure 15 Figure 15 A via hole distribution diagram of a gate drive circuit region provided in embodiments of the present application is shown in the figure, wherein the gate drive circuit region NA1 includes both the first via hole 71 for electrical connection and the second via hole 72 not for electrical connection. The first via hole 71 and the second via hole 72 are distinguished by different filling patterns.

[0070] Alternatively, embodiments of the present application can also arrange the above-mentioned second via hole 72 in both the gate drive circuit region NA1 and the gate drive circuit region NA2.

[0071] By arranging the second via hole 72 not for electrical connection in the gate drive circuit region NA1 and / or the gate drive circuit region NA2, embodiments of the present application can balance the via hole density of the gate drive circuit region NA1 and / or the gate drive circuit region NA2 originally having uneven via hole density, and further balance the hydrogen content of the first inorganic insulating layer 641 and the active structure 60 at different positions in the gate drive circuit region NA1 and / or the gate drive circuit region NA2 when hydrogenation treatment is performed on the first inorganic insulating layer 641 and the active structure 60, so as to make the characteristics of the TFT devices at different positions in the gate drive circuit region NA1 and / or the gate drive circuit region NA2 consistent, thereby making the brightness of the sub-pixels at different positions consistent when the peripheral circuit composed of the TFTs in the gate drive circuit region NA1 and / or the gate drive circuit region NA2 drives the sub-pixels in the display region to display, avoiding the display unevenness phenomenon of over-dark or over-bright at some positions, and being beneficial to improving the display uniformity of the display panel.

[0072] For example, the first electrode 611 can be a gate electrode, the second electrode 612 can be a source electrode, and the third electrode 613 can be a drain electrode.

[0073] The first inorganic insulating layer 641 can include a two-layer or multi-layer structure formed in steps.

[0074] Optionally, in order to ensure that the second via hole 72 is not used for electrical connection of the conductor structures on the upper and lower sides thereof, the second via hole 72 is arranged away from the active structure 60, as shown in Figure 13 ​​As shown, the second electrode 62 and the third electrode 63 can also be configured such that the normal projection of the second electrode 62 on the plane of the display panel and the normal projection of the third electrode 63 on the plane of the display panel do not overlap with the normal projection of the second via hole 72 on the plane of the display panel. For example, when the metal layer of the second electrode 62 and the third electrode 63 is prepared by sputtering or evaporation, a shielding part can be arranged at the position corresponding to the second via hole 72 to avoid the metal material from falling on the position, so as to avoid the formation of the metal material filling the second via hole 72 in the second via hole 72.

[0075] Optionally, after the preparation of the second electrode 62 and the third electrode 63 is completed, a second inorganic insulating layer 642 can be formed on the side of the second electrode 62 and the third electrode 63 away from the active structure 60, and the second inorganic insulating layer 642 can be a passivation layer. The second via hole 72 can be filled with the material of the second inorganic insulating layer 642. Figure 13

[0076] In the embodiments of the present application, by additionally arranging the second via hole 72 in the non-display area NA which does not serve the purpose of electrical connection, the density of the via holes including the first via hole 71 and the second via hole 72 at different positions in the non-display area NA can be made the same. Specifically, as shown in Figure 14 and Figure 15 the density of the via holes at different positions in the gate drive circuit area NA1 and the gate drive circuit area NA2 is the same. By setting the density of the via holes at different positions in the non-display area including the gate drive circuit area NA1 and the gate drive circuit area NA2 to be the same, the embodiments of the present application can balance the hydrogen content of the first inorganic insulating layer 641 and the active structure 60 at different positions in the gate drive circuit area NA1 and / or the gate drive circuit area NA2 to a greater extent, and thus can make the performance of the TFTs at different positions in the gate drive circuit area NA1 and / or the gate drive circuit area NA2 consistent, so as to make the display brightness at different positions in the display area consistent when the peripheral circuit composed of the TFTs drives the display of the sub-pixels in the display area.

[0077] ​In addition, in the prior art design, the density of TFTs in the display area AA is generally greater than the density of TFTs in the non-display area. In particular, as the pixel resolution increases, the density of TFTs in the display area AA also becomes greater. Therefore, the density of the first via holes 71 in the non-display area NA that serve the electrical connection function is less than the density of the first via holes 71 in the display area AA. The embodiments of the present application can increase the via hole density in the non-display area NA by adding the second via holes 72 that do not serve the electrical connection function in the non-display area NA, and can make the via hole density in the non-display area NA consistent or tend to be consistent with the via hole density in the display area AA on the basis of balancing the via hole density at different positions in the non-display area NA, so that the hydrogenation degree of the first inorganic insulating layer 641 and the active structure 60 at different positions in the display area AA and the non-display area NA in the entire display panel can be consistent or tend to be consistent, so that the hydrogen content of the first inorganic insulating layer 641 and the active structure 60 at different positions in the display area AA and the non-display area NA in the display panel can be the same or tend to be the same, and the TFT characteristics in the display area AA and the non-display area NA in the display panel can be consistent or tend to be consistent, which can further improve the brightness uniformity of the display panel.

[0078] For example, when the second via hole 72 is arranged in the gate drive circuit area NA1, as shown in FIG. 6, Figure 16 Figure 16 FIG. 7 is an enlarged schematic view of a part of the position of a gate drive circuit area provided by an embodiment of the present application, in which two adjacent gate drive circuit units 4 are shown as an example, and each gate drive circuit unit 4 can be arranged according to the structure shown in FIG. 5, that is, including 10 transistors T21, T22, T23, …, T28, T29, T30 and three storage capacitors C21, C22, C33. Figure 9 Figure 10 The source and drain of each of the transistors T21, T22, T23, …, T28, T29, T30 are connected to the active structure 60 through the first sub via hole 711 and the second sub via hole 712. The embodiments of the present application arrange the orthographic projection of the second via hole 72 on the plane of the display panel between the orthographic projections of the adjacent two gate drive circuit units 4 on the plane of the display panel, so as to increase the number of via holes between the adjacent two gate drive circuit units 4 and make the via hole density between the gate drive circuit units 4 and inside the gate drive circuit units 4 consistent.

[0079] ​​Currently, the circuit structures between and within the gate drive circuit units 4 are not completely identical. Generally, because other circuit traces are provided between adjacent gate drive circuit units 4, the spacing between adjacent gate drive circuit units 4 is increased, resulting in a relatively low via density near the TFTs at the edges of the gate drive circuit units 4. By adding a second via 72 between two adjacent gate drive circuit units 4, the embodiment of the present invention can make the via density at different locations in the gate drive circuit area NA1 more consistent, thereby making the characteristics of the TFTs at different locations in the gate drive circuit unit 4 more consistent, thereby improving the display uniformity of the display panel.

[0080] It should be noted that Figure 2 The gate drive circuit area NA1 shown as being arranged on the left side of the display area AA is merely an illustration. In fact, the gate drive circuit area NA1 may also be arranged on the right side of the display area AA, or the gate drive circuit area NA1 may be arranged on both the left and right sides of the display area to drive the scan lines from both sides, that is, using a bilateral drive method to reduce the impact of signal delay.

[0081] in addition, Figure 16 The arrangement of the second vias 72 shown is for illustration only. In actual arrangement, the second vias 72 may be arranged according to the arrangement pattern of the first vias 71 within a single gate drive circuit unit 4. Specifically, the arrangement pattern of the vias includes characteristics such as the arrangement direction of the vias, the spacing between adjacent vias, and the area and depth of the vias.

[0082] For example, when the second via hole 72 is provided in the gate circuit area NA2, as shown in FIG. Figure 17 As shown, Figure 17 This is an enlarged schematic diagram of a portion of a gating circuit area NA2 provided in an embodiment of the present invention, wherein two adjacent gating circuit groups 5 are shown as an example, wherein each gating circuit group 5 can be configured as follows: Figure 11 and Figure 12 The structure shown includes six transistors, M1, M2, ..., M5, and M6. The same clock signal line can connect corresponding TFTs belonging to different gating circuit groups. In this embodiment of the present invention, the orthographic projection of the second via 72 on the plane where the display panel is located is located between the orthographic projections of two adjacent gating circuit groups 5 on the plane where the display panel is located, thereby increasing the number of vias between two adjacent gating circuit groups 5 and making the via density between and within the gating circuit groups 5 tend to be consistent.

[0083] At present, the circuit structures between the gate circuit groups 5 and inside the gate circuit groups 5 are also not completely the same. Generally, some other circuit wires are also arranged between the adjacent gate circuit groups 5, so that the spacing between the adjacent gate circuit groups 5 is enlarged, and the via hole density near the TFTs at the edge of the gate circuit group 5 is relatively small. The embodiment of the present application can make the via hole densities at different positions in the gate circuit area NA2 consistent by additionally arranging the second via hole 72 between the two adjacent gate circuit groups 5, so as to make the characteristics of the TFTs at different positions in the gate circuit group 5 consistent, and improve the display uniformity of the display panel.

[0084] It should be noted that, Figure 17 The arrangement mode of the second via hole 72 shown is only schematic, and in actual arrangement, the second via hole 72 can be arranged according to the arrangement rule of the first via hole 71 inside the single gate circuit group 5.

[0085] In the embodiment of the present application, on the basis of arranging the second via hole 72, the embodiment of the present application can arrange the wires passing through the corresponding positions of the second via hole 72 as winding wires such as serpentine winding or Z-shaped winding, so as to balance the load uniformity of each wire. Moreover, when the shape of the display panel is designed as a circular shape or a special shape including a notch, the embodiment of the present application can also arrange some connecting wires between different circuit devices at the positions of the second via holes, so as to narrow the frame width of the display panel.

[0086] For example, taking the design of the shape of the display panel as a circular shape as an example, as shown in Figure 18 Figure 18 ​A schematic diagram of another display panel provided for an embodiment of the present invention, wherein a gating circuit area provided with a gating circuit group 5 and a gate driving circuit area provided with a gate driving circuit unit 4 are both arranged around the display area. Moreover, in an embodiment of the present invention, the gating circuit area can be arranged on a side of the gate driving circuit area close to the display area AA. On this basis, the embodiment of the present invention allows a certain spacing between two adjacent gate driving circuit units 4, so that the driver chip IC can be connected to the driver chip IC and the gating circuit group 5 through the spacing between the two adjacent gate driving circuit units 4. Similarly, the embodiment of the present invention can also allow a certain spacing between two adjacent gating circuit groups 5, so that the gate driving circuit unit 4 can be connected to the scan line 2 of the display area AA through the wiring between the gating circuit groups 5. Such a setting can fully and effectively utilize the space of the non-display area and narrow the border of the display panel. Moreover, such a setting is equivalent to reusing the space in the area where the second via 72 is located. On the basis of improving the uniformity of the via density at different positions in the display panel, by setting the connection lines between the driver chip IC and the selection circuit group 5, as well as the gate driver circuit unit 4 and the scan line 2 at the location of the second via 72, the setting of the peripheral circuits including the gate driver circuit unit 4 and the selection circuit group 5 in the non-display area of ​​the display panel can be made more compact.

[0087] It is understandable that Figure 2 and 18 The shape of the display panel shown is for illustration only. In actual panel design, the display panel can be designed in other shapes based on different usage requirements. The layout of the gate drive circuit unit and the gating circuit group in the non-display area can be adjusted accordingly to match the display panel shape. Accordingly, the location of the second via 72 can also take into account the overall wiring layout of the display panel. The location of the second via can be flexibly adjusted based on the comprehensive considerations of reducing the area of ​​the non-display area and balancing the load of each wiring.

[0088] like Figure 19 and Figure 20 As shown, Figure 19 A schematic top view of another display panel provided by an embodiment of the present invention is shown. Figure 20 for Figure 19 An enlarged schematic diagram of the middle area Q, wherein the display area of ​​the display panel includes a first display area AA1 and a second display area AA2; the density of sub-pixels in the first display area AA1 is less than the density of sub-pixels in the second display area AA2, and accordingly, the density of pixel circuits 11 in the first display area AA1 is also less than the density of pixel circuits 11 in the second display area AA2, so as to improve the light transmittance of the first display area AA1. Subsequently, an under-screen camera can be set corresponding to the first display area AA1 to increase the screen-to-body ratio of the display panel.

[0089] Optionally, the pixel circuits 11 in the first display area AA1 and the second display area AA2 can adopt the following Figure 6 and Figure 7 The 7T1C structure shown includes seven transistors T11, T12, ..., T16, T17 and one storage capacitor C1, wherein the transistors T11, T12, ..., T16, T17 are each provided with a first sub-via 711 and a second sub-via 712 for electrical connection.

[0090] On the basis of improving the light transmittance of the first display area AA1, as Figure 20 As shown, in an embodiment of the present invention, a second via 72 may be provided in the first display area AA1 to balance the via density at different positions in the first display area AA1, thereby making the hydrogenation degrees of the first inorganic insulating layer 641 and the active structure 60 at different positions in the first display area AA1 close, so that the performance of the TFTs at different positions in the first display area AA1 tends to be consistent, thereby improving the brightness uniformity of the sub-pixels in the first display area AA1.

[0091] Specifically, such as Figure 20 As shown, the orthographic projection of the second via 72 on the plane where the display panel is located is located between two adjacent pixel circuits 11 in the first display area AA1, so that the via density at different positions in the first display area AA1 tends to be consistent, and further the characteristics of the TFTs at different positions in the pixel circuits included in the first display area AA1 tend to be consistent, so as to further improve the display uniformity of the first display area AA1.

[0092] Optionally, when providing the second via holes 72 , the arrangement pattern of the second via holes 72 may be substantially the same as the arrangement pattern of the first via holes 71 in a single pixel circuit in the first display area AA1 .

[0093] For example, in an embodiment of the present invention, the arrangement pattern of the vias in the first display area AA1 and the second display area AA2 can be made substantially the same. For example, on the basis of the identical structure of the pixel circuits in the first display area AA1 and the second display area AA2, by making the arrangement pattern of the second vias 72 substantially the same as the arrangement pattern of the first vias 71 in a single pixel circuit in the first display area AA1, the via density and arrangement pattern of the vias in the first display area AA1 and the second display area AA2 can be made consistent, thereby ensuring that the display brightness at different positions of the entire display panel, including the first display area AA1 and the second display area AA2, can be made consistent.

[0094] The embodiment of the present invention also provides a method for preparing a display panel, Figure 2 、 Figure 13 and Figure 21 As shown, Figure 21A flowchart of a preparation method of a display panel is provided for an embodiment of the present application. The display panel includes a display area AA and a non-display area NA. The non-display area NA includes a gate drive circuit area NA1 and a gate control circuit area NA2. The preparation method includes the following steps.

[0095] Step S1: providing a substrate 01;

[0096] Then, pixel circuits, a gate control circuit group 5, and a gate drive circuit unit 4 are formed on one side of the substrate 01. The pixel circuits are located in the display area AA. The gate control circuit group 5 is located in the gate control circuit area NA2. The gate drive circuit unit 4 is located in the gate drive circuit area NA1. The pixel circuits, the gate control circuit group 5, and the gate drive circuit unit 4 each include a plurality of transistors TFT. The transistors include an active structure 60, a first electrode 61, a second electrode 62, and a third electrode 63.

[0097] In combination with FIGS. 1-3, Figure 13 and Figure 21 As shown in FIGS. 1-3, the method of forming the pixel circuits, the gate control circuit group 5, and the gate drive circuit unit 4 includes the following steps.

[0098] Step S2: forming the active structure 60, the first electrode 61, and a first inorganic insulating layer 641 on one side of the substrate 01. The first inorganic insulating layer 641 is located on a side of the active structure 60 away from the substrate 01. Illustratively, the first inorganic insulating layer 641 can include a two-layer structure formed in steps.

[0099] Step S3: forming a via in the first inorganic insulating layer 641. The via includes a first via 71 and a second via 72. The first via 71 includes a first sub-via 711 and a second sub-via 712. The first sub-via 711 and the second sub-via 712 each at least partially overlap the active structure 60 in a projection of a plane in which the substrate 01 is located. The second via 72 does not overlap the active structure 60 in the projection of the plane in which the substrate 01 is located. The gate control circuit area NA2 includes the second via 72. And / or, the gate drive circuit area NA1 includes the second via 72.

[0100] Step S4: performing a hydrogenation treatment on the first inorganic insulating layer 641. Illustratively, when the hydrogenation treatment is performed on the first inorganic insulating layer 641, hydrogen atoms can move from the first inorganic insulating layer to the active structure 60 located below the first inorganic insulating layer, so that hydrogen atoms can also be doped in the active structure 60, thereby improving the conductivity of the active structure 60.

[0101] Step S5: forming a second electrode 62 and a third electrode 63 on the side of the hydrogenated first inorganic insulating layer 641 away from the base substrate 01 , wherein the second electrode 62 is electrically connected to the active structure 60 through the first sub-via 711 , and the third electrode 63 is electrically connected to the active structure 60 through the second sub-via 712 .

[0102] The method for preparing a display panel provided by an embodiment of the present invention can balance the via density of the gate drive circuit area NA1 and / or the gate circuit area NA2, which originally has uneven via density, by setting a second via 72 that does not serve as an electrical connection in the gate drive circuit area NA1 and / or the gate circuit area NA2. Furthermore, when the first inorganic insulating layer 641 and the active structure 60 are hydrogenated, the hydrogen content of the first inorganic insulating layer 641 and the active structure 60 at different positions in the gate drive circuit area NA1 and / or the gate circuit area NA2 can be balanced, thereby making the characteristics of the TFT devices at different positions in the gate drive circuit area NA1 and / or the gate circuit area NA2 tend to be consistent. Therefore, when the peripheral circuit composed of these TFTs in the gate drive circuit area NA1 and / or the gate circuit area NA2 drives the display of the sub-pixels located in the display area, the brightness of the sub-pixels at different positions can be made consistent, thereby avoiding the uneven display phenomenon of some positions being too dark or too bright, which is beneficial to improving the display uniformity of the display panel.

[0103] For example, Figure 13 As shown, the orthographic projection of the second electrode 62 on the plane where the base substrate 01 is located and the orthographic projection of the third electrode 63 on the plane where the base substrate 01 is located do not overlap with the orthographic projection of the second via hole 72 on the plane where the base substrate 01 is located.

[0104] When setting the second via hole 72, optionally, Figure 14 and Figure 15 As shown, the density of the via holes at different positions in the non-display area NA can be made the same.

[0105] In addition, in the embodiment of the present invention, the density of the via holes in the display area AA and the non-display area NA may be made the same.

[0106] For example, Figure 20 As shown, the display area AA includes a first display area AA1 and a second display area AA2; the density of pixel circuits in the first display area AA1 is less than the density of pixel circuits in the second display area AA2; when setting the second via hole 72, the second via hole 72 can be set in the first display area AA1.

[0107] Optional, such as Figure 20 As shown, in the embodiment of the present invention, the orthographic projection of the second via hole 72 on the plane where the display panel is located can be located between two adjacent pixel circuits in the first display area AA1.

[0108] For example, the density of the via holes in the first display area AA1 and the second display area AA2 can be the same.

[0109] The specific arrangement position of the second via hole 72 and the corresponding beneficial effect can be referred to the content of the display panel part, which will not be repeated here.

[0110] The embodiment of the present application also provides a display device, such as Figure 22 As shown in the figure, Figure 22 A schematic diagram of a display device provided by the embodiment of the present application is shown, wherein the display device comprises the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiment, which will not be repeated here. Of course, Figure 22 The display device shown in the figure is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a tablet computer, a notebook computer, an e-paper or a television.

[0111] The display device provided by the embodiment of the present application can balance the via hole density of the gate driving circuit area and / or the gate driving circuit area which originally has uneven via hole density in the display device by arranging the second via hole which does not have the electrical connection function in the gate driving circuit area and / or the gate driving circuit area, and then can balance the hydrogen content of the first inorganic insulating layer and the active structure at different positions in the gate driving circuit area and / or the gate driving circuit area when the hydrogenation treatment is performed on the first inorganic insulating layer and the active structure, and then the characteristics of the TFT devices at different positions in the gate driving circuit area and / or the gate driving circuit area tend to be consistent, so that the brightness of the sub-pixels at different positions tends to be consistent when the peripheral circuit composed of the TFT in the gate driving circuit area and / or the gate driving circuit area drives the sub-pixels in the display area to display, and the display uneven phenomenon of over-dark or over-bright at some positions can be avoided, which is beneficial to improve the display uniformity of the display panel.

[0112] The above only describes the preferred embodiments of the present application and should not be used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A display area, the display area including a first display area and a second display area, the light transmittance of the first display area being greater than the light transmittance of the second display area; Also includes: substrate; a plurality of pixel circuits, the pixel circuits comprising a plurality of transistors, the transistors comprising active structures; a first inorganic insulating layer, wherein the first inorganic insulating layer is located on a side of the active structure away from the substrate; a via hole penetrating the first inorganic insulating layer, the via hole including a second via hole located in the first display area; There is a gap between the orthographic projection of the second via hole on the substrate and the orthographic projection of the active structure on the substrate; The second via hole is a dummy via hole.

2. The display panel according to claim 1, wherein: The first display area and the second display area both include the pixel circuits, wherein a density of the pixel circuits in the first display area is smaller than a density of the pixel circuits in the second display area.

3. The display panel according to claim 1, wherein: The first display area includes a plurality of pixel circuits; The orthographic projection of the second via hole on the plane where the display panel is located is located between the orthographic projections of two adjacent pixel circuits in the first display area on the plane where the display panel is located.

4. The display panel according to claim 2, wherein: The orthographic projection of the second via hole on the plane where the display panel is located is located between the orthographic projection of the pixel circuit in the first display area on the plane where the display panel is located and the orthographic projection of the pixel circuit in the second display area on the plane where the display panel is located.

5. The display panel according to claim 1, wherein: The transistor further includes a first electrode, a second electrode and a third electrode, wherein the first electrode is a gate of the transistor; The via hole further includes a first via hole; The first via includes a first sub-via and a second sub-via; the second electrode is electrically connected to the active structure through the first sub-via, and the third electrode is electrically connected to the active structure through the second sub-via; The second display area includes the first via hole.

6. The display panel according to claim 5, wherein: The first inorganic insulating layer is located between the second electrode and the active structure.

7. The display panel according to claim 5, wherein: The density of the via holes in the first display area and the second display area is the same.

8. The display panel according to claim 1, wherein: The device further includes a non-display area, the non-display area including a gate drive circuit area, the gate drive circuit area including a plurality of gate drive circuit units; the gate drive circuit units including a plurality of transistors having active structures; the first inorganic insulating layer is located on a side of the active structure of the transistors of the gate drive circuit units away from the base substrate; The via hole further includes a second via hole located in the gate driving circuit area.

9. The display panel according to claim 8, wherein: The display area further includes a scan line electrically connected to the pixel circuit; The orthographic projection of the second via hole in the gate driving circuit area on the plane where the display panel is located is located between the orthographic projections of two adjacent gate driving circuit units on the plane where the display panel is located.

10. The display panel according to claim 1, wherein The device further comprises a non-display area, wherein the non-display area comprises a gate circuit area, wherein the gate circuit area comprises a plurality of gate circuit groups; the gate circuit groups comprise a plurality of transistors having active structures; and the first inorganic insulating layer is located on a side of the active structures of the transistors of the gate circuit groups away from the substrate. The vias further include a second via located in the gate circuit region.

11. The display panel according to claim 10, wherein: The display area further includes a data line electrically connected to the pixel circuit; The gating circuit group includes M transistors; The non-display area further includes a data driver, the data driver including a plurality of data output terminals, one of the data output terminals being electrically connected to M data lines via one of the gating circuit groups; wherein M is an integer greater than 1; The orthographic projection of the second via hole in the gating circuit area on the plane where the display panel is located is located between the orthographic projections of two adjacent gating circuit groups on the plane where the display panel is located.

12. The display panel according to claim 1, wherein The first inorganic insulating layer includes at least two film layers.

13. A display panel, characterized in that: include: Display area, the display area includes a first display area and a second display area, the first display area is the under-screen camera setting area; Also includes: substrate; a plurality of pixel circuits, the pixel circuits comprising a plurality of transistors, the transistors comprising active structures; a first inorganic insulating layer, wherein the first inorganic insulating layer is located on a side of the active structure away from the substrate; a via hole penetrating the first inorganic insulating layer, the via hole including a second via hole located in the first display area; There is a gap between the orthographic projection of the second via hole on the substrate and the orthographic projection of the active structure on the substrate; The second via hole is a dummy via hole.

14. The display panel according to claim 13, wherein: The first display area and the second display area both include the pixel circuits, wherein a density of the pixel circuits in the first display area is smaller than a density of the pixel circuits in the second display area.

15. The display panel according to claim 13, wherein: The transistor further includes a first electrode, a second electrode and a third electrode, wherein the first electrode is a gate of the transistor; The via hole further includes a first via hole located in the second display area; The first via includes a first sub-via and a second sub-via; the second electrode is electrically connected to the active structure through the first sub-via, and the third electrode is electrically connected to the active structure through the second sub-via.

16. The display panel according to claim 15, wherein: The first inorganic insulating layer is located between the second electrode and the active structure.

17. The display panel according to claim 15, wherein: The density of the via holes in the first display area and the second display area is the same.

18. The display panel according to claim 13, wherein: The orthographic projection of the second via hole on the plane where the display panel is located is located between the orthographic projections of two adjacent pixel circuits in the first display area on the plane where the display panel is located.

19. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 13 to 18.

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