SiC power device termination structure with n-type equipotential ring

Abstract

The application discloses a SiC power device terminal structure with an N-type equipotential ring, which comprises a substrate, the substrate is arranged on a drain metal layer, a drift layer is arranged on the substrate, a source region, a transition region and a terminal region are sequentially arranged on the drift layer from the center to the edge, a first ohmic contact metal of a source region cell structure, a second ohmic contact metal of the transition region and a third ohmic contact metal of the terminal region are all electrically connected with a source electrode of the source region, and a gate run track electrode of the transition region is electrically connected with a gate electrode of the source region. The application does not need an additional process step and has good compatibility with different cell structures and terminal structures.

Description

Technical Field

[0001] This invention belongs to the field of SiC power device technology, specifically relating to a SiC power device termination structure with an N-type equipotential ring. Background Technology

[0002] Compared to Si, 4H-SiC offers several key advantages in power device applications: a larger bandgap (2.9 times that of Si), resulting in significantly higher operating temperatures and radiation resistance; a higher critical breakdown field (approximately 10 times that of Si), leading to lower drift region on-resistance while meeting voltage requirements; a higher electron saturation velocity (twice that of Si), enabling faster turn-on and turn-off processes and making it more suitable for high-frequency applications; and higher thermal conductivity (3.3 times that of Si), resulting in better heat dissipation for Si-based power devices, reducing the need for heat dissipation devices in power electronic systems and facilitating further miniaturization. Furthermore, SiC power devices offer better process flow compatibility with Si-based devices, making them a strong alternative in cutting-edge technology fields such as rail transportation, new energy vehicles, photovoltaic inverters, renewable energy power generation, and military defense.

[0003] Power devices are typically fabricated using a process that connects several cell structures in parallel on a semiconductor wafer. While the surface voltages between the cells in the active region are roughly the same, the voltage between the terminal (outermost end) and the substrate differs significantly. Therefore, measures are needed to reduce the surface electric field and increase the breakdown voltage. This technique is called junction termination technology. Junction termination technology involves setting an extension structure at the edge of the active region, widening the main junction depletion region outwards to improve the device's breakdown voltage, thus preventing the gate of the power device from being broken down and protecting the chip device.

[0004] In the fabrication of silicon carbide power device terminals, due to the long transition region, a reasonable approach is to add an equipotential ring before the field ring, clamping the front end of the field ring to zero potential at the source via an ohmic contact. However, the mainstream equipotential ring implantation region is currently P-type doped. For silicon carbide processes, the ohmic contact quality of P-type doping is inferior to that of N-type doping. Furthermore, the added equipotential ring introduces additional drain-source capacitance in the terminal region. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a SiC power device termination structure with an N-type equipotential ring to address the shortcomings of the prior art and solve the technical problems of poor ohmic contact quality and increased drain-source capacitance in the termination region.

[0006] The present invention adopts the following technical solution:

[0007] A SiC power device termination structure with an N-type equipotential ring includes a substrate disposed on a drain metal layer and a drift layer disposed on the substrate. An active region, a transition region, and a termination region are sequentially disposed on the drift layer from the center to the edge. The first ohmic contact metal of the active region cell structure, the second ohmic contact metal of the transition region, and the third ohmic contact metal of the termination region are all electrically connected to the source of the active region. The gate raceway electrode of the transition region is electrically connected to the gate of the active region.

[0008] The transition region, from bottom to top, includes a drain, an N+ substrate, and an N-type drift region. The N-type drift region, from the center to both ends, includes an oxide layer of adjacent cell structures and polysilicon, a P- region and an N+ region of adjacent cells, a second ohmic contact metal, and a P+ main ring. The P+ main ring is provided with a field oxide layer, a gate raceway, a gate raceway metal, and a passivation layer.

[0009] Specifically, the cell structure is a silicon carbide MOSFET or a silicon carbide IGBT.

[0010] Furthermore, when the cell structure is a silicon carbide MOSFET, it includes, from bottom to top, a drain, an N+ substrate, an N-type drift region, a P region, an N+ region, a P+ region, an oxide layer, polysilicon, and a first ohmic contact metal.

[0011] Specifically, the protocellular structure is hexagonal, strip-shaped, or rectangular.

[0012] Specifically, the substrate is a silicon carbide substrate of the first conductivity type, and the drift layer is of the first conductivity type.

[0013] Specifically, the grid track and the second ohmic contact metal are isolated by a passivation layer.

[0014] Specifically, the polysilicon gate track and the polysilicon gate in the active region are formed simultaneously and connected by a polysilicon bridge.

[0015] Furthermore, the second ohmic contact metal covers the P+ region, N+ region / P+ region, or N+ region of the cell structure.

[0016] Specifically, the terminal area includes a P area, which is connected to the P+ main ring of the transition area. Above the P area are an N+ area, a third ohmic contact metal, and a P+ ring. Above the P+ ring are a field oxygen layer, an N+ stop ring, and a passivation layer.

[0017] Specifically, the terminal area is a JTE structure or a field-limiting loop structure.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects:

[0019] A SiC power device termination structure with an N-type equipotential ring faces challenges during breakdown voltage testing. The P+ main ring in the transition region can be tens of micrometers long, with some chip corners reaching approximately one hundred micrometers. This can lead to a potential difference between the two sides of the P+ main ring (active region side and field ring side), affecting the electric field distribution in the termination section, resulting in a lower breakdown voltage and poorer blocking characteristics. To address this, a common practice is to create a window in the passivation layer at the end of the P+ main ring and connect it to the source metal using an ohmic contact process, clamping it to zero potential. This effectively improves the device's blocking characteristics and reliability. However, the P-type ohmic contact process for SiC materials is less stable than the N-type ohmic contact process, resulting in relatively higher contact resistance and poorer ohmic contact quality. To address this issue, this invention, based on the above design, performs an additional P- and N+ injection at the end of the P+ main ring (field ring side) and connects the N+ ring to the source metal via an ohmic contact, clamping it to zero potential; this is called an N+ equipotential ring. Because the N-type ohmic contact process has higher quality and the contact resistance difference between different regions of the equipotential ring is smaller, the electric field distribution at the device terminal is more uniform, the blocking characteristics are more stable, and the reliability is better.

[0020] Furthermore, the N+ equipotential ring does not require additional process steps, and the injection parameters of the N+ part and the ohmic contact process parameters are consistent with the fabrication process of the active region of the device.

[0021] Furthermore, the N+ injection window on the active region side of the P+ main ring is enlarged to cover the source ohmic contact window; thus, the ohmic contacts on both sides of the P+ main ring are N-type ohmic contacts, resulting in better consistency. Essentially, the P+ main ring is no longer directly coupled to the device source, but rather through a unidirectional PN diode, which reduces the drain-source capacitance of the device transition region.

[0022] Furthermore, for the terminal structure without a grid, a relatively long transition region is still required at the corner of the device. This invention performs P- / N+ injection below the entire transition region and uses an N+ equipotential ring to clamp the transition region in front of the field ring to zero potential, making the electric field distribution in the transition region of the device more uniform and improving the blocking characteristics of the device.

[0023] Furthermore, the transition region, from bottom to top, includes a drain, an N+ substrate, and an N-type drift region. The N-type drift region, from the center to both ends, includes an oxide layer and polysilicon of adjacent cell structures, a P- region and an N+ region of adjacent cells, a second ohmic contact metal, and a P+ main ring. All structural designs are compatible with the fabrication process of the active region and require no additional process steps.

[0024] Furthermore, this invention only targets the transition region and does not require changes to the process steps and parameters of the active region of the device. Therefore, it is compatible with different cell structures, such as SiC MOSFETs and SiC IGBTs with different voltage ratings.

[0025] Furthermore, this invention only applies to the transition region and does not require changes to the process steps and parameters of the terminal region. Therefore, it is compatible with different terminal structures, including JTE structures and field-limiting ring structures.

[0026] In summary, the N-type equipotential ring used in this invention has good ohmic contact quality, can effectively and uniformly distribute the electric field in the transition region during withstand voltage, improve the blocking characteristics of the device, and reduce the drain-source capacitance in the transition region; it requires no additional process steps and has good compatibility with different cell structures and termination structures.

[0027] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0028] Figure 1 This is a top view of a traditional silicon carbide MOSFET chip.

[0029] Figure 2 This is a schematic cross-sectional view of the silicon carbide MOSFET chip of the present invention.

[0030] Figure 3 This is a schematic diagram of the second cross-sectional structure of the silicon carbide MOSFET chip of the present invention;

[0031] Figure 4 This is a schematic diagram of the third cross-sectional structure of the silicon carbide MOSFET chip of the present invention.

[0032] Wherein, 101. Terminal; 102. Active region; 103. Gate electrode; 104. Source electrode; 201. First substrate; 202. First drift layer; 203. First drain metal layer; 210. First active region; 211. First well region; 212. First source region; 213. First enhancement region; 214. First gate oxide layer; 215. First gate; 216. First gate insulating layer; 217. First source metal layer; 218. Second well region; 219. Second source region; 220. First transition region; 221. Second enhancement region; 222. Third well region; 2 23. Third source region; 224. Third source metal layer; 225. First field oxide layer; 226. First gate raceway; 227. First gate raceway insulating layer; 228. Gate raceway metal layer; 229. Second source metal layer; 230. First termination region; 231. First field limiting ring; 232. Second field oxide layer; 233. First cutoff ring; 301. Second substrate; 302. Second drift layer; 303. Second drain metal layer; 310. Second active region; 311. Fourth well region; 312. Fourth source region; 313. Third enhancement region; 314. Second gate oxide layer; 315. Second gate; 316. Second gate insulating layer; 317. Fourth source metal layer; 318. Fifth well region; 319. Fifth source region; 320. Second transition region; 321. Fourth enhancement region; 322. Sixth well region; 323. Sixth source region; 324. Sixth source metal layer; 325. Third field oxide layer; 326. Second gate raceway; 327. Second gate raceway insulating layer; 328. Second gate raceway metal layer; 329. Fifth source metal layer; 330. Second termination region; 331. Second field limiting ring; 332. Fourth field oxide layer; 333. Second cut-off region. 401. Stop ring; 402. Third substrate; 403. Third drift layer; 410. Third drain metal layer; 411. Third active region; 412. Seventh well region; 413. Seventh source region; 414. Fifth enhancement region; 415. Third gate oxide layer; 416. Third gate; 417. Seventh source metal layer; 418. Eighth well region; 419. Eighth source region; 420. Third termination region; 421. Eighth source metal layer; 422. Sixth enhancement region; 423. Third field limiting ring; 424. Fifth field oxide layer; 425. Third stop ring. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0036] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0037] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0038] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] Please see Figure 1 Terminal 101 and active region 102 are fabricated on the same substrate, with metal and passivation layers covering their surfaces. The area below the surface of terminal 101 is the designed field ring and transition region, and the area below the surface of 102 is the cell portion. Gate electrode 103 is the gate metal window exposed by the passivation layer of terminal 101 and active region 102. The area below the surface of gate electrode 103 is a polysilicon gate connected to the gate of the cell. Source electrode 104 is the source metal window exposed by the passivation layer of terminal 101 and active region 102. Source electrode 104 includes two symmetrical source electrodes, both connected to the source of the cell.

[0041] This invention provides a SiC power device termination structure with an N-type equipotential ring, which improves the problems of poor ohmic contact quality and increased drain-source capacitance in the termination region without increasing or adjusting the process flow.

[0042] The present invention discloses a SiC power device termination structure with an N-type equipotential ring, comprising a substrate, a drift layer, an active region, a transition region, and a termination region; the drift layer is located above the substrate, and the active region, the transition region, and the termination region are arranged sequentially from the center to the edge on the drift layer.

[0043] The substrate is a silicon carbide substrate of the first conductivity type, and the drift layer is of the first conductivity type.

[0044] Optionally, the cell structure of the active region is a silicon carbide MOSFET or a silicon carbide IGBT.

[0045] When the cell structure of a SiC power device is a silicon carbide MOSFET, it includes, from bottom to top, a drain, an N+ substrate, an N-type drift region, a P region, an N+ region, a P+ region, an oxide layer, polysilicon, and a first ohmic contact metal.

[0046] The transition region, from bottom to top, includes the drain, the N+ substrate, and the N-type drift region.

[0047] The drift region includes, from the center to both ends, the oxide layer and polysilicon of the adjacent cells, the P- region and N+ region of the adjacent cells, the second ohmic contact metal, the P+ main ring and the field oxide layer on the P+ main ring, the gate raceway and the gate raceway metal, and the passivation layer above.

[0048] The terminal region is located above the drift region and includes the P region connected to the P+ main ring, the N+ region above the P region, the third ohmic contact metal, the P+ ring and the field oxygen layer above it, the N+ stop ring, and the passivation layer.

[0049] The ohmic contact metals of the cell structure, transition region, and terminal region are all electrically connected to the source electrode of the active region, and the electrode of the gate raceway is electrically connected to the gate of the active region.

[0050] The polysilicon gate in the transition region and the polysilicon gate in the active region are formed simultaneously and connected by a polysilicon bridge.

[0051] The grid track and the ohmic contact metal are isolated by a passivation layer.

[0052] The second ohmic contact metal in the transition region can cover P+, N+ / P+, or N+.

[0053] The transition zone can remove the fence runway area.

[0054] The protocell structure is hexagonal, strip-shaped, or rectangular.

[0055] The terminal area is either a JTE structure or a field-limited loop structure.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0057] The N-type doping and P-type doping mentioned in the embodiments of this invention are relative terms, and can also be referred to as the first doping and the second doping. That is, the interchangeability of N-type and P-type applies to the device as well.

[0058] In this embodiment of the invention, the structure of the MOSFET device is taken as SiC.

[0059] Example 1

[0060] Combination Figure 2As shown, this embodiment provides a SiC MOSFET device with an N+ equipotential ring. The SiC MOSFET device includes a first substrate 201, a first drift layer 202, a first drain metal layer 203, a first active region 210, a first transition region 220, and a first termination region 230.

[0061] For example, the first substrate 201 is an N+ silicon carbide substrate.

[0062] The first drift layer 202 is an N-type drift layer located above the first substrate 201. The doping concentration and thickness of the first drift layer 202 are adjusted according to the different voltage withstand capabilities of the chip.

[0063] The first drain metal layer 203 is located below the first substrate 201 and forms an ohmic contact with the first substrate 201.

[0064] The first active region 210, the first transition region 220 and the first terminal region 230 are all disposed on the first drift layer 202, with the first transition region 220 located between the first active region 210 and the first terminal region 230.

[0065] The first active region 210 includes several cellular structures, exemplarily, Figure 3 Only one cell structure is given, which includes a first well region 211, a first source region 212, a first enhancement region 213, a first gate oxide layer 214, a first gate 215, a gate insulating layer 216, a first source metal layer 217, a second well region 218, a second source region 219, and a second source metal layer 229.

[0066] The first well region 211 is P-type and is located on both sides of the cell structure and inside the surface of the first drift layer 202. The upper surface of the first well region 211 is flush with the upper surface of the first drift layer 202.

[0067] The first source region 212 is an N-type source region located within the surface of the first well region 211. The upper surface of the first source region 212 is flush with the upper surface of the first drift layer 202. The width of the first source region 212 is smaller than the width of the first well region 211. The width difference near the center of the cell structure forms a channel (not shown in the figure) between the first gate oxide layer 214 and the channel. The region between two adjacent channels is the JFET region (not shown in the figure).

[0068] The first enhancement region 213 is a P-type enhancement region. It is disposed side-by-side with the first source region 212 within the surface of the first well region 211 and contacts the end of the first source region 212 furthest from the cell structure center. The upper surface of the first enhancement region 213 is flush with the upper surface of the first drift layer 202. The end of the first enhancement region 213 furthest from the cell structure center is flush with the end of the first well region 211 furthest from the cell structure center; that is, the side of the surface of the first well region 211 furthest from the cell structure center is completely covered by the first enhancement region 213. The ion doping concentration of the first enhancement region 213 is greater than that of the first well region 211.

[0069] The planar gate is located at the center of the cell and includes a first gate oxide layer 214 and a first gate 215.

[0070] The first gate oxide layer 214 is located above the first drift layer 202 and simultaneously contacts the surfaces of the first source region 212, the first well region 211, and the first drift layer 202 to form a conductive channel. The thickness of the first gate oxide layer 214 is approximately 50 Nm. The first gate 215 is located above the first gate oxide layer 214 and is a polysilicon gate.

[0071] The first source metal layer 217 is located above the source region 212 and the first enhancement region 213, and simultaneously forms a good ohmic contact with both the first source region 212 and the first enhancement region 213. The first source metal 217 cannot contact the first drift layer 202. The first source metal 217 can be a metal with low contact resistivity, such as aluminum or nickel. The first source metal 217 is isolated from the gate insulating layer 214 and the first gate 215 by an interlayer dielectric layer 216.

[0072] The second well region 218 is P-type and is located at the junction of the cell structure and the transition region. The second well region 218 and the first well region 211 are formed by the same ion implantation process. Therefore, the upper surface of the second well region 218 is flush with the first well region 211, and the depth and doping concentration are the same.

[0073] The second source region 219 is an N-type source region located within the surface of the second well region 218. The upper surface of the second source region 219 is flush with the upper surface of the first drift layer 202. The width of the second source region 219 is smaller than the width of the second well region 218, and the width difference near the center of the cell structure forms a channel (not shown in the figure) between it and the first gate oxide layer 214. The second source region 219 and the first source region 212 are formed by the same ion implantation process, therefore the upper surface of the second source region 219 is flush with the first source region 212, and their depth and doping concentration are the same.

[0074] The second source metal layer 229 is located above the second source region 219, and its width is smaller than that of the second source region 219, with a width difference on both the left and right sides. The second source metal layer 229 forms a good ohmic contact with the second source region 219. The second source metal layer 229 can be a metal with low contact resistivity, such as aluminum or nickel.

[0075] The gate insulating layer 216 is located on the upper surface of the first source region 212 and the second source region 219, separating the first gate 215 from the first source metal layer 217 and the second source metal layer 229, and covering the first gate 215.

[0076] The first transition region 220 includes a second enhancement region 221, a third well region 222, a third source region 223, a third source metal layer 224, a first field oxygen layer 225, a first gate raceway 226, a first gate raceway insulating layer 227, and a first gate raceway metal layer 228.

[0077] The second enhancement region 221 is a P-type enhancement region located within the surface of the first drift layer 202. The upper surface of the second enhancement region 221 is flush with the upper surface of the first drift layer 202. The ion doping concentration of the second enhancement region 221 is the same as that of the first enhancement region 213, and the depth of the second enhancement region 221 is the same as that of the first enhancement region 213.

[0078] The third well region 222 is a P-type well region with its upper surface flush with the first drift layer 202. The ion doping concentration of the third well region 222 is the same as that of the first well region 211 in terms of both ion doping concentration and depth.

[0079] The upper surface of the third source region 223 is flush with the third well region 222, and the width of the third source region is smaller than the width of the third well region. The depth and doping concentration of the third source region 223 are the same as those of the first source region 212.

[0080] The third source metal layer 224 is located above the third source region 223, with a width smaller than that of the third source region 223, and a width difference on both the left and right sides. The third source metal layer 224 forms a good ohmic contact with the third source region 223. The third source metal layer 224 can be a metal with low contact resistivity, such as aluminum or nickel.

[0081] The first field oxygen layer 225 is located above the second enhancement region 221, with a thickness of 1 μm, and is horizontally positioned between the second source metal 229 and the third source metal layer 224.

[0082] The first gate raceway 226 is located above the first field oxide layer 225, and its width is smaller than that of the first field oxide layer 225, with a width difference on both the left and right sides. The gate raceway 228 and the first gate 215 are formed in the same step, both being polysilicon gates with the same thickness.

[0083] The first grid runway metal layer 228 is located on the upper surface of the first grid runway 226, and its width is smaller than that of the first grid runway 226, with a width difference on both sides. The grid runway metal layer can be made of metals with low contact resistivity such as nickel and titanium, and it is different from the active region metal layer, and is completed in two steps.

[0084] The first grid runway insulation layer 227 extends from the surface of the first field oxygen layer 225 to the top of the first grid runway 226, covering the portions of the first grid runway 226 that are not covered by the first grid runway metal layer 228.

[0085] The first terminal region 230 includes a first field limiting ring 231, a second field oxygen layer 232, and a first cutoff ring 233.

[0086] The first field-limiting ring 231 refers to a number of implantation rings spaced apart within the first drift layer 202, all of which are heavily doped P-type regions. The upper surface of the first field-limiting ring 231 is flush with the upper surface of the first drift layer 202. The ion doping concentration of the first field-limiting ring 231 can be the same as that of the first enhancement region 213, or it can be a heavily doped region with other concentrations.

[0087] The second field oxide layer 232 is located on the upper surface of the first field limiting ring 231 and is adjacent to the third source metal layer 224. The second field oxide layer and the first field oxide layer are generated in the same process step, and both have a thickness of 1 μm.

[0088] The upper surface of the first cutoff ring 233 is flush with the first drift layer 202 and located at the edge of the device. The first cutoff ring 233 is heavily N-type doped, using the same ion doping concentration and depth as the source region.

[0089] Example 2

[0090] Please see Figure 3 This embodiment provides a SiC MOSFET device with an N+ equipotential ring. The SiC MOSFET device includes a second substrate 301, a second drift layer 302, a second drain metal layer 303, a second active region 310, a second transition region 320, and a second terminal region 330.

[0091] The second active region 310 includes a fourth well region 311, a fourth source region 312, a third enhancement region 313, a second gate oxide layer 314, a second gate 315, a second gate insulating layer 316, a third source metal layer 317, a fifth well region 311, a fourth source region 312, and a fourth source metal layer 329.

[0092] The second transition region 320 includes a fourth enhancement region 321, a sixth well region 311, a seventh source region 323, a third source metal layer 324, a third field oxygen layer 325, a second gate raceway 326, a second gate raceway insulating layer 327, and a second gate raceway metal layer 328.

[0093] The second terminal region 330 includes a second field limiting ring 331, a fourth field oxygen layer 332, and a second cutoff ring 333.

[0094] Example 2 differs slightly from Example 1 only in the boundary between the second active region 310 and the second transition region 320. The main differences are in the fifth well region 311, the fourth source region 312, the fourth enhancement region 321, the fifth source metal layer 329, and the third field oxygen layer 325. The structures of the other regions are completely identical and will not be described in detail.

[0095] The fifth well region 311 is P-type, and its upper surface is flush with the upper surface of the second drift layer 302. The ion doping concentration and depth are the same as those of the fourth well region 311.

[0096] The fourth source region 312 is an N-type source region located within the fifth well region 311. The upper surface of the fourth source region 312 is flush with the upper surface of the second drift layer 302. The width of the fourth source region 312 is smaller than the width of the fifth well region 311. The width difference near the center of the cell structure forms a channel (not shown) with the first gate oxide layer 214, while the width on the side furthest from the center of the cell structure is flush. The fourth source region 312 and the fifth well region 311 are formed by the same ion implantation process, with equal ion doping concentration and depth.

[0097] The fourth enhancement region 321 is a P-type enhancement region located within the surface of the drift layer 302, adjacent to the second well region and the second source region. The upper surface of the fourth enhancement region 321 is flush with the upper surface of the second drift layer 302, and the ion doping concentration and depth of the fourth enhancement region 321 are the same as those of the third enhancement region 313.

[0098] The fifth source metal layer 329 is located above the junction of the fourth source region 312 and the fourth enhancement region 321, and partially overlaps with the fourth source region 312 in the direction close to the cell structure and partially overlaps with the fourth enhancement region 321 in the direction close to the transition region.

[0099] The third field oxygen layer 325 is located above the second enhancement region 221, with a thickness of 1 μm, and is adjacent to the fifth source metal layer 329.

[0100] Example 3

[0101] Combination Figure 4 As shown, this embodiment provides a SiC MOSFET device with an N+ equipotential ring. The SiC MOSFET device includes a third substrate 401, a third drift layer 402, a third drain metal layer 403, a third active region 410, and a third termination region 420.

[0102] The third active region 410 includes a seventh well region 411, a seventh source region 412, a fifth enhancement region 413, a third gate oxide layer 414, a third gate 415, a third gate insulating layer 416, a seventh source metal layer 417, an eighth well region 418, and an eighth source region 419.

[0103] The third terminal region 420 includes the sixth enhancement region 422, the third field limiting ring 423, the second field oxygen layer 424, and the third cutoff ring 425.

[0104] The main difference between Example 3 and Example 1 is that the transition region is removed and the third terminal region 420 is slightly modified. The main addition is the sixth enhancement region 422. The other structures are completely the same and will not be described in detail here.

[0105] The sixth enhancement region 422 is located below the fifth field oxide layer 424. It is a P-type enhancement region, situated within the surface of the third drift layer 402, and adjacent to the eighth well region 418 and the eighth source region 419. The upper surface of the sixth enhancement region 422 is flush with the upper surface of the third drift layer 402. The ion doping concentration and depth of the sixth enhancement region 422 are the same as those of the fifth enhancement region 413.

[0106] In summary, the present invention provides a SiC power device termination structure with an N-type equipotential ring. During the withstand voltage test, the equipotential ring clamps the end of the main ring to zero potential. At the same time, the use of an N+ equipotential ring can improve the ohmic contact quality above the equipotential ring and reduce the source-drain capacitance in the transition region. Furthermore, it has good compatibility with existing designs and processes.

[0107] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A termination structure for a SiC power device with an N-type equipotential ring, characterized in that, Includes a substrate, which is disposed on a drain metal layer. A drift layer is disposed on the substrate. An active region, a transition region, and a terminal region are disposed sequentially from the center to the edge of the drift layer. The first ohmic contact metal of the active region cell structure, the second ohmic contact metal of the transition region, and the third ohmic contact metal of the terminal region are all electrically connected to the source of the active region. The gate raceway electrode of the transition region is electrically connected to the gate of the active region. The transition region includes, from bottom to top, a drain, an N+ substrate, and an N-type drift region. The N-type drift region includes, from the center to both ends, an oxide layer of adjacent cell structure and polysilicon, a P- region and an N+ region of adjacent cell, a second ohmic contact metal, and a P+ main ring. The P+ main ring is provided with a field oxide layer, a gate raceway, a gate raceway metal, and a passivation layer. A P-injection region and an N+ injection region are provided on the field ring side at the end of the P+ main ring, and the N+ ring formed by the N+ injection region is connected to the source metal through an ohmic contact. The N+ injection window on the active region side of the P+ main ring is enlarged to cover the source ohmic contact window, so that the ohmic contacts on both sides of the P+ main ring are N-type ohmic contacts. The polysilicon gate track is formed simultaneously with the polysilicon gate of the active region and connected by a polysilicon bridge.

2. The SiC power device termination structure with an N-type equipotential ring according to claim 1, characterized in that, The cell structure is a silicon carbide MOSFET or a silicon carbide IGBT.

3. The SiC power device termination structure with an N-type equipotential ring according to claim 2, characterized in that, When the cell structure is a silicon carbide MOSFET, from bottom to top, it includes drain, N+ substrate, N-type drift region, P region, N+ region, P+ region, oxide layer, polysilicon and first ohmic contact metal.

4. The SiC power device termination structure with an N-type equipotential ring according to claim 1, 2, or 3, characterized in that, The cellular structure is hexagonal or strip-shaped.

5. The SiC power device termination structure with an N-type equipotential ring according to claim 1, characterized in that, The substrate is a silicon carbide substrate of the first conductivity type, and the drift layer is of the first conductivity type.

6. The SiC power device termination structure with an N-type equipotential ring according to claim 1, characterized in that, The grid track and the second ohmic contact metal are isolated by a passivation layer.

7. The SiC power device termination structure with an N-type equipotential ring according to claim 1, characterized in that, The terminal area is a JTE structure or a field-limiting loop structure.

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