Semiconductor structure and formation method

Abstract

This application provides a semiconductor structure and its formation method. The semiconductor structure includes: a SiC substrate with a SiC epitaxial layer on the SiC substrate; and a gate structure located on or within the SiC epitaxial layer. The gate structure includes a passivation layer and a gate layer located on the passivation layer, wherein the passivation layer includes a first film with a thermal conductivity of 10 W / m·K to 28 W / m·K. This application can improve the channel carrier mobility of SiC MOSFET devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming it. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, has been widely studied due to its wide bandgap, high critical breakdown field strength, high thermal conductivity, and high electron saturation drift velocity. It is expected to replace silicon (Si) devices and second-generation semiconductor devices in high-temperature, high-frequency, and high-power applications. Furthermore, since SiC is the only wide-bandgap semiconductor material that can be directly oxidized to silicon dioxide (SiO2), this will simplify the fabrication process of metal-oxide-semiconductor field-effect transistors (MOSFETs) using SiC. Therefore, SiC MOSFET devices have attracted considerable attention.

[0003] However, defects exist at the interface between the gate oxide layer and the underlying SiC substrate in SiC MOSFET devices. These defects trap and scatter charge carriers, resulting in low channel carrier mobility and excessive on-resistance, which in turn increases power loss. Therefore, the electrical characteristics of SiC MOSFET devices are not ideal. Thus, it is necessary to improve the channel carrier mobility of SiC MOSFET devices. Summary of the Invention

[0004] The technical problem to be solved by this application is to improve the channel carrier mobility of SiC MOSFET devices.

[0005] To address the aforementioned technical problems, this application provides a semiconductor structure comprising: a SiC substrate, wherein a SiC epitaxial layer is present on the SiC substrate; a gate structure located on or within the SiC epitaxial layer, wherein the gate structure comprises a passivation layer and a gate layer located on the passivation layer, wherein the passivation layer comprises a first film layer with a thermal conductivity of 10 W / m·K to 28 W / m·K.

[0006] In some embodiments of this application, the material of the first film layer includes at least one of aluminosilicate, AlTiOx, and AlHfOx.

[0007] In some embodiments of this application, the passivation layer further includes a second film layer located on the first film layer, the second film layer having a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m·K to 30 W / m·K.

[0008] In some embodiments of this application, the material of the second film layer includes at least one of Al2O3, HfO2, or Si3N4.

[0009] In some embodiments of this application, the passivation layer further includes a third film layer located between the first film layer and the SiC epitaxial layer, and the material of the third film layer includes SiON.

[0010] In some embodiments of this application, the thickness of the first film layer and the second film layer is 10 nm to 100 nm, and the thickness of the third film layer is 0.5 nm to 2 nm.

[0011] In some embodiments of this application, the passivation layer further includes a silicon oxide layer located on the first film layer, and the material of the silicon oxide layer includes SiO2.

[0012] In some embodiments of this application, the thickness of the silicon oxide layer is 2 nm to 10 nm.

[0013] In some embodiments of this application, the semiconductor structure is a lateral double-diffused field-effect transistor, the gate structure is located on the SiC epitaxial layer, and the semiconductor structure further includes: a well region located in the SiC epitaxial layer, and the surface of the well region is flush with the top surface of the SiC epitaxial layer; a source region and a drain region located in the well region, and the surfaces of the source region and the drain region are flush with the top surface of the well region, wherein the gate structure is located on the surface of the well region between the source region and the drain region, and extends to a portion of the surface of the source region and the drain region.

[0014] In some embodiments of this application, the semiconductor structure is a vertical double-diffused field-effect transistor, the gate structure is located on the SiC epitaxial layer, and the semiconductor structure further includes: a well region located in the SiC epitaxial layer on both sides of the gate structure and extending to the bottom of a portion of the gate structure, and the surface of the well region is flush with the top surface of the SiC epitaxial layer; and a source region located in the well region on both sides of the gate structure, and the surface of the source region is flush with the top surface of the well region.

[0015] In some embodiments of this application, the semiconductor structure is a trench double-diffused field-effect transistor, the gate structure is located in the SiC epitaxial layer, and the semiconductor structure further includes: a well region located in the SiC epitaxial layer on both sides of the gate structure, wherein the surface of the well region is flush with the top surface of the SiC epitaxial layer, and the bottom surface of the well region is higher than the bottom surface of the gate structure; and a source region located in the well region on both sides of the gate structure, wherein the surface of the source region is flush with the top surface of the well region.

[0016] This application also provides a method for forming a semiconductor structure, comprising: providing a SiC substrate, wherein the SiC substrate includes a SiC epitaxial layer; forming a gate structure on or in the SiC epitaxial layer, wherein the method for forming the gate structure includes: forming a passivation layer on or in the SiC epitaxial layer, wherein the passivation layer includes a first film layer with a thermal conductivity of 10 W / m·K to 28 W / m·K; and forming a gate layer on the passivation layer.

[0017] In some embodiments of this application, the material of the first film layer includes at least one of aluminosilicate, AlTiOx and AlHfOx, and the formation process of the first film layer is chemical vapor deposition. The gas of the chemical vapor deposition includes silane, trimethylaluminum and oxygen, and the ratio of aluminum atoms, silicon atoms and oxygen atoms in the silane, trimethylaluminum and oxygen is (20-40):(1-10):(40-60).

[0018] In some embodiments of this application, the passivation layer further includes a second film layer located on the first film layer, the second film layer having a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m·K to 30 W / m·K.

[0019] In some embodiments of this application, the material of the second film layer includes at least one of Al2O3, HfO2, or Si3N4.

[0020] In some embodiments of this application, the passivation layer further includes a third film layer located between the first film layer and the SiC epitaxial layer. The material of the third film layer includes SiON, and the method for forming the third film layer includes: forming a silicon oxide layer on or in the SiC epitaxial layer, wherein the material of the silicon oxide layer includes SiO2; performing a nitriding treatment on the silicon oxide layer to form the third film layer, wherein the nitriding treatment includes: using a plasma nitriding process to replace some oxygen atoms in the silicon oxide layer with nitrogen atoms to form Si-N bonds; then performing a nitriding treatment at a first temperature and in an inert gas atmosphere to repair lattice damage and form stable Si-N bonds; and then performing a re-oxidation treatment at a second temperature to repair the SiO2 / SiC interface, wherein the second temperature is lower than the first temperature.

[0021] The technical solution of this application uses a passivation layer with high thermal conductivity to replace the conventional gate oxide layer, and the passivation layer includes a first film layer with a thermal conductivity of 10 W / mK to 28 W / m·K, which can effectively improve the channel carrier mobility of the semiconductor structure.

[0022] A second film layer is disposed on the first film layer, and the second film layer not only has high thermal conductivity, but also has high dielectric constant, which can further improve the channel carrier mobility of the semiconductor structure.

[0023] A third film layer is disposed between the first film layer and the SiC epitaxial layer, and the material of the third film layer includes SiON. The third film layer can improve the defect problem of the SiO2 / SiC interface on the one hand, and on the other hand, since SiON material has high thermal conductivity, it can improve the channel carrier mobility of the semiconductor structure.

[0024] The technical solution of this application can also isolate the silicon oxide layer and the SiC epitaxial layer through the first film layer to solve the defect problem of the SiO2 / SiC interface. At the same time, the first film layer also has high thermal conductivity, so it can effectively improve the channel carrier mobility of the semiconductor structure. Attached Figure Description

[0025] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figure 1 This is a schematic diagram of a first structure of the semiconductor structure according to an embodiment of this application when used in a trench double-diffused field-effect transistor;

[0027] Figure 2 This is a schematic diagram of a second structure of the semiconductor structure according to an embodiment of this application when used in a trench double-diffused field-effect transistor;

[0028] Figure 3 This is a schematic diagram of a third structure of the semiconductor structure in this application used in a trench double-diffused field-effect transistor.

[0029] Figure 4 This is a schematic diagram of a fourth structure of the semiconductor structure used in a trench double-diffused field-effect transistor according to an embodiment of this application.

[0030] Figures 5 to 8 for Figure 3 The diagram shows the structural schematics of each step in the method for forming the semiconductor structure.

[0031] Figure 9 This is a schematic diagram of a first structure of the semiconductor structure of this application used in a lateral double-diffused field-effect transistor;

[0032] Figure 10 This is a schematic diagram of a second structure of the semiconductor structure used in a lateral double-diffused field-effect transistor according to an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of a third structure of the semiconductor structure in an embodiment of this application when used in a lateral double-diffused field-effect transistor;

[0034] Figure 12 This is a schematic diagram of a fourth structure of the semiconductor structure used in a lateral double-diffused field-effect transistor according to an embodiment of this application.

[0035] Figures 13 to 15 for Figure 11 The diagram shows the structural schematics of each step in the method for forming the semiconductor structure.

[0036] Figure 16 This is a schematic diagram of a first structure of the semiconductor structure of this application used in a vertical double-diffused field-effect transistor;

[0037] Figure 17 This is a schematic diagram of a second structure of the semiconductor structure according to an embodiment of this application when used in a vertically double-diffused field-effect transistor;

[0038] Figure 18 This is a schematic diagram of a third structure of the semiconductor structure in this application used in a vertical double-diffused field-effect transistor.

[0039] Figure 19 This is a schematic diagram of a fourth structure of the semiconductor structure used in a vertical double-diffused field-effect transistor according to an embodiment of this application. Detailed Implementation

[0040] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0041] Based on the current problem of low channel carrier mobility in SiC MOSFET devices, the semiconductor structure of this application adopts a passivation layer with high thermal conductivity, which can better release the heat generated by the SiC MOSFET device during operation and reduce the temperature of the SiC MOSFET device. The inventors found that when the temperature is lowered, it is beneficial to the migration of channel carriers, thereby effectively improving the channel carrier mobility of the SiC MOSFET device.

[0042] The semiconductor structure of the technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] The semiconductor structure in this application embodiment can be any SiC MOSFET device structure, such as a trench double-diffused MOSFET, a lateral double-diffused MOSFET (LDMOS), or a vertical double-diffused MOSFET (VDMOS).

[0044] Please refer to Figure 1 A semiconductor structure 10 according to an embodiment of this application can serve as a trench double-diffused field-effect transistor. The semiconductor structure 10 includes a SiC substrate 11, a SiC epitaxial layer 12, and a gate structure. The semiconductor structure 10 also includes a well region 15, a source region 16, and a heavy-body region 17. The SiC substrate 11 can be made of materials such as 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC, and can be heavily doped, for example, with a doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 (i.e., 1×10) 18 cm -3 1×10 20 cm -3 The SiC substrate 11 can be N-type doped or P-type doped, with the specific doping type depending on the device type (e.g., N-type MOSFET or P-type MOSFET). This embodiment uses N-type doping as an example. The SiC epitaxial layer 12 is located on the SiC substrate 11, and the doping type of the SiC epitaxial layer 12 is the same as that of the SiC substrate 11. The doping concentration of the SiC epitaxial layer 12 can be lower than that of the SiC substrate 11; for example, the doping concentration of the SiC epitaxial layer 12 can be 1E14cm⁻¹. -3 Up to 1E16cm -3 .

[0045] The gate structure is located in the SiC epitaxial layer 12. The well regions 15 are located in the SiC epitaxial layers 12 on both sides of the gate structure, and the surface of the well regions 15 is flush with the top surface of the SiC epitaxial layer 12, wherein the bottom surface of the well regions 15 is higher than the bottom surface of the gate structure. The doping type of the well regions 15 is different from that of the SiC epitaxial layer 12, and they are used to define the body region of the semiconductor structure 10. The source regions 16 are located in the well regions 15 on both sides of the gate structure, and the surface of the source regions 16 is flush with the top surface of the well regions 15. The heavy body region 17 is located on the side of the source regions 16 away from the gate structure, and the surface of the heavy body region 17 is flush with the top surface of the source regions 16. The bottom surface of the heavy body region 17 may also be flush with the bottom surface of the source regions 16. The doping type of the heavy body region 17 is the same as that of the well regions 15, and the doping concentration of the heavy body region 17 is higher than that of the well regions 15.

[0046] The gate structure includes a passivation layer and a gate layer 14 located on the passivation layer, wherein the material of the gate layer 14 may include at least one of doped polysilicon, metal, and silicide. The passivation layer includes a first film layer 13a, and the thermal conductivity of the first film layer 13a is 10 W / m·K to 28 W / m·K. In this embodiment, the material of the first film layer 13a includes at least one of aluminosilicates (ALSG), AlTiOx, and AlHfOx. The thickness of the first film layer 13a can be 10 nm to 100 nm. Using ALSG with high thermal conductivity can effectively improve the channel carrier mobility of the semiconductor structure 10. Compared with a SiO2 layer of the same thickness, the first film layer 13a can effectively suppress direct tunneling and reduce gate leakage current.

[0047] Please refer to Figure 2To further improve the channel carrier mobility of the semiconductor structure 10, a second film layer 13b can be formed on the first film layer 13a. The second film layer 13b not only has high thermal conductivity but also a high dielectric constant. Specifically, the dielectric constant k of the second film layer 13b should be greater than 3.9, and the thermal conductivity should be 28 W / m·K to 30 W / m·K. In this embodiment, the material of the second film layer 13b includes Al2O3. The thickness of the second film layer 13b can be 10 nm to 100 nm. Furthermore, since Al2O3 has good thermal stability, using Al2O3 as a passivation layer can adapt to the high-temperature conditions of the SiC process, thereby improving the device performance. In other embodiments, the material of the second film layer 13b can also be HfO2, Si3N4, etc. Under an electric field strength of 7 MV / cm, when using a SiO2 layer as a passivation layer, the gate current density is approximately 1E(-6) A / cm. 2 When the first film layer 13a and the second film layer 13b of this application are used as passivation layers, the gate current density is approximately 1E(-8) A / cm². 2 Therefore, when the passivation layer of the present application embodiment is used, the device has a smaller leakage current.

[0048] Please refer to Figure 3 The passivation layer may further include a third film layer 13c, which is located between the first film layer 13a and the SiC epitaxial layer 12. The material of the third film layer 13c includes SiON. The thickness of the third film layer 13c can be 0.5 nm to 2 nm. Replacing SiO2 with SiON material can improve the defect problem at the SiO2 / SiC interface. Simultaneously, SiON material also has high thermal conductivity (27 W / m·K). Therefore, setting the third film layer 13c can effectively improve the channel carrier mobility of SiC MOSFET devices.

[0049] refer to Figure 4 In some embodiments, the passivation layer includes a first film layer 13a and a silicon oxide layer 13d, with the silicon oxide layer 13d located on the first film layer 13a. The material of the silicon oxide layer 13d includes SiO2. The thickness of the silicon oxide layer 13d can be 2 nm to 10 nm. The silicon oxide layer 13d can be formed by conventional chemical vapor deposition. The first film layer 13a can isolate the silicon oxide layer 13d from the SiC epitaxial layer 12, solving the defect problem at the SiO2 / SiC interface. Simultaneously, the first film layer 13a also has high thermal conductivity, thus effectively improving the channel carrier mobility of the SiC MOSFET device.

[0050] When the semiconductor structure 10 is in operation, a positive voltage is applied between the gate 14 and the source region 16. A vertical channel is formed between the well region 15 and the region adjacent to the gate 14. Since the channel has a first film layer with high thermal conductivity, the channel carrier mobility of the semiconductor structure 10 can be improved. At the same time, since the first film layer replaces the conventional gate oxide layer, the problem of reduced channel carrier mobility caused by the presence of defects at the interface between the gate oxide layer and the SiC epitaxial layer is avoided.

[0051] The method for forming the semiconductor structure 10 may include:

[0052] Step S10: Provide a SiC substrate, wherein the SiC substrate includes a SiC epitaxial layer;

[0053] Step S20: Form a gate structure on or in the SiC epitaxial layer.

[0054] The method for forming the gate structure includes:

[0055] Step S21: A passivation layer is formed on or in the SiC epitaxial layer, and the passivation layer includes a first film layer with a thermal conductivity of 10 W / m·K to 28 W / m·K;

[0056] Step S22: Form a gate layer on the passivation layer.

[0057] The following is Figure 3 Taking the semiconductor structure 10 shown as an example, the method for forming the semiconductor structure of this application embodiment will be described in detail. Figures 5 to 8 for Figure 3 The diagram shows the structural schematic of each step in the method for forming the semiconductor structure 10.

[0058] Please refer to Figure 5 In step S10, the SiC substrate 11 has a first doping type, and a SiC epitaxial layer 12 is formed on the SiC substrate 11. The SiC epitaxial layer 12 can be formed by an epitaxial growth process. The SiC epitaxial layer 12 also has a first doping type, and the doping concentration of the SiC epitaxial layer 12 is higher than that of the SiC substrate 11. After the SiC epitaxial layer 12 is formed, a well region 15 is formed in the SiC epitaxial layer 12 by an ion implantation process. The well region 15 has a second doping type opposite to that of the SiC substrate 11 and the SiC epitaxial layer 12.

[0059] Please refer to Figure 6The source region 16 and the heavy body region 17 are formed by ion implantation. The source region 16 is located in the well region 15 and the SiC epitaxial layer 12. The heavy body region 17 is located in the well regions 15 on both sides of the source region 16. The source region 16 has a first doping type, the heavy body region 17 has a second doping type, and the doping concentration of the heavy body region 17 is greater than the doping concentration of the well region 15.

[0060] Please refer to Figure 7 A gate trench 18 is formed in the source region 16, the well region 15 and the SiC epitaxial layer 12. The process for forming the gate trench 18 is a conventional etching process.

[0061] Please refer to Figure 8 The passivation layer is formed on the sidewalls and bottom of the gate trench 18. The passivation layer includes a first film layer 13a, a second film layer 13b, and a third film layer 13c. Specifically, the method for forming the passivation layer includes: first forming the third film layer 13c, wherein the material of the third film layer 13c includes SiON, and the method for forming the third film layer 13c may include: forming a silicon oxide layer on the sidewalls and bottom of the gate trench 18, which can be formed using a conventional chemical vapor deposition process, wherein the material of the silicon oxide layer includes SiO2; then performing a nitriding treatment on the silicon oxide layer to form the third film layer 13c. The method for performing the nitriding treatment on the silicon oxide layer may include: using a plasma nitriding process to replace some oxygen atoms in the silicon oxide layer with nitrogen atoms to form Si-N bonds; then performing a nitriding treatment at a first temperature and in an inert gas atmosphere to repair lattice damage and form stable Si-N bonds; and then performing a re-oxidation treatment at a second temperature, wherein the second temperature is lower than the first temperature. The above-described nitriding treatment method can form a high-quality third film layer 13c to improve the channel carrier mobility of the semiconductor structure 10.

[0062] Then, the first film layer 13a is formed on the surface of the third film layer 13c, and the material of the first film layer 13a includes aluminosilicate. The formation process of the first film layer 13a can be chemical vapor deposition, atomic layer deposition, or sputtering, etc. When a chemical vapor deposition process is used, the deposition gas includes silane, trimethylaluminum, and oxygen, and the ratio of aluminum atoms, silicon atoms, and oxygen atoms in the silane, trimethylaluminum, and oxygen is (20-40):(1-10):(40-60).

[0063] A second film layer 13b is then formed on the surface of the first film layer 13a. The second film layer 13b has a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m·K to 30 W / m·K. The material of the second film layer 13b may include Al2O3. The second film layer 13b can be formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD).

[0064] After the passivation layer is formed, step S22 is performed. A gate layer 14 is formed on the passivation layer. The method for forming the gate layer 14 includes: depositing a gate material layer on the passivation layer using deposition processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, wherein the gate material layer fills the gate trench and covers the surfaces of the source region 16 and the heavy body region 17, and then grinding the gate material layer so that the surface of the gate material layer is flush with the top surface of the source region 16, thereby forming the gate layer 14. Subsequently, conventional structures such as source metal and drain metal can also be formed, which will not be described in detail here.

[0065] refer to Figure 9 This application also provides a semiconductor structure 20 that can serve as a lateral double-diffused field-effect transistor. The semiconductor structure 20 includes a SiC substrate 21, a SiC epitaxial layer 22, and a gate structure. The semiconductor structure 20 further includes a well region 25, a source region 26a, and a drain region 26b. The SiC substrate 21 can be made of materials such as 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC. The SiC substrate 21 can be heavily doped, for example, with a doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 (i.e., 1×10) 18 cm -3 1×10 20 cm -3 The SiC substrate 21 can be N-type doped or P-type doped, depending on the device type (e.g., N-type MOSFET or P-type MOSFET). This embodiment uses an N-type doped SiC substrate 21 as an example. The SiC substrate 21 includes a SiC epitaxial layer 22, the doping type of which is the same as that of the SiC substrate 21, and the doping concentration of the SiC epitaxial layer 22 can be lower than that of the SiC substrate 21. For example, the doping concentration of the SiC epitaxial layer 22 can be 1E14c. m-3 Up to 1E16cm -3 .

[0066] The gate structure is located on the SiC epitaxial layer 22, and the well region 25 is located within the SiC epitaxial layer 22, with the surface of the well region 25 flush with the top surface of the SiC epitaxial layer 22. The doping type of the well region 25 is different from that of the SiC epitaxial layer 22, and it is used to define the body region of the semiconductor structure 20. The source region 26a and the drain region 26b are located within the well region 25, with the surfaces of the source region 26a and the drain region 26b flush with the top surface of the well region 25. The gate structure is located on the surface of the well region 25 between the source region 26a and the drain region 26b, and extends to a portion of the surface of the source region 26a and the drain region 26b.

[0067] The gate structure includes a passivation layer and a gate layer 24 located on the passivation layer, wherein the material of the gate layer 24 may include at least one of doped polysilicon, metal, and silicide. The passivation layer includes a first film layer 23a, and the thermal conductivity of the first film layer 23a is 10 W / mK to 28 W / mK. In this embodiment, the material of the first film layer 23a includes aluminosilicates (ALSG). The thickness of the first film layer 23a can be 10 nm to 100 nm. Using ALSG with high thermal conductivity can effectively improve the channel carrier mobility of the semiconductor structure 10.

[0068] Please refer to Figure 10 To further improve the channel carrier mobility of the semiconductor structure 20, a second film layer 23b can be formed on the first film layer 23a. The second film layer 23b not only has high thermal conductivity but also a high dielectric constant. Specifically, the dielectric constant k of the second film layer 23b should be greater than 3.9, and the thermal conductivity should be 28 W / m·K to 30 W / m·K. In this embodiment, the material of the second film layer 23b includes Al2O3. The thickness of the second film layer 13b can be 10 nm to 100 nm.

[0069] Please refer to Figure 11 The passivation layer may further include a third film layer 23c, which is located between the first film layer 23a and the SiC epitaxial layer 22. In this embodiment, the third film layer 23c directly contacts the first film layer 23a and the well region 25. The material of the third film layer 23c includes SiON. The thickness of the third film layer 23c can be 0.5 nm to 2 nm. Replacing SiO2 with SiON material can improve the defect problem of the SiO2 / SiC interface. At the same time, SiON material also has a high thermal conductivity (27 W / m·K). Therefore, setting the third film layer 23c can effectively improve the channel carrier mobility of SiC MOSFET devices.

[0070] refer to Figure 12 In some embodiments, the passivation layer includes a first film layer 23a and a silicon oxide layer 23d, with the silicon oxide layer 23d located on the first film layer 23a. The material of the silicon oxide layer 23d includes SiO2. The thickness of the silicon oxide layer 23d can be 2 nm to 10 nm. The silicon oxide layer 23d can be formed by conventional chemical vapor deposition. The first film layer 23a can isolate the silicon oxide layer 23d from the well region 25, solving the defect problem at the SiO2 / SiC interface. Simultaneously, the first film layer 23a also has high thermal conductivity, thus effectively improving the channel carrier mobility of the SiC MOSFET device.

[0071] The following is Figure 11 Taking the semiconductor structure 20 shown as an example, the method for forming the semiconductor structure of this application embodiment will be described in detail. Figures 13 to 15 for Figure 11 The diagram shows the structural schematic of each step in the method for forming the semiconductor structure 20.

[0072] Please refer to Figure 13 A SiC substrate 21 is provided, and the SiC substrate 21 has a first doping type. An epitaxial layer 22 is formed on the SiC substrate 21 using an epitaxial growth process. The SiC epitaxial layer 22 also has a first doping type, and the doping concentration of the SiC epitaxial layer 22 is higher than that of the SiC substrate 21. After forming the SiC epitaxial layer 22, a well region 25 is formed in the SiC epitaxial layer 22 by an ion implantation process. The well region 25 has a second doping type opposite to that of the SiC substrate 21 and the SiC epitaxial layer 22.

[0073] Please refer to Figure 14The passivation layer is formed on the SiC epitaxial layer 22. Specifically, the passivation layer is formed on a portion of the surface of the well region 25, and the passivation layer includes a first film layer 23a, a second film layer 23b, and a third film layer 23c. The method for forming the passivation layer includes: first forming the third film layer 23c, the material of the third film layer 23c including SiON, and the method for forming the third film layer 23c may include: forming a silicon oxide layer on a portion of the surface of the well region 25, which can be formed using a conventional chemical vapor deposition process, the material of the silicon oxide layer including SiO2; then performing a nitriding treatment on the silicon oxide layer to form the third film layer 23c. The method for performing the nitriding treatment on the silicon oxide layer may include: using a plasma nitriding process to replace some oxygen atoms in the silicon oxide layer with nitrogen atoms to form Si-N bonds; then performing a nitriding treatment at a first temperature and an inert gas atmosphere to repair lattice damage and form stable Si-N bonds; and then performing a re-oxidation treatment at a second temperature, where the second temperature is lower than the first temperature, to repair the SiO2 / SiC interface. The above-described nitriding treatment method can form a high-quality third film layer 23c to improve the channel carrier mobility of the semiconductor structure 20.

[0074] Then, the first film layer 23a is formed on the surface of the third film layer 23c, and the material of the first film layer 23a includes aluminosilicate. The formation process of the first film layer 23a can be chemical vapor deposition, wherein the gas of the chemical vapor deposition includes silane, trimethylaluminum and oxygen.

[0075] A second film layer 23b is then formed on the surface of the first film layer 23a. The second film layer 23b has a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m·K to 30 W / m·K. The material of the second film layer 23b may include Al2O3. The second film layer 23b can be formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD).

[0076] After the passivation layer is formed, a gate layer 24 is formed on the passivation layer. The method for forming the gate layer 24 includes: depositing a gate material layer on the surface of the SiC epitaxial layer 22, the well region 25 and the passivation layer using deposition processes such as chemical vapor deposition, physical vapor deposition and atomic layer deposition; and then etching away the gate material layer on the surface of the SiC epitaxial layer 22 and the well region 25 to form the gate layer 24.

[0077] Please refer to Figure 15Source regions 26a and drain regions 26b are formed in the well regions 25 on both sides of the gate structure using an ion implantation process. The source regions 26a and drain regions 26b also extend below a portion of the gate structure. The doping type of the source regions 26a and drain regions 26b is different from that of the well region 25. Subsequently, a conventional metal interconnect structure can also be formed, which will not be described in detail here.

[0078] Please refer to Figure 16 Another semiconductor structure 30 in this application embodiment can be used as a vertical double-diffused field-effect transistor. The semiconductor structure 30 includes a SiC substrate 31, a SiC epitaxial layer 32, and a gate structure. The semiconductor structure 30 also includes a well region 35, a source region 36, and a heavy-body region 37. The material of the SiC substrate 31 can be 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC, etc. The SiC substrate 31 can be heavily doped, for example, the doping concentration can be 1E18cm⁻¹. -3 ~1E20cm -3 (i.e., 1×10) 18 cm -3 1×10 20 cm -3 The doping type can be N-type or P-type. This application uses an N-type doped SiC substrate 31 as an example for illustration. The SiC epitaxial layer 32 is located on the SiC substrate 31, and the doping type of the SiC epitaxial layer 32 is the same as that of the SiC substrate 31. The doping concentration of the SiC epitaxial layer 32 can be lower than that of the SiC substrate 31; for example, the doping concentration of the SiC epitaxial layer 32 can be 1E14cm⁻¹. -3 Up to 1E16cm -3 .

[0079] The gate structure is located on the SiC epitaxial layer. The well regions 35 are located in the SiC epitaxial layers 32 on both sides of the gate structure, and the well regions 35 extend to a portion below the gate structure. The surface of the well regions 35 is flush with the top surface of the SiC epitaxial layers 32. The doping type of the well regions 35 is different from that of the SiC epitaxial layers 32, and they define the body region of the semiconductor structure 30. The source regions 36 are located in the well regions 35 on both sides of the gate structure, and the surface of the source regions 36 is flush with the top surface of the well regions 35. The heavy body region 37 is located on the side of the source regions 36 away from the gate structure, and the surface of the heavy body region 37 is flush with the top surface of the source regions 36. The doping type of the heavy body region 37 is the same as that of the well regions 35, and the doping concentration of the heavy body region 37 is higher than that of the well regions 35.

[0080] The gate structure includes a passivation layer and a gate layer 34 located on the passivation layer, wherein the material of the gate layer 34 may include at least one of doped polysilicon, metal, and silicide. The passivation layer includes a first film layer 33a, and the thermal conductivity of the first film layer 33a is 10 W / m·K to 28 W / m·K. In this embodiment, the material of the first film layer 33a includes aluminosilicates (ALSG). The thickness of the first film layer 33a can be 10 nm to 100 nm. Using ALSG with high thermal conductivity can effectively improve the channel carrier mobility of the semiconductor structure 30.

[0081] Please refer to Figure 17 To further improve the channel carrier mobility of the semiconductor structure 30, a second film layer 33b can be formed on the first film layer 33a. The second film layer 33b not only has high thermal conductivity but also a high dielectric constant. Specifically, the dielectric constant k of the second film layer 33b should be greater than 3.9, and the thermal conductivity should be 28 W / m·K to 30 W / m·K. In this embodiment, the material of the second film layer 33b includes Al₂O₃. The thickness of the second film layer 33b can be 10 nm to 100 nm.

[0082] Please refer to Figure 18 The passivation layer may further include a third film layer 33c, which is located between the first film layer 33a and the SiC epitaxial layer 32. In this embodiment, the third film layer 33c is located on the surface of a portion of the epitaxial layer 32 and a portion of the well region 35. The material of the third film layer 33c includes SiON. The thickness of the third film layer 33c can be 0.5 nm to 2 nm. Replacing SiO2 with SiON material can improve the defect problem of the SiO2 / SiC interface. SiON material also has high thermal conductivity (27 W / m·K). Therefore, setting the third film layer 33c can effectively improve the channel carrier mobility of the SiC MOSFET device.

[0083] refer to Figure 19In some embodiments, the passivation layer includes a first film layer 33a and a silicon oxide layer 33d, with the silicon oxide layer 33d located on the first film layer 33a. The material of the silicon oxide layer 33d includes SiO2. The thickness of the silicon oxide layer 33d can be 2 nm to 10 nm. The silicon oxide layer 33d can be formed by conventional chemical vapor deposition. The first film layer 33a can isolate the silicon oxide layer 33d from the well region 35 and the SiC epitaxial layer 32, solving the defect problem at the SiO2 / SiC interface. Simultaneously, the first film layer 33a also has high thermal conductivity, thus significantly improving the channel carrier mobility of the SiC MOSFET device.

[0084] The following is Figure 18 Taking the semiconductor structure 30 shown as an example, the method for forming the semiconductor structure of this application embodiment will be described in detail.

[0085] A SiC substrate 31 is provided, and the SiC substrate 31 has a first doping type. An epitaxial layer 32 is formed on the SiC substrate 31 using an epitaxial growth process. The SiC epitaxial layer 32 also has a first doping type, and the doping concentration of the SiC epitaxial layer 32 is higher than that of the SiC substrate 31. After forming the SiC epitaxial layer 32, a well region 35 is formed in the SiC epitaxial layer 32 using an ion implantation process. The well region 35 has a second doping type opposite to that of the SiC substrate 31 and the SiC epitaxial layer 32.

[0086] Then, the passivation layer is formed on the SiC epitaxial layer 32. Specifically, the passivation layer is formed on the surface of the SiC epitaxial layer 32 and a portion of the surface of the well region 35, and the passivation layer includes a first film layer 33a, a second film layer 33b, and a third film layer 33c. The method for forming the passivation layer includes: first forming the third film layer 33c, wherein the material of the third film layer 33c includes SiON, and the method for forming the third film layer 33c may include: forming a silicon oxide layer on the surface of the SiC epitaxial layer 32 and a portion of the surface of the well region 35, which can be formed using a conventional chemical vapor deposition process, wherein the material of the silicon oxide layer includes SiO2; and then performing a nitriding treatment on the silicon oxide layer to form the third film layer 33c. The method for nitriding the silicon oxide layer may include: employing a plasma nitriding process to replace some oxygen atoms in the silicon oxide layer with nitrogen atoms to form Si-N bonds; then performing nitriding at a first temperature and in an inert gas atmosphere to repair lattice damage and form stable Si-N bonds; followed by re-oxidation at a second temperature lower than the first temperature to repair the SiO2 / SiC interface. The above-described nitriding method can form a high-quality third film layer 33c, thereby improving the channel carrier mobility of the semiconductor structure 30.

[0087] Then, the first film layer 33a is formed on the surface of the third film layer 33c, and the material of the first film layer 33a includes aluminosilicate. The formation process of the first film layer 33a can be chemical vapor deposition, wherein the gas of the chemical vapor deposition includes silane, trimethylaluminum and oxygen.

[0088] A second film layer 33b is then formed on the surface of the first film layer 33a. The second film layer 33b has a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m·K to 30 W / m·K. The material of the second film layer 33b may include Al2O3. The second film layer 33b can be formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD).

[0089] After the passivation layer is formed, a gate layer 34 is formed on the passivation layer. The method for forming the gate layer 34 includes: depositing a gate material layer on the surface of the well region 35 and the passivation layer using deposition processes such as chemical vapor deposition, physical vapor deposition and atomic layer deposition, and then etching away the gate material layer on the surface of the well region 35 to form the gate layer 34.

[0090] Source regions 36 are formed in the well regions 35 on both sides of the gate structure using an ion implantation process, and a heavy body region 37 is formed on the side of the source regions 36 away from the gate structure. The source regions 36 and the well regions 35 have different doping types, while the heavy body region 37 and the well regions 35 have the same doping type. Subsequently, conventional structures such as source metal and drain metal can also be formed, which will not be described in detail here.

[0091] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0092] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0093] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0094] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0095] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: SiC substrate, wherein the SiC substrate includes a SiC epitaxial layer; A gate structure is located on or within the SiC epitaxial layer, and the gate structure includes a passivation layer and a gate layer located on the passivation layer, wherein the passivation layer has a thermal conductivity of 10 W / m. K-28W / m The first film layer of K, the passivation layer further includes a second film layer located on the first film layer, the second film layer having a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m. K-30W / m K.

2. The semiconductor structure according to claim 1, characterized in that, The material of the first film layer includes at least one of aluminosilicate, AlTiOx, and AlHfOx.

3. The semiconductor structure according to claim 1, characterized in that, The material of the second film layer includes at least one of Al2O3, HfO2, or Si3N4.

4. The semiconductor structure according to claim 1, characterized in that, The passivation layer further includes a third film layer located between the first film layer and the SiC epitaxial layer, and the material of the third film layer includes SiON.

5. The semiconductor structure according to claim 4, characterized in that, The thickness of the first and second films is 10 nm to 100 nm, and the thickness of the third film is 0.5 nm to 2 nm.

6. The semiconductor structure according to claim 1, characterized in that, The passivation layer further includes a silicon oxide layer located on the first film layer, and the material of the silicon oxide layer includes SiO2.

7. The semiconductor structure according to claim 6, characterized in that, The thickness of the silicon oxide layer is 2nm to 10nm.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure is a lateral double-diffused field-effect transistor, the gate structure is located on the SiC epitaxial layer, and the semiconductor structure further includes: A well region is located in the SiC epitaxial layer, and the surface of the well region is flush with the top surface of the SiC epitaxial layer; A source region and a drain region are located in the well region, and the surfaces of the source region and the drain region are flush with the top surface of the well region, wherein the gate structure is located on the surface of the well region between the source region and the drain region and extends to a portion of the surface of the source region and the drain region.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure is a vertical double-diffused field-effect transistor, the gate structure is located on the SiC epitaxial layer, and the semiconductor structure further includes: The well region is located in the SiC epitaxial layer on both sides of the gate structure and extends to the bottom of part of the gate structure, and the surface of the well region is flush with the top surface of the SiC epitaxial layer. The source region is located in the well regions on both sides of the gate structure, and the surface of the source region is flush with the top surface of the well region.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure is a trench double-diffused field-effect transistor, the gate structure is located in the SiC epitaxial layer, and the semiconductor structure further includes: The well region is located in the SiC epitaxial layer on both sides of the gate structure, and the surface of the well region is flush with the top surface of the SiC epitaxial layer, while the bottom surface of the well region is higher than the bottom surface of the gate structure. The source region is located in the well regions on both sides of the gate structure, and the surface of the source region is flush with the top surface of the well region.

11. A method for forming a semiconductor structure, characterized in that, include: A SiC substrate is provided, wherein a SiC epitaxial layer is included on the SiC substrate; A gate structure is formed on or in the SiC epitaxial layer, wherein the method for forming the gate structure includes: A passivation layer is formed on or within the SiC epitaxial layer, and the passivation layer comprises a layer with a thermal conductivity of 10 W / m. K~28W / m The first film layer of K, the passivation layer further includes a second film layer located on the first film layer, the second film layer having a dielectric constant greater than 3.9 and a thermal conductivity of 28 W / m. K~30W / m K; A gate layer is formed on the passivation layer.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The material of the first film layer includes at least one of aluminosilicate, AlTiOx and AlHfOx, and the formation process of the first film layer is chemical vapor deposition. The gas of the chemical vapor deposition includes silane, trimethylaluminum and oxygen, and the ratio of aluminum atoms, silicon atoms and oxygen atoms in the silane, trimethylaluminum and oxygen is (20~40):(1~10):(40~60).

13. The method for forming a semiconductor structure according to claim 11, characterized in that, The material of the second film layer includes at least one of Al2O3, HfO2, or Si3N4.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, The passivation layer further includes a third film layer located between the first film layer and the SiC epitaxial layer, the material of the third film layer including SiON, and the method for forming the third film layer includes: A silicon oxide layer is formed on or in the SiC epitaxial layer, and the material of the silicon oxide layer includes SiO2; The silicon oxide layer is nitrided to form the third film layer, wherein the nitriding treatment includes: The plasma nitriding process is used to replace some oxygen atoms in the silicon oxide layer with nitrogen atoms to form Si-N bonds; Then, nitriding is performed at the first temperature and in an inert gas atmosphere to repair lattice damage and form stable Si-N bonds; Next, a re-oxidation treatment is performed at a second temperature, which is lower than the first temperature, to repair the SiO2 / SiC interface.

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