A level acquisition circuit

Abstract

This invention provides a level acquisition circuit, relating to the field of level acquisition circuit technology, including a configuration circuit, an interface circuit U8, an interface circuit U6, and an output circuit. The input terminals of the configuration circuit are connected to the VCH terminal and the EN terminal, respectively. The output terminals of the configuration circuit are connected to the IN terminal of the interface circuit U8 and the IN terminal of the interface circuit U6, respectively. The signal input IN1 terminal is connected to the IN terminal of the interface circuit U8 through a resistor R3, and the signal input IN2 terminal is connected to the IN terminal of the interface circuit U6 through a resistor R4. The OUT terminals of the interface circuit U8 and the OUT terminals of the interface circuit U6 are connected to the input terminals of the output circuit, respectively. The output terminals of the output circuit output signals through the OUT1 and OUT2 terminals, solving the problems of single detection mode and low integration in existing level acquisition circuits.

Description

Technical Field

[0001] This invention relates to the field of level acquisition circuit technology, and specifically to a level acquisition circuit. Background Technology

[0002] Level acquisition circuit: The function of the level acquisition circuit is to acquire level signals of different voltage ranges output by external circuits and convert them into level signals with a certain driving capability that can be recognized and processed by the subsequent electronic control system.

[0003] Low-active-level acquisition circuit: The acquisition circuit will output a trigger level that is valid for the subsequent stage only when the input level is low. When the input is high or floating, the output of the acquisition circuit is the normal level of the subsequent stage circuit.

[0004] High active level acquisition circuit: The acquisition circuit will output a trigger level that is valid for the subsequent stage only when the input level is high. When the input is low or floating, the output of the acquisition circuit is the normal level of the subsequent stage circuit.

[0005] In existing technologies, only one of the high-activity circuit or low-activity circuit can be used, resulting in a single detection mode. It cannot be changed to a low-activity circuit by configuring the port voltage, which leads to insufficient flexibility. In addition, most of them use discrete circuits, which also have the problems of low integration and high cost. Summary of the Invention

[0006] This invention provides a level acquisition circuit that uses easily integrated components suitable for various mainstream BCD processes, facilitating integration and expansion of the acquisition circuit. By configuring the input levels of the EN and VCH terminals, the output levels of the OU1 and OUT2 terminals are changed respectively to achieve the conversion between low-active and high-active circuits, enhancing the compatibility of the acquisition circuit and solving the problems of single detection mode and low integration in existing level acquisition circuits.

[0007] In view of the above problems, the technical solution proposed by the present invention is as follows:

[0008] A level acquisition circuit includes: a configuration circuit, an interface circuit U8, an interface circuit U6, and an output circuit. The interface circuit U8 and the interface circuit U6 have completely identical structures. The input terminals of the configuration circuit are connected to the VCH terminal and the EN terminal, respectively. The output terminals of the configuration circuit are connected to the IN terminal of the interface circuit U8 and the IN terminal of the interface circuit U6, respectively. The signal input IN1 terminal is connected to the IN terminal of the interface circuit U8 through a resistor R3, and the signal input IN2 terminal is connected to the IN terminal of the interface circuit U6 through a resistor R4. The OUT terminals of the interface circuit U8 and the OUT terminals of the interface circuit U6 are connected to the input terminals of the output circuit, respectively. The output terminals of the output circuit output signals through the OUT1 and OUT2 terminals.

[0009] To better realize the technical solution of the present invention, the following technical measures were also adopted.

[0010] Furthermore, the configuration circuit includes current sources I1, I2, I3, and I4, a PMOS transistor MP1, an NMOS transistor MN1, resistors R1 and R2. One end of each current source I1, I2, and I3 is connected to the VCH terminal. The other end of current source I1 is connected to the EN terminal through resistors R1 and R2. The other end of current source I2 is connected to the input terminal of the interface circuit. The other end of current source I3 is connected to the source (S) terminal of the PMOS transistor MP1. The gate (G) and drain (D) terminals of the PMOS transistor MP1 and the gate (G) and drain (D) terminals of the NMOS transistor MN1 are interconnected and simultaneously connected to the EN terminal and the input terminal of the interface circuit through resistor R2. The source (S) terminal of the NMOS transistor MN1 is grounded through current source I4.

[0011] Furthermore, the interface circuit U8 includes an isolation circuit and a filtering circuit. The isolation circuit includes NMOS transistors MN2, MN3, MN4, MN7, MN5, MN6, MN8, and MN9. The filtering circuit includes resistors R5, R6, R7, R8, and R9, and capacitor C1. The drain (D) terminal of NMOS transistor MN2 is connected in series with resistors R7 and R6, and then connected to the IN terminal of the interface circuit U8. The gate (G) terminals of NMOS transistors MN2, MN3, and MN9 are connected in series with each other. The gate (G) terminals of N7, MN8, and MN9 are connected to the gates of NMOS transistors MN4, MN5, and MN6 via inverter U4. The EN terminal outputs an ENA signal through a resistor, which is then connected to the gates of NMOS transistors MN4, MN5, and MN6. The ENA signal is then inverted by U4 to output an ENB signal. The source (S) terminals of NMOS transistors MN2 and MN3 are connected to one end of diode D1, and the other end of diode D1 is connected to the NMOS transistor... The gate (G) of MN2 is connected to the gate (G) of NMOS transistor MN3. The drain (D) of NMOS transistor MN3 is connected to the drain (D) of NMOS transistor MN7 and the VCH terminal via resistors R9 and R5, respectively. One end of diode D3 is connected to the gate (G) of both NMOS transistors MN7 and MN8, and the other end of diode D3 is connected to the source (S) of NMOS transistor MN7 and the drain (D) of NMOS transistor MN8. The source (S) of NMOS transistor MN8 is connected to the source (S) of NMOS transistor MN9. The drain (D) of NMOS transistor MN9 is connected to the OUT terminal of interface circuit U8 via Schmitt inverter U3. The NMOS transistor MN9 is connected to ground via capacitor C1. The drains of NMOS transistor MN9 and NMOS transistor MN6 are connected and connected to a bias power supply IB. The source (S) of NMOS transistor MN6 is connected to the source (S) of NMOS transistor MN5. The drains of NMOS transistor MN5 and the source of NMOS transistor MN4 are connected to one end of diode D2. The other end of diode D2 is connected to the gate (G) of NMOS transistor MN4 and the gate (G) of NMOS transistor MN5. One end of resistor R8 is connected between resistors R6 and R7, and the other end of resistor R8 is connected to the drain of NMOS transistor MN4.

[0012] Furthermore, the output circuit includes inverter U1 and inverter U2. The input terminal of inverter U1 is connected to the OUT terminal of the interface circuit U8, and the output terminal of inverter U1 is connected to the OUT1 terminal. The input terminal of inverter U2 is connected to the OUT terminal of the interface circuit U6, and the output terminal of inverter U2 is connected to the OUT2 terminal. Inverters U1 and U2 are also connected to the VCL terminal.

[0013] Furthermore, NMOS transistors MN2, MN3, MN4, and MN7 are high-voltage NMOS transistors, while NMOS transistors MN5, MN6, MN8, and MN9 are low-voltage NMOS transistors.

[0014] Compared with the prior art, the beneficial effects of the present invention are: it uses easily integrated devices that are suitable for various mainstream BCD processes, making integration convenient, and it also facilitates the expansion of the acquisition circuit. By configuring the input levels of the EN and VCH terminals, the output levels of the OU1 and OUT2 terminals are changed respectively to achieve the conversion between low-active-mode and high-active-mode circuits, which enhances the compatibility of the acquisition circuit and solves the problems of single detection mode and low integration in existing level acquisition circuits.

[0015] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a current-technical level acquisition circuit;

[0017] Figure 2 This is a schematic diagram of the level acquisition circuit disclosed in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the interface circuit U8 disclosed in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0020] See attached document Figure 1-3As shown, a level acquisition circuit includes a configuration circuit, an interface circuit U8, an interface circuit U6, and an output circuit. The interface circuit U8 and the interface circuit U6 have completely identical structures. The input terminals of the configuration circuit are connected to the VCH terminal and the EN terminal, respectively. The output terminals of the configuration circuit are connected to the IN terminal of the interface circuit U8 and the IN terminal of the interface circuit U6, respectively. The signal input IN1 terminal is connected to the IN terminal of the interface circuit U8 through a resistor R3, and the signal input IN2 terminal is connected to the IN terminal of the interface circuit U6 through a resistor R4. The OUT terminal of the interface circuit U8... The OUT terminal of the interface circuit U6 and the OUT terminal of the interface circuit U8 are respectively connected to the input terminal of the output circuit. The output terminal of the output circuit outputs signals through the OUT1 and OUT2 terminals. Specifically, the output circuit includes inverter U1 and inverter U2. The input terminal of inverter U1 is connected to the OUT terminal of the interface circuit U8, and the output terminal of inverter U1 is connected to the OUT1 terminal. The input terminal of inverter U2 is connected to the OUT terminal of the interface circuit U6, and the output terminal of inverter U2 is connected to the OUT2 terminal. Inverters U1 and U2 are also connected to the VCL terminal.

[0021] See attached document Figure 2-3 As shown, specifically, in this embodiment of the invention, the configuration circuit includes current source I1, current source I2, current source I3, current source I4, PMOS transistor MP1, NMOS transistor MN1, resistor R1, and resistor R2. One end of current source I1, current source I2, and current source I3 are connected to the VCH terminal. The other end of current source I1 is connected to the EN terminal through resistors R1 and R2. The other end of current source I2 is connected to the input terminal of the interface circuit. The other end of current source I3 is connected to the source (S) terminal of PMOS transistor MP1. The gate (G) and drain (D) terminals of PMOS transistor MP1 and the gate (G) and drain (D) terminals of NMOS transistor MN1 are interconnected and simultaneously connected to the EN terminal and the input terminal of the interface circuit through resistor R2. The source (S) terminal of NMOS transistor MN1 is grounded through current source I4.

[0022] See attached document Figure 2-3As shown, specifically, in this embodiment of the invention, the interface circuit U8 includes an isolation circuit and a filtering circuit. The isolation circuit includes NMOS transistors MN2, MN3, MN4, MN7, MN5, MN6, MN8, and MN9. The filtering circuit includes resistors R5, R6, R7, R8, and R9, and capacitor C1. The drain (D) terminal of NMOS transistor MN2 is connected in series with resistors R7 and R6 and then connected to the in terminal of the interface circuit U8. The gate (G) terminals of NMOS transistors MN2 and MN3 are also connected in series. The gates (G) of NMOS transistors MN7, MN8, and MN9 are connected to the gates of NMOS transistors MN4, MN5, and MN6 respectively via inverter U4. The EN terminal outputs an ENA signal through a resistor, which is connected to the gates of NMOS transistors MN4, MN5, and MN6. The ENA signal is then inverted by U4 to output an ENB signal. The source (S) terminals of NMOS transistors MN2 and MN3 are connected to one end of diode D1, and the other end of diode D1 is connected to... The gate (G) of NMOS transistor MN2 and the gate (G) of NMOS transistor MN3 are connected. The drain (D) of NMOS transistor MN3 is connected to the drain (D) of NMOS transistor MN7 and the VCH terminal via resistors R9 and R5, respectively. One end of diode D3 is connected to the gate (G) of both NMOS transistor MN7 and NMOS transistor MN8, and the other end of diode D3 is connected to both the source (S) of NMOS transistor MN7 and the drain (D) of NMOS transistor MN8. The source (S) of NMOS transistor MN8 is connected to the source (S) of NMOS transistor MN9. The drain (D) of NMOS transistor MN9 is connected to the output terminal (O) of interface circuit U8 via Schmitt inverter U3. The UT terminal is connected. The drain (D) of NMOS transistor MN9 is grounded through capacitor C1. The drains of NMOS transistor MN9 and NMOS transistor MN6 are connected and connected to a bias power supply IB. The source (S) of NMOS transistor MN6 is connected to the source (S) of NMOS transistor MN5. The drains of NMOS transistor MN5 and the source of NMOS transistor MN4 are connected to one end of diode D2. The other end of diode D2 is connected to the gate (G) of NMOS transistor MN4 and the gate (G) of NMOS transistor MN5. One end of resistor R8 is connected between resistors R6 and R7. The other end of resistor R8 is connected to the drain (D) of NMOS transistor MN4.

[0023] It should be noted that NMOS transistors MN2, MN3, MN4, and MN7 are high-voltage NMOS transistors, while NMOS transistors MN5, MN6, MN8, and MN9 are low-voltage NMOS transistors, passing through the EN terminal.

[0024] Specific working principle:

[0025] It should be noted that the signal input IN1 terminal, resistor R3, interface circuit U8, inverter U1, and OUT1 terminal constitute channel 1, and the signal input IN2 terminal, resistor R4, interface circuit U6, inverter U2, and OUT2 terminal constitute channel 2. The signal input IN1 terminal and signal input IN2 terminal are used for input signals, and the OUT1 terminal and OUT2 terminal are used for output signals.

[0026] 1. When the EN input is low, the internal current source pulls up the voltage of the IN1 input signal. At this time, channel 1 and channel 2 have the same function, both being active low circuits. When the signal input IN1 and signal input IN2 are floating or connected to a high level, the outputs of OUT1 and OUT2 are low. Only when the signal input IN1 and signal input IN2 are connected to a low level will the outputs of OUT1 and OUT2 be high.

[0027] 2. If the EN input is high (such as VCH or VCL), the internal current source of the circuit is turned on. At this time, channel 1 is a high-active circuit. When the signal input IN1 is connected to a high level, the output of OUT1 is low. Channel 2 is unaffected and is a low-active circuit.

[0028] 3. The chip can also be used with the VCH terminal floating. In this case, the VCH terminal is floating and the VCL terminal is connected to a logic level power supply, then both channel 1 and channel 2 are active high circuits.

[0029] Channel 2 is active low by default. Channel 1 can be selected by the level input at the EN terminal, and can be active high or active low. When the EN terminal is floating or connected to a high level (VEN>VCL), Channel 1 is active high. When the EN terminal is connected to a low level, both Channel 1 and Channel 2 are active low.

[0030] The specific input and output functions are shown in Tables 1 and 3.

[0031] Table 1

[0032]

[0033] Table 2

[0034]

[0035] Table 3

[0036]

[0037] The above circuit uses a 2-channel example. Depending on the application requirements, channels 2 to n (n>2) can be selected. The power input port voltage can then be configured as needed to obtain the desired level acquisition circuit. This level acquisition circuit can flexibly configure multiple acquisition channels according to requirements. By configuring the input levels of the EN and VCH terminals, compatibility with high-active and low-active input acquisition circuits can be achieved. Furthermore, this level acquisition circuit has high integration and is suitable for various mainstream BCD processes, exhibiting high integration and low power consumption.

[0038] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A level acquisition circuit, characterized in that, include: The system includes a configuration circuit, an interface circuit U8, an interface circuit U6, and an output circuit. The interface circuit U8 has the same structure as the interface circuit U6. The input terminals of the configuration circuit are connected to the VCH terminal and the EN terminal, respectively. The output terminals of the configuration circuit are connected to the IN terminal of the interface circuit U8 and the IN terminal of the interface circuit U6, respectively. The signal input IN1 terminal is connected to the IN terminal of the interface circuit U8 through a resistor R3, and the signal input IN2 terminal is connected to the IN terminal of the interface circuit U6 through a resistor R4. The OUT terminals of the interface circuit U8 and the OUT terminals of the interface circuit U6 are connected to the input terminals of the output circuit, respectively. The output terminals of the output circuit output signals through the OUT1 and OUT2 terminals. The configuration circuit includes current source I1, current source I2, current source I3, current source I4, PMOS transistor MP1, NMOS transistor MN1, resistor R1, and resistor R2. One end of current source I1, current source I2, and current source I3 are connected to the VCH terminal. The other end of current source I1 is connected to the EN terminal through resistors R1 and R2. The other end of current source I2 is connected to the input terminal of the interface circuit. The other end of current source I3 is connected to the source (S) terminal of PMOS transistor MP1. The gate (G) and drain (D) terminals of PMOS transistor MP1 and the gate (G) and drain (D) terminals of NMOS transistor MN1 are interconnected and simultaneously connected to the EN terminal and the input terminal of the interface circuit through resistor R2. The source (S) terminal of NMOS transistor MN1 is grounded through current source I4. The interface circuit U8 includes an isolation circuit and a filtering circuit. The isolation circuit includes NMOS transistors MN2, MN3, MN4, MN7, MN5, MN6, MN8, and MN9. The filtering circuit includes resistors R5, R6, R7, R8, and R9, and capacitor C1. The drain (D) terminal of NMOS transistor MN2 is connected in series with resistors R7 and R6, and then connected to the IN terminal of the interface circuit U8. The gate (G) terminals of NMOS transistors MN2, MN3, and MN7 are connected in series with the gate (G) terminals of NMOS transistors MN7, MN8, and MN9. The gates (G) of NMOS transistors MN8, MN9, and MN4, MN5, and MN6 are connected via inverter U4. The EN terminal outputs an ENA signal through a resistor, which is then connected to the gates of NMOS transistors MN4, MN5, and MN6. The ENA signal is then inverted by U4 to output an ENB signal. The source (S) terminals of NMOS transistors MN2 and MN3 are connected to one end of diode D1, and the other end of diode D1 is connected to the gate of NMOS transistor MN6. The gate (G) of diode 2 is connected to the gate (G) of NMOS transistor MN3. The drain (D) of NMOS transistor MN3 is connected to the drain (D) of NMOS transistor MN7 and the VCH terminal via resistors R9 and R5, respectively. One end of diode D3 is connected to the gate (G) of both NMOS transistor MN7 and NMOS transistor MN8. The other end of diode D3 is connected to both the source (S) of NMOS transistor MN7 and the drain (D) of NMOS transistor MN8. The source (S) of NMOS transistor MN8 is connected to the source (S) of NMOS transistor MN9. The drain (D) of NMOS transistor MN9 is connected to the OUT terminal of interface circuit U8 via Schmitt inverter U3. The drain (D) of NMOS transistor MN9 is grounded through capacitor C1. The drains of NMOS transistor MN9 and NMOS transistor MN6 are connected and connected to a bias power supply IB. The source (S) of NMOS transistor MN6 is connected to the source (S) of NMOS transistor MN5. The drains of NMOS transistor MN5 and the source of NMOS transistor MN4 are connected to one end of diode D2. The other end of diode D2 is connected to the gate (G) of NMOS transistor MN4 and the gate (G) of NMOS transistor MN5. One end of resistor R8 is connected between resistors R6 and R7, and the other end of resistor R8 is connected to the drain of NMOS transistor MN4. NMOS transistors MN2, MN3, MN4, and MN7 are high-voltage NMOS transistors, while NMOS transistors MN5, MN6, MN8, and MN9 are low-voltage NMOS transistors.

2. The level acquisition circuit according to claim 1, characterized in that: The output circuit includes inverter U1 and inverter U2. The input terminal of inverter U1 is connected to the OUT terminal of interface circuit U8, and the output terminal of inverter U1 is connected to the OUT1 terminal. The input terminal of inverter U2 is connected to the OUT terminal of interface circuit U6, and the output terminal of inverter U2 is connected to the OUT2 terminal. Inverters U1 and U2 are also connected to the VCL terminal.

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