Method for creating vertical channel structures in three-dimensional integrated semiconductor memory

Abstract

The invention relates to a method for producing vertical channel structures in a layer stack in the production of a three-dimensional integrated semiconductor memory, a layer stack for use in the production of a three-dimensional integrated semiconductor memory and a three-dimensional integrated semiconductor memory having the layer stack. The invention specifically relates to a specific method step (channel hole etching) in the production of a three-dimensional integrated semiconductor memory. According to the invention, the method step is characterized in that the vertical channel structures (112) to be produced thereby, so-called channel holes, are produced by applying an anodic etching method. Thereby, layer stacks (100) having significantly more individual layers (101, 102) than in conventional technology can be processed. Thus, the number of individual layers (101, 102) within the layer stack (100) to be processed can be increased, so that the storage capacity of the layer stack (100) can be significantly increased.

Description

Technical Field

[0001] The present invention relates to a method for generating a vertical channel structure in a layer stack during the production of a three-dimensional integrated semiconductor memory, a layer stack for the production of a three-dimensional integrated semiconductor memory, and a three-dimensional integrated semiconductor memory having the layer stack. Background Technology

[0002] So-called flash memory elements are implemented, for example, using NAND cells. To achieve the high storage capacity of flash memory, the NAND cells involved are arranged vertically above and below each other, which is also known as three-dimensional system integration. Such a three-dimensional memory device with several memory cells arranged vertically above and below each other is also called 3D NAND.

[0003] In conventional manufacturing methods used to produce 3D NAND memory, numerous individual layers of Si3N4-SiO2 (silicon nitride – silicon dioxide) are stacked one on top of the other, creating a vertical layer stack. The individual layers of the stack are then laterally exposed through vertically etched holes within the layer stack so that the Si3N4 layer can be selectively etched relative to the SiO2 layer.

[0004] This is one of the core processes in the production of vertical memory cell structures, also known as "via etching." Due to its geometry, the vertically etched holes created are also referred to as channel structures. These etched channel structures, also known as "via channels" within "via etching," are what flash memory cells will be established in subsequent processes. To achieve the highest possible storage density or capacity, up to 100 alternating layers of SiO2 and Si3N4 are deposited, thereby forming a vertical stack of layers with up to 100 alternating SiO2 and Si3N4 layers, which then forms the vertical memory cell structure. As described above, this vertical stack (approximately 6 to 10 μm) is processed using "via etching" (with hole diameters on the order of approximately 100 nm and hole spacing on the order of approximately 25 nm).

[0005] Therefore, to increase the storage capacity of this vertical stacking, the number of individual layers stacked one on top of the other must be increased. Obviously, as the number of individual layers increases, the height of the vertical stack also increases, so the vertical channel structure must be made deeper, that is, the aspect ratio (depth to width ratio) of the vertical channel structure must be increased.

[0006] As mentioned above, providing a vertical channel structure has the particular advantage of providing pathways to individual layers stacked one on top of the other, and via these pathways, selectively etching the Si3N4 layer relative to the SiO2 layer. However, due to the increased aspect ratio of the vertical channel structure mentioned earlier, it becomes increasingly difficult to produce channel holes with a constant diameter using previously known methods. In fact, the etching rate is not perfectly aligned (perpendicular to the layer stack) but has a lateral component, resulting in channel holes with a larger diameter at the top than at the bottom. Therefore, within the vertical channel structure, an approximately funnel-shaped necking is formed that gradually tapers towards the bottom.

[0007] For this reason, vertical channel structures cannot be implemented at any depth, because otherwise, due to the extremely high aspect ratio, increasingly noticeable deviations from the ideal channel would occur. Currently, this technology can etch up to 100 individual layers (so-called high aspect ratio channel etching). Therefore, the number of individual layers within a vertical layer stack is limited to approximately 100. However, this also means that a vertical layer stack may not have substantially more individual layers, which again correspondingly limits the storage capacity of vertical layer stacks. The resulting problem is the limitation on the number of individual layers within a vertical layer stack, and therefore, the corresponding limitation on storage capacity.

[0008] Therefore, it is desirable to improve conventional methods for producing three-dimensional integrated semiconductor memories, thereby increasing the uniformity of etching rates when generating vertical channel structures (channel holes), which can increase the number of individual layers within the layer stack to correspondingly increase the storage capacity of the semiconductor memory. Summary of the Invention

[0009] This objective is achieved through a method for creating vertical channel structures in a layer stack during the production of three-dimensional integrated semiconductor memories.

[0010] In a first aspect, when manufacturing three-dimensional integrated semiconductor memories, the method of the present invention is essentially used to create vertical channel structures (channel vias) in a vertical layer stack. Here, firstly, a substrate is provided. On the substrate, a vertical layer stack having several individual layers stacked one on top of the other is created by depositing several individual layers of a first material and several individual layers of a different second material alternately on top of each other. The first material and the second material are each conductive or semiconductive. At least one vertical channel structure is created in the layer stack, wherein the vertical channel structure extends vertically, at least partially through the layer stack, such that one or more of the individual layers are exposed within the vertical channel structure and are accessible through the vertical channel structure. A specific feature of the method of the present invention is that the structured vertical channel structure is created by applying an anodic etching method. Here, a first voltage potential is applied to a first portion of the layer stack and different second voltage potentials are applied to different second portions of the layer stack. Thus, the current that creates the vertical channel structure in the layer stack by directional anodic etching flows vertically through the layer stack between the first and second portions.

[0011] In some embodiments, the vertical channel structure produced by the anodic etching method has an aspect ratio greater than 50:1 or greater than 100:1 with respect to its length and width. In some embodiments, the vertical channel structure produced by the anodic etching method includes a diameter that deviates by less than 50% over the entire length of the vertical channel structure, thus remaining approximately constant. In some embodiments, the vertical channel structure extends in a straight line between the first portion and the second portion of the layer stack. In some embodiments, the vertical recess extends through several of the individual layers of the layer stack, or wherein the vertical recess extends through all the individual layers of the layer stack. In some embodiments, the applied anodic etching method can produce multiple vertical channel structures in a layer stack having more than 100 individual layers, more than 200 individual layers, or more than 300 individual layers. In some embodiments, the method further includes the step of selectively removing the individual layer of the first material from the layer stack by applying an etching process while maintaining the individual layer of the second material, wherein the etching medium passes through the vertical channel structure to reach the layer stack and to the individual layer of the first material and the individual layer of the second material exposed and accessible within the vertical channel structure, and selectively releases the individual layer of the first material from the layer stack.

[0012] In some embodiments, the individual layers of the first material and the individual layers of the second material include different etching behaviors for a particular etching medium, such that the first material includes high etch selectivity relative to the second material. In some embodiments, the individual layer of the first material includes or is composed of a first doped semiconductor material, and / or the individual layer of the second material includes or is composed of a second doped semiconductor material, wherein the first doped semiconductor material and the second doped semiconductor material are different. In some embodiments, the first doped semiconductor material includes a different doping type or a different doping degree compared to the second doped semiconductor material. In some embodiments, the individual layer of the first material includes or is composed of germanium or silicon-germanium, and / or the individual layer of the second material includes or is composed of silicon.

[0013] In a second aspect, a layer stack for the production of a three-dimensional integrated semiconductor memory is provided, wherein the layer stack includes a plurality of vertical channel structures produced according to the method of the first aspect.

[0014] In a third aspect, a three-dimensional integrated semiconductor memory having a layer stack according to the second aspect is provided.

[0015] In the vertical semiconductor memory of the aforementioned known conventional techniques, the vertical layer stack is produced by alternating successive Si3N4 and SiO2 layers. Anisotropic etching methods, such as directional ion beam deep etching, are used to etch these layers. The aspect ratio of the vertical channel structure produced by these anisotropic etching methods is limited, and therefore the number of individual layers is also limited.

[0016] However, the method of the present invention proposes the use of directional anode etching for so-called channel via etching in the production of three-dimensional integrated semiconductor memories, instead of the previously used anisotropic etching methods. Compared to previously used etching techniques (e.g., ion beam deep etching), directional anode etching has significantly higher etching rate uniformity, i.e., it can produce vertical channel structures with a significantly larger aspect ratio, thereby creating significantly deeper channel structures within the layer stack. In anode etching, funnel-shaped necking as seen in conventional techniques does not occur. Because significantly deeper channel structures can be selectively produced, the number of individual layers within the vertical layer stack can be significantly increased, thereby correspondingly significantly increasing the storage capacity of the resulting three-dimensional integrated semiconductor memory. Attached Figure Description

[0017] Some embodiments of the present invention are illustrated exemplarily in the accompanying drawings and will be discussed below. Wherein:

[0018] Figure 1A-1EA schematic cross-sectional side view is shown illustrating the individual process steps for producing a conventional 3D semiconductor memory using conventional methods and techniques.

[0019] Figure 1F A portion of a schematic cross-sectional side view of a vertical recess in a conventional layer stack according to conventional techniques is shown to illustrate problems with previously used methods.

[0020] Figure 2 A schematic cross-sectional side view of the layer stack that can be produced by the method steps according to the invention is shown, and

[0021] Figures 3A-3H and Figure 3J-3N A schematic cross-sectional side view is shown of individual (partially optional) method steps for illustrating the production of the 3D semiconductor memory of the present invention according to the method. Detailed Implementation

[0022] In the following description, embodiments will be described in more detail with reference to the accompanying drawings, wherein elements having the same or similar functions have the same reference numerals.

[0023] The method steps illustrated or described in this disclosure may also be performed in a different order than those shown or described. Furthermore, method steps associated with specific features of the apparatus may be interchanged with features of the apparatus, and vice versa.

[0024] When this disclosure refers to the vertical direction, it is a direction perpendicular to the plane spanned by the individual layer. For example, if the length and width of the individual layer extend in the xy plane, the vertical direction corresponds to the z-axis. In this case, for example, the length and width of the individual layer are measured in the x or y direction, while the thickness of the individual layer is measured in the z direction. Within a layer stack, the corresponding individual layers are stacked one on top of the other along this vertical direction (z-axis), such that the layer stack extends vertically from the substrate toward the top.

[0025] When this disclosure relates to a lateral direction, this is a direction extending in or parallel to the xy-plane spanned by a single layer, or a direction extending perpendicular to the vertical extension direction (z-axis) of the layer stack. Therefore, in the case of a vertically extending layer stack, the lateral direction can be substantially equal to the horizontal direction.

[0026] The innovative concept described in this paper relates to specific methodological steps for generating vertical channel structures in a method for producing three-dimensional integrated semiconductor memories. In this context, these vertical channel structures are also referred to as vertical channel vias. In the context of 3D semiconductor memories, the corresponding method is also referred to as vertical channel via etching. The innovative concept described in this paper describes a novel method for generating vertical channel structures with high anisotropy, thereby significantly increasing the number of layers in a vertical semiconductor memory and thus significantly increasing its storage capacity.

[0027] This invention belongs to the technical field of manufacturing three-dimensional integrated semiconductor memories, such as three-dimensional NAND flash memory. Compared with conventional planar technology (xy direction), three-dimensional integration additionally creates devices in the vertical direction (z direction).

[0028] Before describing the method of the present invention, conventional techniques will be discussed first. Figures 1A to 1E A method for manufacturing a three-dimensional integrated semiconductor memory 10 using conventional techniques is illustrated. For example... Figure 1A As can be seen, firstly, several individual layers 1 and 2 are arranged alternately on the silicon substrate 11. These are individual layers 1 of silicon oxide (SiO2) and individual layers 2 of silicon nitride (Si3N4). These individual layers 1 and 2 arranged alternately on the substrate form a vertical layer stack 20.

[0029] Figure 1B The next process step is shown, in which one or more vertical recesses 6 are structured into the vertical layer stack 20.

[0030] Figure 1C The support structure 5 is shown to be formed in the vertical recess 6. The support structure 5 is mechanically connected to and stabilizes the individual layers 1 and 2. The support structure 5 can form a gate NAND structure in a semiconductor memory.

[0031] The vertical channel structure 7 is structured between two support structures 5 in the layer stack 20. This is known as "via etching". Through this vertical channel structure 7, individual layers 1 and 2 are laterally exposed, allowing individual layers 1 and 2 to be freely accessible within the vertical channel structure 7.

[0032] During the wet chemical etching process, thermal phosphoric acid can enter the layer stack 20 through the vertical channel structure 7. Thus, the thermal phosphoric acid reaches the exposed individual layers 1 and 2 and selectively etches away the silicon nitride individual layer 2, leaving only the silicon oxide individual layer 1 (…). Figure 1D A void 8 is created between the individual silicon oxide layers 1, at the original location of the individual silicon nitride layer 2.

[0033] like Figure 1EAs can be seen, these gaps 8 are then filled with tungsten 9. This creates a vertical layer stack 20, which includes individual silicon oxide layers 1 and tungsten layers 19 arranged alternately on top of each other.

[0034] As mentioned above, the production of 3D NAND memory cells aims to increase their storage capacity per unit volume. This is achieved, in particular, by alternately stacking more and more individual layers of silicon nitride (Si3N4) and silicon oxide (SiO2) one on top of the other, but this obviously also increases the total height of the vertical layer stack 20. As mentioned above, in order to enable lateral etching of all the individual silicon nitride layers 10, a vertical channel structure 7 is introduced into the layer stack 20. Through the vertical channel structure 7, thermal phosphoric acid reaches the individual silicon nitride layers 2 that are exposed and accessible within the vertical channel structure 7. However, as the height of the layer stack 20 increases, the aspect ratio of the vertical channel structure 7 must also increase accordingly, i.e., the vertical channel structure 7 must become deeper. However, with the increase in aspect ratio, along the vertical channel structure 7, i.e. towards the bottom, more and more etch rate non-uniformity is caused, resulting in an increased isotropic portion of the originally anisotropic etched portion. Therefore, a certain funnel-shaped necking is created towards the bottom of the vertical channel structure 7.

[0035] This funnel-shaped necking can have the effect of preventing the stacked layers 20 from being completely etched through. Due to the funnel shape, the vertical channel structure 7 has different dimensions along its depth, which can exceed and fall below the target size, making the useful production of the memory impossible.

[0036] Figure 1F The problem is illustrated here. Only a portion of the vertical channel structure 7 (channel via) within the layer stack is shown schematically. This layer stack has several individual layers 1, 2 arranged alternately one above the other. These are silicon oxide layer 1 and silicon nitride layer 2. The silicon nitride layer 2 is selectively etched relative to the silicon oxide layer 1.

[0037] like Figure 1F As can be seen, when a vertical channel structure (channel hole etching) is created, a funnel-shaped necking is produced, wherein the diameter at the bottom of the vertical channel structure 7 is significantly smaller than the diameter at the top of the vertical channel structure 7.

[0038] The resulting problem is the limitation on the number of individual layers within the stack and the associated storage capacity. This means that the vertical channel structure 7 cannot be implemented at any depth, otherwise it would result in increasingly pronounced contractions with the funnel-shaped necking shown herein. Currently, up to 96 individual layers can be vertically etched using this technique, and then selectively etched laterally. Therefore, the number of individual layers within the stack is limited to these 96 individual layers. However, this also means that the stack may not include significantly more individual layers, which correspondingly limits the storage capacity of the stack.

[0039] The novel method for etching channel holes in the production of 3D semiconductor memories described in this paper allows for the generation of vertical channel holes on a large number of individual layers with significantly different anisotropies. This results in a significant reduction in the funnel-shaped necking of the channel holes in the vertical layer stack, allowing the number of individual layers within the stack to be significantly increased to correspondingly increase the storage capacity of the semiconductor memory.

[0040] first, Figure 2 A schematic diagram of a vertical layer stack 100 of the present invention is shown, having a vertical channel structure 112 (channel hole) produced by applying the method of the present invention (channel hole etching). This vertical channel structure 112 is also referred to as a channel hole and may have, for example, a hole shape.

[0041] In the method of the present invention, firstly, a substrate 200 is provided. A layer stack 100 is formed on the substrate 200. The layer stack 100 includes several individual layers 101, 102. The layer stack 100 is formed by depositing individual layers 101 of a first material and several individual layers 102 of a different second material alternately on top of each other. The individual layers 101, 102 may be deposited or epitaxially grown, for example, alternately.

[0042] According to the present invention, both the first material and the second material are conductive or semiconductive. For example, a single layer 101 of the first material may include or be composed of a first doped semiconductor material. Alternatively or additionally, a single layer 102 of the second material may include or be composed of a second doped semiconductor material, wherein the first doped semiconductor material and the second doped semiconductor material are different.

[0043] Here, for example, the first doped semiconductor material may include a different doping type or a different doping degree than the second doped semiconductor material. The doping degree is also called the doping intensity, which is the strength of the doping. Here, strong doping (n...) can be distinguished. + ; p + Medium doping (n; p) and weak doping (n - p - ).

[0044] Due to different doping (i.e., different doping types and / or different doping degrees), the two semiconductor materials also exhibit different etching behaviors. Therefore, in later method steps ( Figure 3J In this process, one semiconductor material can be selectively etched relative to a corresponding other semiconductor material. See below for reference. Figures 3A to 3H and Figures 3J to 3NSelective etching and the associated necessity of maximizing the etch selectivity of one material relative to another will be discussed in more detail.

[0045] The method of the present invention provides for structuring at least one vertical channel structure 112 (channel via) in a vertical layer stack 100. According to the invention, the vertical channel structure 112 is structured into the layer stack 100 by applying an anodizing process. For the purpose of anodizing, it is advantageous when both individual layers 101, 102 are conductive or semi-conductive.

[0046] like Figure 2 As exemplarily shown, for an anodic etching process, a first potential U1 can be applied to a first portion 210 of the layer stack 100. Furthermore, a second potential U2, different from the first potential U1, can be applied to a different second portion 220 of the layer stack 100. Thus, current that generates the vertical channel structure 112 in the layer stack 100 through directional anodic etching flows between the first portion 210 and the second portion 220 of the layer stack 100.

[0047] The first portion 210 of the layer stack 100 may be, for example, the portion 210 of the layer stack 100 facing the substrate 200 or closest to the substrate 200. The first portion 210 of the layer stack may be, for example, the bottom of the layer stack 100. This may be, for example, the lowest single layer, i.e., the single layer closest to the substrate 200.

[0048] The second portion 220 of the layer stack 100 may be, for example, the portion 220 of the layer stack 100 that is opposite to or furthest from the substrate 200. The second portion 220 of the layer stack 100 may be, for example, the top of the layer stack 100. This may be, for example, the top individual layers 101, 102, i.e., the individual layers furthest from the substrate 200.

[0049] However, the first portion 210 of the layer stack 100 can also be any single layer in the lower half of the layer stack 100, and the second portion 220 of the layer stack 100 can also be any single layer 101, 102 in the upper half of the layer stack 100.

[0050] This can be particularly due to the depth to be etched, i.e., the depth to which the vertical channel structure 112 to be created will reach. For example, if the vertical channel structure 112 is to be structured downwards over the entire layer stack 100 to the substrate 200, the first portion could be the bottom of the layer stack 100 or the lowest individual layers 101, 102. However, if the etching is performed only to a specific individual layer in the lower half of the layer stack 100, a first potential U1 can be applied to that specific individual layer.

[0051] Figure 2Only a schematic diagram of the layer stack 100 is shown, in which the corresponding individual layers 101, 102 are in direct contact. It is also possible for a first electrode structure (not explicitly shown herein) to contact a first portion 210 of the layer stack 100 (e.g., the bottom individual layer) and / or for a second electrode structure (not explicitly shown herein) to contact a second portion 220 of the layer stack 100 (e.g., the top individual layer). Therefore, voltage can be connected to the corresponding electrode structures. This will also be discussed below.

[0052] The first potential U1 can have a first quantity, while the second potential U2 can have a different second quantity. For example, the first voltage potential U1 can be the ground potential, while the second voltage potential U2 can have a quantity with a positive or negative sign different from the ground potential.

[0053] Therefore, the resulting current flows vertically through the vertical stack 100 according to its sign. This means that the current flows vertically through the stack 100, for example, from the first portion 210 (e.g., the bottom) to the second portion 220 (e.g., the top) of the stack 100, and creates a vertical channel structure 112. Thus, in this example, the current will flow from the bottom to the top.

[0054] The vertical channel structure 112 (channel hole) is particularly intended to provide a pathway for the etching medium to enter the interior of the layer stack 100. By means of the etching medium entering the layer stack 100 through the channel hole 112, when producing three-dimensional integrated semiconductor layers, a single layer 101 of one material can be selectively etched relative to a corresponding single layer 102 of another material.

[0055] Figures 3A to 3H and Figures 3J to 3N The individual method steps for producing a three-dimensional integrated semiconductor memory by applying the method of the present invention are illustrated schematically. Here, the method of the present invention relates to specific steps during the process for producing a three-dimensional integrated semiconductor memory. The process step of the present invention (channel etching) is used to produce the vertical channel structure 112 (channel hole) and is performed by applying the anodic etching process according to the present invention.

[0056] first, Figure 3A A vertical or three-dimensional layer stack 100 in its original or initial state is shown. The layer stack 100 is disposed on a substrate 200. The layer stack 100 can be produced by alternately depositing several individual layers 101 of a first material and several individual layers 102 of a different second material on the substrate 200. The individual layers 101, 102 can be deposited one on top of the other or epitaxially grown, for example.

[0057] The materials of individual layers 101, 102, or individual layers 101, 102, are chosen such that they have very high etch selectivity relative to each other. For example, the individual layer 101 of the first material may include germanium (Ge) or silicon germanium (SiGe), or may be composed of germanium or silicon germanium. On the other hand, the individual layer 102 of the second material may include silicon (Si) or may be composed of silicon.

[0058] As mentioned above, high etch selectivity can also be achieved between the two types of individual layers 101 and 102 because each individual layer 101 and 102 has a different doping type and / or doping degree. The following will refer to... Figure 3J The reasons for the high etch selectivity that should exist between the single layer 101 of the first material and the single layer 102 of the second material will be discussed in more detail.

[0059] Besides etching selectivity, there is another reason regarding the type or degree of doping. For the purposes of anodic etching, which will be described in more detail below, it is advantageous when both types of individual layers 101, 102, namely, the individual layer 101 of the first material and the individual layer 102 of the second material, are conductive. This can also be adjusted by the doping type and / or doping degree of the respective individual layers 101, 102.

[0060] In the method of the present invention, the individual layer 101 of the first material and / or the individual layer 102 of the second material may additionally have an amorphous structure. This means that the individual layers 101 and 102 do not necessarily need to have a crystalline structure. For example, the individual layers 101 and 102 may comprise amorphous silicon or amorphous silicon germanium, or may be composed of amorphous silicon or amorphous silicon germanium.

[0061] exist Figure 3A In the example shown, a single layer 101 of the first material (e.g., SiGe) is merely arranged as an exemplary bottom layer or first layer on the substrate 200. Then, additional single layers 102 of the second material and additional single layers 101 of the first material are each arranged alternately on top of each other on the first single layer 101. This results in a vertically stacked layer 100 having several single layers 101 of the first material and several single layers 102 of the second material arranged alternately. The order of the single layers 101, 102 can also be interchanged, such that, for example, a single layer 102 of the second material is arranged as a first layer on the substrate 200.

[0062] A first electrode structure 250 can be disposed between the substrate 200 and the lowest individual layers 101, 102. The first electrode structure 250 may include a contact portion 251 for electrical contact. A potential U1 can be applied to the contact portion 251. The element on which the first potential U1 is applied is also referred to as a first potential contact.

[0063] The first potential U1 can have a specific value. For example, the first potential U1 can be the ground potential.

[0064] The first electrode structure 250 can be conductively connected to the first or lowest individual layer 101 of the stack 100, such that the lowest individual layer 101 is also at the first potential U1 and thus forms a first potential contact. Alternatively, the lowest individual layer 101 can be directly contacted instead of the first electrode structure 250, as described above. Figure 2 Exemplary discussion.

[0065] On the side opposite to substrate 200, i.e., on top of layer stack 100, a single layer, either the last or the top, is arranged. Figure 3A In the example shown, this is a single layer 102 of the second material. A single layer 101 of the first material can also form the top layer.

[0066] The second electrode structure 252 can be disposed on the top layer 102. Here, the top layer 102 can be structured in a predetermined manner. (Refer to...) Figure 3B Here, it can be seen that one or more vertical recesses 111 are to be generated.

[0067] If possible Figure 3A As seen again, the top layer 102 can be structured so that a portion of the top layer 102, 102A, is retained in subsequent process steps. Figure 3B A vertical recess 111 to be formed in ) Figure 3B At those locations. At other locations, i.e., where the recess 111 is not to be formed, the top layer 102 can be removed.

[0068] The top second electrode structure 252 can be arranged on the structured top layer 102 or on the remaining portion 102A of the structured top layer 102, such that the structured top layer 102 is in conductive contact with the second electrode structure 252.

[0069] The second electrode structure 252 may include a contact portion 253 for electrical contact. A second potential U2 may be applied to the contact portion 253. The element on which the second potential U2 is applied is also referred to as a second potential contact.

[0070] Potential U2 can have a different value than the first potential U1, thus creating a potential drop or voltage. This can be an alternating current voltage or a direct current voltage.

[0071] Because the second electrode structure 252 is conductively connected to the last or top structured individual layer 102 of the layer stack 100, the top structured individual layer 102 is also at potential U2. Therefore, in this example, the structured top individual layer 102 forms a second potential contact. (Refer to the above text.) Figure 2As exemplarily discussed, the top structured individual layer 102 can also be accessed directly.

[0072] One of the two potentials U1 and U2 can be ground potential. The voltage generated at the two potential contacts can be a DC voltage or an AC voltage. For example, a DC voltage or an AC voltage can be applied between the first potential contact or the first portion 210 of the stack 100 (e.g., the bottom single layer 101) and the second potential contact or the second portion 220 of the stack 100 (e.g., the top structured single layer 102). For this purpose, a suitable voltage source can be connected to the two electrodes 250, 252 or the potential contacts, for example.

[0073] Current 260 flows between two potential contacts due to the applied voltage or due to the potential difference between the two potentials U1 and U2, in this example, between the top structured layer 102 and the bottom layer 101.

[0074] like Figure 3B As shown, one or more vertical recesses 111 are created in the layer stack 100. These vertical recesses 111 are structured in the layer stack 100. For this purpose, an anodizing etching method can be applied.

[0075] However, it should be mentioned here that the application of the anodic etching method used to create the vertical recess 111 is merely optional. The vertical recess 111 is not a so-called channel hole, but rather a space in which the support structure 105 is subsequently to be created. Figure 3E The vertical recesses 111 described herein can also be formed using other etching methods. These support structures 105 can, for example, form gate NAND structures.

[0076] The process steps of this invention involve a so-called channel hole etching step for producing a vertical channel structure 112 (channel hole), which will be referred to... Figures 3E to 3H This step will be discussed in more detail. For this purpose, according to the invention, an anodizing method is used. This provides the advantage that the layer stack 100 as a whole can include more individual layers 101, 102. For this reason, a reference can also be suitably produced by using an anodizing method. Figures 3A to 3D The vertical recess 111 is described. Nevertheless, this is still entirely optional.

[0077] exist Figure 3A In the example shown, whenever an anodizing method is used to create the vertical recess 111, current 260 flows vertically downward from the second potential contact (e.g., the second electrode structure 252 or the last or top structured separate layer 102 in contact with it) in the direction of the first potential contact (e.g., the first electrode 250 or the first or bottom separate layer 101 connected to it).

[0078] A current 260 can flow through the entire layer stack 100 and can remove the individual layers 101, 102 stacked between the first and second potential contacts in the direction of current flow. This is also known as anodic etching. Its advantage is that it can etch far more than the previously common approximately 100 individual layers with very high anisotropy. This means that the funnel-shaped necking of the vertical recess 111 in the etching direction will not be formed as in conventional techniques (see...). Figure 1F ).

[0079] like Figure 3B As can be seen, the vertical recess 111 extends completely or entirely through the layer stack 100, i.e., through all the individual layers 101, 102 present. In other embodiments not explicitly illustrated herein, the vertical channel structure 111, created by anodic etching, may also extend through at least one or several (but not all) of the individual layers 101, 102. This depends on which individual layer the first potential U1 or the second potential U2 is applied to, i.e., which individual layers form the first potential contact or the second potential contact. Since the current 260 flows only between the respective two potential contacts (or individual layers), only the individual layer located between these two potential contacts (or individual layers) is removed or anodic etched. Thus, for example, a vertical recess 111 that extends only partially through the layer stack 100 may be created within the layer stack 100, for example, extending from the top of the layer stack 100 rather than all the way down to the substrate 200.

[0080] Figure 3C An alternative option for anodic etching of the vertical recess 111 is shown, wherein... Figure 3A and Figure 3B The same elements in the figure have the same reference numerals.

[0081] Here, firstly, a layer stack 100 can be seen having several individual layers 101 of a first material and individual layers 102 of a second material arranged alternately on top of each other. The first or bottom individual layer 101 may optionally form a first potential contact via a first electrode structure 250. The first potential contact may include a first potential U1.

[0082] Reference Figure 3A The difference in the discussed embodiments is that the second electrode structure 252 can be arranged on a single layer 102, either at the end or the top of the layer stack 100, and the second electrode structure 252 optionally has several electrode portions 252A, 252B. The single layer 102 at the top can, but is not necessarily, as... Figure 3A The structure is not as defined in the previous example. This means that in this embodiment, the last or top individual layer 102 can be complete and therefore unstructured.

[0083] The second electrode structure 252 or its electrode portions 252A, 252B are again arranged in the subsequently generated vertical recess 111 of the stack 100. Figure 3D Those parts of ).

[0084] The second electrode structure 252 or its electrode portions 252A and 252B can form a second potential contact and can be connected to the second potential U2. The second electrode structure 252 or its electrode portions 252A and 252B can extend along the depth direction on the last or top separate layer 102, i.e., into the plane of the attached drawing.

[0085] Again, the current 260, which is used for anodic etching or removal of the intermediate individual layer, flows between the first potential contact and the second potential contact.

[0086] As can be seen in the following figures, the previously created vertical recesses 111 can be filled with material to form a support structure 105 within each of the respective vertical recesses 111. The support structure 105 is connected to the respective individual layers 101, 102 to mechanically stabilize or support the individual layers 101, 102.

[0087] To create such a support structure 105, the vertical recess 111 may, for example, be provided with or filled with a layer system that forms the gate and charge memory channel regions and isolators for subsequent NAND memory cells. To occupy or fill the vertical recess 111, layers are used to create the isolators and channel regions (gate isolators / memory and channel components) of the NAND memory. The materials used for occupying or filling may include one or more components from the group consisting of, for example, silicon oxide, silicon nitride, and silicon. A possible layer order may be (from inside to outside): silicon oxide, silicon nitride, silicon oxide, silicon. After filling, the corresponding vertical recess 111 can be closed by layer deposition.

[0088] Figures 3E to 3H The process steps (channel etching) to be assigned to the method of the present invention are shown. These process steps are used to create vertical channel structures 112 (channel holes) in a layer stack 100 during the production of a three-dimensional integrated semiconductor memory.

[0089] In the layer stack 100, a vertical channel structure 112 (channel hole) can be created (see...). Figure 3F and Figure 3H Here, the vertical channel structure 112 can be formed, for example, between the support structures 105 (NAND gate structures). Although the anodizing method is only optionally applied to create the aforementioned vertical recesses 111, references below... Figures 3E to 3H The anodic etching described for producing the vertical channel structure 112 is a step of the present invention of the method disclosed herein.

[0090] like Figure 3E As can be seen, the first electrode structure 250 can be disposed between the substrate 200 and the first or bottom individual layers 101, 102. The first electrode structure 250 may include a contact portion 251 for electrical contact. A potential U1 can be applied to the contact portion 251. The element on which the first potential U1 is applied is also referred to as a first potential contact.

[0091] The first potential U1 can have a certain value. The first potential U1 can be, for example, the ground potential.

[0092] The first electrode structure 250 can be conductively connected to the first or lowest individual layer 101 of the stack 100, such that the bottom individual layer 101 is also at the first potential U1, thereby forming a first potential contact. Alternatively, the bottom individual layer 101 can be directly contacted instead of the first electrode structure 250, as described above. Figure 2 This is discussed exemplarily.

[0093] On the side opposite to the substrate 200, i.e., on top of the layer stack 100, a final or top separate layer is formed. In the example shown in FIG3E, this is a separate layer 102 of the second material. A separate layer 101 of the first material can also form the top layer.

[0094] The second electrode structure 252 can be arranged on the top layer 102. Here, the top layer 102 can be structured in a predetermined manner. For example... Figure 3F As can be seen, a vertical channel structure 112 (channel hole) is to be created. The vertical channel structure 112 is used in a three-dimensional integrated semiconductor memory manufacturing process to introduce an etching medium (e.g., etching gas, wet chemical etching solution, etc.) into the layer stack 100. The etching medium is used to selectively etch or remove a separate layer 101 of the first material exposed within the vertical channel structure 112 relative to a separate layer 102 of the exposed second material. This means that the etching medium is introduced through the vertical channel structure 112, selectively etching or removing one of the two materials relative to the corresponding other material. A separate layer of one material is removed, while a separate layer of the corresponding other material is not removed, i.e., it is retained. This distinguishes the vertical channel structure 112 from the aforementioned vertical recess 111. As already mentioned, the recess 111 is not a so-called channel hole.

[0095] In order to create the vertical channel structure 112 by anodic etching, the second electrode structure 252 can be disposed at those locations of the top individual layer 102 where the vertical channel structure 112 is to be created. Figure 3F ).

[0096] The second electrode structure 252 can be connected to the second potential U2, and thus form a second potential contact.

[0097] Here again, current 260 flows between the first potential contact and the second potential contact during anodic etching or removal of the intermediate individual layers 101, 102. As a result, a... Figure 3F The vertical channel structure 112 (channel hole) shown is illustrated.

[0098] The vertical channel structure 112 produced by the anodic etching method according to the invention can extend between the first or bottom portion 210 of the stack 100 (e.g., the first potential contact or the lowest individual layer) and the second or top portion 220 of the stack 100 (e.g., the second potential contact or the top layer), extending substantially in a straight line through the stack 100.

[0099] The vertical channel structure 112 produced by the anodic etching method according to the present invention may further have an aspect ratio of greater than 50:1 or greater than 100:1 with respect to its length and width.

[0100] Using the method of the present invention, a layer stack 100 having more than 100, 200, or even 300 individual layers 101, 102 stacked one on top of the other can be processed. This means that more than 100, 200, or even more than 300 individual layers 101, 102 can be etched or removed by anodic etching to produce a vertical channel structure 112 (channel via). Up to 1000 or more individual layers 101, 102 can even be processed. Anodic etching has very high anisotropy, which is why the resulting vertical channel structure 112 has a relatively constant diameter along its entire length despite a large aspect ratio.

[0101] The vertical channel structure 112 produced by the anodic etching method according to the present invention can, for example, have a diameter between 20 nm and 150 nm. The diameter of the vertical channel structure 112 can have a deviation of less than 10% or less than 50% over the entire length of the channel structure 112, and thus can remain approximately constant. However, in conventional techniques ( Figure 1F In the process, etching of more than 96 layers for imaging will have a funnel-shaped necking effect that tapers towards the bottom, resulting in a deviation of more than 50% between the diameter in the bottom region and the diameter in the top region of the vertical channel structure 7 (Fig. 1).

[0102] Figure 3G and Figure 3H Alternative variants for producing the vertical channel structure 112 by anodic etching are shown, wherein, as in Figure 3E and Figure 3F The same elements in the figure have the same reference numerals.

[0103] Similarly, a layer stack 100 is first shown here, having several individual layers 101 of a first material and individual layers 102 of a second material arranged alternately on top of each other. The first or bottom individual layer 101 may optionally form a first potential contact via a first electrode structure 250. The first potential contact may have a first potential U1.

[0104] References above Figure 3E The difference in the discussed embodiments is that the second electrode structure 252 can be disposed on the last or top separate layer 102 of the layer stack 100, wherein the top separate layer 102 is structured in a predetermined manner. The top layer 102 can be structured such that at least a portion 102A of the top layer 102 is retained in subsequent process steps to form the vertical channel structure 112. Figure 3H At the location of ), the top layer 102 can be removed at other locations, i.e., where the vertical channel structure 112 is not to be formed.

[0105] The second electrode structure 252 can now be arranged on the structured top layer 102 or on the remaining portion 102A of the structured top layer 102, such that the structured top layer 102 contacts the electrode structure 252 in a conductive manner.

[0106] The second electrode structure 252 may include a contact portion 253 for electrical contact. A second potential U2 may be applied to the contact portion 253. The element on which the second potential U2 is applied is also referred to as a second potential contact.

[0107] Potential U2 can have a different value than the first potential U1, thus creating a potential drop or voltage. This can be an alternating current voltage or a direct current voltage.

[0108] Because the second electrode structure 253 is conductively connected to the last or top structured individual layer 102 of the layer stack 100, the top structured individual layer 102 is also at potential U2. Therefore, in this example, the structured top individual layer 102 forms a second potential contact. However, it is also possible to refer to the above... Figure 2 As exemplarily discussed, it directly contacts the top structured individual layer 102.

[0109] One of the two potentials U1 and U2 can be ground potential. The voltage generated at the two potential contacts due to the potential difference can be a DC voltage or an AC voltage. For example, a DC voltage or an AC voltage can be applied between the first potential contact or the first portion 210 of the stack 100 (e.g., the bottom single layer 101) and the second potential contact or the second portion 220 of the stack 100 (e.g., the top structured single layer 102). For this purpose, a suitable voltage source can be connected to the two electrodes 250, 252 or the potential contacts.

[0110] Due to the applied voltage or due to the potential difference between the two potentials U1 and U2, current 260 again flows between the two potential contacts, in this example, between the top structured layer 102 and the bottom layer 101.

[0111] In this example, current 260 flows vertically downward from the second potential contact (e.g., the second electrode structure 252 or the last or top structured separate layer 102 in contact with it) in the direction of the first potential contact (e.g., the first electrode 250 or the first or lowest or bottommost separate layer 101 in contact with it).

[0112] like Figure 3H As can be seen, vertical channel structures 112 (channel holes) are formed in the layer stack 100 along the current flow direction. According to the present invention, the vertical channel structures 112 are structured in the layer stack 100 by anodizing.

[0113] Here, current 260 can flow through the entire layer stack 100 and individual layers 101, 102 stacked between the first potential contact and the second potential contact in the direction of current flow can be removed.

[0114] like Figure 3H As can also be seen, the vertical channel structure 112 extends completely or entirely through the layer stack 100, i.e., through all the individual layers 101, 102 present. In other embodiments not explicitly illustrated herein, the vertical channel structure 112, created by anodic etching, may also extend through at least one or several (but not all) of the individual layers 101, 102. This depends on which individual layer the first potential U1 or the second potential U2 is applied to, i.e., which individual layers form the first potential contact or the second potential contact. Since the current 260 flows only between the respective two potential contacts (or individual layers), only the individual layer located between these two potential contacts (or individual layers) is removed or anodic etched. Thus, for example, a vertical channel structure 112 that extends only partially through the layer stack 100 can be created within the layer stack 100, e.g., extending from the top of the layer stack 100 rather than all the way down to the substrate 200.

[0115] Within the vertical channel structure 112, the individual layers 101 and 102 are laterally exposed, meaning the vertical channel structure 112 forms pathways to the corresponding individual layers 101 and 102 of the stack 100, in this case, to the individual layers 101 of the first material and 102 of the second material present in the stack 100 at this time. Therefore, within the vertical channel structure 112, the individual layers 101 and 102, arranged vertically to each other, are partially exposed, allowing these individual layers 101 and 102 to be freely accessible via the vertical channel structure 112.

[0116] As mentioned above, in the manufacturing method of a three-dimensional integrated semiconductor memory, a vertical channel structure 112 is used to introduce an etching medium (e.g., etching gas, wet chemical etching solution, etc.) into the layer stack 100. This etching medium is used to selectively etch or remove a separate layer 101 of a first material exposed within the vertical channel structure 112 relative to a separate layer 102 of an exposed second material. This means that one of two materials is selectively etched, removed, or released relative to the corresponding other material through the vertical channel structure 112.

[0117] For example, the etching medium can flow through the vertical channel structure 112 into the layer stack 100 and reach the individual layers 101, 102 of the first material and the second material that are respectively accessible.

[0118] Therefore, the method of the present invention includes the step of selectively removing a separate layer 101 of a first material that is accessible within the layer stack 100, while retaining a separate layer 102 of a second material. Preferably, this is performed by applying an etching process, wherein an etching medium passes through a vertical channel structure 112 to reach the layer stack 100, and to reach the separate layers 101 of the first material and the separate layers 102 of the second material that are exposed and accessible within the vertical channel structure 112, and selectively etches away only a separate layer of one of the two materials from the layer stack 100.

[0119] For the reasons stated above, it is advantageous when the individual layer 101 of the first material has high etch selectivity relative to the individual layer 102 of the second material. As mentioned above, this can be adjusted, in particular, by the doping (type and / or degree of doping) of the respective individual layers 101, 102.

[0120] To selectively etch specific individual layers, the etching medium (e.g., etching gas) used during the etching process described herein first reaches individual layers 101 of the first material and 102 of the second material in the layer stack 100, with individual layers 101 and 102 partially exposed through the vertical channel structure 112. Combined with the etching medium used, the two materials exhibit very high etching selectivity relative to each other. With the etching medium used, individual layers of one material can be removed very selectively relative to corresponding individual layers of the other material.

[0121] For example, the etching medium can preferably selectively etch away the individual layer 101 of the first material relative to the individual layer 102 of the second material in the lateral direction. The lateral direction is the direction that extends substantially orthogonal to the (vertical) layer direction of the layer stack 100. The layer direction is the direction in which the individual layers 101, 102 are stacked one on top of the other, and in the present case, for example, vertically stacked from the substrate 200 to the top. In this case, the lateral direction is, for example, the horizontal direction. Therefore, the individual layer 101 of the first material can be etched away from the layer stack 100 approximately in the horizontal direction starting from the vertical channel structure 112. On the other hand, the individual layer 102 of the second material is not significantly eroded by the etching medium used, and therefore is not etched away but remains in the layer stack 100.

[0122] Figure 3J A layer stack 100 is shown after selectively etching away the individual layer 101 of the first material. Here, only the individual layer 102 of the second material is retained. Meanwhile, gaps 108 are formed between the retained individual layers 102 of the second material at the original locations of the removed individual layers 101 of the first material. The retained individual layers 102 of the second material are supported by a support structure 105. The support structure 105 is connected to the substrate 200.

[0123] Figure 3K Optional further process steps for producing a three-dimensional integrated semiconductor memory are illustrated. A third material may be introduced into the voids 108 formed between the individual layers 102 of the retained second material. Here, individual layers 103 of the third material are formed in these voids 108 between the retained individual layers 102 of the second material. This produces a vertical layer stack 100 in which the individual layers 102 of the second material and the individual layers 103 of the third material are arranged alternately above and below each other.

[0124] Introducing a third material into the voids 108 between the retained individual layers 102 of the second material can be done, for example, by means of an additive drying process, preferably from the gas phase. For instance, the third material can be introduced into the voids 108 by applying an LPCVD (low-pressure chemical vapor deposition) process. Here, process gas can be introduced into the process chamber (where the layer stack 100 is located). Specifically, via the vertical channel structure 112, the process gas reaches the voids 108 between the individual layers 102 of the second material and expands within the voids 108. The gas molecules of the process gas impact the individual layers 102 of the second material, having the effect of the third material (e.g., SiO2) growing in the voids 108 between the retained individual layers 102 of the second material (e.g., Si).

[0125] The third material may be different from the second material. Preferably, the third material may have electrical insulating properties. The third material may include, for example, silicon dioxide (SiO2) or may be composed of silicon dioxide.

[0126] Figure 3L Further optional process steps for producing a three-dimensional integrated semiconductor memory are illustrated. Here, at least one additional vertical channel structure 113 is structured into the layer stack 100. Figure 3L As exemplarily shown, the other vertical channel structure 130 can be created again between the support structures 105. Furthermore, another vertical channel structure 112 can be created by anodizing as described above.

[0127] The other vertical channel structure 130 also extends vertically from top to bottom through the stack 100, for example, between the first portion 210 (e.g., the bottom) and the second portion 220 (e.g., the top) of the stack 100. This other vertical channel structure 130 further extends through at least one of the individual layers 102, 103, preferably through several individual layers 102, 103, and more preferably through all the individual layers 102, 103 of the stack 100 down to the substrate 200. In this case, these are individual layers 102 of the second material and individual layers 103 of the third material.

[0128] Another vertical channel structure 113 forms a pathway to the corresponding individual layers 102, 103 of the stack 100, in this case to the individual layers 102 of the second material and 103 of the third material present in the stack 100. These individual layers 102 of the second material and 103 of the third material are respectively exposed within the other vertical channel structure 113 and can be accessed via the other vertical channel structure 113.

[0129] The other vertical channel structure 113 may also be referred to as a channel hole. Therefore, the method of the present invention further includes producing the other vertical channel structure 113 by applying an anodic etching method, wherein all the contents described above with respect to the first material layer 101 and the second material layer 102 are similarly applied to the second material layer 102 and the third material layer 103 in this step (e.g., producing the vertical channel structure 113).

[0130] Further optional method steps include selectively removing a single layer of one material that has become accessible relative to a single layer of the corresponding other material. In the present case, the method includes selectively removing a single layer 102 of the second material relative to a single layer 103 of the third material. This selective removal is performed by applying an etching process guided in the lateral direction through a suitable etch medium entering the layer stack 100 via another vertical channel structure 113. In this etching step, the etch medium can be an etching gas (dry etching) or a wet chemical etching solution (wet etching).

[0131] In the case of a dry etching process, the dry etching process may include at least one etching step supported by a plasma containing a fluorine gas. Dry etching can be performed, for example, as an isotropic CDE process (CDE: chemical dry etching) using a fluorine-containing gas, wherein, for example, silicon (as a possible material for individual layer 102) can be etched very selectively relative to SiO2 (as a possible material for individual layer 103). SF6 can be used as the etching gas, for example. In particular, plasma etching with very high SF6 flow rates, low O2 flow rates, and high process pressures allows for very selective etching between Si and SiO2, exhibiting the isotropic etching behavior desired by such etching.

[0132] Through another vertical channel structure 113, the etching medium (e.g., SF6 gas) reaches the individual layers 102, 103 of the second and third materials that are exposed and accessible within the other vertical channel structure 113. Here, the etching medium selectively removes the individual layer 102 of the second material in the lateral direction relative to the individual layer 103 of the third material, such that after the selective removal of the individual layer 102 of the second material, only the individual layer 103 of the third material remains. This means that the individual layer 102 of the second material is etched out from the layer stack 100.

[0133] Figure 3M A layer stack 100 is shown after the selective etching away of a separate layer 102 of the second material. Here, only a separate layer 103 of the third material is retained. At the same time, gaps 109 are formed between the retained separate layers 103 of the third material at the original locations where the removed separate layers 102 of the second material were. The retained separate layers 103 of the third material are supported by a support structure 105.

[0134] Figure 3NOptional further process steps are shown, at the end of which a three-dimensional integrated semiconductor memory 1000 is produced. A fourth material can be introduced, in particular, via another vertical channel structure 113 into the voids 109 formed between the individual layers 103 of the retained third material. Here, individual layers 104 of the fourth material are each formed within these voids 109 between the retained individual layers 103. This produces a vertical layer stack 100 in which the individual layers 103 of the third material and the individual layers 104 of the fourth material are stacked alternately on top of each other.

[0135] The fourth material may be different from the third material. Preferably, the fourth material may include at least one component selected from the group consisting of tungsten, cobalt, molybdenum, doped silicon, and ruthenium, or may be composed of at least one component selected from the group consisting of tungsten, cobalt, molybdenum, doped silicon, and ruthenium. The individual layer 104 of the fourth material may form the word lines of the now-produced three-dimensional integrated semiconductor memory 1000.

[0136] The three-dimensional integrated semiconductor 1000 may in particular be a 3D NAND flash memory. According to possible embodiments, the three-dimensional integrated semiconductor 1000 may therefore be, for example, a 3D NAND flash memory.

[0137] The gate NAND structure can be integrated into one of the support structures 105, or it can be generated by creating another vertical channel structure in the layer stack 100 and occupying the other vertical channel structure with a corresponding layer after the layer stack 100 is filled with a fourth material (e.g., tungsten).

[0138] The method of the invention described herein is particularly advantageous when the individual layer 101 of the first material comprises germanium (Ge) or silicon germanium (SiGe) or is composed of germanium (Ge) or silicon germanium (SiGe). Ge or SiGe can be etched very precisely by means of a dry etching method, particularly by the application of HCl gas, and furthermore, it has very high selectivity relative to, for example, silicon (as the material of the individual layer 102). Moreover, both silicon and silicon germanium are conductive, making these materials very suitable for producing vertical channel structures 112 (channel holes) by applying the anodic etching process described herein. In conventional techniques, individual layers of silicon oxide and silicon nitride are used. However, since silicon nitride is not conductive, the anodic etching method cannot be applied here.

[0139] A significant advantage of anodic etching is its very high anisotropy, meaning that the funnel-shaped necking known in conventional techniques no longer occurs. Figure 1F Thus, the vertical channel structure 112 can be generated through significantly more individual layers 101, 102, thereby significantly increasing the storage capacity of the layer stack 10.

[0140] Therefore, the basic idea of ​​the method described herein is to produce vertical channel structures 112 (e.g., holes or so-called channel holes) with extremely high aspect ratio and high uniformity by anodic etching.

[0141] Therefore, conductive / semiconductor materials are required. The layer sequence can consist, for example, of Si / SiGe layers 101, 102 grown as multilayer epitaxial layers (a sequence of hundreds of layers). This invention is not limited to crystalline layers, as the anodic etching method is also applicable to amorphous materials. For multilayer systems, both materials are semiconductive and selective etching through different etching behaviors is crucial. Etching selectivity is important for the subsequent production of flash memory cells.

[0142] As an alternative to Si–SiGe, different material systems with the following characteristics can be used: a stack of layers 100 with hundreds of different levels of A-BAB-... can be produced from two different materials A and B. The entire stack of layers 100 is conductive, allowing it to be oriented by anodic etching, thereby producing vertical channel structures 112 (channel holes). Materials A and B have different etching behaviors for different etching media, allowing material A to be selectively etched relative to material B for subsequent etching, and vice versa (process sequence: (1) producing a multilayer stack of materials A and B, (2) channel hole etching, (3) selective etching of A relative to B to produce memory cells).

[0143] By using anodic etching, a very high aspect ratio can be achieved. Furthermore, it is also possible to perform via etching in a layer system with many layers.

[0144] According to possible embodiments, during the application of the anodic etching method, a direct light source with a predetermined wavelength can be directed to the stack 100 to increase the charge carrier density in the stack 100, thereby supporting the directional anodic etching process.

[0145] The light source is a direct light source directed directly onto the layer stack 100. This light is provided in addition to spatial lighting that is otherwise present in a process room (e.g., a clean room). The light source may have a predetermined wavelength, for example, greater than the bandgap of the respective material of the individual layers 101, 102 of the layer stack 100.

[0146] Photons emitted by the light source can excite electrons in the corresponding individual layers 101 and 102. This increases the charge carrier density in the respective individual layers 101 and 102. Due to the increased charge carrier density, the anodic etching process can be optimized. This means, for example, that the anodic etching process can be accelerated, and / or the directional etching effect can be improved, i.e., the anisotropy of the anodic etching process can be increased.

[0147] If more layer stacks 100 are generated on the wafer, a light source can be directed onto the wafer to illuminate the layer stacks 100 located thereon.

[0148] The above embodiments are merely illustrative of the principles of the invention. It should be understood that modifications and variations to the arrangements and details described herein will be readily apparent to those skilled in the art. Therefore, the invention is intended to be limited only by the scope of the appended claims, and not by the specific details presented through the description and explanation of the embodiments herein.

[0149] Although some aspects have been described in the context of the apparatus, it is clear that these aspects also represent descriptions of the corresponding methods, such that blocks or devices of the apparatus also correspond to the corresponding method steps or features of the method steps. Similarly, aspects described in the context of method steps also represent descriptions of corresponding blocks, details, or features of the corresponding apparatus.

Claims

1. A method for generating a vertical channel structure (112) in a layer stack (100) during the production of a three-dimensional integrated semiconductor memory (1000), the method comprising: A substrate (200) is provided, comprising a stack (100) of several individual layers (101, 102) disposed on the substrate (200), wherein several individual layers (101) of a first material and several individual layers (102) of a different second material are deposited alternately on top of each other. The first material and the second material are each either conductive or semi-conductive. At least one vertical channel structure (112) is formed in the layer stack (100), wherein the vertical channel structure (112) extends at least partially through the layer stack (100) in the vertical direction, such that one or more of the individual layers (101, 102) are exposed within the vertical channel structure (111, 112) and can be accessed through the vertical channel structure (112). Its features The vertical channel structure (112) is structured in the layer stack (100) by applying an anodic etching method, wherein a first voltage potential (U1) is applied to a first portion (210) of the layer stack (100), and wherein different second voltage potentials (U2) are applied to different second portions (220) of the layer stack (100), wherein a current (260) flows vertically through the layer stack (100) between the first portion (210) and the second portion (220), which produces the vertical channel structure (112) in the layer stack (100) by directional anodic etching.

2. The method according to claim 1, The vertical channel structure (112) produced by the anodic etching method has an aspect ratio of more than 50:1 or more than 100:1 with respect to its length and width.

3. The method according to claim 1, The vertical channel structure (112) produced by the anodic etching method includes a diameter that deviates by less than 50% over the entire length of the vertical channel structure (112), thus remaining approximately constant.

4. The method according to claim 1, The vertical channel structure (112) extends in a straight line between the first portion (210) and the second portion (220) of the layer stack (100).

5. The method according to claim 1, The vertical recess (112) extends through several of the individual layers (101, 102) of the layer stack (100), or the vertical recess (112) extends through all the individual layers (101, 102) of the layer stack (100).

6. The method according to claim 1, The applied anodic etching method can produce multiple vertical channel structures (112) in a layer stack (100) having more than 100 individual layers (101, 102), more than 200 individual layers (101, 102), or more than 300 individual layers (101, 102).

7. The method according to claim 1, It also includes the step of selectively removing the individual layer (101) of the first material from the layer stack (100) by applying an etching process, while maintaining the individual layer (102) of the second material. The etching medium passes through the vertical channel structure (112) to reach the layer stack (100), and to the individual layer (101) of the first material and the individual layer (102) of the second material that are exposed and accessible within the vertical channel structure (112), and selectively releases the individual layer (101) of the first material from the layer stack (100).

8. The method according to claim 1, The individual layers (101) of the first material and the individual layers (102) of the second material include different etching behaviors for a particular etching medium, such that the first material has high etching selectivity relative to the second material.

9. The method according to claim 1, The individual layer (101) of the first material comprises or is composed of a first doped semiconductor material, and / or The individual layer (102) of the second material comprises or is composed of a second doped semiconductor material. The first doped semiconductor material and the second doped semiconductor material are different.

10. The method according to claim 9, The first doped semiconductor material includes different doping types or different doping degrees compared to the second doped semiconductor material.

11. The method according to claim 1, The individual layer (101) of the first material comprises or is composed of germanium or silicon-germanium, and / or The individual layer (102) of the second material comprises or is composed of silicon.

12. The method according to claim 1, The individual layer (101) of the first material and / or the individual layer (102) of the second material each comprise an amorphous structure.

13. The method according to claim 1, During the application of the anodic etching behavior, a direct light source with a predetermined wavelength is directed onto the layer stack (100) to increase the charge carrier density in the layer stack (100) and thereby support the directional anodic etching process.

14. A layer stack (100) for use in the production of a three-dimensional integrated semiconductor memory (1000), The layer stack (100) includes a plurality of vertical channel structures (112) produced by the method of claim 1.

15. A three-dimensional integrated semiconductor memory (1000) having a layer stack (100) according to claim 14.

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