Component, transistor device, power device, and method for manufacturing a component

Abstract

A structure includes a silicon-based substrate layer; a transition layer disposed above the silicon-based substrate layer; a gallium nitride (GaN) buffer layer disposed above the transition layer. The structure also includes a gallium oxide layer. The structure facilitates co-integration of ultra-wide bandgap technology with wide bandgap technology, such as by using the gallium oxide layer and the gallium nitride buffer layer on a low-cost silicon substrate, such as the silicon-based substrate layer. Thus, the structure provides a pathway to dispose the gallium nitride buffer layer (or gallium nitride) on the silicon-based substrate layer (or silicon production line), thereby improving thermal and electrical properties.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor devices, and more specifically, to components, transistor devices, power devices, and methods for manufacturing components. Background Technology

[0002] Semiconductor devices typically function based on the electronic properties of semiconductor materials such as silicon (Si) and germanium (Ge). These devices are fabricated as individual devices or integrated circuits (ICs), such as traditional silicon (Si)-based field-effect transistors (FETs). However, the overall performance of traditional Si-based FETs is degraded due to the narrow bandgap (or energy gap) and low electric field between the components of the traditional Si material. Traditionally, efforts have been made to find possible alternatives to traditional Si-based FETs by developing wide-bandgap (WBG) or ultra-wide-bandgap (UWBG) semiconductor materials. Examples of wide-bandgap (WBG) semiconductor materials include, but are not limited to, gallium nitride (GaN) with a bandgap of 3.4 electron volts (eV) and silicon carbide (SiC) with a bandgap of 3.3 eV. Similarly, examples of ultrawide bandgap (UWBG) semiconductor materials include, but are not limited to, gallium oxide (or gallium trioxide, Ga2O3) with a bandgap of 4.9 eV, diamond with a bandgap of 5.5 eV, and aluminum nitride (AlN) with a bandgap of 6.28 eV. Wide bandgap and ultrawide bandgap semiconductor materials offer superior material properties, such as larger bandgap and higher critical electric fields. Wide bandgap semiconductor materials have achieved partial performance improvements at the device and system levels; for example, semiconductor manufacturers have already used conventional enhancement-mode GaN and SiC power FETs in various products. Therefore, wide bandgap and ultrawide bandgap semiconductor materials promise significantly improved performance compared to conventional silicon-based FETs. Ultrawide bandgap semiconductor materials can provide various figures of merit (FOMs) for device performance, and these FOMs are non-linearly proportional to the bandgap.

[0003] Typically, high power is required for both power switching and individual application control in high-power electronic devices. For example, conventional wide-bandgap FETs based on wide-bandgap semiconductor materials can reduce power switching to a lower level, where heat dissipation and heat sinks are not hindered by system design, and overall losses and costs are reduced. Such semiconductor devices can achieve stronger doping at a given breakdown voltage, thereby reducing overall conductivity and power switching. Therefore, the power conversion efficiency of such semiconductor devices is improved. Traditionally, semiconductor devices can achieve stronger doping, for example, by using silicon carbide (or vertical silicon carbide) to achieve high breakdown voltage, or by using gallium nitride (GaN) to achieve low breakdown voltage. For conventional wide-bandgap technologies, the common method for mass production of semiconductor devices for various applications is to co-integrate GaN onto a low-cost silicon substrate. However, to achieve high-performance semiconductor devices, it is necessary to co-integrate ultra-wide-bandgap technologies (e.g., gallium oxide) with GaN onto a low-cost silicon substrate. Furthermore, using established GaN on silicon production lines allows for faster production of GaN-based devices. However, due to the low thermal conductivity associated with gallium oxide, it is difficult to co-integrate ultra-wide bandgap technologies (e.g., gallium oxide) with gallium nitride onto low-cost silicon substrates. Therefore, due to the low thermal conductivity of gallium oxide, there is a technical problem in co-integrating ultra-wide bandgap technologies (e.g., gallium oxide) with gallium nitride onto low-cost silicon substrates.

[0004] Therefore, in light of the above discussion, it is necessary to overcome the aforementioned drawbacks associated with traditional ultrawide bandwidth technology. Summary of the Invention

[0005] This invention provides components, transistor devices, power devices, and methods for manufacturing the components. The invention provides a solution to existing problems by co-integrating ultra-wide bandgap technology (e.g., gallium oxide) with silicon-based gallium nitride technology. The object of this invention is to provide a solution that at least partially addresses the problems encountered in the prior art, and to provide improved components, transistor devices, power devices, and improved methods for manufacturing the components to solve problems associated with conventional ultra-wide bandgap technology.

[0006] One or more objects of the present invention are achieved by means of the solutions provided in the appended independent claims. Advantageous embodiments of the invention are further defined in the dependent claims.

[0007] In one aspect, the present invention provides a component comprising: a silicon substrate layer; a transition layer disposed above the silicon substrate layer; a gallium nitride (GaN) buffer layer disposed above the transition layer; and the component further comprising a gallium oxide layer.

[0008] The components described in this invention imply different properties of the gallium oxide layer (e.g., ultra-wide bandgap) to achieve the benefits of higher electrical performance (e.g., breakdown voltage (BV), figure-of-merit (FOM)) in power semiconductor devices. Advantageously, the components described in this invention eliminate limitations associated with conventional ultra-wide bandgap technologies, such as the thermal limitations (e.g., low thermal conductivity) associated with the gallium oxide layer, which are achieved by transferring the active region of the conventional gallium oxide layer to a gallium nitride buffer layer (or suitable gallium nitride) and onto a silicon-based substrate (or silicon carbide (SiC) substrate). Furthermore, due to the improved thermal conductivity and electrical performance, the components can be used in power devices or optoelectronic devices.

[0009] In one implementation, the gallium oxide (Ga2O3) layer is deposited over the gallium nitride (GaN) buffer layer.

[0010] In this implementation, the gallium oxide layer is in direct contact with the gallium nitride buffer layer. Therefore, this structure eliminates the thermal limitations associated with conventional gallium oxide layers (or ultra-wide bandgap technologies).

[0011] In another implementation, the component further includes a passivation layer located between the gallium nitride (GaN) buffer layer and the gallium oxide (Ga2O3) layer, wherein the passivation layer comprises aluminum oxide, silicon dioxide, or silicon nitride.

[0012] The passivation layer prevents the gallium nitride (GaN) buffer layer from oxidizing.

[0013] In another implementation, the gallium oxide (Ga2O3) layer is deposited on the gallium nitride (GaN) buffer layer, which is located in an opening of the passivation layer.

[0014] In this implementation, the gallium oxide layer is selectively placed on a heterogeneous substrate, such as the gallium nitride (GaN) buffer layer and the silicon-based substrate layer.

[0015] In another implementation, the gallium oxide (Ga2O3) layer is deposited on top of the gallium nitride (GaN) buffer layer by depositing it on the passivation layer.

[0016] The passivation layer can enhance the adhesion of the gallium oxide layer and reduce the risk of potential delamination.

[0017] In another implementation, the gallium oxide (Ga2O3) layer is deposited in a region defined by photolithography removing at least a portion of the passivation layer, wherein the gallium oxide (Ga2O3) layer is deposited on the remaining portion of the passivation layer.

[0018] In this implementation, the gallium oxide layer is selectively placed on the passivation layer.

[0019] In another implementation, the gallium oxide (Ga2O3) layer is deposited on the silicon substrate through openings in the gallium nitride (GaN) buffer layer and the transition layer.

[0020] By using the opening, the gallium oxide layer is in direct contact with the silicon substrate layer.

[0021] In another implementation, the component further includes a passivation layer located on the silicon substrate layer.

[0022] Advantageously, the passivation layer provides electrical isolation, enhances the adhesion between the silicon substrate layer and the gallium oxide layer, and also reduces the risk of delamination.

[0023] In another implementation, the component further includes a p-doped gallium nitride (GaN) layer disposed between the gallium nitride (GaN) buffer layer and the gallium oxide (Ga2O3) layer.

[0024] The p-doped gallium nitride layer (or the p-type doping capability of gallium nitride technology) helps to eliminate the current limitation associated with doping in conventional gallium oxide layers.

[0025] In another implementation, the gallium oxide (Ga2O3) layer is an n-doped gallium oxide layer.

[0026] A PN junction can be formed between the p-doped gallium nitride layer and the n-doped gallium oxide layer by using the p-doped gallium nitride layer and the n-doped gallium oxide layer.

[0027] In another implementation, the gallium oxide (Ga2O3) layer includes an n-doped gallium oxide (Ga2O3) layer located on top of a semi-insulating gallium oxide (Ga2O3) layer.

[0028] By using the n-doped gallium oxide layer and the semi-insulating gallium oxide layer, the component of the present invention eliminates the current limitation associated with conventional gallium oxide layer materials in terms of doping capability.

[0029] In another aspect, the present invention provides a metal-semiconductor field-effect transistor (MESFET) device, the MESFET device comprising a component; the component further comprising: a source node layer, a gate node layer, and a drain node layer disposed above the n-doped gallium oxide (Ga2O3) layer; an ohmic contact layer formed between the n-doped gallium oxide (Ga2O3) layer and the source node layer, and an ohmic contact layer formed between the n-doped gallium oxide (Ga2O3) layer and the drain node layer.

[0030] The metal-semiconductor field-effect transistor (MESFET) device achieves all the advantages and technical effects of the components described in this invention.

[0031] In another aspect, the present invention provides a metal-oxide-semiconductor field-effect transistor (MESFET) device, the MESFET device comprising: a source node layer, a gate node layer, and a drain node layer disposed above the n-doped gallium oxide (Ga2O3) layer; an ohmic contact layer formed between the n-doped Ga2O3 layer and the source node layer, and an ohmic contact layer formed between the n-doped gallium oxide (Ga2O3) layer and the drain node layer; and a dielectric layer formed between the gate node layer, the source node layer, the n-doped gallium oxide (Ga2O3) layer, and the drain node layer.

[0032] The metal-oxide-semiconductor field-effect transistor (MOSFET) device achieves all the advantages and technical effects of the components described in this invention.

[0033] In another implementation, the present invention provides a component wherein the gallium oxide (Ga2O3) layer includes an n-(Si)-doped gallium oxide (Ga2O3) layer on top of an n+(Sn)-doped gallium oxide (Ga2O3) layer; an anode layer is formed above the n-(Si)-doped gallium oxide (Ga2O3) layer; and a cathode layer is formed below the gallium oxide (Ga2O3) layer, thereby forming a Schottky diode device.

[0034] The Schottky diode device described herein achieves all the advantages and technical effects of the components described in this invention.

[0035] In another aspect, the present invention provides a component wherein the gallium oxide (Ga2O3) layer is used to partially cover the p-doped gallium nitride (GaN) layer to form an exposed region of the p-doped gallium nitride (GaN) layer; the component further includes: a cathode formed on the gallium oxide (Ga2O3) layer; and one or more anodes formed on the p-doped gallium nitride (GaN) layer.

[0036] The component facilitates the formation of a blind ultraviolet photodetector, thereby achieving all the advantages and technical effects of the component described in this invention.

[0037] In another aspect, the present invention provides a power device including the aforementioned component.

[0038] The power device described herein achieves all the advantages and technical effects of the components described in this invention. Furthermore, the disclosed power device can perform high-speed switching with lower power consumption.

[0039] In another aspect, the present invention provides an optoelectronic device including the aforementioned component.

[0040] The aforementioned optoelectronic device achieves all the advantages and technical effects of the components described in this invention. Furthermore, the disclosed optoelectronic device improves optical communication.

[0041] In another aspect, the present invention provides a method for manufacturing a component, wherein the method includes transferring the gallium oxide (Ga2O3) layer to the component.

[0042] The method achieves all the advantages and technical effects of the components described in this invention.

[0043] It should be understood that all of the above implementation methods can be combined.

[0044] It should be noted that all devices, elements, circuits, units, and modules described in this application can be implemented by software or hardware elements or any combination thereof. All steps performed by the various entities described in this application, and the functions described as being performed by the various entities, are intended to indicate that the respective entities are suitable for or used to perform the respective steps and functions. Although in the following detailed description of specific embodiments, a particular function or step performed by an external entity is not reflected in the detailed description of the specific element of the entity performing that particular step or function, it should be apparent to those skilled in the art that these methods and functions can be implemented in the corresponding hardware or software elements or any combination thereof. It should be understood that various combinations of the features of the invention can be made without departing from the scope of the invention as defined in the appended claims.

[0045] Additional aspects, advantages, features and objects of the invention will become apparent from the accompanying drawings and the detailed description of illustrative implementations as explained in conjunction with the following appended claims. Attached Figure Description

[0046] A better understanding of the above overview and the following detailed description of illustrative embodiments can be obtained by reading the accompanying drawings. Exemplary structures of the invention are shown in the drawings to illustrate the invention. However, the invention is not limited to the specific methods and tools disclosed herein. Furthermore, those skilled in the art will understand that the drawings are not drawn to scale. Where possible, the same elements are represented by the same numbers.

[0047] Embodiments of the invention will now be described by way of example only with reference to the following accompanying drawings, in which:

[0048] Figures 1A to 1G These are different schematic diagrams of the components provided in various examples of the present invention;

[0049] Figure 2 This is a flowchart illustrating a method for manufacturing a component, as provided in an example of the present invention;

[0050] Figure 3 This is a schematic diagram of a metal-semiconductor field-effect transistor (MESFET) device provided as an example of the present invention.

[0051] Figures 4A to 4C These are different schematic diagrams of metal-oxide-semiconductor field-effect transistor (MOSFET) devices provided in various examples of the present invention;

[0052] Figures 5A to 5B These are different schematic diagrams of Schottky diode devices provided in various examples of the present invention;

[0053] Figure 6 This is a schematic diagram of a blind ultraviolet (UV) photodetector provided as an example of the present invention;

[0054] Figure 7 This is a block diagram of a power device provided as an example of the present invention;

[0055] Figure 8 This is a block diagram of an optoelectronic device provided as an example of the present invention.

[0056] In the accompanying diagram, underlined numbers indicate the item to which the underlined number is located or the item adjacent to the underlined number. Ununderlined numbers refer to the items identified by the line connecting the ununderlined number to the item. When a number is ununderlined and has an associated arrow, the ununderlined number identifies the general item that the arrow points to. Detailed Implementation

[0057] The following detailed description illustrates embodiments of the present invention and ways in which these embodiments can be implemented. Although some modes of implementing the invention have been disclosed, those skilled in the art will recognize that other embodiments for implementing or carrying out the invention may also exist.

[0058] Figure 1A This is a schematic diagram of a component provided in one embodiment of the present invention. (See reference) Figure 1A The diagram shows a schematic of component 100A, which includes a silicon substrate layer 102, a transition layer 104, a gallium nitride (GaN) buffer layer 106, and a gallium oxide (Ga2O3) layer 108.

[0059] This invention provides a component 100A, comprising:

[0060] Silicon substrate layer 102;

[0061] A transition layer 104 is disposed above the silicon substrate layer 102;

[0062] A gallium nitride (GaN) buffer layer 106 is disposed above the transition layer 104; the component 100A also includes a gallium oxide (Ga2O3) layer 108.

[0063] The component 100A is a semiconductor structure comprising one or more layers of semiconductor material. In one example, one layer of semiconductor material may be the same as (or different from) another layer of semiconductor material. The component 100A may also include material layers or structures other than semiconductor materials. Furthermore, the component 100A may constitute a semiconductor device or be contained within a semiconductor device. The component 100A of the present invention signifies the co-integration of ultrawide-bandgap (UWBG) technology and wide-bandgap technology, for example, co-integrating the gallium oxide (Ga2O3) layer 108 with the gallium nitride buffer layer 106, the gallium nitride buffer layer 106 being located on a low-cost silicon substrate such as the silicon substrate layer 102.

[0064] The silicon substrate 102 is a thin layer of semiconductor material, also known as a single wafer or chip. The silicon substrate 102 serves as the base for the component 100A. Due to its ample availability, the silicon substrate 102 is a low-cost material. The silicon substrate 102 has different sizes, such as six inches (6”), eight inches (8”), and twelve inches (12”).

[0065] The transition layer 104 is a material layer used to fully relieve stress and limit or prevent the formation of cracks in the gallium nitride buffer layer 106.

[0066] The gallium nitride buffer layer 106 is a gallium nitride semiconductor material layer, and the gallium nitride semiconductor material is a wide-bandgap (WBG) semiconductor material. The bandgap value of the gallium nitride buffer layer 106 is 3.4 electron volts (eV).

[0067] The gallium oxide (Ga2O3) layer 108 is a gallium oxide semiconductor material layer, and the gallium oxide semiconductor material is an ultra-wide bandgap (UWBG) semiconductor material. The bandgap value of the gallium oxide layer 108 is 4.9 eV.

[0068] In other words, the silicon substrate layer 102 of the component 100A serves as the substrate of the component 100A. Furthermore, the transition layer 104 is deposited over the silicon substrate layer 102. The component 100A also includes the gallium nitride buffer layer 106, which is disposed on the transition layer 104. In other words, the gallium nitride buffer layer 106 is disposed on the silicon substrate layer 102 to form a silicon-based gallium nitride substrate, such as... Figure 1AAs shown. Advantageously, the transition layer 104 can adequately relieve stress and also limits or prevents the formation of cracks in the gallium nitride buffer layer 106. Therefore, the component 100A utilizes the existing gallium nitride (SiC or Si) technology infrastructure, such as the gallium nitride buffer layer 106 located on a low-cost silicon substrate such as the silicon-based substrate layer 102. Advantageously, the component 100A utilizes higher gallium nitride (SiC or Si) processing capabilities, for example, by using the gallium nitride buffer layer 106 in the mass production of complementary metal-oxide-semiconductor (CMOS) lines (e.g., 6”, 8”, and 12”). The component 100A also includes the gallium oxide layer 108. Therefore, the component 100A utilizes the properties of the gallium oxide layer 108 (i.e., an ultra-wide bandgap semiconductor material) to improve the electrical performance of power semiconductor devices, such as breakdown voltage (BV) and figure-of-merit (FOM). Advantageously, the component 100A improves thermal conductivity by transferring the active region of the gallium oxide layer 108 into the gallium nitride buffer layer 106 (or suitable gallium nitride) and onto the silicon-based substrate layer 102 (or silicon carbide (SiC) substrate).

[0069] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is deposited on top of the gallium nitride (GaN) buffer layer 106. In one example, the thickness of the gallium oxide layer 108 is between the nanometer (nm) and micrometer (μm) scales. Furthermore, the gallium oxide layer 108 is in direct contact with the gallium nitride buffer layer 106.

[0070] Therefore, the component 100A utilizes the different properties of the gallium oxide layer 108 (e.g., ultra-wide bandgap) to enable power semiconductor devices to achieve higher electrical performance (e.g., breakdown voltage (BV), figure-of-merit (FOM)). Advantageously, the component 100A eliminates the limitations associated with conventional ultra-wide bandgap technologies. For example, the component 100A improves thermal conductivity by transferring the active region of the gallium oxide layer 108 into the gallium nitride buffer layer 106 (or suitable gallium nitride) and onto the silicon substrate layer 102 (or silicon carbide (SiC) substrate). Furthermore, due to the improved thermal conductivity, the component 100A is advantageous for use in power devices or optoelectronic devices.

[0071] Figure 1B This is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A element pairs in Figure 1B Provide a description. (See reference.) Figure 1B The diagram shows a schematic of component 100B, which includes a passivation layer 110, a gallium nitride (GaN) buffer layer 106, and a gallium oxide (Ga2O3) layer 108.

[0072] The passivation layer 110 is used to prevent the gallium nitride (GaN) buffer layer 106 from oxidation. Examples of the passivation layer 110 include, but are not limited to, silicon dioxide (SiO2) layers, silicon nitride (SiN) layers, or aluminum oxide (Al2O3) layers.

[0073] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is deposited on the gallium nitride (GaN) buffer layer 106, the gallium nitride (GaN) buffer layer 106 being located in an opening of the passivation layer 110. In one example, the passivation layer 110 is initially deposited on top of the gallium nitride buffer layer 106. Subsequently, the passivation layer 110 is removed at several points (or locations) by photolithography, photolithography, or electron beam lithography, thereby defining the opening in the passivation layer 110. Thus, the gallium nitride buffer layer 106 is exposed through the opening, as... Figure 1B As shown. Subsequently, the gallium oxide layer 108 is deposited in the opening and above the gallium nitride buffer layer 106. Therefore, the gallium oxide layer 108 is selectively placed on the heterogeneous substrate, such as the gallium nitride (GaN) buffer layer 106 and the silicon substrate layer 102.

[0074] Figure 1C This is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A and Figure 1B element pairs in Figure 1C Provide a description. (See reference.) Figure 1C The diagram shows a schematic of component 100C, which includes the silicon substrate layer 102, the transition layer 104, the gallium nitride buffer layer 106, the gallium oxide layer 108, and the passivation layer 110.

[0075] According to one embodiment, the component 100C includes a passivation layer 110 located between the gallium nitride (GaN) buffer layer 106 and the gallium oxide (Ga2O3) layer 108, wherein the passivation layer 110 comprises aluminum oxide, silicon dioxide, or silicon nitride, etc. Those skilled in the art will understand that other materials with properties similar to aluminum oxide, silicon dioxide, or silicon nitride can be used without limiting the scope of the invention. In the component 100C, the passivation layer 110 is deposited over the gallium nitride buffer layer 106. Subsequently, the gallium oxide layer 108 is deposited over the passivation layer 110. Advantageously, the passivation layer 110 prevents oxidation of the gallium nitride buffer layer 106. Examples of the passivation layer 110 include, but are not limited to, silicon dioxide (SiO2) layers, silicon nitride (SiN) layers, or aluminum oxide (Al2O3) layers. In one example, the passivation layer 110 is deposited by one of the known possible passivation methods, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVP), atomic layer deposition (ALD) passivation, etc.

[0076] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is deposited on top of the gallium nitride (GaN) buffer layer 106 by deposition on the passivation layer 110. In the component 100C, the passivation layer 110 is deposited on the gallium nitride buffer layer 106, forming passivated gallium nitride. Subsequently, the gallium oxide layer 108 is deposited on top of the passivation layer 110, as... Figure 1C As shown. In the component 100C, a sheet of gallium oxide layer 108 (e.g., having a specific area and thickness) is deposited on the passivated gallium nitride (or aluminum gallium nitride (AlGaN)) layer. Advantageously, the passivation layer 110 can enhance the adhesion of the gallium oxide layer 108 and reduce the potential risk of delamination.

[0077] Figure 1D This is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B and Figure 1C element pairs in Figure 1D Provide a description. (See reference.) Figure 1D The diagram shows a schematic of component 100D, which includes the gallium nitride buffer layer 106, the gallium oxide layer 108, and the passivation layer 110.

[0078] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is deposited in a region defined by photolithography to remove at least a portion of the passivation layer 110, wherein the gallium oxide (Ga2O3) layer 108 is deposited on the remaining portion of the passivation layer 110. In other words, the passivation layer 110 is initially deposited over the gallium nitride buffer layer 106. Subsequently, photolithography is used to define one (or more) regions in which the passivation layer 110 serves as the underlayer for depositing the gallium oxide layer 108. In other words, photolithography is used to remove at least a portion of the passivation layer 110 from over the gallium nitride buffer layer 106, such as... Figure 1D As shown. Subsequently, the gallium oxide layer 108 is deposited on the remaining portion of the passivation layer 110 (e.g., the over-defined passivation region). Advantageously, the component 100D enables selective placement of the gallium oxide layer 108 on the passivation layer 110.

[0079] Figure 1E This is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C and Figure 1D element pairs in Figure 1E Provide a description. (See reference.) Figure 1E The diagram shows a schematic of component 100E, which includes the silicon substrate layer 102, the transition layer 104, the gallium nitride buffer layer 106, and the gallium oxide layer 108.

[0080] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is deposited on the silicon substrate 102 through openings in the gallium nitride (GaN) buffer layer 106 and the transition layer 104. In other words, the transition layer 104 is deposited on the silicon substrate 102, and the gallium nitride buffer layer 106 is deposited on the transition layer 104. Thereafter, openings (or trenches) are formed in the gallium nitride buffer layer 106 and the transition layer 104 (e.g., by photolithography) to expose the underlying silicon substrate 102. Furthermore, the gallium oxide layer 108 is deposited in the openings, such as... Figure 1E As shown. In other words, the gallium oxide layer 108 is deposited on the silicon substrate layer 102 (or the exposed silicon substrate). Therefore, the gallium oxide layer 108 is in direct contact with the silicon substrate layer 102. In one implementation, the silicon substrate layer 102 is p-type doped before the gallium oxide layer 108 is deposited. In another implementation, the silicon substrate layer 102 is n-type doped before the gallium oxide layer 108 is deposited.

[0081] Figure 1FThis is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E element pairs in Figure 1F Provide a description. (See reference.) Figure 1F The diagram shows a schematic of component 100F, which includes the silicon substrate layer 102, the transition layer 104, the gallium nitride buffer layer 106, the gallium oxide layer 108, and the passivation layer 110.

[0082] According to one embodiment, the component 100F further includes a passivation layer (i.e., the passivation layer 110) located on the silicon substrate layer 102. In one example, the transition layer 104 is deposited on the silicon substrate layer 102, and the gallium nitride buffer layer 106 is deposited on the transition layer 104. Thereafter, openings (or trenches) are formed in the gallium nitride buffer layer 106 and the transition layer 104 (e.g., by a photolithography step) to expose the underlying silicon substrate layer 102. Subsequently, the passivation layer 110 is deposited in the opening on one side (e.g., the vertical side) of the gallium nitride buffer layer 106 and in the opening on one side (e.g., the horizontal side) of the transition layer 104, as shown. Figure 1F As shown. Furthermore, the gallium oxide layer 108 is deposited on the passivation layer 110. Therefore, the passivation layer 110 is inserted between the silicon substrate layer 102 (or the exposed silicon substrate) and the gallium oxide layer 108. Advantageously, the passivation layer 110 provides electrical isolation, enhances the adhesion between the silicon substrate layer 102 and the gallium oxide layer 108, and also reduces the risk of delamination. Additionally, the gallium oxide layer 108 can be deposited on the component 100B (… Figure 1B ) and the component 100D ( Figure 1D The gallium oxide layer 108 is deposited on the passivation layer 110 in a similar manner to that obtained in the previous step.

[0083] Figure 1G This is a schematic diagram of a component provided in another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F element pairs in Figure 1G Provide a description. (See reference.) Figure 1GThe diagram shows a schematic of component 100G, which includes a p-doped gallium nitride (GaN) layer 112, an n-doped gallium oxide (Ga2O3) layer 114, a silicon substrate layer 102, a transition layer 104, a gallium nitride buffer layer 106, and a gallium oxide layer 108. The p-doped gallium nitride layer 112 corresponds to p-type doped gallium nitride, and the n-doped gallium oxide layer 114 corresponds to n-type doped gallium oxide layer 108.

[0084] According to one embodiment, the component 100G includes the p-doped gallium nitride (GaN) layer 112 disposed between the gallium nitride (GaN) buffer layer 106 and the gallium oxide (Ga2O3) layer 108. In one example, the gallium nitride buffer layer 106 is deposited on the transition layer 104, and the gallium nitride buffer layer 106 is further covered by the p-doped gallium nitride layer 112. Subsequently, the gallium oxide layer 108 is deposited directly on the p-doped gallium nitride layer 112. In one example, the gallium oxide layer 108 is deposited on a selective portion of the p-doped gallium nitride layer 112. Advantageously, the component 100G utilizes the p-doped gallium nitride layer 112 (or the p-type doping capability of gallium nitride technology).

[0085] According to one embodiment, the component 100G is characterized in that the gallium oxide (Ga2O3) layer 108 is an n-doped gallium oxide layer. Because the gallium oxide layer 108 is an n-doped gallium oxide layer, for example... Figure 1G The n-doped gallium oxide layer 114 shown is such that a PN junction is formed between the n-doped gallium oxide layer 114 and the p-doped gallium nitride layer 112 (or gallium nitride material). By using the n-doped gallium oxide layer 114, the component 100G eliminates the limitations associated with conventional gallium oxide layer materials in terms of doping capability. In one implementation, the gallium oxide layer 108 includes the n-doped gallium oxide layer 114, which may be disposed on top of a semi-insulating gallium oxide layer, for example, see [details omitted]. Figure 3 .

[0086] Figure 2 This is a flowchart of a method for manufacturing a component according to an embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 2 Provide a description. (See reference.) Figure 2 The method 200 is shown, which includes steps 202 and 204.

[0087] Method 200 is used to manufacture a component (e.g., component 100A), wherein method 200 includes transferring the gallium oxide (Ga2O3) layer (i.e., the gallium oxide layer 108) to the component (e.g., component 100A). Method 200 implies the co-integration of ultrawide-bandgap (UWBG) technology and bandgap technology to improve the thermal conductivity and p-type doping capability of UWBG technology. In other words, method 200 co-integrates the gallium oxide (Ga2O3) layer 108 and the gallium nitride buffer layer 106 on a low-cost silicon substrate such as the silicon substrate layer 102 of component 100A. Method 200 is applicable to all components 100A, 100B, 100C, 100D, 100E, 100F, and 100G.

[0088] In step 202, method 200 includes transferring the gallium oxide (Ga2O3) layer (i.e., the gallium oxide layer 108) to the component (e.g., component 100A). For example, component 100A includes the silicon substrate layer 102, which serves as the substrate of component 100A. Subsequently, a transition layer 104 is deposited on the silicon substrate layer 102, and then a gallium nitride buffer layer 106 is deposited on the transition layer 104. Therefore, component 100A includes the silicon substrate layer 102, the transition layer 104, and the gallium nitride buffer layer 106, for example, forming a silicon-based gallium nitride substrate. Furthermore, method 200 includes transferring the gallium oxide (Ga2O3) layer 108 to component 100A. This means that the gallium oxide layer 108 is deposited on the gallium nitride buffer layer 106. In this way, method 200 co-integrates the gallium oxide (Ga2O3) layer 108 with the gallium nitride buffer layer 106 on a low-cost silicon substrate. Therefore, method 200 enables power semiconductor devices to achieve higher electrical performance (BV, FOM). Advantageously, method 200 eliminates the limitations associated with conventional ultra-wide bandgap technologies. For example, method 200 improves thermal conductivity by transferring the active region of the gallium oxide layer 108 into the gallium nitride buffer layer 106 (or suitable gallium nitride) and onto the silicon substrate layer 102 (or silicon carbide (SiC) substrate), thus eliminating the thermal limitations associated with conventional gallium oxide.

[0089] In step 204, method 200 further includes transferring the gallium oxide (Ga2O3) layer 108 to the component 100A. In one example, the gallium oxide (Ga2O3) layer 108 can be transferred to the component 100A using transfer techniques, such as smart dicing or other known techniques for transferring fine layers of crystalline material onto a mechanical support. In other words, method 200 includes transferring an ultrafine layer of the gallium oxide layer 108 to the component 100A, or depositing the gallium oxide layer 108 onto the gallium nitride buffer layer 106 of the component 100A. Typically, smart dicing is a process capable of transferring ultrafine layers of crystalline silicon material onto a mechanical support. In one implementation, smart dicing is primarily used in the production of silicon-on-insulator (SOI) wafer substrates.

[0090] According to one embodiment, method 200 further includes transferring the gallium oxide (Ga2O3) layer 108 to the component 100A using a large-area lift-off technique. In other words, method 200 includes utilizing a large-area lift-off technique. In one example, the large-area lift-off technique enables the release layer (or sheet) to be cleaved or mechanically peeled off, such as the release layer of the gallium oxide layer 108. The release layer of the gallium oxide layer 108 can then be transferred to any substrate, such as the component 100A.

[0091] According to one embodiment, method 200 further includes transferring the gallium oxide (Ga2O3) layer 108 to the component 100A using an electrochemical etching technique. In other words, method 200 includes utilizing an electrochemical or photo-electrochemical (PEC) etching technique, which facilitates the reaction through radiation light with electrical energy above the band gap and an applied external bias voltage. Therefore, electrochemical etching can also be used as a starting step in method 200 for transferring the gallium oxide layer 108 to the component 100A. Advantageously, electrochemical etching is very promising in terms of high selectivity and reduction of introduced new defects.

[0092] Therefore, method 200 includes utilizing the different properties of the gallium oxide layer 108 (e.g., ultra-wide bandgap) to enable power semiconductor devices to achieve higher electrical performance (e.g., breakdown voltage (BV), figure-of-merit (FOM)). Advantageously, method 200 eliminates the limitations associated with conventional ultra-wide bandgap technologies. For example, method 200 eliminates the thermal limitations (e.g., low thermal conductivity) associated with conventional gallium oxide by transferring the active region of the gallium oxide layer 108 on the component 100A (e.g., the gallium nitride buffer layer 106 and the silicon substrate layer 102) and improves thermal conductivity.

[0093] Steps 202 to 204 are merely illustrative, and other alternatives may be provided, in which one or more steps are added, one or more steps are deleted, or one or more steps are provided in a different order, without departing from the scope of the claims herein.

[0094] Figure 3 This is a schematic diagram of a metal-semiconductor field-effect transistor (MESFET) device provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 3 Provide a description. (See reference.) Figure 3 The diagram illustrates a metal-semiconductor field-effect transistor (MESFET) device 300, which includes a semi-insulating gallium oxide (Ga2O3) layer 302, a source node layer 304, a gate node layer 306, a drain node layer 308, and ohmic contact layers 310A and 310B. The MESFET also includes component 100A, which comprises the silicon substrate layer 102, the transition layer 104, the gallium nitride buffer layer 106, the passivation layer 110, and the n-doped gallium oxide layer 114.

[0095] The MESFET device 300 is a semiconductor device typically used to amplify or switch electronic signals. The MESFET device 300 is one of the fundamental components of modern electronic devices. The MESFET device 300 is composed of semiconductor materials having at least three layers (or terminals), such as the source node layer 304, the gate node layer 306, and the drain node layer 308.

[0096] The semi-insulating gallium oxide layer 302 can also be referred to as a semi-insulating substrate. In one example, the gallium oxide layer 108 includes the semi-insulating gallium oxide layer 302 to block subthreshold current. Examples of materials used for the semi-insulating gallium oxide layer 302 include, but are not limited to, magnesium (Mg), iron (Fe), carbon (C), etc.

[0097] The source node layer 304, the gate node layer 306, and the drain node layer 308 correspond to the source terminal, gate terminal, and drain terminal of the MESFET device 300. The source node layer 304, gate node layer 306, and drain node layer 308 are used for connection purposes (e.g., connecting the MESFET device 300 to a power source). Examples of metals used to configure the source node layer 304, gate node layer 306, and drain node layer 308 include, but are not limited to, titanium / gold (Ti / Au). In one example, platinum (Pt) metal may be used to configure the gate node layer 306 above the n-doped gallium oxide layer 114.

[0098] The ohmic contact layers 310A and 310B are used for current flow (and further electrical connections). Examples of materials used to form the ohmic contact layers 310A and 310B include, but are not limited to, titanium / gold (Ti / Au), titanium (Ti), indium (In), silver (Ag), tin (Sn), tungsten (W), molybdenum (Mo), scandium (Sc), zinc (Zn), and zirconium (Zr).

[0099] According to one embodiment, the gallium oxide (Ga2O3) layer 108 includes an n-doped gallium oxide (Ga2O3) layer 114, which is located on top of the semi-insulating gallium oxide (Ga2O3) layer 302. The MESFET device 300 is based on the component 100A, which includes: a transition layer 104, for example, the transition layer 104 deposited on the silicon substrate layer 102; and a gallium nitride buffer layer 106 deposited on the transition layer 104. Furthermore, the gallium oxide layer 108 is deposited on the gallium nitride buffer layer 106, and the gallium oxide layer 108 also includes the semi-insulating gallium oxide layer 302 and the n-doped gallium oxide layer 114. The semi-insulating gallium oxide layer 302 is deposited on the gallium nitride buffer layer 106, and the n-doped gallium oxide layer 114 is deposited on the semi-insulating gallium oxide layer 302, such as... Figure 3 As shown. Optionally, component 100A of the MESFET device 300 may include the passivation layer 110, which is deposited on the gallium nitride buffer layer 106. In this case, the semi-insulating gallium oxide layer 302 may be deposited on the passivation layer 110. Advantageously, the gallium oxide layer 108 includes the semi-insulating gallium oxide layer 302 (or a semi-insulating substrate) to block subthreshold current. However, the MESFET device 300 may be fabricated according to one of components 100B, 100C, and 100D.

[0100] The metal-semiconductor field-effect transistor (MESFET) device 300 includes a component 100A; the component 100A further includes a source node layer 304, a gate node layer 306, and a drain node layer 308, disposed above the n-doped gallium oxide (Ga2O3) layer 114; an ohmic contact layer 310A is formed between the n-doped gallium oxide (Ga2O3) layer 114 and the source node layer 304, and an ohmic contact layer 310B is formed between the n-doped gallium oxide (Ga2O3) layer 114 and the drain node layer 308. In other words, the MESFET device 300 includes the component 100A, and the component 100A further includes two ohmic contact layers formed on the n-doped gallium oxide layer 114 (e.g., on both sides) for current flow. Subsequently, the source node layer 304, the gate node layer 306, and the drain node layer 308 are directly disposed above the n-doped gallium oxide layer 114. Therefore, the ohmic contact layer 310A is disposed between the n-doped gallium oxide layer 114 and the source node layer 304, and the ohmic contact layer 310B is disposed between the n-doped gallium oxide layer 114 and the drain node layer 308. Therefore, the MESFET device 300 is advantageous for co-integrating the n-doped gallium oxide layer 114 and the semi-insulating gallium oxide layer 302 (or ultra-wide bandgap technology) with the gallium nitride buffer layer 106 and the silicon substrate layer 102 (or silicon-based gallium nitride technology). Furthermore, the MESFET device 300 is advantageous for use in high-power electronic devices. Since the conduction process (i.e., current) primarily involves only one type of charge carrier (i.e., electron or hole), the MESFET device 300 is a unipolar device. Therefore, compared with bipolar transistors, the MESFET device 300 has a higher switching speed and operating frequency.

[0101] According to one embodiment, a metal-semiconductor field-effect transistor (MESFET) device 300 includes a diode; the component 100A further includes a second gallium oxide (Ga2O3) layer, the second gallium oxide (Ga2O3) layer having a p-doped gallium nitride (GaN) layer 112 disposed below the second Ga2O3 layer, wherein the second gallium oxide (Ga2O3) layer is connected to the drain node layer 308 via a contact bridge. In one implementation, the MESFET device 300 may include the diode, and for this device, the component 100A includes the p-doped gallium nitride layer 112 disposed on the gallium nitride buffer layer 106. The component 100A further includes the second gallium oxide layer (e.g., Figure 4B As shown, the second gallium oxide layer is disposed on the p-doped gallium nitride layer 112. The connection between the second gallium oxide layer and the p-doped gallium nitride layer 112 enables the formation of the diode in the MESFET device 300. Furthermore, the component 100A uses the contact bridge to connect the second gallium oxide layer to the drain node layer 308 of the component 100A. Therefore, the component 100A facilitates the fabrication of a power transistor with an integrated diode (i.e., the MESFET device 300). In one implementation, the second gallium oxide layer is connected to the drain node layer 308 via a via (i.e., connecting two contacts), the via which can be formed on the drain node layer 308 (or the upper metallization layer) to form a common contact.

[0102] According to one embodiment, a metal-semiconductor field-effect transistor (MESFET) device 300 includes a diode; wherein, the component 100A further includes the p-doped gallium nitride (GaN) layer 112, the p-doped gallium nitride (GaN) layer 112 being disposed above the gallium nitride (GaN) buffer layer 106; wherein, the p-doped gallium nitride (GaN) layer 112 is connected to the source node layer 304 via an ohmic contact layer through a bridge, and the gallium nitride buffer layer 106 is connected to the drain node layer 308 via an ohmic contact layer through a second bridge. In other words, the MESFET device 300 includes the diode and the component 100A. The component 100A further includes the p-doped gallium nitride layer 112, the p-doped gallium nitride layer 112 being disposed on the gallium nitride buffer layer 106. In one example, the ohmic contact layer ( Figure 3 Not shown in the image, but... Figure 4C(as shown in the diagram) is formed on the p-doped gallium nitride layer 112, and another ohmic contact layer ( Figure 3 (Not shown) is formed on the gallium nitride buffer layer 106. The ohmic contact layer formed on the p-doped gallium nitride layer 112 is also connected via the contact bridge ( Figure 3 (Not shown) The p-doped gallium nitride (GaN) layer 112 is connected to the source node layer 304 of the component 100A. Alternatively, the contact bridge and the ohmic contact layer connect the p-doped gallium nitride (GaN) layer 112 to the source node layer 304 of the component 100A. Furthermore, the ohmic contact layer (formed on the gallium nitride buffer layer 106) Figure 3 (not shown in the image) also via the second contact bridge ( Figure 3 (Not shown) The gallium nitride buffer layer 106 is connected to the drain node layer 308 of the component 100A. Alternatively, the second bridge and the ohmic contact layer connect the gallium nitride buffer layer 106 to the drain node layer 308 of the component 100A. Therefore, the component 100A is advantageous for fabricating a power transistor with an integrated diode to fabricate the MESFET device 300 with a diode disposed between the gallium nitride buffer layer 106 and the ohmic contact layer.

[0103] According to one embodiment, the component 100A further has the following feature: the gallium nitride (GaN) buffer layer 106 includes an aluminum gallium nitride (AlGaN) layer, which is located on top of the unintentionally doped (UID) gallium nitride (GaN) layer. In the MESFET device 300, the gallium nitride buffer layer 106 of the component 100A includes the aluminum gallium nitride (AlGaN) layer, which is located on top of the unintentionally doped (UID) gallium nitride (GaN) layer. In other words, the unintentionally doped gallium nitride layer (of the gallium nitride buffer layer 106) is deposited directly on the silicon substrate layer 102, and the aluminum gallium nitride layer (of the gallium nitride buffer layer 106) is deposited on the unintentionally doped gallium nitride layer. Advantageously, the aluminum gallium nitride layer of the gallium nitride buffer layer 106 improves the electrical connection with the drain node layer 308 of the MESFET device 300. In one implementation, a two-dimensional electron gas is formed at the interface between the aluminum gallium nitride (AlGaN) layer and the underlying unintentionally doped gallium nitride layer. Furthermore, the diode of the MESFET device 300 is formed between the p-doped gallium nitride layer 112 and the two-dimensional electron gas.

[0104] According to one embodiment, at least one of the ohmic contact layers comprises titanium and / or gold. Since the ohmic contact layer is used for current flow and further electrical connection, the electrical connection is improved by utilizing metals such as titanium and / or gold through the use of the ohmic contact layer of the component 100A (e.g., ohmic contact layers 310A and 310B).

[0105] Figure 4A This is a schematic diagram of a metal-oxide-semiconductor field-effect transistor (MOSFET) device provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 3 element pairs in Figure 4A Provide a description. (See reference.) Figure 4A The diagram shows a schematic of a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400A, which includes a dielectric layer 402, a silicon substrate layer 102, a transition layer 104, a gallium nitride buffer layer 106, a passivation layer 110, an n-doped gallium oxide layer 114, a semi-insulating gallium oxide (Ga2O3) layer 302, a source node layer 304, a gate node layer 306, a drain node layer 308, and ohmic contact layers 310A and 310B.

[0106] The MOSFET device 400A is a semiconductor device typically used to amplify or switch electronic signals. The MOSFET device 400A is one of the fundamental components of modern electronic devices. The MOSFET device 400A is composed of semiconductor materials with different layers (or terminals), such as the source node layer 304, the gate node layer 306, the drain node layer 308, and the dielectric layer 402.

[0107] The dielectric layer 402 may also be referred to as the gate dielectric layer. Examples of materials used to form the dielectric layer 402 include, but are not limited to, aluminum oxide (Al2O3), silicon nitride (SiN), silicon oxide (or silicon dioxide) (SiO2), hafnium oxide (HfO2), and zirconium dioxide (ZrO2). Advantageously, the dielectric layer 402 serves to protect the n-doped gallium oxide layer 114 (or prevent the n-doped gallium oxide layer 114 from oxidation).

[0108] This invention provides a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400A, comprising a component 100A; wherein a source node layer 304, a gate node layer 306, and a drain node layer 308 are disposed above an n-doped gallium oxide (Ga2O3) layer 114; an ohmic contact layer 310A is formed between the n-doped gallium oxide (Ga2O3) layer 114 and the source node layer 304, and an ohmic contact layer 310B is formed between the n-doped gallium oxide (Ga2O3) layer 114 and the drain node layer 308; a dielectric layer 402 is formed between the gate node layer 306, the source node layer 304, the n-doped gallium oxide (Ga2O3) layer 114, and the drain node layer 308. In other words, the MOSFET device 400A includes the component 100A, which further includes: the silicon substrate layer 102; the transition layer 104 deposited on the silicon substrate layer 102; and the gallium nitride buffer layer 106 deposited on the transition layer 104. The component 100A of the MOSFET device 400A also includes the passivation layer 110 and the gallium oxide layer 108. For example, the passivation layer 110 is deposited on the gallium nitride buffer layer 106, and the gallium oxide layer 108 is disposed on the passivation layer 110. In one example, the gallium oxide layer 108 further includes the semi-insulating gallium oxide layer 302 and the n-doped gallium oxide layer 114, such as... Figure 4AAs shown. Alternatively, the semi-insulating gallium oxide layer 302 is deposited on the gallium nitride buffer layer 106, and the n-doped gallium oxide layer 114 is deposited on the semi-insulating gallium oxide layer 302. The component 100A of the MOSFET device 400A further includes two ohmic contact layers 310A and 310B, which are formed on the n-doped gallium oxide layer 114 for current flow. Thereafter, the source node layer 304 and the drain node layer 308 are directly disposed above the n-doped gallium oxide layer 114. Therefore, an ohmic contact layer 310A is disposed between the n-doped gallium oxide layer 114 and the source node layer 304, and an ohmic contact layer 310B is disposed between the n-doped gallium oxide layer 114 and the drain node layer 308. Thereafter, the dielectric layer 402 is formed on the n-doped gallium oxide layer 114. In one example, the dielectric layer 402 is formed to partially cover the drain node layer 308 and the source node layer 304. The component 100A of the MOSFET device 400A also includes the gate node layer 306, which is disposed directly on the dielectric layer 402. For example, the gate node layer 306 is disposed in an optional region of the dielectric layer 402 (or the gate dielectric layer). Therefore, the dielectric layer 402 of the MOSFET device 400A is formed between the gate node layer 306, the source node layer 304, the n-doped gallium oxide layer 114, and the drain node layer 308. Examples of materials used to form the dielectric layer 402 include, but are not limited to, alumina (Al2O3), silicon nitride (SiN), silicon oxide (or silicon dioxide) (SiO2), hafnium oxide (HfO2), and zirconium dioxide (ZrO2). Advantageously, the dielectric layer 402 serves to protect the n-doped gallium oxide layer 114 or prevent its oxidation. Therefore, the MOSFET device 400A facilitates the co-integration of the n-doped gallium oxide layer 114 and the semi-insulating gallium oxide layer 302 (or ultra-wide bandgap technology) with the gallium nitride buffer layer 106 and the silicon substrate layer 102 (or silicon-based gallium nitride technology). Due to the improved thermal conductivity and electrical performance of the component 100A, the MOSFET device 400A is advantageous for use in high-power electronic devices.

[0109] Figure 4B This is a schematic diagram of a metal-oxide-semiconductor field-effect transistor device according to another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 3 and Figure 4Aelement pairs in Figure 4B Provide a description. (See reference.) Figure 4B The diagram illustrates a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400B, which includes a diode 404, a second gallium oxide (Ga2O3) layer 406, a contact bridge 408A, and another contact bridge 408B. The MOSFET 400B also includes a silicon substrate layer 102, a gallium nitride buffer layer 106, a passivation layer 110, a p-doped gallium nitride layer 112, an n-doped gallium oxide layer 114, a source node layer 304, a gate node layer 306, and a drain node layer 308.

[0110] The diode 404 is a two-terminal semiconductor device that acts as a unidirectional current flow switch, and can also be referred to as a body diode, integrated body diode, etc. Typically, the diode 404 allows current to flow freely in one direction, but restricts current flow in the opposite direction. The second gallium oxide layer 406 is similar to the gallium oxide layer 108.

[0111] Each of the contact bridge 408A and the other contact bridge 408B serves as an electrode contact terminal. The contact bridge 408A and the other contact bridge 408B correspond to an overhead return line used for current transmission, etc.

[0112] According to one embodiment, a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400B includes a diode 404; wherein, the component 100A further includes a second gallium oxide (Ga2O3) layer 406, the second gallium oxide (Ga2O3) layer 406 having a p-doped gallium nitride (GaN) layer 112 disposed below the second gallium oxide (Ga2O3) layer 406; wherein, the second gallium oxide (Ga2O3) layer 406 is connected to the drain node layer 308 via a contact bridge 408A. In other words, the MOSFET device 400B includes the diode 404 and the component 100A. The component 100A further includes a gallium nitride buffer layer 106, the gallium nitride buffer layer 106 being directly deposited on the silicon substrate layer 102. The component 100A further includes the passivation layer 110, which is selectively deposited on the gallium nitride buffer layer 106, and the n-doped gallium oxide layer 114 is also selectively disposed on the passivation layer 110. The component 100A also includes: a p-doped gallium nitride layer 112, selectively disposed on a portion of the gallium nitride buffer layer 106; and a second gallium oxide layer 406 disposed on the p-doped gallium nitride layer 112. The second gallium oxide layer 406 above the p-doped gallium nitride layer 112 is connected to form the diode 404 in the MOSFET device 400B. Furthermore, the component 100A uses a contact bridge 408A to connect the second gallium oxide layer 406 to the drain node layer 308 of the component 100A. In one example, the component 100A also uses another contact bridge 408B to connect the source node layer 304 to the p-doped gallium nitride layer 112, as shown below. Figure 4C Further illustration and description are provided below. Therefore, the MOSFET device 400B serves as a power transistor with an integrated diode (such as the diode 404). Furthermore, the MOSFET device 400B is advantageous for use in power electronic devices and other such applications.

[0113] Figure 4C This is a schematic diagram of a metal-oxide-semiconductor field-effect transistor device according to another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 3 , Figure 4A and Figure 4B element pairs in Figure 4C Provide a description. (See reference.) Figure 4C The diagram illustrates a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400C, which includes an ohmic contact layer 410, a second contact bridge 412, an unintentionally doped (UID) gallium nitride (GaN) layer 414, and an aluminum gallium nitride (AlGaN) layer 416. The MOSFET 400C also includes a silicon substrate layer 102, a gallium nitride buffer layer 106, a passivation layer 110, a p-doped gallium nitride layer 112, an n-doped gallium oxide layer 114, a source node layer 304, a gate node layer 306, a drain node layer 308, a diode 404, and another contact bridge 408B.

[0114] According to one embodiment, a metal-oxide-semiconductor field-effect transistor (MOSFET) device 400C includes a diode 404; wherein, the component 100A further includes a p-doped gallium nitride (GaN) layer 112, the p-doped gallium nitride (GaN) layer 112 being disposed above the gallium nitride (GaN) buffer layer 106; wherein, the p-doped gallium nitride (GaN) layer 112 is connected to the source node layer 304 via an ohmic contact layer 410 through a contact bridge (i.e., the other contact bridge 408B), and the gallium nitride (GaN) buffer layer 106 is connected to the drain node layer 308 via an ohmic contact layer through a second contact bridge 412. In other words, the metal-oxide-semiconductor field-effect transistor (MOSFET) device 400C includes the diode 404 and the component 100A. The component 100A includes: a gallium nitride buffer layer 106, directly deposited on the silicon substrate layer 102; and a passivation layer 110, selectively deposited on the gallium nitride buffer layer 106. The component 100A also includes a p-doped gallium nitride layer 112 disposed on the gallium nitride buffer layer 106. The component 100A further includes an ohmic contact layer 410 formed (e.g., deposited) on the p-doped gallium nitride layer 112. The ohmic contact layer 410 connects the p-doped gallium nitride (GaN) layer 112 and the source node layer 304 via another contact bridge 408B. Alternatively, the other contact bridge 408B and the ohmic contact layer 410 connect the p-doped gallium nitride (GaN) layer 112 to the source node layer 304 of the MOSFET device 400C. In one example, the ohmic contact layer ( Figure 4C A diode (not shown) is also formed on the gallium nitride buffer layer 106 to connect the gallium nitride buffer layer 106 and the second contact bridge 412. The second contact bridge 412 is also connected to the drain node layer 308 of the component 100A. Therefore, the component 100A of the present invention is advantageous for manufacturing a power transistor with an integrated diode to manufacture the MOSFET device 400C having the diode 404, the MOSFET device 400C being disposed between the gallium nitride buffer layer 106 and the ohmic contact layer 410.

[0115] According to one embodiment, the component 100A further features the following: the gallium nitride (GaN) buffer layer 106 includes an aluminum gallium nitride (AlGaN) layer 416, which is located on top of an unintentionally doped (UID) gallium nitride (GaN) layer 414. In other words, the unintentionally doped gallium nitride layer 414 (of the gallium nitride buffer layer 106) is deposited directly on the silicon substrate layer 102, and the aluminum gallium nitride layer 416 (of the gallium nitride buffer layer 106) is deposited on the unintentionally doped gallium nitride layer 414. Advantageously, the aluminum gallium nitride layer 416 of the gallium nitride buffer layer 106 achieves an improved connection with the drain node layer 308 of the component 100A via the second contact bridge 412.

[0116] According to one embodiment, at least one of the ohmic contact layers comprises titanium and / or gold. Since the ohmic contact layers are used for connection purposes, titanium and / or gold are used to achieve improved connection through one of the ohmic contact layers in the component 100A.

[0117] Figure 5A This is a schematic diagram of a Schottky diode device provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 5A Provide a description. (See reference.) Figure 5A The diagram shows a schematic of a Schottky diode device 500A, which includes a cathode layer 502, an n+ (Sn)-doped gallium oxide (Ga2O3) layer 504, an n- (Si)-doped gallium oxide (Ga2O3) layer 506, and an anode layer 508. The Schottky diode device 500A also includes a silicon substrate layer 102, a transition layer 104, a gallium nitride buffer layer 106, a gallium oxide layer 108, and a passivation layer 110.

[0118] The Schottky diode device 500A is a semiconductor diode (or a metal-semiconductor junction diode), which can also be called a hot carrier diode or a Schottky barrier diode. For various applications (e.g., power electronic devices), the switching operation of the Schottky diode device 500A is very fast.

[0119] The cathode layer 502 and the anode layer 508 correspond to the two terminals of the Schottky diode device 500A. In one example, the anode layer 508 is the metal side of the Schottky diode device 500A, and the cathode layer 502 is the semiconductor side of the Schottky diode device 500A. In one implementation, the anode layer 508 comprises platinum, titanium, or gold, and the cathode layer 502 comprises titanium or gold.

[0120] The n+(Sn) doped gallium oxide (Ga2O3) layer 504 corresponds to gallium oxide doped with n+ tin (Sn), and the n-(Si) doped gallium oxide (Ga2O3) layer 506 corresponds to gallium oxide doped with n- silicon (Si).

[0121] The present invention provides the component 100A, wherein the gallium oxide (Ga2O3) layer 108 includes an n-(Si)-doped gallium oxide (Ga2O3) layer 506, the n-(Si)-doped gallium oxide (Ga2O3) layer 506 being located on top of an n+(Sn)-doped gallium oxide (Ga2O3) layer 504; an anode layer 508 is formed above the n-(Si)-doped gallium oxide (Ga2O3) layer 506; and a cathode layer 502 is formed below the gallium oxide (Ga2O3) layer 108. The component 100A thereby forms a Schottky diode device 500A. In other words, the component 100A is included in the Schottky diode device 500A, and the component 100A includes: a transition layer 104 deposited on the silicon substrate layer 102; and a gallium nitride buffer layer 106 directly deposited on the transition layer 104. The component 100A further includes the cathode layer 502, which is formed on the gallium nitride buffer layer 106. Optionally, the passivation layer 110 may also be formed on the gallium nitride buffer layer 106, in which case the cathode layer 502 is formed on the passivation layer 110, such as... Figure 5AAs shown. The component 100A further includes the gallium oxide layer 108 disposed on the cathode layer 502. The gallium oxide layer 108 further includes the n+(Sn)-doped gallium oxide layer 504 and the n-(Si)-doped gallium oxide layer 506. For example, the n+(Sn)-doped gallium oxide layer 504 is deposited on the cathode layer 502, and the n-(Si)-doped gallium oxide layer 506 is deposited on the n+(Sn)-doped gallium oxide layer 504. Thereafter, the component 100A includes the anode layer 508 formed on the n-(Si)-doped gallium oxide layer 506. Therefore, the component 100A forms the Schottky diode device 500A, which is advantageous for use in high-power electronic devices. In one example, the Schottky diode device 500A includes a metal stack for a Schottky contact layer. Examples of metals used in the metal stack for the Schottky contact layer include, but are not limited to, nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), copper (Cu), and iridium (Ir). Furthermore, by using the component 100A, the Schottky diode device 500A facilitates the co-integration of the n-(Si)-doped gallium oxide layer 506 and the n+(Sn)-doped gallium oxide layer 504 with the gallium nitride buffer layer 106 and the silicon substrate layer 102 (or gallium nitride on silicon technology).

[0122] Figure 5B This is a schematic diagram of a Schottky diode device provided in another embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 5A element pairs in Figure 5B Provide a description. (See reference.) Figure 5B The diagram shows a schematic of a Schottky diode device 500B, which includes a silicon substrate layer 102, a transition layer 104, a gallium nitride buffer layer 106, a gallium oxide layer 108, and a passivation layer 110. The Schottky diode device 500B also includes a cathode layer 502, an n+ (Sn) doped gallium oxide (Ga2O3) layer 504, an n- (Si) doped gallium oxide (Ga2O3) layer 506, and an anode layer 508.

[0123] According to one embodiment, the gallium oxide (Ga2O3) layer 108 includes an n-(Si)-doped gallium oxide (Ga2O3) layer 506, which is located on top of an n+(Sn)-doped gallium oxide (Ga2O3) layer 504; wherein the n-(Si)-doped gallium oxide (Ga2O3) layer 506 partially covers the n+(Sn)-doped gallium oxide (Ga2O3) layer 504 to form an exposed region of the n+(Sn)-doped gallium oxide (Ga2O3) layer 504; an anode layer 508 is formed above the n-(Si)-doped gallium oxide (Ga2O3) layer 506; and a cathode layer 502 is formed above the exposed region of the n+(Sn)-doped gallium oxide (Ga2O3) layer 504, thereby forming a Schottky diode device 500B. In other words, the Schottky diode device 500B includes the component 100A. For example, the component 100A further includes: a transition layer 104 deposited on the silicon substrate layer 102; and a gallium nitride buffer layer 106 directly deposited on the transition layer 104. The component 100A also includes a gallium oxide layer 108 formed on the gallium nitride buffer layer 106. The gallium oxide layer 108 further includes an n-(Si)-doped gallium oxide layer 506 and an n+(Sn)-doped gallium oxide layer 504. For example, the n+(Sn)-doped gallium oxide layer 504 is deposited on the gallium nitride buffer layer 106, and the n-(Si)-doped gallium oxide layer 506 is deposited on the n+(Sn)-doped gallium oxide layer 504. Optionally, the passivation layer 110 can be formed on the gallium nitride buffer layer 106. In this case, the n+ (Sn) doped gallium oxide layer 504 is formed on the passivation layer 110, and the n- (Si) doped gallium oxide layer 506 is deposited on the n+ (Sn) doped gallium oxide layer 504, as shown below. Figure 5BAs shown. In this case, the n-(Si)-doped gallium oxide layer 506 is used to partially cover the n+(Sn)-doped gallium oxide layer 504, thereby forming the exposed region of the n+(Sn)-doped gallium oxide layer 504. Alternatively, the n+(Sn)-doped gallium oxide layer 504 is partially covered and partially exposed by the n-(Si)-doped gallium oxide layer 506, such that the cathode layer 502 is formed on the exposed region of the n+(Sn)-doped gallium oxide (Ga2O3) layer 504. Finally, the component 100A includes the anode layer 508, which is formed on the n-(Si)-doped gallium oxide layer 506, to reduce the overall size of the Schottky diode device 500B. Therefore, the component 100A forms the Schottky diode device 500B, which is advantageous for use in high-power electronic devices. By using the component 100A, the Schottky diode device 500B facilitates the co-integration of the n-(Si)-doped gallium oxide layer 506 and the n+(Sn)-doped gallium oxide layer 504 with the gallium nitride buffer layer 106 and the silicon substrate layer 102 (or silicon-based gallium nitride technology).

[0124] According to one embodiment, the anode layer 508 comprises platinum (Pt), titanium (Ti), or gold (Au), and the cathode layer 502 comprises titanium (Ti) or gold (Au). Because the anode layer 508 and the cathode layer 502 are also used for connection purposes to connect the Schottky diode device 500B to a power source, improved connectivity can be obtained through the anode layer 508 and the cathode layer 502 by using platinum, titanium, or gold for the anode layer 508 and titanium or gold for the cathode layer 502.

[0125] Figure 6 This is a schematic diagram of a blind ultraviolet (UV) photodetector provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 6 Provide a description. (See reference.) Figure 6 The diagram shows a schematic of a blind ultraviolet (UV) photodetector 600, which includes a cathode 602, one or more anodes 604A and 604B, a silicon substrate layer 102, a transition layer 104, a gallium nitride buffer layer 106, a p-doped gallium nitride layer 112, and a gallium oxide layer 108.

[0126] The blind ultraviolet photodetector 600 is a semiconductor device used in various applications such as ozone layer hole detection, flame detection, space communication, missile guidance, biochemical detection, and ultraviolet (UV) (leakage) detection. The blind ultraviolet photodetector 600 can also be referred to as a solar-blind deep ultraviolet (DUV) photodetector.

[0127] The cathode 602 and one or more anodes 604A and 604B correspond to the terminals of the blind ultraviolet photodetector 600 for further connection to connect the blind ultraviolet photodetector 600 to a power source.

[0128] According to one embodiment, the gallium oxide (Ga2O3) layer 108 is used to partially cover the p-doped gallium nitride (GaN) layer 112 to form an exposed region of the p-doped gallium nitride (GaN) layer 112; the component 100A further includes: a cathode 602 formed on the gallium oxide (Ga2O3) layer 108; and one or more anodes 604A and 604B formed on the p-doped gallium nitride (GaN) layer 112. In other words, the component 100A includes: a transition layer 104 deposited on the silicon substrate layer 102; and a gallium nitride buffer layer 106 directly deposited on the transition layer 104. The component 100A also includes the p-doped gallium nitride layer 112, which is disposed on the gallium nitride buffer layer 106. Subsequently, the gallium oxide layer 108 is disposed on the p-doped gallium nitride layer 112 to partially cover the p-doped gallium nitride layer 112. In one example, the gallium oxide layer 108 is disposed at the center of the p-doped gallium nitride layer 112. The component 100A further includes: a cathode 602 formed on the gallium oxide layer 108; and one or more anodes 604A and 604B formed on the p-doped gallium nitride layer 112. In one implementation, the cathode 602 formed on the gallium oxide layer 108 is a photocathode. Therefore, the component 100A forms the blind ultraviolet photodetector 600, which is advantageous for use in various applications such as ozone hole detection, flame detection, space communication, missile guidance, biochemical detection, and ultraviolet (UV) leakage detection.

[0129] Figure 7 This is a block diagram of a power device provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 7 Provide a description. (See reference.) Figure 7 The diagram shows a block diagram 700 of a power device 702, which includes the component 100A.

[0130] The power device 702 is a semiconductor device used as a switch or rectifier in power electronic devices such as integrated circuits or power integrated circuits. Examples of the power device 702 include, but are not limited to, power metal-oxide-semiconductor field-effect transistors (MOSFETs), power diodes, thyristors, insulated-gate bipolar transistors (IGBTs), etc.

[0131] The present invention provides a power device 702 including the aforementioned component 100A. By using the component 100A, the power device 702 is advantageous on a low-cost silicon substrate (i.e., ...) of the component 100A. Figure 1A Ultra-wide bandgap technology (e.g., by using the silicon-based substrate layer 102 shown) will be applied to the substrate. Figure 1A The gallium oxide (Ga2O3) layer 108 shown is compared with gallium nitride technology (i.e., Figure 1A The gallium nitride buffer layer 106 shown is co-integrated. Furthermore, the power device 702 may include one of the components 100B, 100C, 100D, 100E, 100F, and 100G (as shown respectively). Figures 1B to 1G (As shown). The power device 702 can also be called an optoelectronic device.

[0132] Figure 8 This is a block diagram of an optoelectronic device provided in one embodiment of the present invention. (In conjunction with...) Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G element pairs in Figure 8 Provide a description. (See reference.) Figure 8 The diagram shows a block diagram 800 of an optoelectronic device 802, which includes the component 100A.

[0133] The optoelectronic device 802 is an electronic device, which may also be referred to as an electro-optic converter or a photoelectric converter. The optoelectronic device 802 provides improved optical communication, and examples of the optoelectronic device 802 include, but are not limited to, light-emitting diodes, laser diodes, photodiodes, and solar cells.

[0134] The present invention provides an optoelectronic device 802, including the aforementioned component 100A. By using the component 100A, the optoelectronic device 802 is advantageous on a low-cost silicon substrate (i.e., ...) of the component 100A. Figure 1A Ultra-wide bandgap technology (e.g., by using the silicon-based substrate layer 102 shown) will be applied to the substrate. Figure 1A The gallium oxide (Ga2O3) layer 108 shown is compared with gallium nitride technology (i.e., Figure 1A The gallium nitride buffer layer 106 shown is co-integrated.

[0135] Modifications to the embodiments of the invention described above may be made without departing from the scope of the invention as defined by the appended claims. The terms “comprising,” “combining,” “having,” “is,” and the like used to describe and claim the invention are intended to be interpreted in a non-exclusive manner, allowing for the presence of items, components, or elements not explicitly described. Singular references should also be interpreted in relation to the plural. The word “exemplary” as used herein means “as an example, instance, or illustration.” Any embodiment described as “exemplary” is not necessarily to be construed as more preferred or advantageous than other embodiments, and / or excludes combinations of features from other embodiments. The word “optionally” as used herein means “provided in some embodiments but not in others.” It should be understood that some features of the invention described in the context of a single embodiment for clarity may also be provided in combination in a single embodiment. Conversely, various features of the invention described in the context of a single embodiment for brevity may also be provided individually, in any suitable combination, or suited to any other described embodiment of the invention.

Claims

1. A metal-oxide-semiconductor field-effect transistor device (400A, 400B, 400C), characterized in that, The system includes components (100A, 100B, 100C, 100D, 100E, 100F, 100G), each component comprising: a silicon substrate layer (102); a transition layer (104) disposed above the silicon substrate layer (102); a gallium nitride (GaN) buffer layer (106) disposed above the transition layer (104); and a gallium oxide (Ga2O3) layer (108). The 2O3 layer (108) includes an n-doped gallium oxide (Ga2O3) layer (114), which is located on top of the semi-insulating gallium oxide (Ga2O3) layer (302). The components (100A, 100B, 100C, 100D, 100E, 100F, 100G) further include a source node layer (304), a gate node layer (306), and a drain node layer (308) disposed above the n-doped gallium oxide (Ga2O3) layer (114). An ohmic contact layer (310A) is formed between the n-doped gallium oxide (Ga2O3) layer (114) and the source node layer (304), and an ohmic contact layer (310B) is formed between the n-doped gallium oxide (Ga2O3) layer (114) and the drain node layer (308); A dielectric layer (402) is formed between the gate node layer (306) and the n-doped gallium oxide (Ga2O3) layer (114).

2. The metal-oxide-semiconductor field-effect transistor device (400A, 400B, 400C) according to claim 1, characterized in that, The device includes a diode (404); the gallium oxide (Ga2O3) layer (108) is deposited on top of the gallium nitride (GaN) buffer layer (106); the components (100A, 100B, 100C, 100D, 100E, 100F, 100G) also include a p-doped gallium nitride (GaN) layer (112), the p-doped gallium nitride (GaN) layer (112) being disposed between the gallium nitride (GaN) buffer layer (106) and the gallium oxide (Ga2O3) layer (108); the components (100A, 100B, 100C, 100D, 100E, 100F, 100G) also include: A second gallium oxide (Ga2O3) layer (406) has a p-doped gallium nitride (GaN) layer (112) disposed below the second gallium oxide (Ga2O3) layer (406), wherein the second gallium oxide (Ga2O3) layer (406) is connected to the drain node layer (308) via a contact bridge (408A).

3. The metal-oxide-semiconductor field-effect transistor device (400A, 400B, 400C) according to claim 1, characterized in that, Includes a diode (404); the components (100A, 100B, 100C, 100D, 100E, 100F, 100G) also include: A p-doped gallium nitride (GaN) layer (112) is disposed above the gallium nitride (GaN) buffer layer (106); wherein the p-doped gallium nitride (GaN) layer (112) is connected to the source node layer (304) via an ohmic contact layer (410) through a bridge (408B), and the gallium nitride (GaN) buffer layer (106) is connected to the drain node layer (308) via an ohmic contact layer through a second bridge (412).

4. The metal-oxide-semiconductor field-effect transistor device (400A, 400B, 400C) according to claim 2 or 3, characterized in that, The components (100A, 100B, 100C, 100D, 100E, 100F, 100G) also have the following characteristics: The gallium nitride (GaN) buffer layer (106) includes an aluminum gallium nitride (AlGaN) layer (416) which is located on top of an unintentionally doped (UID) gallium nitride (GaN) layer (414).

5. The metal-oxide-semiconductor field-effect transistor device (400A, 400B, 400C) according to claim 2 or 3, characterized in that, At least one of the ohmic contact layers (310A, 310B, 410) comprises titanium and / or gold.

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