An FPGA-based SS7 Layer 2 signaling parsing system and method

Abstract

This invention discloses an FPGA-based SS7 Layer 2 signaling parsing system and method, overcoming the problems of high power consumption, weak processing capability, difficult PCB (printed circuit board) routing, poor real-time processing effect, and high difficulty in purchasing components in existing SS7 signaling protocol parsing chips. The system includes: a second FPGA module for implementing SS7 Layer 2 signaling parsing and a data processing module connected to the second FPGA module. The second FPGA module includes a serial-to-parallel data conversion module, which is connected to a data receiving module and a data sending module. A link control module is also connected between the data receiving module and the data sending module. Utilizing FPGA for processing reduces power consumption, increases processing speed, provides strong real-time processing effect, and reduces routing space and complexity.

Description

Technical Field

[0001] This invention relates to the field of data parsing technology, and in particular to an SS7 Layer 2 signaling parsing system and method based on FPGA. Background Technology

[0002] SS7 employs common channel signaling technology, also known as out-of-band signaling, which provides a separate packet-switched network for signaling services. SS7 is used to execute out-of-band signaling in the PSTN network. SS7 enhances the PSTN by handling call setup, information exchange, routing, accounting, and support for Intelligent Network (IN) services.

[0003] SS7 is a digital signaling system applicable to both wireless and wired public switched telephone networks. This standard defines the processes and protocols for establishing calls, finding routes, and controlling network elements through switched digital signaling. Currently, DSPs are primarily used to process SS7 protocols and implement data interaction with user-level exchanges. However, using DSPs for SS7 signaling parsing suffers from drawbacks such as high chip power consumption, weak processing power, a large number of DSP pins leading to complex PCB (printed circuit board) routing, poor real-time processing performance, and difficulty in procuring components. Summary of the Invention

[0004] The purpose of this invention is to overcome the problems of high power consumption, weak processing capability, difficult PCB (printed circuit board) routing, poor real-time processing effect, and high difficulty in purchasing components in the existing SS7 signaling protocol parsing chip. It provides an FPGA-based SS7 Layer 2 signaling parsing system and method, which uses FPGA for processing, reduces power consumption, improves processing speed, has strong real-time processing effect, and reduces routing space and difficulty.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: An FPGA-based SS7 Layer 2 signaling parsing system includes: a second FPGA module for implementing SS7 Layer 2 signaling parsing and a data processing module connected to the second FPGA module. The second FPGA module includes a serial-to-parallel data conversion module, which is connected to a data receiving module and a data sending module. A link control module is also connected between the data receiving module and the data sending module.

[0006] SS7 signaling parsing comprises three layers: the first layer is the physical layer, the third layer is the network layer, and the second layer is the data link layer. In this invention, the second FPGA module implements the second layer, the data link layer. The data processing module implements the first and third layers. The serial-to-parallel data conversion module converts serial data to parallel data. The data receiving module receives the converted PCM data and parses the SS7 signaling. The data sending module sends the converted data back to the first FPGA module. During operation, the serial-to-parallel data conversion module converts the PCM data from the first layer into parallel data and sends it to the data receiving module. The data receiving module parses the data and sends the parsed signaling data to the third layer via the link control module. The data sending module receives signaling messages from the third layer, converts them back into PCM data using the serial-to-parallel data conversion module, and sends them to the first layer, thus enabling the interaction of signaling data.

[0007] This invention uses an FPGA to replace the original DSP. The DSP is a serial processing and pipelined architecture, while the FPGA is a parallel processing architecture with better real-time performance than the DSP. In addition, the FPGA consumes less power than the DSP. The FPGA's ability to process SS7 is twice that of the DSP. The FPGA uses fewer pins than the DSP, reducing wiring space and complexity.

[0008] Preferably, the data processing module includes a first FPGA module for controlling timing and an E1 interface module connected to the first FPGA module for converting external data into PCM data. The E1 interface module is connected to a user-level switch, and the first FPGA module is also connected to a central processing unit.

[0009] When this system is working, the user-level switch sends data to the internal board, which converts it into digital PCM data via the E1 interface chip. Then, through the time-slot switching within the first FPGA module, the signaling data is input to the second FPGA module. The second FPGA module parses the data and transmits it to the central processing unit (CPU). After processing, the signaling data is sent back to the second FPGA for further processing, then output to the E1 interface chip through the time-slot switching of the first FPGA module, and finally sent to the user-level switch, thus realizing the interaction between signaling messages. The CPU is used to process SS7 Layer 3 messages; that is, after the second FPGA module processes the Layer 2 messages, it sends the data to the CPU for processing.

[0010] Preferably, the second FPGA module includes a serial-to-parallel data conversion module, which is connected to a data receiving module and a data sending module. A link control module is also connected between the data receiving module and the data sending module.

[0011] Preferably, the serial-to-parallel data conversion module includes a serial-to-parallel module for receiving PCM data and a parallel-to-serial module for transmitting PCM data. The serial-to-parallel module is connected to the first FPGA module and the data receiving module, and the parallel-to-serial module is connected to the first FPGA module and the data transmitting module.

[0012] The serial-to-parallel conversion module receives PCM (Pulse Code Modulation) data from the E1 interface module, converts the serial PCM data into 8-bit parallel data, and stores the 8-bit parallel data in the FPGA's internal BRAM (Block RAM), thereby acquiring the raw signaling data. All subsequent data processing follows the 8-bit parallel data format. The parallel-to-serial conversion module reads data from the data transmission module, converts the 8-bit parallel data back into PCM serial data, and sends the PCM data to the first layer of the signaling data link.

[0013] Preferably, the data transmission module includes a transmission module and a transmission control module connected to the transmission module. The transmission module is connected to the serial-to-parallel data conversion module, and the transmission control module is connected to the link control module.

[0014] The sending module reads signaling data and verifies the signaling units. The sending control module parses the verified signaling units to obtain data including address and control information. After parsing, the control link control module performs link control.

[0015] Preferably, the data receiving module includes a receiving module and a receiving control module connected to the receiving module. The receiving module is connected to a serial-to-parallel data conversion module, and the receiving control module is connected to a link control module.

[0016] The transmission control module needs to send a link establishment message before the signaling link is established, following the SS7 signaling protocol. The transmission module is mainly used for delimiting, locating, and detecting errors in the transmission signaling units. It reads data from the transmission buffer in the transmission control module, processes the data, adds a flag "F" at the beginning of each frame, inserts a "0" after five "1"s in the data, calculates the CRC using a cyclic CRC algorithm, fills the last two data points with the CRC data, adds the flag "F" again, and stores the data in the switching buffer of the transmission module.

[0017] Preferably, the link control module includes a link status control module and an initial positioning control module. The link status control module is used for link status control and management, and the initial positioning control module is used for the initiation and recovery of the signaling link.

[0018] The link status control module is used for link status control and management. When it receives a signaling unit related to the link status, it notifies the relevant functional modules of the link status at the other end and controls the sending and receiving of the transmission and reception modules according to the requirements of the relevant functional modules and the status of the signaling link itself. The start-up and positioning control module is used to start and restore the signaling link. The signaling link can provide the necessary procedures for service use.

[0019] Preferably, the second FPGA module further includes a positioning error rate monitoring module for monitoring the positioning status and a signaling error rate monitoring module for detecting the quality of service of the signaling link. The positioning error rate monitoring module and the signaling error rate monitoring module are both connected to the link control module and the data receiving module.

[0020] The positioning error rate monitoring module, in idle state, sets a tolerance for positioning errors. During the positioning process, it counts the received erroneous signaling units, and when the error rate reaches a certain threshold, it considers the link faulty. This monitoring is used during the initial positioning acceptance phase. The signaling error rate monitoring module is used to detect the service quality of the signaling link. It counts each received erroneous signaling unit, and when the error rate reaches a certain threshold, it considers the link faulty. This monitoring is used to monitor signaling link faults while the link is operational.

[0021] An FPGA-based SS7 Layer 2 signaling parsing method includes the following steps: S1: Process the PCM data sent by the first layer to obtain the raw signaling data; S2: Demarcate, locate, and perform CRC checks on signaling units; store signaling data that passes the check and discard unqualified data. S3: Parse the signaling unit that has passed the verification, and after parsing, send it to the third layer; S4: Delimit, locate, and detect errors in the signaling units to be sent from the third layer. Convert the qualified data and send it to the first layer.

[0022] It enables information exchange between the three-layer network and the parsing of SS7 signaling.

[0023] Preferably, step S3 further includes: When the signaling link is idle, it will receive normal signaling messages and send them to the third layer. When a signaling unit related to the link status is received, the link status of the other end is notified to the third layer, and the sending and receiving of signaling messages are controlled according to the relevant requirements of the third layer and the status of the signaling link itself. The signaling link includes a normal start-up positioning procedure and an emergency start-up positioning procedure.

[0024] When the signaling link is idle, Layer 3 messages can be transmitted transparently. The main difference between the normal start-up positioning procedure and the emergency start-up positioning procedure is the different acceptance period. The acceptance period for the normal start-up positioning procedure is longer, while the acceptance period for the emergency start-up positioning procedure is shorter. Currently, both positioning FPGA procedures are supported.

[0025] Therefore, the present invention has the following beneficial effects: it uses an FPGA to replace the original DSP. The DSP is a serial processing and pipelined architecture, while the FPGA is a parallel processing architecture, which has better real-time performance than the DSP. Moreover, the FPGA consumes less power than the DSP. The FPGA's ability to process SS7 is twice that of the DSP. The FPGA uses fewer pins than the DSP, which reduces wiring space and difficulty. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the system structure of the present invention.

[0027] Figure 2 This is a schematic diagram of the system structure of the second FPGA module in this invention.

[0028] Figure 3 This is a schematic diagram of the HDLC frame format in this invention.

[0029] In the diagram: 1. User-level switch; 2. First FPGA module; 3. E1 interface module; 4. Second FPGA module; 5. Central processing unit; 6. Voice conversion network; 7. Serial-to-parallel module; 8. Parallel-to-serial module; 9. Transmitting module; 10. Transmitting control module; 11. Receiving module; 12. Receiving control module; 13. Link status control module; 14. Start positioning control module; 15. Positioning error rate monitoring module; 16. Signaling error rate monitoring module. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: This embodiment is an SS7 Layer 2 signaling parsing system based on FPGA, such as... Figure 1 As shown, it includes: a first FPGA module 2, which is connected to an E1 interface module 3, a central processing unit 5 (CPU), a second FPGA module 4, and a voice conversion network 6. The E1 interface module is connected to a user-level switch 1. The first FPGA module mainly controls the timing and communication logic between the central processing unit and external chips.

[0031] In this embodiment, the E1 interface module uses the IDT82P2288 E1 interface chip; the voice conversion network uses a VoIP module. SS7 signaling parsing is similar to the OSI network architecture, consisting of several layers. The first layer is the physical layer, which is the physical medium for data transmission; the third layer is the network layer, which controls and manages the entire call process in SS7; the second layer is the data link layer, which is implemented by the second FPGA module in this invention.

[0032] When this system is working, the user-level switch sends data to the internal board, which converts it into digital PCM data through the E1 interface chip. Then, through the time-slot switching within the first FPGA module, the signaling data is input to the second FPGA module. The second FPGA module parses the data, processes it, and sends the signaling data. This data is then output to the E1 interface chip through the time-slot switching of the first FPGA module and finally sent to the user-level switch, realizing the interaction between signaling signals. The voice conversion network is used to convert the voice data in PCM into network data. Specifically, it uses SS7 signaling to establish a link. After a call or conversation, the voice is transmitted via VoIP, enabling hands-free communication. This is one application scenario in this embodiment.

[0033] This invention uses an FPGA to replace the original DSP. The DSP is a serial processing and pipelined architecture, while the FPGA is a parallel processing architecture with better real-time performance than the DSP. In addition, the FPGA consumes less power than the DSP. The FPGA's ability to process SS7 is twice that of the DSP. The FPGA uses fewer pins than the DSP, reducing wiring space and complexity.

[0034] The specific structure of the second FPGA module is as follows: Figure 2 As shown, the second FPGA module includes a serial-to-parallel conversion module 7, a parallel-to-serial conversion module 8, a transmitting module 9, a transmitting control module 10, a receiving module 11, a receiving control module 12, a link status control module 13, a starting positioning control module 14, a positioning error rate monitoring module 15, and a signaling error rate monitoring module 16. The serial-to-parallel conversion module and the parallel-to-serial conversion module are both connected to the first FPGA module. The receiving module is connected to the serial-to-parallel conversion module, and the receiving control module is connected to the receiving module. The receiving module is also connected to the positioning error rate monitoring module, the signaling error rate monitoring module, and the starting positioning control module. The starting positioning control module, the receiving control module, and the signaling error rate monitoring module are all connected to the link status control module, and the positioning error rate monitoring module is connected to the starting positioning control module. The transmitting module is connected to the parallel-to-serial conversion module and the transmitting control module, respectively. The transmitting control module is connected to the starting positioning control module and the link status control module, respectively.

[0035] The transmission control module is equipped with a transmission buffer and a switching buffer.

[0036] During work: The serial-to-parallel (STP) module converts PCM (Pulse Code Modulation) serial data into 8-bit parallel data and stores the 8-bit parallel data in the BRAM (Block RAM) inside the second FPGA module, thereby acquiring the original signaling data. All subsequent data processing follows the 8-bit parallel data format.

[0037] The receiving module (DAEDR) reads data from the BRAM. According to the HDLC (High-Level Data Link Control) protocol requirements (when the peer sends 5 bits of '1', a '0' must be added afterward; when the receiving end receives 5 bits of '1', if the following bit is '0', the extra '0' needs to be removed), if the received data is "01111110", it indicates that the flag "F" has been received. The data between the two "F"s is called a signaling unit. Cyclic redundancy check (CRC) is performed on each data item, checking data within the range of the two "F"s. After the check, the data value is 0x1D0F, indicating that the data is correct). Figure 3 As shown, the signaling unit is demarcated, located, and subjected to CRC (error check). When a frame of data is received, the data length meets the requirements, and the verification is successful, it is stored in the FPGA's BRAM. If an error occurs, the error is reported to both the location error rate monitoring module and the signaling error rate monitoring module, and the frame is discarded.

[0038] The receive control module (RC module) reads the BRAM data (i.e., the data that passed verification in the aforementioned process) from the receive module, and controls the reading of signaling units and parses the signaling. The receive control module can parse the received signaling units entirely according to the protocol requirements, such as... Figure 3 As shown, this includes parsing data such as addresses and control information. After parsing the received data, it is sent to the Link State Control module (LSC module) for link state control. When the signaling link is idle, normal signaling messages are sent to the third layer.

[0039] This enabled the parsing of SS7 data.

[0040] The link state control module is used for link state control and management. When it receives a signaling unit related to the link state, it notifies the relevant functional modules or the third layer of the link state from the other end. This module also controls the sending and receiving of the link control module and the sending control module according to the relevant requirements of the third layer and the state of the signaling link itself. This part can be implemented using the state machine function of an FPGA.

[0041] The Initiation Positioning Control Module (IAC module) is used to start and restore the signaling link, which provides the necessary procedures for service use. Signaling System No. 7 provides two positioning procedures: a normal initiation positioning procedure and an emergency initiation positioning procedure. The main difference lies in the acceptance period; the normal initiation positioning procedure has a longer acceptance period, while the emergency initiation positioning procedure has a shorter acceptance period. Currently, both positioning FPGA procedures are supported.

[0042] Therefore, the link was controlled.

[0043] The Transmit Control Module (TXC module) needs to send connection establishment messages before the signaling link is established, following the Signalling Standard No. 7 protocol. When the signaling link is in operation, it can send signaling messages. When a signaling message is sent at Layer 3, the message is sent to the Transmit Control Module and stored in the Transmit Buffer TB. The Transmit Buffer TB is requested using the BRAM module built into the second FPGA module. Data is also written to the Reset Buffer (RTB), which is also a built-in BRAM module of the second FPGA module, but its primary purpose is for retransmission after data transmission problems.

[0044] The DEADT (Delivery Module) is primarily used for delimiting, locating, and detecting errors in the transmitted signaling units. It reads data from the transmit buffer in the transmit control module, processes the data, adds a flag "F" at the beginning of each frame, inserts "0"s after five "1"s in the data, calculates the CRC (Circular Curve Correction) algorithm, fills the last two data entries with the CRC data, adds the flag "F" again, and stores the data in the switching buffer within the transmit module.

[0045] The Parallel-to-Serial (PTS) module's main function is to read data from the buffer in the transmitting module, convert 8-bit parallel data into serial data, and send the resulting serial data to the first physical layer.

[0046] This enables the data transmission process to form a closed loop, allowing for the transparent transmission of Layer 3 messages when the signaling link is idle.

[0047] Step 1: Process the PCM data sent by the first layer to obtain the raw signaling data.

[0048] The PCM serial data is converted into 8-bit parallel data, and the converted 8-bit parallel data is stored to obtain the original signaling data. All subsequent data processing follows the 8-bit parallel data format.

[0049] The second step is to delineate, locate, and perform CRC checks on the signaling units. Signaling data that passes the check is stored, while unqualified data is discarded.

[0050] According to the HDLC protocol, signaling units are demarcated, located, and subjected to CRC checks. Once a data frame is received, its length meets the requirements, and the check is successful, it is stored. If an error occurs, the frame is discarded, and the error is reported. HDLC (High-Level Data Link Control) is an international standard for link-layer protocols used to enable resource sharing and information exchange between remote users. The HDLC protocol ensures that data transmitted to the next layer is accurately received during transmission, meaning there is no loss during error handling, and the sequence is correct.

[0051] Step 3: Parse the signaling units that pass the verification, and then send them to the third layer.

[0052] When the signaling link is idle, it will receive normal signaling messages and send them to the third layer; when it receives a signaling unit related to the link status, it will notify the third layer of the link status of the other end, and control the sending and receiving of signaling messages according to the relevant requirements of the third layer and the status of the signaling link itself. The signaling link can provide the procedures necessary for service use, including normal initial location procedures and emergency initial location procedures in this embodiment. When the signaling link is in operation, it can send signaling messages.

[0053] Step 4: Delimit, locate, and perform error detection on the signaling units to be sent from the third layer. Data that passes the detection is then converted and sent to the first layer. The signaling data is processed by adding a flag "F" at the beginning of each frame, and inserting a "0" after five "1"s in the data. A CRC checksum is calculated using a cyclic CRC algorithm, and the CRC data is filled into the last two data segments. Finally, the flag "F" is added again, resulting in 8 bits of parallel data, which is then stored. This 8-bit parallel data is converted into serial data and sent to the first layer, completing the signaling data transmission.

[0054] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Other variations and modifications are possible without departing from the technical solutions described in the claims.

Claims

1. An SS7 Layer 2 signaling parsing system based on FPGA, characterized in that, include: A second FPGA module for SS7 Layer 2 signaling parsing and a data processing module connected to the second FPGA module are provided. The second FPGA module includes a serial-to-parallel data conversion module, which is connected to a data receiving module and a data sending module. A link control module is also connected between the data receiving module and the data sending module. The data sending module includes a sending control module, which sends a link establishment message before the signaling link is established and sends a signaling message when the signaling link is opened. When a signaling message is sent at Layer 3, the signaling message is stored in the sending buffer and switching buffer of the sending control module. When the link control module receives a signaling unit related to the link status, it notifies Layer 3 of the link status of the other end and controls sending and receiving according to the requirements of Layer 3 and the status of the signaling link itself.

2. The SS7 Layer 2 signaling parsing system based on FPGA according to claim 1, characterized in that, The data processing module includes a first FPGA module for controlling timing and an E1 interface module connected to the first FPGA module for converting external data into PCM data. The E1 interface module is connected to a user-level switch, and the first FPGA module is also connected to a central processing unit.

3. The SS7 Layer 2 signaling parsing system based on FPGA according to claim 1, characterized in that, The serial-to-parallel data conversion module includes a serial-to-parallel module for receiving PCM data and a parallel-to-serial module for transmitting PCM data. The serial-to-parallel module is connected to the first FPGA module and the data receiving module, and the parallel-to-serial module is connected to the first FPGA module and the data transmitting module.

4. The SS7 Layer 2 signaling parsing system based on FPGA according to claim 1, characterized in that, The data transmission module includes a transmission module connected to the transmission control module, the transmission module being connected to the serial-to-parallel data conversion module, and the transmission control module being connected to the link control module.

5. An FPGA-based SS7 Layer 2 signaling parsing system according to claim 1, 3, or 4, characterized in that, The data receiving module includes a receiving module and a receiving control module connected to the receiving module. The receiving module is connected to a serial-to-parallel data conversion module, and the receiving control module is connected to a link control module.

6. The SS7 Layer 2 signaling parsing system based on FPGA according to claim 1, 3, or 4, characterized in that, The link control module includes a link status control module and an initial positioning control module. The link status control module is used for link status control and management, and the initial positioning control module is used for the start and recovery of the signaling link.

7. An FPGA-based SS7 Layer 2 signaling parsing system according to claim 1, 2, 3, or 4, characterized in that, The second FPGA module also includes a positioning error rate monitoring module for monitoring positioning status and a signaling error rate monitoring module for detecting signaling link service quality. Both the positioning error rate monitoring module and the signaling error rate monitoring module are connected to the link control module and the data receiving module.

8. An FPGA-based SS7 Layer 2 signaling parsing method, applied to the FPGA-based SS7 Layer 2 signaling parsing system described in any one of claims 1-7, characterized in that, include: S1: Process the PCM data sent by the first layer to obtain the raw signaling data; S2: Demarcate, locate, and perform CRC checks on signaling units; store signaling data that passes the check and discard unqualified data. S3: Parse the signaling unit that has passed the verification, and after parsing, send it to the third layer; S4: Delimit, locate, and detect errors in the signaling units to be sent from the third layer. Convert the qualified data and send it to the first layer.

9. The SS7 Layer 2 signaling parsing system based on FPGA according to claim 8, characterized in that, Step S3 further includes: When the signaling link is idle, it will receive normal signaling messages and send them to the third layer. When a signaling unit related to the link status is received, the link status of the other end is notified to the third layer, and the sending and receiving of signaling messages are controlled according to the relevant requirements of the third layer and the status of the signaling link itself. The signaling link includes a normal start-up positioning procedure and an emergency start-up positioning procedure.

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