Fault diagnosis and state monitoring method based on on-state voltage online monitoring circuit

Abstract

The application discloses a fault diagnosis and state monitoring method for an on-state voltage online monitoring circuit of a T-type three-level converter, and belongs to the field of fault diagnosis and reliability of core components of power electronic equipment. The on-state voltage online monitoring circuit comprises a voltage limiter circuit, an absolute value circuit, a minimum value circuit and a voltage comparison circuit. Based on the proposed on-state voltage online monitoring circuit, a data acquisition method with a double switching frequency is proposed, which can realize accurate acquisition of on-state voltage and acquisition of switching state information with the least devices and sampling channel numbers. Based on the on-state voltage of the T-type three-level converter, open-circuit fault diagnosis only needs a simple lookup table, without complex feature extraction and threshold setting steps, and can realize power device fault diagnosis and state monitoring simultaneously, which is beneficial to comprehensively guaranteeing the reliability of the 3L-T inverter. Experimental results show that the method has the advantages of high measurement accuracy, fast response speed, short fault diagnosis time and the like.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power electronic device fault diagnosis and reliability, more particularly, to a fault diagnosis and state monitoring method of a T-type three-level converter based on on-state voltage online monitoring circuit. BACKGROUND

[0002] There are three three-level inverter topologies, including three-level neutral-point clamped, three-level active neutral-point clamped and T-type three-level, which are mainly used in renewable energy generation, rail traction and motor drive applications. It is generally believed that the T-type three-level topology has higher efficiency and lower cost than other topologies in low-voltage and medium-voltage switching frequency applications. According to the survey, power switch faults account for 21% of converter system faults, and 34% of respondents choose power switch devices as the most vulnerable components in power electronic systems. Power switch faults are roughly divided into open circuit faults and short circuit faults. Since the three-level T-type inverter belongs to a power switch intensive topology, the likelihood of open circuit faults in the system increases.

[0003] The existing fault diagnosis method and state monitoring method are completely separated, which is not conducive to ensuring the reliability of the operation of the T-type three-level converter. At the same time, the existing state monitoring method is mainly for a single switch tube, and there is no research on the state monitoring circuit of the T-type three-level topology. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a fault diagnosis and state monitoring method of a T-type three-level converter based on an on-state voltage online monitoring circuit, which reduces the hardware cost through the on-state voltage online monitoring circuit of the T-type three-level converter, can simultaneously realize power device fault diagnosis and state monitoring, and is conducive to comprehensively ensuring the reliability of the T-type three-level converter.

[0005] To achieve the above purpose, the present application provides a fault diagnosis and state monitoring method of a T-type three-level converter based on an on-state voltage online monitoring circuit, comprising:

[0006] (1) constructing an on-state voltage sampling hardware circuit for measuring the on-state voltage of the switch tube;

[0007] (2) based on the space voltage vector modulation mode, the sampling frequency is twice the switching frequency, and the on-state voltage of the switch tube is obtained through DSP data acquisition;

[0008] (3) fault diagnosis based on the on-state voltage of the switch tube obtained through DSP data acquisition;

[0009] (4) state monitoring based on the on-state voltage of the switch tube obtained through DSP data acquisition.

[0010] In some alternative implementations, step (1) includes:

[0011] For bridge arm X (X = phases A, B, C), its on-state voltage sampling hardware circuit includes three modules: one for measuring voltage u. OX The first module contains four sub-circuits: a voltage limiter circuit, an absolute value circuit, the first part of a minimum value circuit, and a voltage comparator circuit; used to measure voltage u. PX The second module contains three sub-circuits: a voltage limiter circuit, an absolute value circuit, and a second part of a minimum value circuit; used to measure voltage u. NX The third module contains three sub-circuits: a voltage limiter circuit, an absolute value circuit, and a third part of a minimum value circuit. The first, second, and third parts of the minimum value circuit together form the overall minimum value circuit. OX The voltage between DC-side terminals O and X is u. PX The voltage between DC-side terminals P and X is u. NX This is the voltage between DC-side terminals P and X.

[0012] In some alternative implementations, a voltage limiter circuit is used to implement voltage clamping, with the voltage limiter circuit input voltage u. OX u PX u NX The output voltage is its limited voltage u OX_L u PX_L u NX_L ;

[0013] An absolute value circuit is used to take the absolute value of an input voltage. The input voltage u of the absolute value circuit is... OX_L u PX_L u NX_L The output voltage is the voltage after taking the absolute value |u OX_L |、|u PX_L |、|u NX_L |;

[0014] Minimum value circuits are used to find |u PX_L |,|u OX_L | and |u NX_L The minimum value in | is the output voltage u. AD_X u AD_X =min{|u PX_L |,|u OX_L |,|u NX_L |};

[0015] A voltage comparator is used to implement |u OX_L | Compare with voltage threshold V th The comparison outputs variable C. OX for:

[0016] In some optional implementations, the voltage limiter circuit has a bidirectional voltage clamping function, with M1 and M2 being PMOS transistors, Z1 and Z2 being Zener diodes, and D1 and D2 being general-purpose diodes; when the input voltage u OX Greater than V Z2 +V D2 At that time, V Z2 V is the Zener diode Z2's regulated voltage. D2 The forward voltage drop of a common diode D2 is the voltage u of the voltage limiter output voltage. OX_L equals V Z2 +V D2 When voltage u OX Less than -V Z1 -V D1 At that time, V Z1 V is the Zener diode Z1's regulated voltage. D1 The forward voltage drop of a common diode D1 is the voltage drop across the voltage limiter output voltage u. OX_L equal to -V Z1 -V D1 When the input voltage u OX Less than V Z2 +V D2 And greater than -V Z1 -V D1 At that time, the voltage limiter output voltage u OX_L Equal to input voltage u OX .

[0017] In some alternative implementations, for bridge arm X, the first, second, and third modules in the on-state voltage sampling hardware circuit are all referenced to X and powered by an isolated power supply, and no electrical isolation is required between the first, second, and third modules.

[0018] In some alternative implementations, in step (2), the relationship between the X-phase state and the X-phase switch state is defined as follows: when the X-phase state is P, the switch state (S) X1 ,S X3 ,S X2 ,S X4 (1001) When the X-phase state is O, the switch state (S) is... X1 ,S X3 ,S X2 ,S X4 (0101) When the X-phase state is N, the switch state (S) is (0101). X1 ,S X3 ,S X2 ,S X4(0110) represents the three terminals on the DC side, where P, O, and N are the three terminals on the DC side.

[0019] Two interrupts are configured in the DSP to trigger signal sampling: one when the count is zero and another when the count reaches the periodic value. The u signal is acquired during the zero interrupt. OX and C OX Defined as u OX_z and C OX_z u acquired during periodic interruption OX and C OX Defined as u OX_p and C OX_p In this case, data sampling is performed after a Td delay following the arrival of zero-interrupt and periodic interrupt events;

[0020] During zero interruption, phase X is in state P, and when phase current i X When S is greater than zero X1 When the transistor is turned on, the input voltage of the first module is -u. dc1 +u PX The input voltage of the second module is u ce_X1 The input voltage of the third module is -u dc +u PX Through the voltage limiter circuit, absolute value circuit, and minimum value circuit, the total output voltage is u. ce_X1 Switch S X1 The on-state voltage u of the IGBT in ce_X1 The data is acquired by the DSP, where the on-state voltage of the switching transistor includes the IGBT's on-state voltage and the voltage of the parallel diode D. X1 The on-state voltage drop, u dc1 For DC side bus capacitor C high voltage, u ce_X1 Let u be the voltage across the collector and emitter of power transistor X1. dc This is the bus voltage.

[0021] In some alternative implementations, step (3) includes:

[0022] Open circuit fault via digital quantity C OX_p Or C OX_z To locate the fault, the open-circuit fault diagnosis rules are as follows:

[0023]

[0024] Where θ is the voltage vector V in space voltage vector modulation. nor The vector angle, with * indicating an irrelevant term, is any one of the phase states P, O, and N, V. nor This refers to the space voltage vector in the SVPWM modulation method.

[0025] In some alternative implementations, in step (4), the normal state monitoring rule for the switching transistor is as follows:

[0026]

[0027]

[0028] Among them, the voltage vector that can be used represents the synthesis of the three-phase phase states (P, O, and N), u f_X1 The forward voltage drop of the diode connected in anti-parallel to power transistor X1 is u. ce_X3 The voltage between the collector (C) and emitter (E) terminals of the IGBT in the X3 power transistor is u. f_X4 The forward voltage drop of the diode connected in anti-parallel to the X4 power transistor, u ce_X4 The voltage between the collector (C) and emitter (E) terminals of the IGBT in the X4 power transistor is u. f_X3 The forward voltage drop of the diode connected in anti-parallel to the X3 power transistor is u. f_X2 The forward voltage drop of the diode connected in anti-parallel to the X2 power transistor is u. ce_X2 This is the voltage between the collector (C) and emitter (E) terminals of the IGBT in the X2 power transistor.

[0029] In some alternative implementations, in step (4), the rule for monitoring the switch status under open-circuit faults is as follows:

[0030]

[0031] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0032] (1) By using the on-state voltage online monitoring circuit of the T-type three-level converter, the hardware cost can be reduced, and the power device fault diagnosis and status monitoring can be realized simultaneously, which is conducive to ensuring the reliability of the T-type three-level converter.

[0033] (2) A T-type three-level converter on-state voltage online monitoring circuit is proposed. Its on-state voltage sampling hardware circuit includes three modules and four sub-circuits: voltage limiter circuit, absolute value circuit, minimum value circuit, and voltage comparator circuit. Compared with existing methods, the number of components and output ports is reduced.

[0034] (3) The proposed open-circuit fault diagnosis method based on on-state voltage can be implemented with only a simple lookup table and requires little computation.

[0035] (4) The proposed state monitoring method for T-type three-level converter can perform online state monitoring of the switching transistor and its anti-parallel diode, and the sampling frequency is only twice the switching frequency.

[0036] (5) A fault diagnosis and condition monitoring method is proposed, which can simultaneously realize power device fault diagnosis and condition monitoring, which is conducive to fully ensuring the reliability of 3L-T inverter. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating a fault diagnosis and status monitoring method for a T-type three-level converter based on an online on-state voltage monitoring circuit, provided in an embodiment of the present invention.

[0038] Figure 2 This is an online monitoring circuit for the on-state voltage of a T-type three-level converter provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the experimental results of online monitoring of the on-state voltage of a T-type three-level converter provided in an embodiment of the present invention, wherein (a) is the input voltage u of the monitoring circuit. PA ,u OA ,u NA and output voltage u AD_A (b) is S A1 Gate voltage and terminal voltage u of the switching transistor OA and output signal C OA Waveforms (c) and (d) are obtained by sampling u at twice the switching frequency. AD_A_z and u AD_A_p ;

[0040] Figure 4 This is a schematic diagram of the experimental results for open-circuit fault diagnosis of a T-type three-level converter provided in an embodiment of the present invention, wherein (a) is the electrode voltage u. OA Phase current i A and monitoring circuit output voltage u AD_A (b) and (c) are C values ​​acquired at twice the switching frequency. OA_z and C OA_p , (d) is the fault flag F_switch. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0042] In the embodiments of the present invention, "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order or sequence.

[0043] like Figure 1As shown, the present invention provides a fault diagnosis and status monitoring method for a T-type three-level converter based on an online on-state voltage monitoring circuit, comprising the following steps:

[0044] S1: Construct the hardware circuit for sampling on-state voltage;

[0045] In embodiments of the present invention, such as Figure 2 As shown, for bridge arm X (X = phases A, B, and C), its on-state voltage sampling hardware circuit includes three modules. These are used to measure voltage u. OX The first module contains four sub-circuits: a voltage limiter circuit, an absolute value circuit, the first part of a minimum value circuit, and a voltage comparator circuit. It is used to measure voltage u. PX The second module comprises three sub-circuits: a voltage limiter circuit, an absolute value circuit, and a second part of a minimum value circuit. It is used to measure voltage u. NX The third module comprises three sub-circuits: a voltage limiter circuit, an absolute value circuit, and the third part of a minimum value circuit. The voltage comparator circuit is unique to the first module. The first, second, and third parts of the minimum value circuit together form the overall minimum value circuit, with the voltage u... OX The voltage between DC-side terminals O and X, where X = phases A, B, and C. Terminal voltage u. PX : Voltage between DC side terminals P and X, where X = phases A, B, and C. NX : Voltage between DC side terminal P and terminal X, where X = phases A, B, and C.

[0046] In this embodiment of the invention, a voltage limiter circuit is used to implement voltage clamping. With voltage u... OX u PX u NX For example, the input voltage u of the voltage limiter circuit OX u PX u NX The output voltage is its limited voltage u OX_L u PX_L u NX_L .

[0047] An absolute value circuit is used to take the absolute value of an input voltage. For example, the voltage u... OX_L u PX_L u NX_L For example, the input voltage u of the absolute value circuit OX_L u PX_L u NX_L The output voltage is the voltage after taking the absolute value |u OX_L |、|u PX_L |、|u NX_L |

[0048] Minimum value circuits are used to find |uPX_L |,|u OX_L | and |u NX_L The minimum value in | is the output voltage u. AD_X u AD_X =min{|u PX_L |,|u OX_L |,|u NX_L |}, where |u PX_L |,|u OX_L |, and |u NX_L | These represent the output voltages of the absolute value circuits in the first, second, and third modules, respectively.

[0049] A voltage comparator is used to implement |u OX_L | Compare with voltage threshold V th The comparison outputs variable C. OX for:

[0050] In this embodiment of the invention, the voltage limiter has a bidirectional voltage clamping function, M1 and M2 are PMOS transistors, Z1 and Z2 are Zener diodes, and D1 and D2 are ordinary diodes.

[0051] When the input voltage u OX Greater than V Z2 +V D2 Time (V) Z2 V is the Zener diode Z2's regulated voltage. D2 (The forward voltage drop of ordinary diode D2) Zener diode Z2 operates in reverse clamping mode, and its leakage current flows through resistor R1, causing PMOS transistor M1 to operate in high-impedance mode. At this time, the voltage limiter output voltage u... OX_L equals V Z2 +V D2 Similarly, when the voltage u OX Less than -V Z1 -V D1 Time (V) Z1 V is the Zener diode Z1's regulated voltage. D1 (The forward voltage drop of a common diode D1), the output voltage u of the voltage limiter OX_L equal to -V Z1 -V D1 .

[0052] When the input voltage u OX Less than V Z2 +V D2 And greater than -V Z1 -V D1 When Z1 and Z2 are both off, PMOS transistors M1 and M2 are both on. The resistance and voltage drop across the PMOS transistors are negligible. The output voltage u of the voltage limiter is...OX_L Equal to input voltage u OX .

[0053] In this embodiment of the invention, for bridge arm X, all three modules in the designed on-state voltage sampling hardware circuit are referenced to ground X, so only one isolated power supply is needed, and no electrical isolation is required between the three modules. The output of the designed on-state voltage sampling hardware circuit is an analog quantity u. AD_X and digital quantity C OX Compared to the traditional approach of designing a dedicated on-state voltage sampling hardware circuit for each power device, the proposed T-type three-level converter on-state voltage sampling hardware circuit reduces the required number of sampling channels and devices. Furthermore, the proposed on-state voltage sampling hardware circuit features a modular structure, allowing each sub-module to be replaced by other circuits with the same functionality.

[0054] S2: DSP data acquisition;

[0055] In this embodiment of the invention, the proposed DSP data acquisition method is based on space voltage vector modulation mode, and the sampling frequency is twice the switching frequency. The relationship between the X-phase state and the X-phase switching transistor states (P, O, and N) is defined as follows:

[0056] Table 1

[0057]

[0058]

[0059] Among them, P, O, and N are the three terminals on the DC side. The traditional two-level voltage level has P and N terminals, while the three-level voltage level has three terminals: P, O, and N.

[0060] Two interrupts are configured in the DSP to trigger signal sampling: one when the count is zero and another when the count reaches the periodic value. The u signal acquired during the zero interrupt... OX and C OX Defined as u OX_z and C OX_z u acquired during periodic interruption OX and C OX Defined as u OX_p and C OX_p It is worth noting that, due to the transient setup time of the signal, data sampling is performed after a Td delay following the arrival of zero-interrupt and periodic interrupt events.

[0061] During zero interruption, phase X is in state P. When phase current i X When S is greater than zero X1 When the transistor is turned on, the input voltage of the first module is -u. dc1 +u PXThe input voltage of the second module is u ce_X1 The input voltage of the third module is -u dc +u PX Through the voltage limiter circuit, absolute value circuit, and minimum value circuit, it can be determined that the total output voltage is u. ce_X1 Finally, the switching transistor S... X1 The on-state voltage u of the IGBT in ce_X1 Acquired by the DSP. The on-state voltage of the switching transistor includes the IGBT's on-state voltage u. ce_X1 and the diode D connected in parallel X1 The on-state voltage drop, u dc1 For DC side bus capacitor C high voltage, u ce_X1 Let u be the voltage across the collector and emitter of power transistor X1. dc This is the bus voltage.

[0062] S3: Fault diagnosis;

[0063] Open circuit fault via digital quantity C OX_p Or C OX_z To locate the fault, the open-circuit fault diagnosis rules are shown in Table 2.

[0064] Table 2

[0065]

[0066]

[0067] Where θ is the voltage vector V in space voltage vector modulation. nor The vector angle, with the symbol "*" indicating an irrelevant term, can be any of the phase states P, O, and N, V nor This refers to the space voltage vector in the SVPWM modulation method.

[0068] The rules for monitoring the status of switching transistors under normal circumstances are shown in Table 3.

[0069] Table 3

[0070]

[0071] Among them, the voltage vector that can be used represents the synthesis of the three-phase phase states (P, O, and N), u f_X1 The forward voltage drop of the diode connected in anti-parallel to power transistor X1 is u. ce_X3 The voltage between the collector (C) and emitter (E) terminals of the IGBT in the X3 power transistor is u. f_X4 The forward voltage drop of the diode connected in anti-parallel to the X4 power transistor, u ce_X4 The voltage between the collector (C) and emitter (E) terminals of the IGBT in the X4 power transistor is u. f_X3The forward voltage drop of the diode connected in anti-parallel to the X3 power transistor is u. f_X2 The forward voltage drop of the diode connected in anti-parallel to the X2 power transistor is u. ce_X2 This is the voltage between the collector (C) and emitter (E) terminals of the IGBT in the X2 power transistor.

[0072] S4: Status monitoring;

[0073] It can realize the status monitoring of the switch under open circuit fault, and the status monitoring rules under open circuit fault are shown in Table 4.

[0074] Table 4

[0075]

[0076]

[0077] To describe this embodiment more clearly, Figure 3 and Figure 4 The experimental results for this embodiment are presented, and the main parameters used in the experimental results are shown in Table 5.

[0078]

[0079] Taking phase A as an example, Figure 3 The effectiveness of the state monitoring method based on the on-state voltage online monitoring circuit of a T-type three-level converter was evaluated. Figure 3 In diagram (a), the input voltage u of the monitoring circuit is... PA ,u OA ,u NA and output voltage u AD_A Due to the output voltage u AD_A It is a function of the phase current, therefore u AD_A The envelope is sinusoidal. Figure 3 (b) is S A1 Gate voltage and terminal voltage u of the switching transistor OA and output signal C OA Waveform. Figure 3 As shown in (b), the system setup time Td is 12.5 μs, which mainly comes from the dead time (3 μs), the settling time of the monitoring circuit, and the delay time of the additional optical isolation circuit. Figure 3 In (c) and (d), u is obtained by sampling at twice the switching frequency. AD_A_z and u AD_A_p Based on Table 3, the acquired signals can be separated to obtain the on-state voltages of different switching transistors within one cycle, such as... Figure 3 As shown in (c) and (d).

[0080] Taking phase A as an example, Figure 4The effectiveness of the fault diagnosis method based on the online monitoring circuit of the on-state voltage of a T-type three-level converter was evaluated. Figure 4 In the middle (a), the polarity u is the polarity voltage. OA Phase current i A and monitoring circuit output voltage u AD_A The waveform shows that an open-circuit fault causes distortion in the positive half-cycle of the current in phase A. Figure 4 In (b) and (c), C is obtained by sampling at twice the switching frequency. OA_z and C OA_p As can be seen from the waveform, under normal circumstances, C OA_z and C OA_p It is a rectangular wave. Under open-circuit fault conditions, C OA_z It is at a high level. As shown in Table 2, S is at this time... A1 The switching transistor has failed. Figure 4 In the diagram, (d) represents the fault flag F_switch. As shown in the figure, the fault diagnosis time is 0.6ms, indicating a fast diagnosis speed.

[0081] The above results demonstrate that the T-type three-level converter on-state voltage online monitoring circuit and fault diagnosis and status monitoring method proposed in this invention have advantages such as high measurement accuracy, fast response speed, and short fault diagnosis time.

[0082] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0083] The above embodiments are described for specific open-circuit faults; the analysis results for other open-circuit faults are the same as those in the embodiments. The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. Those skilled in the art will readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A fault diagnosis and status monitoring method for a T-type three-level converter based on an online on-state voltage monitoring circuit, characterized in that, include: (1) Construct a hardware circuit for sampling on-state voltage to measure the on-state voltage of the switching transistor; (2) Based on the space voltage vector modulation mode, the sampling frequency is twice the switching frequency, and the on-state voltage of the switching transistor is obtained by DSP data acquisition; (3) Fault diagnosis is performed based on the on-state voltage of the switching transistor obtained from DSP data acquisition; (4) Status monitoring is performed based on the on-state voltage of the switching transistor obtained from DSP data acquisition; Step (3) includes: Open circuit fault via digital quantity C OX_p or C OX_z To locate the fault, the open-circuit fault diagnosis rules are as follows: in, θ Voltage vector in space voltage vector modulation V nor The vector angle, with * indicating an irrelevant term, represents the phase state. P , O ,and N any one of them, V nor The space voltage vector in the SVPWM modulation method. C OX The digital value output by the hardware circuit for sampling the on-state voltage of bridge arm X is acquired with zero interrupts. C OX Defined as C OX_z Data collected during periodic interruptions C OX Defined as C OX_p , X = Phases A, B, and C; In step (4), the normal monitoring rules for the switching transistor's status are as follows: Among them, the voltage vectors that can be used represent the synthesis of the three-phase phase states (P, O, and N). u f_X1 for X The forward voltage drop of the diode connected in anti-parallel to the power transistor. u ce_X3 for X The voltage between the collector (C) and emitter (E) terminals of the IGBT in a power transistor. u f_X4 for X The forward voltage drop of the diodes connected in anti-parallel with 4 power transistors. u ce_X4 for X 4. The voltage between the collector (C) and emitter (E) terminals of the IGBT in a power transistor. u f_X3 for X The forward voltage drop of the diodes connected in anti-parallel with three power transistors. u f_X2 for X The forward voltage drop of the diodes connected in anti-parallel with two power transistors. u ce_X2 for X 2. The voltage between the collector (C) and emitter (E) terminals of the IGBT in a power transistor. u ce_X1 for X 1. The voltage across the collector (C) and emitter (E) of the power transistor; The rules for implementing switch status monitoring under open-circuit fault conditions are as follows: 。 2. The method according to claim 1, characterized in that, Step (1) includes: For bridge arm X ( X = Phases A, B, and C), its on-state voltage sampling hardware circuit contains three modules: for measuring voltage u OX The first module contains four sub-circuits: a voltage limiter circuit, an absolute value circuit, the first part of a minimum value circuit, and a voltage comparator circuit; used for measuring voltage. u PX The second module contains three sub-circuits: a voltage limiter circuit, an absolute value circuit, and a second part of a minimum value circuit; used for measuring voltage. u NX The third module contains three sub-circuits: a voltage limiter circuit, an absolute value circuit, and the third part of a minimum value circuit. The first, second, and third parts of the minimum value circuit together form the overall minimum value circuit. u OX DC side endpoint O With endpoints X The voltage between them u PX DC side endpoint P With endpoints X The voltage between them u NX DC side endpoint N With endpoints X The voltage between them.

3. The method according to claim 2, characterized in that, The voltage limiter circuit is used to achieve voltage clamping. The input voltage of the voltage limiter circuit is... u OX , u PX , u NX The output voltage is its limited voltage. u OX_L , u PX_L , u NX_L ; An absolute value circuit is used to take the absolute value of the input voltage. u OX_L , u PX_L , u NX_L The output voltage is the voltage after taking the absolute value. u OX_L |、| u PX_L |、| u NX_L |; Minimum circuits are used to find | u PX_L |,| u OX_L | and | u NX_L The minimum value in | is the output voltage. u AD_X , ; Voltage comparators are used to implement | u OX_L |Voltage comparison threshold V th Comparison, output variables C OX for: .

4. The method according to claim 3, characterized in that, The voltage limiter circuit has a bidirectional voltage clamping function. M1 and M2 are PMOS transistors, Z1 and Z2 are Zener diodes, and D1 and D2 are ordinary diodes. When the input voltage... u OX Greater than V Z2 +V D2 At that time, V Z2 V is the Zener diode Z2's regulated voltage. D2 The forward voltage drop of a common diode D2 is the output voltage of the voltage limiter. u OX_L equals V Z2 +V D2 When the voltage u OX Less than -V Z1 -V D1 At that time, V Z1 V is the Zener diode Z1's regulated voltage. D1 The forward voltage drop of a common diode D1 is the output voltage of the voltage limiter. u OX_L equal to -V Z1 -V D1 When the input voltage u OX Less than V Z2 +V D2 And greater than -V Z1 -V D1 At that time, the voltage limiter output voltage u OX_L equal to input voltage u OX .

5. The method according to claim 4, characterized in that, For bridge arm X, the first, second, and third modules in the on-state voltage sampling hardware circuit are all referenced to X and powered by an isolated power supply. No electrical isolation is required between the first, second, and third modules.

6. The method according to claim 5, characterized in that, In step (2), the relationship between the state of phase X and the state of the switch transistor in phase X is defined as follows: when the state of phase X is... P At that time, the state of the switching transistor ( S X1 , S X3 , S X2 , S X4 (1001) is in phase X. O At that time, the state of the switching transistor ( S X1 , S X3 , S X2 , S X4 (0101) is in phase X state. N At that time, the state of the switching transistor ( S X1 , S X3 , S X2 , S X4 (0110) is the value of (0110). P , O , N These are the three terminals on the DC side; Two interrupts are configured in the DSP to trigger signal sampling: one when the count is zero and another when the count reaches the periodic value. The signal sampled during the zero interrupt... u OX and C OX Defined as u OX_z and C OX_z Data collected during periodic interruptions u OX and C OX Defined as u OX_p and C OX_p In this case, data sampling is performed after a Td delay following the arrival of zero-interrupt and periodic interrupt events; When there are zero interrupts, the X phase state is: P When the phase current i X When greater than zero, S X1 When the transistor is turned on, the input voltage of the first module is - u dc1 + u PX The input voltage of the second module is u ce_X1 The input voltage of the third module is - u dc + u PX Through the voltage limiter circuit, absolute value circuit, and minimum value circuit, the total output voltage is u ce_X1 Switching transistor S X1 The on-state voltage of the IGBT in u ce_X1 The data is acquired by the DSP, where the on-state voltage of the switching transistor includes the IGBT's on-state voltage and the voltage of the parallel diode. D X1 The on-state voltage drop, u dc1 DC side bus capacitor C high voltage, u ce_X1 for X The voltage across the collector (C) and emitter (E) of the power transistor. u dc This is the bus voltage.

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