Bandgap reference voltage generation circuit with self-start function

Abstract

The present invention discloses a bandgap reference voltage generation circuit structure with a self-starting function. The provided bandgap reference voltage generation circuit with a self-starting function, on the one hand, uses a diode to replace the traditional triode, reducing the chip layout area; on the other hand, it adopts a highly reliable and low-delay startup circuit, without using passive devices such as resistors and capacitors, further reducing the chip area and improving the reliability of the bandgap reference voltage generation circuit. The technical solution provided by the present invention has the advantages of low cost and small area, and can be widely applied to various high-precision analog and mixed-signal integrated circuit systems.

Description

Technical Field

[0001] The present invention relates to a bandgap reference voltage generation circuit with a self-starting function, belonging to the field of integrated circuit technology. Background Art

[0002] For high-precision analog and mixed-signal integrated circuit systems, the bandgap reference voltage generation circuit is a key basic module. Its main function is to generate a stable DC reference voltage that is independent of the process, not affected by the power supply voltage and ambient temperature. The temperature stability and noise immunity of the bandgap reference voltage generation circuit directly affect the accuracy and performance of the entire system chip. Usually, after the chip power supply voltage VCC is powered on, the bandgap reference circuit is the first circuit in the entire chip to be turned on and operate normally. Therefore, it is necessary to provide a high-performance startup circuit to provide a certain initial bias signal to the bandgap reference voltage generation circuit to generate a fixed reference voltage or reference current, which has an important impact on the performance of the overall bandgap reference voltage generation circuit. The present invention provides a bandgap reference voltage generation circuit with a self-starting function. Summary of the Invention

[0003] The object of the present invention is to overcome the deficiencies in the prior art and provide a bandgap reference voltage generation circuit with a self-starting function.

[0004] The bandgap reference voltage generation circuit with a self-starting function provided according to the present invention is characterized by including a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth PMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first PMOS transistor M21, a twenty-second NMOS transistor M22, a twenty-third PMOS transistor M23, a twenty-fourth PMOS transistor M24, a twenty-fifth PMOS transistor M25, a twenty-sixth NMOS transistor M26, a twenty-seventh NMOS transistor M27, a twenty-eighth PMOS transistor M28, a twenty-ninth NMOS transistor M29, a thirtieth NMOS transistor M30, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first diode D1, a second diode D2, and a current source array composed of N cascode current sources;

[0005] Among them, the gate of the first PMOS transistor M1 is connected to the drain of the first PMOS transistor M1 and the source of the second PMOS transistor M2;

[0006] The source of the first PMOS transistor M1 is connected to the sources of the seventh PMOS transistor M7, the ninth PMOS transistor M9, the twelfth PMOS transistor M12, the seventeenth PMOS transistor M17, the nineteenth PMOS transistor M19, the twenty-first PMOS transistor M21, the twenty-third PMOS transistor M23, the twenty-fifth PMOS transistor M25, the twenty-eighth PMOS transistor M28, the thirty-first PMOS transistor M31, and the source of the Nth PMOS transistor MN, and is simultaneously connected to the chip power supply voltage VDD;

[0007] The gate of the second PMOS transistor M2 is connected to the drain of the second PMOS transistor M2 and the gates of the ninth PMOS transistor M9, the third NMOS transistor M3, the twenty-third PMOS transistor M23, the twenty-eighth PMOS transistor M28, the twenty-ninth NMOS transistor M29, the thirty-first PMOS transistor M31, and the Nth PMOS transistor MN;

[0008] The gate of the third NMOS transistor M3 is connected to the gates of the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the drain of the nineteenth PMOS transistor M19, the drain of the twentieth NMOS transistor M20, the gate of the twenty-first PMOS transistor M21, and the gate of the twenty-second NMOS transistor M22;

[0009] The source of the third NMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4;

[0010] The source of the fourth NMOS transistor M4 is connected to the sources of the sixth NMOS transistor M6, the eighth NMOS transistor M8, the eleventh NMOS transistor M11, the gate of the twelfth PMOS transistor M12, the gates of the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the source of the sixteenth NMOS transistor M16, the source of the eighteenth NMOS transistor M18, the source of the twentieth NMOS transistor M20, the source of the twenty-second NMOS transistor M22, the negative terminal of the first diode D1, the negative terminal of the second diode D2, and the lower end of the eighth resistor R8, and is simultaneously connected to the ground voltage GND;

[0011] The drain of the fifth NMOS transistor M5 is connected to the gate of the seventh PMOS transistor M7, the drain of the seventh PMOS transistor M7, the drain of the eighth NMOS transistor M8, the gate of the tenth PMOS transistor M10, the gate of the twenty-fourth PMOS transistor M24, the gate of the thirty-second PMOS transistor M32, and the gate of the (N + 1)th PMOS transistor M(N + 1);

[0012] The source of the fifth NMOS transistor M5 is connected to the drain of the sixth NMOS transistor M6;

[0013] The gate of the eighth NMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10, the drain of the eleventh NMOS transistor M11, the gate of the eleventh NMOS transistor M11, and the gate of the sixteenth NMOS transistor M16;

[0014] The drain of the ninth PMOS transistor M9 is connected to the source of the tenth PMOS transistor M10;

[0015] The drain of the twelfth PMOS transistor M12 is connected to the source of the thirteenth PMOS transistor M13;

[0016] The drain of the thirteenth PMOS transistor M13 is connected to the source of the fourteenth PMOS transistor M14;

[0017] The drain of the fourteenth PMOS transistor M14 is connected to the source of the fifteenth PMOS transistor M15;

[0018] The drain of the fifteenth PMOS transistor M15 is connected to the drain of the sixteenth NMOS transistor M16, the gate of the seventeenth PMOS transistor M17, and the gate of the eighteenth NMOS transistor M18;

[0019] The drain of the seventeenth PMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18, the gate of the nineteenth PMOS transistor M19, and the gate of the twentieth NMOS transistor M20;

[0020] The drain of the twenty-first PMOS transistor M21 is connected to the drain of the twenty-second NMOS transistor M22;

[0021] The drain of the twenty-third PMOS transistor M23 is connected to the source of the twenty-fourth PMOS transistor M24;

[0022] The drain of the twenty-fourth PMOS transistor M24 is connected to the left end of the first resistor R1, the upper end of the second resistor R2, and the upper end of the fourth resistor R4;

[0023] The right end of the first resistor R1 serves as the reference voltage Vref output node;

[0024] The lower end of the second resistor R2 is connected to the upper end of the third resistor R3, the gate of the twenty-sixth NMOS transistor M26, and the gate of the twenty-ninth NMOS transistor M29;

[0025] The lower end of the third resistor R3 is connected to the upper end of the first diode D1;

[0026] The lower end of the fourth resistor R4 is connected to the upper end of the fifth resistor R5 and the gate of the twenty-seventh NMOS transistor M27;

[0027] The lower end of the fifth resistor R5 is connected to the upper end of the second diode D2 and the gate of the thirtieth NMOS transistor M30;

[0028] The gate of the twenty-fifth PMOS transistor M25 is connected to the drain of the twenty-fifth PMOS transistor M25, the drain of the twenty-sixth NMOS transistor M26, and the gate of the twenty-eighth PMOS transistor M28;

[0029] The source of the twenty-sixth NMOS transistor M26 is connected to the drain of the twenty-seventh NMOS transistor M27;

[0030] The source of the twenty-seventh NMOS transistor M27 is connected to the upper end of the sixth resistor R6;

[0031] The lower end of the sixth resistor R6 is connected to the lower end of the seventh resistor R7 and the upper end of the eighth resistor R8;

[0032] The source of the twenty-ninth NMOS transistor M29 is connected to the drain of the thirtieth NMOS transistor M30;

[0033] The source of the thirtieth NMOS transistor M30 is connected to the upper end of the seventh resistor R7;

[0034] The current source array is composed of N identical cascode current sources 1 to cascode current source N; the cascode current source 1 is composed of a thirty-first PMOS transistor M31 and a thirty-second PMOS transistor M32 connected in series. The source of the thirty-first PMOS transistor M31 is connected to VDD, and the drain of the thirty-first PMOS transistor M31 is connected to the source of the thirty-second PMOS transistor M32;

[0035] Wherein, N is a positive integer.

[0036] The advantages of the present invention are: the bandgap reference voltage generation circuit with a self-starting function provided by the present invention, on the one hand, uses diodes instead of traditional triodes, reducing the chip layout area; on the other hand, a highly reliable and low-delay starting circuit is adopted, improving the reliability of the bandgap reference voltage generation circuit. Brief Description of the Drawings

[0037] Figure 1 It is the schematic diagram of the bandgap reference voltage generation circuit with a self-starting function of the present invention. Detailed Embodiment

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples.

[0039] Figure 1 This is the schematic diagram of the bandgap reference voltage generation circuit with self-starting function of the present invention. The bandgap reference voltage generation circuit with self-starting function includes: a current source array composed of a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth PMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first PMOS transistor M21, a twenty-second NMOS transistor M22, a twenty-third PMOS transistor M23, a twenty-fourth PMOS transistor M24, a twenty-fifth PMOS transistor M25, a twenty-sixth NMOS transistor M26, a twenty-seventh NMOS transistor M27, a twenty-eighth PMOS transistor M28, a twenty-ninth NMOS transistor M29, a thirtieth NMOS transistor M30, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first diode D1, a second diode D2, and N cascode current sources;

[0040] Wherein, the gate of the first PMOS transistor M1 is connected to the drain of the first PMOS transistor M1 and the source of the second PMOS transistor M2;

[0041] The source of the first PMOS transistor M1 is connected to the sources of the seventh PMOS transistor M7, the ninth PMOS transistor M9, the twelfth PMOS transistor M12, the seventeenth PMOS transistor M17, the nineteenth PMOS transistor M19, the twenty-first PMOS transistor M21, the twenty-third PMOS transistor M23, the twenty-fifth PMOS transistor M25, and the twenty-eighth PMOS transistor M28, and is simultaneously connected to the chip power supply voltage VDD;

[0042] The gate of the second PMOS transistor M2 is connected to the drain of the second PMOS transistor M2, the gate of the ninth PMOS transistor M9, the drain of the third NMOS transistor M3, the gate of the twenty-third PMOS transistor M23, the drain of the twenty-eighth PMOS transistor M28, the drain of the twenty-ninth NMOS transistor M29, the gate of the thirty-first PMOS transistor M31, and the gate of the Nth PMOS transistor MN;

[0043] The gate of the third NMOS transistor M3 is connected to the gates of the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the drain of the nineteenth PMOS transistor M19, the drain of the twentieth NMOS transistor M20, the gate of the twenty-first PMOS transistor M21, and the gate of the twenty-second NMOS transistor M22;

[0044] The source of the third NMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4;

[0045] The source of the fourth NMOS transistor M4 is connected to the sources of the sixth NMOS transistor M6, the eighth NMOS transistor M8, the eleventh NMOS transistor M11, the gates of the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the source of the sixteenth NMOS transistor M16, the source of the eighteenth NMOS transistor M18, the source of the twentieth NMOS transistor M20, the source of the twenty-second NMOS transistor M22, the negative terminal of the first diode D1, the negative terminal of the second diode D2, and the lower end of the eighth resistor R8, and is simultaneously connected to the ground voltage GND;

[0046] The drain of the fifth NMOS transistor M5 is connected to the gates of the seventh PMOS transistor M7, the drain of the seventh PMOS transistor M7, the drain of the eighth NMOS transistor M8, the gate of the tenth PMOS transistor M10, the gate of the twenty-fourth PMOS transistor M24, the gate of the thirty-second PMOS transistor M32, and the gate of the (N + 1)th PMOS transistor M(N + 1);

[0047] The source of the fifth NMOS transistor M5 is connected to the drain of the sixth NMOS transistor M6;

[0048] The gate of the eighth NMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10, the drain of the eleventh NMOS transistor M11, the gate of the eleventh NMOS transistor M11, and the gate of the sixteenth NMOS transistor M16;

[0049] The drain of the ninth PMOS transistor M9 is connected to the source of the tenth PMOS transistor M10;

[0050] The drain of the twelfth PMOS transistor M12 is connected to the source of the thirteenth PMOS transistor M13;

[0051] The drain of the thirteenth PMOS transistor M13 is connected to the source of the fourteenth PMOS transistor M14;

[0052] The drain of the fourteenth PMOS transistor M14 is connected to the source of the fifteenth PMOS transistor M15;

[0053] The drain of the fifteenth PMOS transistor M15 is connected to the drain of the sixteenth NMOS transistor M16, the gate of the seventeenth PMOS transistor M17, and the gate of the eighteenth NMOS transistor M18;

[0054] The drain of the seventeenth PMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18, the gate of the nineteenth PMOS transistor M19, and the gate of the twentieth NMOS transistor M20;

[0055] The drain of the twenty-first PMOS transistor M21 is connected to the drain of the twenty-second NMOS transistor M22;

[0056] The drain of the twenty-third PMOS transistor M23 is connected to the source of the twenty-fourth PMOS transistor M24;

[0057] The drain of the twenty-fourth PMOS transistor M24 is connected to the left end of the first resistor R1, the upper end of the second resistor R2, and the upper end of the fourth resistor R4;

[0058] The right end of the first resistor R1 serves as the reference voltage Vref output node;

[0059] The lower end of the second resistor R2 is connected to the upper end of the third resistor R3, the gate of the twenty-sixth NMOS transistor M26, and the gate of the twenty-ninth NMOS transistor M29;

[0060] The lower end of the third resistor R3 is connected to the upper end of the first diode D1;

[0061] The lower end of the fourth resistor R4 is connected to the upper end of the fifth resistor R5 and the gate of the twenty-seventh NMOS transistor M27;

[0062] The lower end of the fifth resistor R5 is connected to the upper end of the second diode D2 and the gate of the thirtieth NMOS transistor M30;

[0063] The gate of the twenty-fifth PMOS transistor M25 is connected to the drain of the twenty-fifth PMOS transistor M25, the drain of the twenty-sixth NMOS transistor M26, and the gate of the twenty-eighth PMOS transistor M28;

[0064] The source of the twenty-sixth NMOS transistor M26 is connected to the drain of the twenty-seventh NMOS transistor M27;

[0065] The source of the twenty-seventh NMOS transistor M27 is connected to the upper end of the sixth resistor R6;

[0066] The lower end of the sixth resistor R6 is connected to the lower end of the seventh resistor R7 and the upper end of the eighth resistor R8;

[0067] The source of the twenty-ninth NMOS transistor M29 is connected to the drain of the thirtieth NMOS transistor M30;

[0068] The source of the 30th NMOS transistor M30 is connected to the upper end of the seventh resistor R7;

[0069] A current source array composed of N cascode current sources is composed of N identical cascode current sources 1 to cascode current source N; the cascode current source 1 is composed of a 31st PMOS transistor M31 and a 32nd PMOS transistor M32 connected in series. The source of the 31st PMOS transistor M31 is connected to VDD, and the drain of the 31st PMOS transistor M31 is connected to the source of the 32nd PMOS transistor M32.

[0070] Figure 1 In the bandgap reference voltage generation circuit with self-starting function of the present invention, the first PMOS transistor M1, the second PMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh PMOS transistor M7, the eighth NMOS transistor M8, the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh NMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the sixteenth NMOS transistor M16, the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, the nineteenth PMOS transistor M19, the twentieth NMOS transistor M20, the twenty-first PMOS transistor M21 and the twenty-second NMOS transistor M22 form a starting circuit; the twenty-fifth PMOS transistor M25, the twenty-sixth NMOS transistor M26, the twenty-seventh NMOS transistor M27, the twenty-eighth PMOS transistor M28, the twenty-ninth NMOS transistor M29, the 30th NMOS transistor M30, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 form an operational amplifier; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the first diode D1, and the second diode D2 form a bandgap reference core circuit.

[0071] When the power supply VDD is powered on, M9 and M10 inside the startup circuit are first turned on, and provide a current path for M11. After mirroring, M16 is turned on, and a relatively high-level signal is generated at the gates of M17 and M18. After being processed by the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, the nineteenth PMOS transistor M19, and the twentieth NMOS transistor M20, a stable high-level signal is obtained at the drains of the nineteenth PMOS transistor M19 and the twentieth NMOS transistor M20. This high-level signal will cause the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, and the sixth NMOS transistor M6 to be turned on simultaneously, thereby providing a low-level signal to the gates of M23 and M24, causing M23 and M24 to be turned on. After M23 and M24 are turned on, they will supply current to the bandgap reference core circuit composed of the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the first diode D1, and the second diode D2. The bandgap reference core circuit starts to start up, and a reference voltage Vref is generated at the first resistor R1, completing the power-on startup process.

[0072] Compared with various existing startup circuits, the startup circuit of the present invention does not use passive devices such as resistors and capacitors, and can reduce the chip area. A traditional bandgap reference voltage source is usually composed of two PNP transistors and three voltage-dividing resistors. The base-emitter voltage vbe1 of the first PNP transistor and the base-emitter voltage vbe2 of the second PNP transistor both have negative temperature characteristics, while the voltage difference vbe1 - vbe2 has positive temperature characteristics. The temperature coefficients of the positive and negative temperature characteristic voltages are superimposed to be equal to zero, and finally a reference voltage with zero temperature coefficient is obtained. The layout implementation of PNP transistors requires a large chip area. Therefore, the present invention uses 2 PN diodes to replace PNP transistors, thereby achieving a smaller chip area.

[0073] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A bandgap reference voltage generation circuit with a self-starting function, characterized in that, A current source array composed of a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth PMOS transistor M19, a twentieth NMOS transistor M20, a twenty - first PMOS transistor M21, a twenty - second NMOS transistor M22, a twenty - third PMOS transistor M23, a twenty - fourth PMOS transistor M24, a twenty - fifth PMOS transistor M25, a twenty - sixth NMOS transistor M26, a twenty - seventh NMOS transistor M27, a twenty - eighth PMOS transistor M28, a twenty - ninth NMOS transistor M29, a thirtieth NMOS transistor M30, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first diode D1, a second diode D2, and N cascode current sources; Wherein, the gate of the first PMOS transistor M1 is connected to the drain of the first PMOS transistor M1 and the source of the second PMOS transistor M2; The source of the first PMOS transistor M1 is connected to the sources of the seventh PMOS transistor M7, the ninth PMOS transistor M9, the twelfth PMOS transistor M12, the seventeenth PMOS transistor M17, the nineteenth PMOS transistor M19, the twenty - first PMOS transistor M21, the twenty - third PMOS transistor M23, the twenty - fifth PMOS transistor M25, the twenty - eighth PMOS transistor M28, the thirty - first PMOS transistor M31, and the Nth PMOS transistor M3N, and is simultaneously connected to the chip power supply voltage VDD; The gate of the second PMOS transistor M2 is connected to the drain of the second PMOS transistor M2 and the gates of the ninth PMOS transistor M9, the third NMOS transistor M3, the twenty - third PMOS transistor M23, the twenty - eighth PMOS transistor M28, the twenty - ninth NMOS transistor M29, the thirty - first PMOS transistor M31, and the Nth PMOS transistor M3N; The gate of the third NMOS transistor M3 is connected to the gates of the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the drain of the nineteenth PMOS transistor M19, the drain of the twentieth NMOS transistor M20, the gate of the twenty - first PMOS transistor M21, and the gate of the twenty - second NMOS transistor M22; The source of the third NMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4; The source of the fourth NMOS transistor M4 is connected to the sources of the sixth NMOS transistor M6, the eighth NMOS transistor M8, the eleventh NMOS transistor M11, the gates of the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the sources of the sixteenth NMOS transistor M16, the eighteenth NMOS transistor M18, the twentieth NMOS transistor M20, the twenty-second NMOS transistor M22, the negative terminals of the first diode D1, the second diode D2, and the lower end of the eighth resistor R8, and is simultaneously connected to the ground voltage GND; The drain of the fifth NMOS transistor M5 is connected to the gates of the seventh PMOS transistor M7, the drain of the seventh PMOS transistor M7, the drain of the eighth NMOS transistor M8, the gates of the tenth PMOS transistor M10, the twenty-fourth PMOS transistor M24, the thirty-second PMOS transistor M32, and the gate of the (N + 1)th PMOS transistor M(3N + 1); The source of the fifth NMOS transistor M5 is connected to the drain of the sixth NMOS transistor M6; The gate of the eighth NMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10, the drain of the eleventh NMOS transistor M11, the gate of the eleventh NMOS transistor M11, and the gate of the sixteenth NMOS transistor M16; The drain of the ninth PMOS transistor M9 is connected to the source of the tenth PMOS transistor M10; The drain of the twelfth PMOS transistor M12 is connected to the source of the thirteenth PMOS transistor M13; The drain of the thirteenth PMOS transistor M13 is connected to the source of the fourteenth PMOS transistor M14; The drain of the fourteenth PMOS transistor M14 is connected to the source of the fifteenth PMOS transistor M15; The drain of the fifteenth PMOS transistor M15 is connected to the drain of the sixteenth NMOS transistor M16, the gate of the seventeenth PMOS transistor M17, and the gate of the eighteenth NMOS transistor M18; The drain of the seventeenth PMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18, the gate of the nineteenth PMOS transistor M19, and the gate of the twentieth NMOS transistor M20; The drain of the twenty-first PMOS transistor M21 is connected to the drain of the twenty-second NMOS transistor M22; The drain of the twenty-third PMOS transistor M23 is connected to the source of the twenty-fourth PMOS transistor M24; The drain of the twenty-fourth PMOS transistor M24 is connected to the left end of the first resistor R1, the upper end of the second resistor R2, and the upper end of the fourth resistor R4; The right end of the first resistor R1 serves as the reference voltage Vref output node; The lower end of the second resistor R2 is connected to the upper end of the third resistor R3, the gate of the twenty-sixth NMOS transistor M26, and the gate of the twenty-ninth NMOS transistor M29; The lower end of the third resistor R3 is connected to the upper end of the first diode D1; The lower end of the fourth resistor R4 is connected to the upper end of the fifth resistor R5 and the gate of the twenty-seventh NMOS transistor M27; The lower end of the fifth resistor R5 is connected to the upper end of the second diode D2 and the gate of the thirtieth NMOS transistor M30; The gate of the twenty-fifth PMOS transistor M25 is connected to the drain of the twenty-fifth PMOS transistor M25, the drain of the twenty-sixth NMOS transistor M26, and the gate of the twenty-eighth PMOS transistor M28; The source of the twenty-sixth NMOS transistor M26 is connected to the drain of the twenty-seventh NMOS transistor M27; The source of the twenty-seventh NMOS transistor M27 is connected to the upper end of the sixth resistor R6; The lower end of the sixth resistor R6 is connected to the lower end of the seventh resistor R7 and the upper end of the eighth resistor R8; The source of the twenty-ninth NMOS transistor M29 is connected to the drain of the thirtieth NMOS transistor M30; The source of the thirtieth NMOS transistor M30 is connected to the upper end of the seventh resistor R7; The current source array is composed of N identical cascode current sources from cascode current source 1 to cascode current source N; the cascode current source 1 is composed of a thirty-first PMOS transistor M31 and a thirty-second PMOS transistor M32 connected in series. The source of the thirty-first PMOS transistor M31 is connected to VDD, and the drain of the thirty-first PMOS transistor M31 is connected to the source of the thirty-second PMOS transistor M32; Among them, N is a positive integer greater than 1.

2. The bandgap reference voltage generation circuit with a self-starting function according to claim 1, characterized in that The first PMOS transistor M1, the second PMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh PMOS transistor M7, the eighth NMOS transistor M8, the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh NMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the sixteenth NMOS transistor M16, the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, the nineteenth PMOS transistor M19, the twentieth NMOS transistor M20, the twenty-first PMOS transistor M21, and the twenty-second NMOS transistor M22 form a startup circuit; the twenty-fifth PMOS transistor M25, the twenty-sixth NMOS transistor M26, the twenty-seventh NMOS transistor M27, the twenty-eighth PMOS transistor M28, the twenty-ninth NMOS transistor M29, the thirtieth NMOS transistor M30, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 form an operational amplifier; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the first diode D1, and the second diode D2 form a bandgap reference core circuit.

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