Display backplane, electronic device, and method for manufacturing a display backplane

Abstract

An embodiment of the present application provides a display backplane, an electronic device, and a method for manufacturing a display backplane. The display backplane includes: a substrate; a light converging layer disposed on the substrate and including at least one light converging unit; a first planarization layer disposed on the substrate and covering the light converging layer; wherein the refractive index of the light converging unit is different from that of the first planarization layer, and the light converging unit is configured to converge the light emitted by the backlight source to the opening area of the display backplane. According to the technical solution of the embodiment of the present application, the light output path of the backlight source can be changed, the light output effect of the opening area is improved, and the defect that the opening area ratio is reduced due to too high pixel density, thereby affecting the backlight light effect, is improved, thereby improving the display effect of the display backplane.

Description

Technical Field

[0001] This application relates to the technical field of display devices, and particularly to a display backplane, an electronic device, and a method for manufacturing a display backplane. Background Art

[0002] With the rise of the metaverse concept, VR headset products, as port devices, have attracted much attention. Currently, in the market, display products with good effects are usually Micro OLED products with 3000+ PPI. However, Micro OLED products have high costs and great process difficulties, making it difficult to popularize. The glass-based ultra-high PPI technology is expected to produce products with 2000 - 3000 PPI, and at the same time, the cost is only one-tenth of that of silicon-based OLED products, which is very attractive. Therefore, developing ultra-high PPI glass-based VR headsets has great market potential.

[0003] The currently optimal solution for ultra-high PPI is the LCD display technology. Because there is only one switching TFT in the pixel area circuit of the LCD display, it is very conducive to achieving high PPI. However, the transmittance of the LCD is relatively low, and a backplane process solution with a high aperture ratio needs to be developed. Especially when the PPI reaches more than 2000 PPI, various line widths, line spacings, and via hole sizes reach the limit capabilities of display manufacturing equipment, and the area of the opening region is drastically compressed, thereby affecting the backlight light efficiency of the display backplane. Summary of the Invention

[0004] Embodiments of this application provide a display backplane, an electronic device, and a method for manufacturing a display backplane to solve or alleviate one or more technical problems in the prior art.

[0005] In a first aspect, embodiments of this application provide a display backplane, including:

[0006] A substrate;

[0007] A light converging layer disposed on the substrate, including at least one light converging unit;

[0008] A first planarization layer disposed on the substrate and covering the light converging layer;

[0009] Wherein, the refractive index of the light converging unit is different from that of the first planarization layer, and the light converging unit is used to converge the light emitted by the backlight source to the opening region of the display backplane.

[0010] In an embodiment, the sagitta of the light converging unit is 1 to 3 um, the ratio of the diameter to the sagitta is 2 to 11, the refractive index is 1.8 to 2.2, the stress is -200 to 200 Mpa, and the distance between adjacent light converging units is 0 to 2 um; wherein, the material of the light converging layer includes inorganic materials.

[0011] In one embodiment, the light converging layer is deposited on the substrate by a self-alignment process.

[0012] In one embodiment, the display backplane includes a plurality of pixels, and each pixel includes a plurality of sub-pixels.

[0013] The light converging units are arranged in one-to-one correspondence with the sub-pixels; alternatively, one light converging unit corresponds to a plurality of sub-pixels; alternatively, a plurality of light converging units correspond to one sub-pixel.

[0014] Wherein, the light converging unit is used to converge the light emitted by the backlight source to the opening area of the corresponding sub-pixel.

[0015] In one embodiment, the thickness of the first planarization layer is 1 to 5 μm, the refractive index is 1.4 to 1.6, and the temperature tolerance is not less than 350 °C; wherein, the material of the first planarization layer includes silicate glass.

[0016] In one embodiment, the display backplane further includes:

[0017] A buffer layer, an active layer, a gate insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a second planarization layer, a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planarization layer which are sequentially stacked in a direction away from the substrate; and,

[0018] A gate electrode layer and a first source-drain electrode, the gate electrode layer is disposed on a side of the gate insulating layer facing away from the substrate and is located within the first interlayer dielectric layer.

[0019] In one embodiment, the first source-drain electrode is disposed on a side of the first interlayer dielectric layer facing away from the substrate and is located within the second interlayer dielectric layer. The first source-drain electrode is electrically connected to the active layer through a first via hole, wherein the first via hole is defined jointly by the first interlayer dielectric layer and the gate insulating layer.

[0020] In one embodiment, the first source-drain electrode is disposed on a side of the first planarization layer facing away from the substrate and is located within the buffer layer. The first source-drain electrode is electrically connected to the active layer through a first via hole, wherein the first via hole is defined by the buffer layer.

[0021] In one embodiment, the first source-drain electrode is disposed in the light converging layer and is spaced apart from the light converging unit. The first source-drain electrode is electrically connected to the active layer through a first via hole, wherein the first via hole is defined jointly by the first planarization layer and the buffer layer.

[0022] In one embodiment, the display backplane further includes a second source-drain electrode, which is disposed on a side of the second interlayer dielectric layer facing away from the substrate, and is located within the second planarization layer. The second source-drain electrode is electrically connected to the active layer through a second via hole, where the second via hole is jointly defined by the gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer.

[0023] In one embodiment, the material of the second source-drain electrode is a transparent conductive material, and the thickness of the second source-drain electrode is 30 to 120 nm.

[0024] In one embodiment, the buffer layer is one layer or a plurality of layers stacked, the material of the buffer layer includes silicon nitride or silicon oxide, and the thickness of the buffer layer is 200 to 500 nm.

[0025] In a second aspect, an embodiment of the present application provides an electronic device, including the display backplane according to any one of the above embodiments of the present application.

[0026] In a third aspect, an embodiment of the present application provides a method for manufacturing a display backplane, including:

[0027] Form an alignment mark layer on a first surface of the substrate;

[0028] According to the alignment mark layer, form a light converging layer on the first surface by using a self-alignment process; wherein, the light converging unit is used to converge the light emitted by the backlight source to the opening area of the display backplane;

[0029] Form a first planarization layer on the first surface, and the first planarization layer covers the light converging layer;

[0030] Form a buffer layer on the first planarization layer, and form an active layer on the buffer layer;

[0031] Form a gate insulating layer on the buffer layer, and the gate insulating layer covers the active layer; and, form a gate electrode layer on the gate insulating layer;

[0032] Form a first interlayer dielectric layer on the gate insulating layer, and the first interlayer dielectric layer covers the gate electrode layer;

[0033] Form a first via hole penetrating the first interlayer dielectric layer and the gate insulating layer, and the first via hole extends to the active layer; form a first source-drain electrode on the first interlayer dielectric layer, and the first source-drain electrode is electrically connected to the active layer through the first via hole;

[0034] Form a second interlayer dielectric layer on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first source-drain electrode;

[0035] Form a second via hole that penetrates the second interlayer dielectric layer, the first interlayer dielectric layer, and the gate insulating layer, and the second via hole extends to the active layer; form a second source-drain electrode on the second interlayer dielectric layer, and the second source-drain electrode is electrically connected to the active layer through the second via hole;

[0036] Form a second planarization layer on the second interlayer dielectric layer, and the second planarization layer covers the second source-drain electrode; and, sequentially form a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planarization layer on the second planarization layer.

[0037] Fourthly, an embodiment of the present application provides a method for manufacturing a display backplane, including:

[0038] Form an alignment mark layer on the first surface of the substrate;

[0039] According to the alignment mark layer, use a self-alignment process to form a light converging layer on the first surface; wherein, the light converging unit is used to converge the light emitted by the backlight source to the opening area of the display backplane;

[0040] Form a first planarization layer on the first surface, and the first planarization layer covers the light converging layer;

[0041] Form a protective layer on the first planarization layer;

[0042] Flip the substrate, and form a buffer layer on the second surface of the substrate opposite to the first surface, and form an active layer on the buffer layer;

[0043] Form a gate insulating layer on the buffer layer, and the gate insulating layer covers the active layer; and, form a gate electrode layer on the gate insulating layer;

[0044] Form a first interlayer dielectric layer on the gate insulating layer, and the first interlayer dielectric layer covers the gate electrode layer;

[0045] Form a first via hole that penetrates the first interlayer dielectric layer and the gate insulating layer, and the first via hole extends to the active layer; form a first source-drain electrode on the first interlayer dielectric layer, and the first source-drain electrode is electrically connected to the active layer through the first via hole;

[0046] Form a second interlayer dielectric layer on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first source-drain electrode;

[0047] Form a second via hole that penetrates the second interlayer dielectric layer, the first interlayer dielectric layer, and the gate insulating layer, and the second via hole extends to the active layer; form a second source-drain electrode on the second interlayer dielectric layer, and the second source-drain electrode is electrically connected to the active layer through the second via hole;

[0048] A second planarization layer is formed on the second interlayer dielectric layer, and the second planarization layer covers the second source-drain electrode; and, a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planarization layer are sequentially formed on the second planarization layer.

[0049] According to the technology of the embodiments of the present application, by providing a light converging layer on the substrate, and the light converging units of the light converging layer can converge the light emitted by the backlight source to the opening area of the display backplane, thereby changing the light output path of the backlight source, improving the light output effect of the opening area, and improving the defect that the ratio of the opening area is reduced due to too high pixel density, thereby affecting the backlight light efficiency, and further improving the display effect of the display backplane.

[0050] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0052] Figure 1 A schematic structural diagram of a display backplane in the related art is shown.

[0053] Figure 2 A schematic structural diagram of the display backplane according to an embodiment of the present application is shown.

[0054] Figure 3 A schematic diagram of the opening area of the display backplane according to an embodiment of the present application is shown.

[0055] Figures 4 to 7 An arrangement form of the light converging units of the display backplane according to an embodiment of the present application is shown.

[0056] Figure 8 Another schematic structural diagram of the display backplane according to an embodiment of the present application is shown.

[0057] Figure 9 Another schematic structural diagram of the display backplane according to an embodiment of the present application is shown.

[0058] Figure 10 Another schematic structural diagram of the display backplane according to an embodiment of the present application is shown.

[0059] Figure 11 A flowchart of a method for manufacturing a display backplane according to an embodiment of the present application is shown.

[0060] Figures 12 to 20 Schematic diagram of steps of a method for preparing a display backplane according to an embodiment of the present application.

[0061] Figure 21 Flowchart of a method for preparing a display backplane according to another embodiment of the present application. Detailed implementation manners

[0062] In the following, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature and not restrictive.

[0063] In the description of this specification, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0064] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0065] In the embodiments of the present application, the shapes and sizes of the regions in the drawings do not reflect the true proportions of the display backplane structure and are only used to schematically illustrate the content of the present invention.

[0066] Low Temperature Polycrystalline Oxide (LTPO) thin film transistor (TFT) technology places low temperature polycrystalline silicon (LTPS) TFT technology and oxide (Oxide) TFT technology in the same display backplane. LTPS TFTs are used in the gate drive on array (GOA) circuit area, and Oxide TFTs are used in the switching pixel area. That is, both LTPS and Oxide TFT devices are integrated in the same display panel. Among them, the Oxide TFT can be a bottom-gate or top-gate structure, and the LTPS TFT can be a top-gate structure. This new process combines the advantages of strong driving ability of LTPS TFT process and small leakage current, low power consumption, and high transmittance of Oxide TFT process.

[0067] Figure 1 The structure of a display backplane with ultra-high PPI in the related art is shown. It has an LTPO TFT structure. Specifically, it includes: a buffer layer 20, a first semiconductor layer (polycrystalline silicon) 30, a first gate insulating layer 40, a first gate 51 and a second gate 52 arranged in the same layer, a first interlayer dielectric layer 60, a second buffer layer 21, a second semiconductor layer (oxide) 90, a second gate insulating layer 41, a third gate 53, a second interlayer dielectric layer 61, a first source-drain 71, a second source-drain 72, a third source-drain 73, a third interlayer dielectric layer 62, a transfer layer (0-ITO) 170, a planarization layer 110, a third electrode layer 120 (P-ITO), a passivation layer 130, a metal layer 160, and a fourth electrode layer (C-ITO) 140, which are sequentially located on the substrate 10. In the Oxide TFT structure in the display area (the right side of the dotted line in the figure), it is a double-gate structure, and a first ITO layer 170 for transfer is formed. The overall backplane process structure is complex, and it has both the LTPS process and the double-gate process of Oxide TFT, with many manufacturing processes and high production equipment costs. Moreover, the double-gate process of Oxide TFT is not conducive to improving the aperture ratio. Especially for display devices with a pixel density above 2000 PPI, limited by the equipment accuracy, the proportion of the aperture area is severely reduced, resulting in a decrease in the light passing rate, thus affecting the display effect of the display backplane.

[0068] In view of the defects in the related art, the embodiments of the present application provide a display backplane, an electronic device, and a method for preparing a display backplane. According to the technical solution of the embodiments of the present application, while supporting a high pixel density (such as above 2000 PPI), it can effectively improve the backlight passing rate of the aperture area of the display backplane, thereby improving the display effect of the display backplane.

[0069] Example 1

[0070] Figure 2 Shows a schematic structural diagram of a display backplane according to an embodiment of the present application. As Figure 2 shown, the display backplane of the embodiment of the present application includes a substrate 10, a light converging layer 20, and a first planarizing layer 30.

[0071] Specifically, the light converging layer 20 is disposed on the substrate 10 and includes at least one light converging unit 21. The first planarizing layer 30 is disposed on the substrate 10 and covers the light converging layer 20. Wherein, the refractive index of the light converging unit 21 is different from that of the first planarizing layer 30, and the light converging unit 21 is used to converge the light emitted by the backlight source to the opening area 10a of the display backplane.

[0072] In the embodiment of the present application, the opening area 10a of the display backplane can be understood as the pixel display area of the display backplane. As Figure 3 shown, the display backplane has a plurality of pixels, each pixel has a plurality of sub-pixels respectively, and each sub-pixel has a display area (the dotted box area in the figure) and a non-display area (the area outside the dotted box in the figure) respectively, and the display area therein is the opening area 10a of the sub-pixel. The light converging unit 21 is used to refract the light emitted by the backlight source, so that the light emitted by the backlight source is converged to the pixel display area of the corresponding sub-pixel through the light converging unit 21, thereby improving the backlight light effect of the sub-pixel opening area 10a.

[0073] It can be understood that in the process of the light emitted by the backlight source passing through the light converging unit 21 and the first planarizing layer 30 in sequence, since the refractive indices of the light converging unit 21 and the first planarizing layer 30 are different, the propagation speeds of the light in the light converging unit 21 and the first planarizing layer 30 are different. Therefore, after the light passes through the light converging unit 21 and enters the first planarizing layer 30, its propagation direction will change, thereby producing the effects of refracting and converging the light.

[0074] In the embodiment of the present application, other parameters such as the shape, size, refractive index, and arrangement mode of the light converging unit 21, as well as the refractive index of the first planarizing layer 30, can be set accordingly according to the actual situation. For example, it can be set accordingly according to the relative position relationship between the light converging unit 21 and the opening area 10a of the display backplane. The embodiment of the present application does not make specific limitations on this, as long as it satisfies that the light converging unit 21 can converge the light generated by the backlight source to the opening area 10a of the display backplane.

[0075] According to the display backplane of the embodiment of the present application, by providing a light converging layer 20 on the substrate 10, and the light converging unit 21 of the light converging layer 20 can converge the light emitted by the backlight source to the opening area 10a of the display backplane, thereby changing the light output path of the backlight source, improving the light output effect of the opening area 10a, and improving the defect that the proportion of the opening area 10a is reduced due to too high pixel density, thus affecting the backlight light effect, and further improving the display effect of the display backplane.

[0076] It should be noted that the light converging effect of the light converging unit 21 is affected not only by the refractive index difference between the light converging unit 21 and the first flat layer 30, but also by the radius of curvature of the light converging unit 21.

[0077] In one embodiment, the sagitta of the light converging unit 21 is 1 to 3 um, the ratio of the diameter to the sagitta is 2 to 11, the refractive index is 1.8 to 2.2, the stress is -200 to 200 Mpa, and the distance between adjacent light converging units 21 is 0 to 2 um. Among them, the material of the light converging layer 20 includes inorganic materials.

[0078] Exemplarily, the structure of the light converging unit 21 can specifically be a convex lens, and the convex direction of the convex lens is set away from the backlight source. Preferably, the ratio of the diameter to the sagitta of the light converging unit 21 is 6.5, the diameter is 13 um, the sagitta is 2 um, the refractive index is 2, the stress is 25 Mpa, and the distance between adjacent light converging units 21 is 1 um.

[0079] The material of the light converging layer 20 includes inorganic materials. It can be understood that, compared with organic materials, inorganic materials have better high-temperature resistance and higher compatibility with the characteristics of TFT devices. Preferably, the material of the light converging layer 20 can be silicon nitride (SiNx). Since silicon nitride has a high refractive index and light transmittance, the light converging effect of the light converging layer 20 can be further improved.

[0080] In one embodiment, the light converging layer 20 is deposited on the substrate 10 by a self-alignment process.

[0081] Exemplarily, depositing the light converging layer 20 on the substrate 10 by a self-alignment process specifically includes the following steps:

[0082] First, deposit an alignment mark layer 11 for alignment on the substrate 10. The alignment mark layer 11 can be made of Mo (molybdenum) or other metal materials, with a thickness of 50 to 100 nm, preferably 75 nm. Among them, in order to ensure the alignment accuracy, only a partial area of the alignment mark layer 11 is etched, and it is not completely etched.

[0083] Secondly, using the light converging layer 20 as a mask, light converging units 21 are formed at corresponding positions of the alignment mark layer 11 by using a self-alignment process to form the light converging layer 20.

[0084] In one embodiment, the display backplane includes a plurality of pixels, and each pixel includes a plurality of sub-pixels. The light converging units 21 are arranged in one-to-one correspondence with the sub-pixels. Alternatively, one light converging unit 21 corresponds to a plurality of sub-pixels. Alternatively, a plurality of light converging units 21 correspond to one sub-pixel. Among them, the light converging unit 21 is configured to converge the light emitted by the backlight source to the opening region 10a of the corresponding sub-pixel.

[0085] In the embodiments of the present application, each pixel may include an R (Red) sub-pixel, a G (Green) sub-pixel, and a B (Blue) sub-pixel. Among them, the arrangement of the pixels may adopt the RGB standard arrangement form, that is, each pixel is formed by the adjacent and closely arranged R sub-pixel, G sub-pixel, and B sub-pixel. Alternatively, it may also adopt the Delta arrangement form, that is, three R sub-pixels and three B sub-pixels are alternately arranged around two G sub-pixels. In addition, in the embodiments of the present application, the arrangement of the pixels may also adopt other arrangement forms, and the present application does not make specific limitations thereon.

[0086] In an example, the light converging units 21 are arranged in one-to-one correspondence with the sub-pixels. As Figure 4 shown, the pixels adopt the standard arrangement form, and each of the R sub-pixel, G sub-pixel, and B sub-pixel corresponds to one light converging unit 21. As Figure 5 shown, the pixels adopt the Delta arrangement form, and each of the R sub-pixel, G sub-pixel, and B sub-pixel corresponds to one light converging unit 21.

[0087] In another example, one light converging unit 21 corresponds to a plurality of sub-pixels. As Figure 6 shown, the pixels adopt the Delta arrangement form, wherein one light converging unit 21 corresponds to two sub-pixels.

[0088] In still another example, a plurality of light converging units 21 correspond to a plurality of sub-pixels. As Figure 7 shown, each sub-pixel corresponds to two light converging units 21, and each light converging unit 21 corresponds to three sub-pixels, namely the R sub-pixel, G sub-pixel, and B sub-pixel.

[0089] In one embodiment, the thickness of the first planarization layer 30 is 1 to 5 μm, the refractive index is 1.4 to 1.6, and the temperature tolerance is not less than 350 °C. Among them, the material of the first planarization layer 30 includes silicate glass (SOG).

[0090] Preferably, the first flat layer 30 has a thickness of 3 um, a refractive index of 1.5, and a temperature tolerance of 400 °C.

[0091] With such settings, on the one hand, it can ensure that the first flat layer 30 has a good flatness effect. On the other hand, the first flat layer 30 has good high-temperature resistance and can maintain stable physical and chemical properties under the high-temperature manufacturing process of subsequent TFTs.

[0092] In one embodiment, as Figure 2 shown, the display backplane further includes: a buffer layer 40, an active layer 41, a gate insulating layer 42, a first interlayer dielectric layer 43, a second interlayer dielectric layer 44, a second flat layer 45, a pixel electrode 46, a passivation layer 47, a common metal electrode, a transparent electrode, and a third flat layer, which are sequentially stacked in a direction away from the substrate 10; and a gate electrode layer 50 and a first source-drain electrode 51, where the gate electrode layer 50 is disposed on a side of the gate insulating layer 42 facing away from the substrate 10 and is located within the first interlayer dielectric layer 43.

[0093] In the embodiment of the present application, as Figure 2 、 Figure 8 and Figure 9 shown, the buffer layer 40, the active layer 41, the gate insulating layer 42, the first interlayer dielectric layer 43, the second interlayer dielectric layer 44, the second flat layer 45, the pixel electrode 46, the passivation layer 47, the common metal electrode, the transparent electrode, and the third flat layer can be disposed on the same side of the substrate 10 as the light converging layer 20 and the first flat layer 30. Alternatively, as Figure 10 shown, the buffer layer 40, the active layer 41, the gate insulating layer 42, the first interlayer dielectric layer 43, the second interlayer dielectric layer 44, the second flat layer 45, the pixel electrode 46, the passivation layer 47, the common metal electrode, the transparent electrode, and the third flat layer can be disposed on both sides of the substrate 10 with the light converging layer 20 and the first flat layer 30 respectively. For example, the light converging layer 20 and the first flat layer 30 can be disposed on the first surface of the substrate 10, and the buffer layer 40, the active layer 41, the gate insulating layer 42, the first interlayer dielectric layer 43, the second interlayer dielectric layer 44, the second flat layer 45, the pixel electrode 46, the passivation layer 47, the common metal electrode, the transparent electrode, and the third flat layer can be disposed on the second surface of the substrate 10.

[0094] Optionally, the buffer layer 40 is one layer or a plurality of layers stacked, the material of the buffer layer 40 includes silicon nitride (SiNx) or silicon dioxide (SiO2), and the thickness of the buffer layer 40 is 200 to 500 nm.

[0095] Preferably, the buffer layer adopts a single-layer structure, the material of the buffer layer 40 is silicon nitride, and the thickness of the buffer layer 40 is 350 nm.

[0096] Optionally, the active layer 41 may be formed of an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The active layer 41 is formed by patterning. This arrangement ensures that the active layer 41 has a certain light stability.

[0097] Optionally, the gate insulating layer 42 may be formed of an oxide semiconductor material, such as silicon oxide (SiO2) or aluminum oxide (Al2O3). The thickness of the gate insulating layer 42 is 30 to 150 nm. Preferably, the thickness of the gate insulating layer 42 is 90 nm.

[0098] Optionally, the material of the gate electrode layer 50 may be a metal material, for example, one or more of Mo, Al, Ti or other alloy materials may be selected. The thickness of the gate electrode layer 50 is between 200 and 400 nm. Preferably, the thickness of the gate electrode layer 50 is 300 nm.

[0099] Optionally, the first interlayer dielectric layer 43 may be a single-layer structure or a multi-layer structure, the first interlayer dielectric may be made of at least one of silicon nitride (SiNx) or silicon oxide (SiO2), and the thickness of the first interlayer dielectric is 300 to 500 nm. Preferably, the thickness of the first interlayer dielectric is 400 nm.

[0100] Alternatively, if Figure 2 As shown, the first source-drain electrode 51 is disposed on the side of the first interlayer dielectric layer 43 away from the base substrate 10 and is located in the second interlayer dielectric layer 44. The first source-drain electrode 51 is electrically connected to the active layer 41 through the first via hole 22. The first via hole 22 is defined by the first interlayer dielectric layer 43 and the gate insulating layer 42.

[0101] For example, the non-display area of the display backplane (ie Figure 2 The GOA area on the left side of the middle dashed line can be provided with two first via holes 22, and the display area of the display backplane (ie Figure 2 A first via hole 22 may be provided in the pixel area on the right side of the middle dotted line. The first via hole 22 penetrates the first interlayer dielectric layer 43 and the gate insulating layer 42, and extends to the upper surface of the active layer 41. At least a portion of the first source-drain electrode 51 is deposited in the first via hole 22, so that the first source-drain electrode 51 is electrically connected to the active layer 41.

[0102] In one embodiment, Figure 8As shown, the first source-drain electrode 51 is disposed on the side of the first planar layer 30 facing away from the substrate 10 and is located within the buffer layer 40. The first source-drain electrode 51 is electrically connected to the active layer 41 through the first via 22. Among them, the first via 22 is defined by the buffer layer 40.

[0103] With such a setting, the first via 22 can be only formed in the buffer layer 40 without being formed across layers, which is beneficial to the metal thinning of the first source-drain electrode 51.

[0104] Optionally, as Figure 9 shown, the first source-drain electrode 51 is disposed in the light converging layer 20 and is spaced apart from the light converging unit 21. The first source-drain electrode 51 is electrically connected to the active layer 41 through the first via 22. Among them, the first via 22 is jointly defined by the first planar layer 30 and the buffer layer 40.

[0105] With such a setting, after the first source-drain electrode 51 is formed on the substrate 10, the first source-drain electrode 51 can be used as an alignment mark, and then the light converging layer 20 is formed on the substrate 10. Thus, before forming the light converging layer 20, there is no need to separately fabricate an alignment mark, thereby saving the manufacturing process.

[0106] Optionally, the display backplane further includes a second source-drain electrode 53. The second source-drain electrode 53 is disposed on the side of the second interlayer dielectric layer 44 facing away from the substrate 10 and is located within the second planar layer 45. The second source-drain electrode 53 is electrically connected to the active layer 41 through the second via 54. Among them, the second via 54 is jointly defined by the gate insulating layer 42, the first interlayer dielectric layer 43, and the second interlayer dielectric layer 44.

[0107] Exemplarily, the second source-drain electrode 53 is located in the display area of the display backplane, and the second via 54 penetrates through the second interlayer dielectric layer 44, the first interlayer dielectric layer 43, and the gate insulating layer 42 and extends to the upper side surface of the active layer 41. At least a part of the second source-drain electrode 53 is deposited in the second via 54 to electrically connect the second source-drain electrode 53 to the active layer 41.

[0108] Optionally, the material of the second source-drain electrode 53 is a transparent conductive material, and the thickness of the second source-drain electrode 53 is 30 to 120 nm.

[0109] Exemplarily, the material of the second source-drain electrode 53 can be indium tin oxide (ITO).

[0110] Preferably, the thickness of the second source-drain electrode 53 is 50 to 100 nm.

[0111] With such a setting, the light transmittance of the display area of the display backplane can be improved, thereby further improving the light transmittance performance of the display backplane.

[0112] Example 2

[0113] An embodiment of the present application further provides an electronic device, which includes the display backplane described in the above embodiments of the present application. The electronic device can be any suitable product or component such as a tablet computer, a notebook computer, a camera, a navigator, etc. In a specific application example, the electronic device can be a high-PPI VR headset (virtual reality head-mounted display). For the technical effects of the electronic device, reference can be made to the technical effects of the display backplane described in the above embodiments, which will not be elaborated here.

[0114] Example 3

[0115] An embodiment of the present application further provides a method for manufacturing the above display backplane. As Figure 11 shown, the manufacturing method includes the following steps:

[0116] S101: Form an alignment mark layer 11 on the first surface of the substrate 10;

[0117] S102: According to the alignment mark layer 11, form a light converging layer 20 on the first surface by using a self-alignment process; wherein, the refractive index of the light converging unit 21 is different from that of the first flat layer 30, and the light converging unit 21 is used to converge the light emitted by the backlight source to the opening area 10a of the display backplane;

[0118] S103: Form a first flat layer 30 on the first surface, and the first flat layer 30 covers the light converging layer 20;

[0119] S104: Form a buffer layer 40 on the first flat layer 30, and form an active layer 41 on the buffer layer 40;

[0120] S105: Form a gate insulating layer 42 on the buffer layer 40, and the gate insulating layer 42 covers the active layer 41; and form a gate electrode layer on the gate insulating layer 42;

[0121] S106: Form a first interlayer dielectric layer 43 on the gate insulating layer 42, and the first interlayer dielectric layer 43 covers the gate electrode layer; form a first via 22 penetrating the first interlayer dielectric layer 43 and the gate insulating layer 42, and the first via 22 extends to the active layer 41;

[0122] S107: Form a first source-drain electrode 51 on the first interlayer dielectric layer 43, and the first source-drain electrode 51 is electrically connected to the active layer 41 through the first via 22; form a second interlayer dielectric layer 44 on the first interlayer dielectric layer 43, and the second interlayer dielectric layer 44 covers the first source-drain electrode 51;

[0123] S108: Form a second via hole 54 that penetrates through the second interlayer dielectric layer 44, the first interlayer dielectric layer 43, and the gate insulating layer 42, and the second via hole 54 extends to the active layer 41; form a second source-drain electrode 53 on the second interlayer dielectric layer 44, and the second source-drain electrode 53 is electrically connected to the active layer 41 through the second via hole 54;

[0124] S109: Form a second planarization layer 45 on the second interlayer dielectric layer 44, and the second planarization layer 45 covers the second source-drain electrode 53; and, sequentially form a pixel electrode 46, a passivation layer 47, a common metal electrode, a transparent electrode, and a third planarization layer on the second planarization layer 45.

[0125] In a specific example, as Figures 12 to 20 shown, the manufacturing method of the display backplane includes the following steps:

[0126] (1) As Figure 12 shown, deposit an alignment mark layer 11 on the substrate 10. Among them, the material of the alignment mark layer 11 is Mo or other metals, and the thickness is 50 to 100 nm. To ensure the alignment accuracy, the alignment mark layer 11 is not completely etched.

[0127] (2) As Figure 13 and Figure 14 shown, deposit a light converging layer 20 on the substrate 10. The light converging layer 20 is affected by the design of the opening area 10a of the pixel, and it is necessary to ensure that the light converging position of the light converging unit 21 is in the opening area 10a. At the same time, the indicators affecting the light converging effect of the light converging unit 21 mainly include the refractive index difference between the light converging unit 21 and the first planarization layer 30 and the curvature radius of the light converging unit 21. Among them, the material of the light converging layer 20 can be silicon nitride (SiNx). On the one hand, it can improve the high-temperature resistance of the light converging layer 20, and on the other hand, it can improve the compatibility with the TFT device characteristics. More specifically, the ratio of the diameter D to the sagitta H of the light converging unit 21 is 2 to 11, the refractive index is 1.8 to 2.2, the thickness is 1 to 3 um, the distance between adjacent light converging units 21 is 0 to 2 um, and the stress is -200 to 200 Mpa. When performing the dry etching process of the light converging layer 20, the light converging layer 20 can be used as a mask, and an alignment mark can be formed on the alignment mark layer 11 by using a self-alignment process to improve the alignment accuracy.

[0128] (3) Continue to refer to Figure 14As shown, a first planarization layer 30 is deposited on the substrate 10. Since there are high-temperature processes in the subsequent TFT process, certain requirements are imposed on the planarization effect and high-temperature tolerance of the first planarization layer 30. In addition, the refractive index of the first planarization layer 30 is different from that of the light converging layer 20. For example, the material of the first planarization layer 30 can be silicate glass (SOG), with a thickness of 1 to 5 μm, a refractive index of 1.4 to 1.6, and a temperature tolerance of not less than 350 °C.

[0129] (4) As Figure 15 shown, a buffer layer 40 is deposited on the first planarization layer 30. The buffer layer 40 can adopt a single-layer or stacked structure, and the material of the buffer layer 40 can be silicon nitride (SiNx) or silicon dioxide (SiO2), with a thickness of 200 to 500 nm. Then, an active layer 41 is deposited on the buffer layer 40. Among them, the material of the active layer 41 can be a metal oxide, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), etc., so as to improve the light stability of the active layer 41. After depositing the active layer 41, patterning treatment is performed on the active layer 41.

[0130] (5) As Figure 16 shown, a gate insulating layer 42 is deposited on the buffer layer 40. The material of the gate insulating layer 42 can be selected from silicon dioxide (SiO2) or aluminum oxide (Al2O3), with a thickness of 30 to 150 nm. Then, a gate electrode layer 50 is deposited on the gate insulating layer 42. The material of the gate electrode layer 50 can be selected from Mo, Ti, or Al, etc., with a thickness of 200 to 400 n. After depositing the gate electrode layer 50, photolithography and etching processes are performed.

[0131] (6) As Figure 17 shown, a first interlayer dielectric layer 43 is deposited on the gate insulating layer 42. The material of the first interlayer dielectric layer 43 can be selected from silicon dioxide or silicon nitride, etc., with a thickness of 300 to 500 nm. After depositing the first interlayer dielectric layer 43, a first via 22 is formed on the first interlayer dielectric layer 43 through photolithography and etching processes. Among them, a single via is opened in the display area, and a double via is opened in the non-display area.

[0132] (7) As Figure 18 shown, a first source-drain electrode 51 is deposited on the first interlayer dielectric layer 43. The material of the first source-drain electrode 51 is selected from Ti, Al, or Mo, etc., with a thickness of 300 to 500 nm. After depositing the first source-drain electrode 51, patterning treatment is performed on the first source-drain electrode 51.

[0133] (8) As Figure 19As shown, after depositing the second interlayer dielectric layer 44 on the first interlayer dielectric layer 43, a second via 54 is processed on the second interlayer dielectric layer 44, and a second source / drain electrode 53 is deposited. Among them, the material of the second source / drain electrode 53 can be a transparent conductive material, such as indium tin oxide (ITO), etc., with a thickness of 30 to 120 nm.

[0134] (9) As Figure 20 As shown, a second planarization layer 45 is formed on the second interlayer dielectric layer 44, and the second planarization layer 45 covers the second source / drain electrode 53. And, a pixel electrode 46, a passivation layer 47, a common metal electrode, a transparent electrode, and a third planarization layer are sequentially formed on the second planarization layer 45.

[0135] According to the method for manufacturing a display backplane of the above embodiment of the present application, by forming a light converging layer 20 on the substrate 10, and the light converging unit 21 of the light converging layer 20 can converge the light emitted by the backlight source to the opening area 10a of the display backplane, thereby changing the light output path of the backlight source, improving the light output effect of the opening area 10a, and improving the defect that the proportion of the opening area 10a is reduced due to too high pixel density, thereby affecting the backlight light efficiency, and further improving the display effect of the display backplane.

[0136] Example 4

[0137] The embodiment of the present application also provides a method for manufacturing the above display backplane. Different from the manufacturing method of Embodiment 3, in the manufacturing method of Embodiment 4, the light converging layer 20 of the display backplane and the first planarization layer 30 are formed on the first surface of the substrate 10, and the other layers of the display backplane are formed on the second surface of the substrate 10.

[0138] As Figure 21 As shown, the manufacturing method includes the following steps:

[0139] S201: Form an alignment mark layer 11 on the first surface of the substrate 10;

[0140] S202: According to the alignment mark layer 11, use a self-alignment process to form a light converging layer 20 on the first surface; among them, the refractive index of the light converging unit 21 is different from that of the first planarization layer 30, and the light converging unit 21 is used to converge the light emitted by the backlight source to the opening area 10a of the display backplane;

[0141] S203: Form a first planarization layer 30 on the first surface, and the first planarization layer 30 covers the light converging layer 20; and, form a protective layer 55 on the first planarization layer 30;

[0142] S204: Flip the substrate 10, form a buffer layer 40 on the second surface of the substrate 10 opposite to the first surface, and form an active layer 41 on the buffer layer 40;

[0143] S205: Form a gate insulating layer 42 on the buffer layer 40, and the gate insulating layer 42 covers the active layer 41; and, form a gate electrode layer on the gate insulating layer 42;

[0144] S206: Form a first interlayer dielectric layer 43 on the gate insulating layer 42, and the first interlayer dielectric layer 43 covers the gate electrode layer; form a first via 22 penetrating through the first interlayer dielectric layer 43 and the gate insulating layer 42, and the first via 22 extends to the active layer 41;

[0145] S207: Form a first source-drain electrode 51 on the first interlayer dielectric layer 43, and the first source-drain electrode 51 is electrically connected to the active layer 41 through the first via 22; form a second interlayer dielectric layer 44 on the first interlayer dielectric layer 43, and the second interlayer dielectric layer 44 covers the first source-drain electrode 51;

[0146] S208: Form a second via 54 penetrating through the second interlayer dielectric layer 44, the first interlayer dielectric layer 43 and the gate insulating layer 42, and the second via 54 extends to the active layer 41; form a second source-drain electrode 53 on the second interlayer dielectric layer 44, and the second source-drain electrode 53 is electrically connected to the active layer 41 through the second via 54;

[0147] S209: Form a second planarization layer 45 on the second interlayer dielectric layer 44, and the second layer covers the second source-drain electrode 53; and, sequentially form a pixel electrode 46, a passivation layer 47, a common metal electrode, a transparent electrode and a third planarization layer on the second planarization layer 45.

[0148] In the embodiment of the present application, steps S201 to S203 may be before steps S204 to S209, or steps S201 to S203 may be after steps S204 to S209. The embodiment of the present application does not make specific limitations on this.

[0149] Optionally, the material of the protective layer 55 may be silicon nitride (SiN) or silicon oxynitride (SiON), etc.

[0150] According to the method for manufacturing a display backplane in the above embodiment of the present application, by disposing the light converging layer 20 and the first planarization layer 30 of the display backplane on opposite sides of the other layers of the display backplane, the influence of the light converging layer 20 and the first planarization layer 30 on the TFT device characteristics can be avoided, thereby improving the process stability of the display backplane. In addition, separately manufacturing the light converging layer and the display backplane is beneficial to improving the product yield and reducing costs.

[0151] In this application, unless otherwise clearly specified or limited, terms such as "install", "connect", "couple", "fix", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0152] In this application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the horizontal height of the first feature is lower than that of the second feature.

[0153] The above disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure of this application, components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit this application. In addition, this application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed.

[0154] As described above, the above are only specific embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of various changes or substitutions, and these should all be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A display backplane, characterized in that, Comprising: A substrate; A light converging layer disposed on the substrate and including at least one light converging unit; A first planar layer disposed on the substrate and covering the light converging layer; Wherein, the refractive index of the light converging unit is different from that of the first planar layer, and the light converging unit is configured to converge the light emitted by a backlight source to an opening region of a display backplane; Wherein, the display backplane further includes a buffer layer, an active layer, and a first source-drain electrode, the first source-drain electrode is disposed on the light converging layer and is spaced apart from the light converging unit, the first source-drain electrode is electrically connected to the active layer through a first via hole, wherein the first via hole is defined jointly by the first planar layer and the buffer layer.

2. The display backplane according to claim 1, wherein The sag of the light converging unit is 1 to 3 um, the ratio of the diameter to the sag is 2 to 11, the refractive index is 1.8 to 2.2, the stress is -200 to 200 Mpa, and the spacing between adjacent light converging units is 0 to 2 um; wherein, the material of the light converging layer includes an inorganic material.

3. The display backplane according to claim 1, characterized in that, The light converging layer is deposited on the substrate by a self-alignment process.

4. The display backplane according to claim 1, wherein The display backplane includes a plurality of pixels, and each pixel includes a plurality of sub-pixels; The light converging units are arranged in one-to-one correspondence with the sub-pixels; or, one light converging unit corresponds to a plurality of sub-pixels; or, a plurality of light converging units correspond to one sub-pixel; Wherein, the light converging unit is configured to converge the light emitted by a backlight source to an opening region of a corresponding sub-pixel.

5. The display backplane according to claim 1, characterized in that, The thickness of the first planar layer is 1 to 5 um, the refractive index is 1.4 to 1.6, and the temperature tolerance is not less than 350 °C; wherein, the material of the first planar layer includes silicate glass.

6. The display backplane according to any one of claims 1 to 5, characterized in that, Further comprising: A buffer layer, an active layer, a gate insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a second planar layer, a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planar layer that are sequentially stacked in a direction away from the substrate; And, A gate electrode layer and a first source-drain electrode, the gate electrode layer is disposed on a side of the gate insulating layer away from the substrate and is located within the first interlayer dielectric layer.

7. The display backplane according to claim 6, wherein Further comprising a second source-drain electrode, the second source-drain electrode is disposed on a side of the second interlayer dielectric layer away from the substrate and is located within the second planar layer, the second source-drain electrode is electrically connected to the active layer through a second via hole, wherein the second via hole is defined jointly by the gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer.

8. The display backplane according to claim 7, wherein The material of the second source-drain electrode is a transparent conductive material, and the thickness of the second source-drain electrode is 30 to 120 nm.

9. The display backplane according to claim 6, wherein The buffer layer is a single layer or a multi-layer stack, the material of the buffer layer includes silicon nitride or silicon oxide, and the thickness of the buffer layer is 200 to 500 nm.

10. An electronic device, characterized in that, Comprising the display backplane according to any one of claims 1 to 9.

11. A method for preparing a display backplane, characterized in that, Comprising: Forming an alignment mark layer on a first surface of a substrate; Forming a light converging layer on the first surface by a self-alignment process according to the alignment mark layer; The light converging layer includes at least one light converging unit; Wherein, the light converging unit is configured to converge the light emitted by the backlight to the opening area of the display backplane; A first planarization layer is formed on the first surface, and the first planarization layer covers the light converging layer; the refractive index of the light converging unit is different from that of the first planarization layer; A buffer layer is formed on the first planarization layer, and an active layer is formed on the buffer layer; A gate insulating layer is formed on the buffer layer, and the gate insulating layer covers the active layer; and, a gate electrode layer is formed on the gate insulating layer; A first interlayer dielectric layer is formed on the gate insulating layer, and the first interlayer dielectric layer covers the gate electrode layer; A first via hole penetrating through the first interlayer dielectric layer and the gate insulating layer is formed, and the first via hole extends to the active layer; a first source / drain electrode is formed on the first interlayer dielectric layer, and the first source / drain electrode is electrically connected to the active layer through the first via hole; wherein, the first source / drain electrode is disposed on the light converging layer and is spaced apart from the light converging unit, and the first via hole is defined jointly by the first planarization layer and the buffer layer; A second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first source / drain electrode; A second via hole penetrating through the second interlayer dielectric layer, the first interlayer dielectric layer, and the gate insulating layer is formed, and the second via hole extends to the active layer; a second source / drain electrode is formed on the second interlayer dielectric layer, and the second source / drain electrode is electrically connected to the active layer through the second via hole; A second planarization layer is formed on the second interlayer dielectric layer, and the second planarization layer covers the second source / drain electrode; and, a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planarization layer are sequentially formed on the second planarization layer.

12. A method for preparing a display backplane, characterized in that, Comprising: An alignment mark layer is formed on the first surface of the substrate; According to the alignment mark layer, a light converging layer is formed on the first surface by using a self-alignment process; The light converging layer includes at least one light converging unit; wherein, the light converging unit is configured to converge the light emitted by the backlight to the opening area of the display backplane; A first planarization layer is formed on the first surface, and the first planarization layer covers the light converging layer; the refractive index of the light converging unit is different from that of the first planarization layer; A protective layer is formed on the first planarization layer; The substrate is flipped, and a buffer layer is formed on the second surface of the substrate opposite to the first surface, and an active layer is formed on the buffer layer; A gate insulating layer is formed on the buffer layer, and the gate insulating layer covers the active layer; and, a gate electrode layer is formed on the gate insulating layer; A first interlayer dielectric layer is formed on the gate insulating layer, and the first interlayer dielectric layer covers the gate electrode layer; Form a first via hole that penetrates the first interlayer dielectric layer and the gate insulating layer, and the first via hole extends to the active layer; form a first source-drain electrode on the first interlayer dielectric layer, and the first source-drain electrode is electrically connected to the active layer through the first via hole; wherein, the first source-drain electrode is disposed on the light converging layer and is spaced apart from the light converging unit, and the first via hole is jointly defined by the first planar layer and the buffer layer; Form a second interlayer dielectric layer on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first source-drain electrode; Form a second via hole that penetrates the second interlayer dielectric layer, the first interlayer dielectric layer, and the gate insulating layer, and the second via hole extends to the active layer; form a second source-drain electrode on the second interlayer dielectric layer, and the second source-drain electrode is electrically connected to the active layer through the second via hole; Form a second planar layer on the second interlayer dielectric layer, and the second planar layer covers the second source-drain electrode; and, sequentially form a pixel electrode, a passivation layer, a common metal electrode, a transparent electrode, and a third planar layer on the second planar layer.

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