Signal transmission method, controller, source driver and electronic device

Abstract

The present disclosure relates to a signal transmission method, a controller, a source driver and an electronic device. The signal transmission method is used for transmitting a display signal from the controller to the source driver. The signal transmission method comprises: providing the display signal to the source driver in at least two modes through a low-voltage differential signal interface in a frame display period, the display signal comprising a plurality of display sub-signals, each of the plurality of display sub-signals comprising a mode identification signal, the mode identification signal being used for indicating a mode to which the display sub-signal belongs to the source driver, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs. The method realizes a multi-mode transmission operation between the controller and the source driver, thereby realizing multiplexing of the low-voltage differential signal interface, so that the low-voltage differential signal interface is used for providing image data to the source driver and also used for providing configuration data, thereby reducing the number of interfaces used for signal transmission, and ensuring that various control functions can be flexibly embedded into the source driver.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a signal transmission method, a controller, a source driver, and an electronic device. Background Technology

[0002] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light-emitting diode (OLED) display panel typically includes multiple rows of gate lines and multiple columns of data lines intersecting the gate lines. The timing controller (T-con) of the display panel needs to provide gate signals and data signals to the multiple rows of gate lines and multiple columns of data lines through gate driving circuits and source driving circuits, respectively, so as to form the grayscale voltage required for each gray level of the displayed image in the pixel units of each row in a manner such as, for example, line-by-line scanning, thereby displaying a frame of image. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a signal transmission method for a controller to transmit display signals to a source driver. The method includes: providing display signals to the source driver in at least two modes via a low-voltage differential signal interface within a display frame period, wherein the display signals include a plurality of display sub-signals, each of the plurality of display sub-signals including a mode recognition signal, the mode recognition signal being used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs.

[0004] One embodiment of this disclosure provides another signal transmission method for a source driver to receive display signals from a controller. The source driver includes a low-voltage differential signal interface. The method includes: receiving display signals provided by the controller in at least two modes within a display period through the low-voltage differential signal interface, wherein the display signals include a plurality of display sub-signals, each display sub-signal including a mode recognition signal; determining the mode to which each display sub-signal belongs based on the mode recognition signal for each display sub-signal; and processing each display sub-signal according to the mode to which each display sub-signal belongs.

[0005] At least one embodiment of this disclosure provides a controller for transmitting display signals to a source driver. The controller includes a low-voltage differential signal interface configured to provide display signals to the source driver in at least two modes within a display frame period. The display signals include a plurality of display sub-signals, each of the plurality of display sub-signals including a mode recognition signal. The mode recognition signal is used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs.

[0006] At least one embodiment of this disclosure provides a source driver for acquiring display signals from a controller. The source driver includes: a low-voltage differential signal interface configured to receive display signals provided by the controller within a display period in at least two modes, wherein the display signals include a plurality of display sub-signals, each display sub-signal including a mode recognition signal; a mode determination unit configured to determine the mode to which each display sub-signal belongs based on the mode recognition signal; and a processing unit configured to process each display sub-signal according to the mode to which each display sub-signal belongs.

[0007] At least one embodiment of this disclosure provides an electronic device, including a controller provided in any embodiment of this disclosure; a source driver provided in any embodiment of this disclosure, the source driver being connected to the controller via a low-voltage differential signal interface to receive display signals; and a display panel connected to the source driver to receive drive signals provided by the source driver, the drive signals being generated based on the display signals. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0009] Figure 1A A schematic diagram of a circuit driving system architecture for a display panel is shown.

[0010] Figure 1B This diagram illustrates a structure in which the timing controller TCON and the source driver are connected via a mini-LVDS interface.

[0011] Figure 1C A flowchart of a signal transmission method provided in at least one embodiment of this disclosure is shown;

[0012] Figure 2A A schematic diagram is shown illustrating the signal format of a display sub-signal provided in a row configuration mode according to at least one embodiment of the present disclosure;

[0013] Figure 2B This diagram illustrates the signal format of a display sub-signal provided in a frame configuration mode according to at least one embodiment of the present disclosure;

[0014] Figure 2C This diagram illustrates the signal format of a display sub-signal provided by a calibration configuration mode according to at least one embodiment of the present disclosure;

[0015] Figure 3A and 3BThis diagram illustrates a signal format of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

[0016] Figure 4A A timing diagram of a trigger signal provided in at least one embodiment of the present disclosure is shown;

[0017] Figure 4B A timing diagram of a single-mode indication signal provided in at least one embodiment of the present disclosure is shown;

[0018] Figure 5 A timing diagram illustrating a transmission operation in at least two modes provided by at least one embodiment of the present disclosure is shown.

[0019] Figure 6A A timing diagram of a display sub-signal provided in a row configuration mode according to at least one embodiment of the present disclosure is shown;

[0020] Figure 6B A timing diagram of a display sub-signal provided in a frame configuration mode according to at least one embodiment of the present disclosure is shown;

[0021] Figure 7A A flowchart of another signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 7B A flowchart of another signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 8 A schematic block diagram of a controller provided in at least one embodiment of the present disclosure is shown;

[0024] Figure 9 A schematic block diagram of a source driver provided in at least one embodiment of this disclosure is shown; and

[0025] Figure 10 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0028] The various driving circuits used in display panels typically include scan driver integrated circuits (also known as gate drivers or G-ICs), data driver integrated circuits (also known as source drivers or SD-ICs), and controllers. The controller is mainly used to convert data signals, control signals, and clock signals received from external sources (such as storage devices, network modems, etc.) into data signals, gate signals, control signals, and clock signals suitable for the source drivers and gate drivers, for driving the image display of the display panel. For example, the controller can be a timing controller (TCON). The source drivers are mainly used to receive digital signals (display signals or image signals) and control signals provided by the aforementioned controller, converting the digital signals into corresponding analog grayscale voltage signals through digital-to-analog conversion, and inputting them into the pixel units of each column of the pixel array of the display panel. The gate drivers are mainly used to enable each row of pixel units in the pixel array, for example, row by row (or every other row), and, under the action of control signals, cooperate with the source drivers to input the required data signals to the corresponding pixel units for the enabled pixel units, so that the pixel units can display according to the data signals.

[0029] During the display process, video and animation are composed of countless frames displayed sequentially in chronological order (e.g., frame rate of 60Hz or 120Hz). Each frame is a complete image displayed on the display panel. During the display of a frame, the gate driver sequentially activates each row of pixel units in the pixel array from the first row to the last row for scanning. During this scanning process, the source driver inputs the necessary data signals for each row of pixel units into the activated pixel units, thus completing the scanning and display of a frame. For example, due to the manufacturing process of the pixel units in the display panel, the display screen needs to be continuously refreshed to achieve a clear, complete, and high-quality display effect. Each refresh requires displaying one frame, and multiple consecutively displayed frames visually constitute a static or dynamic image.

[0030] Figure 1A A schematic diagram of a circuit driving system architecture for a display panel is shown. Figure 1A As shown, the circuit-driven system architecture includes a timing controller (TCON), a gate driver (G-IC), a source driver (SD-IC), and a display panel. The architecture also includes a power management integrated circuit (PMIC), a gamma circuit, and a common electrode voltage (Vcom) circuit.

[0031] The input voltage Vin of the power management integrated circuit is, for example, 5V or 12V, while the output voltage includes the digital operating voltage DVDD provided to each IC, the analog voltage AVDD provided to the Gamma and Vcom circuits, the gate turn-on voltage VGH provided to the gate driver G-IC, and the turn-off voltage VGL, etc. The common electrode voltage (Vcom) circuit is used to provide a common voltage for the pixel array.

[0032] The timing controller TCON outputs control signals including those provided to the gate driver G-IC and the source driver SD-IC. For example, the control signals provided to the source driver SD-IC include the start horizontal (STH) signal for the start of horizontal data transmission, the clock pulse horizontal (CPH) signal, the data transmission control signal Load, and the data polarity inversion signal POL. Similarly, the control signals provided to the gate driver G-IC include the start vertical (STV) signal representing the start of a frame scan, the clock pulse vertical (CPV) signal, and the enable signal.

[0033] For example, the digital interface type of the input terminals of the timing controller TCON can be, for example, Low-Voltage Differential Signaling (LVDS), Embedded Display Port (eDP) interface, and V-by-One (Vx1) interface. The digital interface type of the output terminals of the timing controller TCON can be, for example, mini-LVDS, used for communication with the source driver SD-IC.

[0034] LVDS interfaces transmit signals in wire pairs, including a clock pair and several signal pairs. For example, an LVDS signal pair includes three control signals: a vertical sync signal, a horizontal sync signal, and an enable signal. The mini-LVDS interface is similar to the LVDS interface, also transmitting signals using differential signal pairs; however, unlike LVDS signal pairs, the mini-LVDS signal pairs do not transmit control signals. These control signals are transmitted through separate signal lines or differential signal pairs.

[0035] Figure 1B A schematic diagram shows a structure in which the timing controller TCON and the source driver are connected via a mini-LVDS interface. Figure 1B As shown, the timing controller TCON provides control signals and image data signals to multiple source drivers. These source drivers may include, for example, source driver SD#1, source driver SD#2, etc. The number of source drivers depends on the physical resolution of the display panel; for a single display panel, this may require dozens or even hundreds. Each source driver is connected via clock signal pairs for transmitting clock signals, mini-LVDS signal pairs for transmitting image data signals, and control signal lines for transmitting multiple control signals. The mini-LVDS signal pairs can be 3 or 6 pairs. The control signal lines may or may not be differential pairs. The mini-LVDS signal lines and the multiple control signal lines are independent of each other.

[0036] For example, the timing controller TCON and the source driver SD#1 are connected via mini-LVDS signal pairs for transmitting data signals, LOAD control signal lines for transmitting data transmission control signals LOAD, POL control signal lines for transmitting control signals POL, and POL2 control signal lines for transmitting control signals POL2; TCON and the source driver SD#2 are also connected via mini-LVDS signal pairs, LOAD control signal lines, and data polarity inversion control signal lines (e.g., POL control signal lines, POL2 control signal lines, and POLC control signal lines).

[0037] Other control signal lines may also be included between each source driver and TCON, such as horizontal dot inversion (H2DOT) control signal lines, bias voltage (PWRC) control signal lines, etc.

[0038] like Figure 1B As shown, the mini-LVDS signal pairs are only used to transmit image data signals and not to transmit control signals such as polarity inversion configuration information or data transmission control information. Therefore, there are multiple signal lines and multiple signal line interfaces between the timing controller and the source drivers, resulting in a large amount of signal routing space occupied in the display panel, especially when the number of source drivers is large. If the available signal routing space in the display panel is insufficient to accommodate these multiple data lines, then some commonly used control functions cannot be flexibly embedded into the source drivers.

[0039] To address this, embodiments of this disclosure provide a signal transmission method for a controller to transmit display signals to a source driver. This signal transmission method includes providing display signals to the source driver in at least two modes via a low-voltage differential signal interface within one display frame period. The display signals include multiple display sub-signals, each of which includes a mode recognition signal. The mode recognition signal indicates to the source driver the mode to which the display sub-signal belongs, enabling the source driver to process the display sub-signal according to its mode. This signal transmission method achieves multi-mode transmission operation between the controller and the source driver through the mode recognition signal, thereby enabling the multiplexing of the low-voltage differential signal interface. This allows the interface to be used for both providing image data and configuration data to the source driver, reducing the number of interfaces used for signal transmission and ensuring that various control functions can be flexibly embedded into the source driver.

[0040] Figure 1C A flowchart illustrating a signal transmission method provided by at least one embodiment of this disclosure is shown. For example, the signal transmission method provided by the embodiments of this disclosure is applicable to both LVDS interfaces and mini-LVDS interfaces.

[0041] like Figure 1C As shown, the signal transmission method includes steps S10 and S20. Figure 1C The provided signal transmission method is, for example, by Figure 1A The timing controller TCON in the system executes this. For example, this signal transmission method is used by the timing controller TCON to transmit display signals to the source driver SD-IC.

[0042] Step S10: Obtain the display signal.

[0043] Step S20: Within a display frame period, a display signal is provided to the source driver in at least two modes through a low-voltage differential signal interface. The display signal includes multiple display sub-signals, each of which includes a mode recognition signal. The mode recognition signal is used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs.

[0044] For step S10, the display signal may include, for example, image data and configuration data. For instance, the timing controller TCON receives an LVDS differential signal from an external source and analyzes the LVDS differential signal to separate the image data, such as RGB data.

[0045] In the embodiments provided in this disclosure, the display signals provided by the low-voltage differential signal interface include both configuration data (e.g., control signals) and image data; therefore, multiple control signal lines independent of mini-LVDS or LVDS signal lines are no longer required between the controller and the source driver. For example, Figure 1B The LOAD control signal line, data polarity inversion control signal line (e.g., POL control signal line, POL2 control signal line, and POLC control signal line), horizontal dot inversion (H2DOT) control signal line, bias voltage (PWRC) control signal line, etc., can be omitted. For example, the signal transmission method provided in the embodiments of this disclosure includes only mini-LVDS signal lines and clock signal lines between the source driver and the controller, and each of the source driver and the controller may only include a mini-LVDS interface and a clock signal interface. Of course, the source driver and the controller may also include other interfaces for backup, such as the LOAD control signal line, the data polarity inversion control signal line POL, etc.

[0046] Therefore, embodiments of this disclosure reduce the number of interfaces and signal lines used for signal transmission, and ensure that various control functions can be flexibly embedded into the source driver.

[0047] For example, configuration data can be generated by the timing control module in the timing controller. This configuration data is used to configure the source driver, enabling it to receive and store the configuration data before processing image data. For instance, the source driver outputs image data to the pixel array based on the timing provided by the configuration data.

[0048] In some embodiments of this disclosure, the configuration data includes control signals required during the display of RGB data by the pixel array. For example, if the display panel is a liquid crystal display panel, then the polarity of the liquid crystal molecules needs to be controlled during the display of RGB data by the liquid crystal display panel. The control signals may include data polarity inversion control signals (e.g., POL control signals, POL2 control signals, and POLC control signals). As another example, a row data start signal is needed during the display of RGB data by the pixel array. The control signals may include a row data start signal STH. Furthermore, the display panel may also be an OLED display panel, etc., and the embodiments of this disclosure do not limit this.

[0049] The configuration data can be set by those skilled in the art according to actual needs. This disclosure does not limit the configuration data. The above-mentioned data polarity reversal control signal, frame scan start signal and row data start signal are only examples.

[0050] For step S20, in embodiments of this disclosure, the low-voltage differential signal interface includes multiple pairs of transmission lines, each pair of transmission lines including two complementary differential signals, through which image data and configuration data are transmitted. For example, the low-voltage differential signal interface can be a mini-LVDS interface or an LVDS interface, etc.

[0051] A display cycle includes, for example, an active frame and a vertical blanking period (VBP). During the active frame, for example, pixels in the pixel array display image data line by line, while during the vertical blanking period, preparation is made for the display of the next frame of image data.

[0052] In some embodiments of this disclosure, for example, display signals are provided to the source driver sequentially in at least two modes via a low-voltage differential signal interface.

[0053] For example, the display signal includes at least one display sub-signal provided by each of at least two modes.

[0054] For example, each mode provides display sub-signals including configuration data and image data. Alternatively, at least two modes include a first mode and a second mode, where the first mode includes both configuration data and image data, and the second mode includes configuration data. Another example is that the first mode includes configuration data, and the second mode includes image data.

[0055] In some embodiments of this disclosure, at least one of at least two modes is a row configuration mode, the configuration data includes row configuration data, and the display sub-signals provided by the row configuration mode include row configuration data and row image data.

[0056] The row configuration mode provides display sub-signals to configure the source driver for displaying image data for a row of pixels. Row image data is, for example, the RGB data corresponding to that row in the pixel array. Row configuration data is used to configure the source driver, causing it to output the row image data and timing control signals to the corresponding row of pixels in response to the row configuration data.

[0057] In some embodiments of this disclosure, at least one of at least two modes is a frame configuration mode. The configuration data includes frame configuration data, and the display sub-signals provided by the frame configuration mode include frame configuration data.

[0058] The display sub-signals provided by the frame configuration mode are used to configure the source driver for displaying a frame of image. Frame configuration data, for example, is used to configure the source driver so that the source driver outputs control signals for that frame of image. Frame configuration data may include, for example, a gamma setting signal, an AMP offset control signal, a shift direction selection signal, etc.

[0059] In some embodiments of this disclosure, at least one of at least two modes includes a calibration configuration mode, the configuration data includes a calibration signal, and the display sub-signal provided by the calibration configuration mode includes a calibration signal, for example, the calibration signal is used to calibrate the timing of the clock signal of the source driver and the display signal.

[0060] In embodiments of this disclosure, each display sub-signal provided in row configuration mode, each display sub-signal provided in frame configuration mode, and each display sub-signal provided in correction configuration mode includes a pattern recognition signal for distinguishing whether the display sub-signal is provided by the controller in row configuration mode, by the controller in frame configuration mode, or by the controller in correction configuration mode.

[0061] In some embodiments of this disclosure, display signals are provided to the source driver via the low-voltage differential signal interface according to at least two signal formats defined by a first signal transmission protocol. The following is in conjunction with... Figures 2A-2C This example illustrates the signal format of at least two modes defined by the first signal transmission protocol.

[0062] Figure 2A A schematic diagram is shown of the signal format of a display sub-signal provided in a row configuration mode according to at least one embodiment of the present disclosure.

[0063] exist Figure 2AThe example illustrates a first and second display sub-signal provided to the source driver in row configuration mode. It is important to understand that the first and second display sub-signals are merely illustrative of the signal format for display sub-signals provided in row configuration mode and do not imply that only two display sub-signals are provided to the source driver in row configuration mode. In practice, the number of display sub-signals provided to the source driver in row configuration mode can be the same as the number of rows in the pixel array; that is, display sub-signals are provided to each row of pixels separately in row configuration mode.

[0064] like Figure 2A As shown, the display sub-signals provided by the row configuration mode include a pattern recognition signal A to indicate that the display sub-signals belong to the row configuration mode.

[0065] like Figure 2A As shown, the display sub-signals provided by the row configuration mode include row configuration data and row image data (e.g., RGB data of a row of pixels). In the following embodiments, RGB (red, green, blue) data is used as an example of image data; however, it should be noted that this disclosure is not limited to this. For example, some display devices may also use image data in forms such as RGBW (red, green, blue, white). For example, the first display sub-signal includes first row configuration data and first row RGB data, and the second display sub-signal includes second row configuration data and second row RGB data.

[0066] It should be noted that the first row of RGB data refers to the RGB data of any randomly selected row of sub-pixels in the pixel array, and the configuration data of the first row is always the configuration data corresponding to the RGB data of that row of sub-pixels.

[0067] In some embodiments of this disclosure, such as Figure 2A As shown, the display sub-signals provided by the row configuration mode include combined data, which combines the row configuration data of each row with the row image data of each row in the image data. For example, the first display sub-signal is composed of the first row configuration data and the first row RGB data, and the second display sub-signal is composed of the second row configuration data and the second row RGB data. That is, the controller sequentially provides the display sub-signals corresponding to each row of pixels to the source driver. In this embodiment, the configuration data and image data of a row are combined and transmitted through a low-voltage differential signal interface, which not only realizes the multiplexing of the low-voltage differential signal interface, but also facilitates the source driver to process the image data of each row in a timely manner according to the configuration data of each row for image display.

[0068] exist Figure 2AIn the signal format example shown, for each display sub-signal, the row configuration data precedes the RGB data. That is, for each display sub-signal, the controller first provides the row configuration data to the source driver, and then provides the RGB data for that row to the source driver. Providing the row configuration data to the source driver first, and then providing the RGB data for that row to the source driver, makes it easier for the source driver to process the RGB data of that row in a timely manner according to the row configuration data.

[0069] Figure 2B A schematic diagram of the signal format of a display sub-signal provided by a frame configuration mode according to at least one embodiment of the present disclosure is shown.

[0070] like Figure 2B As shown, the display sub-signals provided by the frame configuration mode include frame configuration data and invalid data.

[0071] like Figure 2B As shown, the display sub-signals provided by the frame configuration mode include a pattern recognition signal B to indicate that the display sub-signals belong to the frame configuration mode.

[0072] In some embodiments of this disclosure, for example, a frame configuration mode is applied during vertical blanking. During vertical blanking, the pixel array does not display image data, therefore the display sub-signals provided by the frame configuration mode may include invalid data.

[0073] In other embodiments of this disclosure, if the data length of the frame configuration data is the same as the data length of the combined data provided by the row configuration mode, the display sub-signals provided by the frame configuration mode may also not include invalid data. In embodiments of this disclosure, invalid data may, for example, refer to data signals at a logic invalid level.

[0074] exist Figure 2B In the signal format example shown, for each display sub-signal, the frame configuration data is placed before the invalid data. That is, for each display sub-signal, the controller first provides the frame configuration data to the source driver, and then provides the invalid data to the source driver.

[0075] Figure 2C A schematic diagram of the signal format of a display sub-signal provided by a correction configuration mode according to at least one embodiment of the present disclosure is shown.

[0076] like Figure 2C As shown, the display sub-signals provided by the calibration configuration mode include calibration signals. For example, in at least one example, the calibration signal may include, for instance, the delay time length of a clock signal or a data signal used to calculate the delay time length of the clock signal. Those skilled in the art can set the calibration signal according to relevant calibration methods. In some embodiments of this disclosure, the controller provides the calibration signal to the source driver in calibration configuration mode during vertical blanking.

[0077] For example, the transmission of display signals depends on clock signals. Ideally, the rising edge of the clock signal should be aligned with the midpoint of the effective logic level of the display signal. However, in practice, delays in the clock or display signals can cause misalignment between the rising edge of the clock signal and the midpoint of the effective logic level of the display signal. Therefore, correction is required for the clock or display signal. For example, a correction signal might be used to align the rising edge of the clock signal with the midpoint of the effective logic level of the display signal.

[0078] like Figure 2C As shown, the display sub-signals provided by the calibration configuration mode include a pattern recognition signal C to indicate that the display sub-signals belong to the calibration configuration mode.

[0079] In some embodiments of this disclosure, at least two transmission modes include at least two of line configuration mode, frame configuration mode, and correction configuration mode.

[0080] For example, at least two modes include line configuration mode and frame configuration mode. The display sub-signals provided by line configuration mode include line configuration data and image data, while the display sub-signals provided by frame configuration mode include frame configuration data. Please refer to the description above for an explanation of line configuration mode and frame configuration mode.

[0081] In some embodiments of this disclosure, at least two modes also include a calibration configuration mode. The calibration configuration mode provides a display sub-signal including a calibration signal used to correct the timing of the source driver's clock signal and the display signal. Please refer to the description above for an explanation of the calibration configuration mode.

[0082] In some embodiments of this disclosure, since RGB image data needs to be transmitted during image display but not during vertical blanking, display sub-signals are transmitted in different modes during image display and vertical blanking.

[0083] For example, at least two modes include a row configuration mode and a frame configuration mode. During image display, the row configuration mode transmits the display sub-signals required for displaying image data for each row of pixels to the source driver. During vertical blanking, the frame configuration mode transmits the display sub-signals required during vertical blanking to the source driver. For example, the frame configuration mode and the correction configuration mode are used during the vertical blanking period within a frame display cycle. The frame configuration mode and the correction configuration mode enable the source driver to perform frame configuration and timing correction during vertical blanking to prepare for the display of the next image frame. Because frame configuration and timing correction are performed during vertical blanking, time is saved and display efficiency is improved.

[0084] In some embodiments of this disclosure, the frame configuration mode includes a power control sub-mode that provides the source driver with less processing signals during vertical blanking to control (e.g., reduce) the power consumption of the source driver at least during vertical blanking, thereby controlling the overall power consumption of the system.

[0085] For example, the frame configuration data includes power configuration sub-data used to reduce the power consumption of the source driver, at least during vertical blanking. For example, in response to the power configuration sub-data, the source driver enters a low-power operating state, in which at least some circuit modules of the source driver are powered down, thereby reducing the power consumption of the source driver, at least during vertical blanking. The processing signal provided by the power control sub-mode may, for example, be a logic invalid level. In embodiments of this disclosure, for example, the logic invalid level may be a low-level signal representing a processing signal "0", and the logic valid level may, for example, be a high-level signal representing a processing signal "1". During the low-power operating state of the source driver, the controller provides a logic invalid level to the source driver to reduce power consumption during vertical blanking. For example, the power configuration sub-data includes at least some circuit modules of the source driver that are disabled during vertical blanking. Those skilled in the art can define the circuit modules disabled during vertical blanking in the power configuration sub-data to issue the disabled circuit modules to the source driver, causing the source driver to disable the circuit modules in the power configuration sub-data during vertical blanking. In some embodiments of this disclosure, disabling a circuit module may mean powering off that circuit module.

[0086] For example, if the power consumption configuration subdata indicates that the circuit module disabled in the vertical blanking device includes the output driver, then the source driver is configured to power down the output driver during vertical blanking.

[0087] In some embodiments of this disclosure, each display sub-signal includes a data signal. That is, each display sub-signal includes a data signal in addition to a pattern recognition signal. The data signal may include, for example, the image data and configuration data described above. Providing the display signal to the source driver sequentially in at least two modes via a low-voltage differential signal interface includes: providing a plurality of display sub-signals sequentially to the source driver in at least two modes via a low-voltage differential signal interface, wherein for each display sub-signal, after providing a pattern recognition signal to the source driver via the low-voltage differential signal interface, a data signal is then provided to the source driver via the low-voltage differential signal interface.

[0088] For example, for a display sub-signal provided in row configuration mode, the controller first provides a pattern recognition signal A to the source driver through a low-voltage differential signal interface, and then provides row configuration data and row image data to the source driver through the low-voltage differential signal interface.

[0089] like Figures 2A-2C As shown, the pattern recognition signal of the display sub-signal provided in each mode can be located before the configuration data. That is, the controller first provides the pattern recognition signal of each display sub-signal to the source driver, and then provides the configuration data of that display sub-signal to the source driver. For example, for the row configuration mode, the controller first provides the pattern recognition signal A to the source driver, then provides the row configuration data to the source driver, and then provides the row image data to the source driver. As another example, for the frame configuration mode, the controller first provides the pattern recognition signal B to the source driver, then provides the frame configuration data to the source driver, and then provides invalid data to the source driver. As yet another example, for the correction configuration mode, the controller first provides the pattern recognition signal C to the source driver, and then provides the correction signal to the source driver. In embodiments of this disclosure, invalid data can be, for example, a logic invalid level signal, such as a low-level signal.

[0090] The pattern recognition signal is located before the configuration data, which enables the source driver to promptly and correctly parse and process the subsequently received data according to the pattern to which the display sub-signal belongs, so as to obtain row configuration data, frame configuration data or correction signals, etc.

[0091] Figure 3A and 3B A schematic diagram of a display signal format provided by a controller to a source driver according to at least one embodiment of the present disclosure is shown.

[0092] like Figure 3A As shown, in a frame display cycle (including the image display period and the vertical blanking period), the display signals include multiple display sub-signals 301 provided in row configuration mode, display sub-signals 302 provided in frame configuration mode, and display sub-signals 303 provided in correction configuration mode.

[0093] For example, during image display, multiple display sub-signals 301 are provided in a line configuration mode, during vertical blanking, display sub-signals 302 are provided in a frame configuration mode, and display sub-signals 303 are provided in a correction configuration mode.

[0094] like Figure 3A As shown, within one frame display period, providing display signals to the source driver in at least two modes via a low-voltage differential signal interface includes: within one frame display period, providing display signals to the source driver sequentially in at least two modes using a low-voltage differential signal interface, and for each mode, providing one or more display sub-signals to the source driver sequentially using a low-voltage differential signal interface.

[0095] For example, in Figure 3AIn the example, multiple display sub-signals 301 are first provided to the source driver in row configuration mode using a low-voltage differential signal interface, then display sub-signals 302 are provided to the source driver in frame configuration mode, and finally display sub-signals 303 are provided to the source driver in calibration configuration mode. For example, in the row configuration mode including multiple display sub-signals 301, multiple display sub-signals 301 are provided to the source driver sequentially using a low-voltage differential signal interface. That is, in Figure 3A In the example, multiple display sub-signals 301 are first provided to the source driver using the low-voltage differential signal interface, then display sub-signals 302 are provided to the source driver using the low-voltage differential signal interface, and then display sub-signals 303 are provided to the source driver using the low-voltage differential signal interface.

[0096] like Figure 3A As shown, each display sub-signal 301 provided in row configuration mode includes row data (LPC) and image data (e.g., RGB data). Figure 3B As shown, the row data LPC includes a pattern recognition signal A and row configuration data. For example, the pattern recognition signal A includes a reset signal RESET and a row mode start signal LPC Start. For example, the row mode start signal can be a logic invalid level, such as "000 000". Please refer to the description above for the pattern recognition signal and row configuration data of the row configuration mode.

[0097] like Figure 3A As shown, each display sub-signal 302 provided in frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The display sub-signals provided in frame configuration mode include data signals 312 provided in power control sub-mode. (As shown...) Figure 3B As shown, the Frame Data Programming (FPC) includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the Frame Data Programming (FPC) is a reset signal RESET and a frame mode start signal FPC Start. For example, the frame mode start signal differs from the line mode start signal to distinguish between frame configuration mode and line configuration mode; the frame mode start signal can be, for example, a logic active level such as "111 111". Please refer to the description above for the pattern recognition signal and frame configuration data for the frame configuration mode.

[0098] During the period when the controller provides data signals 312 (including invalid data IDLE0 and invalid data IDLE1) to the source driver in power configuration sub-mode, at least some circuit modules in the source driver are in a power-down state to save power.

[0099] like Figure 3AAs shown, the frame configuration mode includes a power control sub-mode. The display sub-signal 302 provided in frame configuration mode includes processing signals provided to the source driver in power control sub-mode, such as invalid data IDLE0 and invalid data IDLE1. During the period when the controller provides invalid data IDLE0 and invalid data IDLE1 to the source driver in power control sub-mode, at least a portion of the circuitry in the source driver is in a power-down state to conserve power. Figure 3A In the example, before providing invalid data IDLE0 to the source driver in power control sub-mode, the controller provides the trigger signal PSI to the source driver again to indicate that the source driver enters a low-power operating state.

[0100] like Figure 3A As shown, each display sub-signal 303 provided in the calibration configuration mode includes calibration data ASC. (As...) Figure 3B As shown, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C can be, for example, a logic invalid level. Please refer to the description above for information about the correction signal.

[0101] like Figure 3A As shown, after transmitting the display signal for one display cycle to the source driver, the display signal for the next display cycle continues to be transmitted to the source driver.

[0102] like Figure 3A As shown, before providing each display sub-signal to the source driver, a trigger signal is provided to the source driver to notify the source driver to perform a transfer operation for at least two modes.

[0103] In some embodiments of this disclosure, the controller can transmit display signals to the source driver in a single mode, in addition to transmitting display signals to the source driver in at least two modes.

[0104] In this embodiment, the trigger signal notifies the source driver of at least two modes of transmission operations, which facilitates compatibility between the source driver and the controller with other transmission operations besides the at least two modes. For example, in addition to at least two modes of transmission operations, the controller and the source driver can also compatiblely perform single-mode transmission operations. For example, a display signal that can be transmitted in at least two modes conforms to a first signal transmission protocol, and a display signal that can be transmitted to the source driver in a single mode conforms to a second signal transmission protocol. If the controller and the source driver perform at least two modes of transmission operations, the controller first provides a trigger signal to the source driver as an indication signal for at least two modes of transmission operations; if the controller and the source driver perform a single-mode transmission operation, the controller first provides the source driver with a single-mode indication signal different from the trigger signal. The second signal transmission protocol can be a protocol different from the first signal transmission protocol, such as some transmission protocols in related technologies. By setting a trigger signal, signal line multiplexing can be achieved, enabling the chip to have multiple functions, thereby reducing the difficulty of promoting the first signal transmission protocol.

[0105] In some embodiments of this disclosure, the trigger signal includes at least one trigger sub-signal, and providing the trigger signal to the source driver includes: sequentially providing at least one trigger sub-signal to the source driver, each trigger sub-signal including a set timing relationship between a data transmission control signal and a data polarity inversion control signal.

[0106] In some embodiments of this disclosure, for example, the trigger signal includes two trigger sub-signals. In response to receiving two consecutive trigger sub-signals, the source driver determines to perform a signal transmission operation in at least two modes. Using multiple trigger sub-signals as the trigger signal can at least partially avoid noise interference and improve the accuracy of pattern recognition.

[0107] In some embodiments of this disclosure, the timing relationship between the data transmission control signal and the data polarity inversion control signal includes: the first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least a portion of the time.

[0108] The data polarity inversion control signal controls the polarity reversal of the source driver's output data signal by switching between high and low levels, thereby achieving AC driving of the LCD. The data transmission control signal is used to latch the data input to the source driver and the data polarity inversion signal on the rising edge, and to release the data to the panel on the falling edge.

[0109] In this example, the controller and source driver can be connected via mini-LVDS, POL, and LOAD signal lines. Therefore, other control signal lines such as POL2 and POLC, H2DOT (Horizontal Dot Inversion) and PWRC (Bias Voltage Control) lines can be omitted, either wholly or partially. Thus, this example not only reduces the number of signal lines between the controller and source driver but also informs the source driver which transmission operation to perform to ensure compatibility with single-mode transmission operations.

[0110] Figure 4A A timing diagram of a trigger signal provided in at least one embodiment of the present disclosure is shown.

[0111] like Figure 4A As shown, the trigger signal includes at least two (two, three or more) trigger sub-signals. For example, in the case of two trigger sub-signals, the trigger signal includes trigger sub-signal PSI1 and trigger sub-signal PSI2.

[0112] Both trigger sub-signals PSI1 and PSI2 include a data transmission control signal LOAD and a data polarity reversal control signal POL, and the data transmission control signal LOAD and the data polarity reversal control signal POL satisfy a set timing relationship.

[0113] like Figure 4A As shown, the timing relationship is set such that the first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than the second transition edge (e.g., rising edge) of the data data transmission control signal LOAD, and the first transition state (e.g., high level state) of the data polarity inversion control signal POL after the first transition edge coincides with the second transition state (e.g., high level state) of the data transmission control signal LOAD after the second transition edge for at least a portion of the time. The time interval tLD_RST is the time interval between the rising edge of the data transmission control signal LOAD and the reset signal; please refer to [reference needed]. Figure 5 The description is as follows. For example, if the source driver receives the rising edge of the data polarity inversion control signal POL in the second trigger sub-signal, it determines to perform a transfer operation in at least two modes.

[0114] In some embodiments of this disclosure, for example, the driver in the controller can be adjusted such that, within the same cycle of the data transmission control signal LOAD and the data polarity inversion control signal POL, the data polarity inversion control signal POL occurs later than the data transmission control signal LOAD by a time length tS2, thereby causing the rising edge of the data polarity inversion control signal POL to occur later than the rising edge of the data transmission control signal LOAD. The data polarity inversion control signal POL and the data transmission control signal LOAD are simultaneously at a high level for a time length tH2 after their rising edges.

[0115] Figure 4B A timing diagram of a single-mode indication signal provided in at least one embodiment of the present disclosure is shown.

[0116] like Figure 4B As shown, the single-mode indication signal includes a data transmission control signal LOAD' and a data polarity inversion control signal POL', and the first transition edge (e.g., rising edge) of the data polarity inversion control signal POL' precedes the second transition edge (e.g., rising edge) of the data transmission control signal LOAD', and the first transition state (e.g., high level state) of the data polarity inversion control signal POL' after the first transition edge coincides with the second transition state (e.g., high level state) of the data transmission control signal LOAD' after the second transition edge at least for a portion of the time.

[0117] In some embodiments of this disclosure, for example, the driver in the controller can be adjusted such that, within the same cycle of the data transmission control signal LOAD' and the data polarity inversion control signal POL', the data polarity inversion control signal POL' precedes the data transmission control signal LOAD' by a time length tS1, thereby causing the rising edge of the data polarity inversion control signal POL' to precede the rising edge of the data transmission control signal LOAD'.

[0118] Figure 4A and Figure 4B The embodiments can distinguish between single-mode transmission operations and transmission operations with at least two modes through data transmission control signals and data polarity reversal control signals, without requiring modifications to the interface hardware circuitry, making them easy to implement. Thus, the same set of controllers and source drivers can select to implement either the first or second signal transmission protocol as needed, without requiring separate sets of controllers and source drivers for the first and second signal transmission protocols. Therefore, this reduces design, development, manufacturing, and management costs for suppliers.

[0119] Figure 5 A timing diagram illustrating a transmission operation in at least two modes provided by at least one embodiment of the present disclosure is shown.

[0120] like Figure 5 As shown, in this example, the signals that operate in at least two modes include the data transmission control signal LOAD, the data polarity reversal control signal POL, and the low voltage differential signal.

[0121] It should be noted that the low-voltage differential signal is transmitted by multiple differential signal pairs, such as 3 or 6 differential signal pairs, with each differential signal pair serving as a signal transmission channel. Since the signal transmission method is similar for each differential signal pair, the timing relationship between only one signal transmission channel LV0 and the data transmission control signal LOAD and the data polarity inversion control signal POL is shown in the example disclosed herein.

[0122] like Figure 5 As shown, the controller provides the data transmission control signal LOAD and the data polarity reversal control signal POL to the source driver according to the set timing relationship as trigger signals. Figure 5 In the example, only one trigger sub-signal PSI is shown as the trigger signal.

[0123] After providing a trigger signal to the source driver, the interval length t HD Then, it provides pattern recognition signals and configuration data to the source driver.

[0124] For example, if the display sub-signal is provided to the source driver in row configuration mode, then during time length t... HD Subsequently, the controller sequentially provides a reset signal and a row mode start signal to the source driver as pattern recognition signals for the row configuration mode. For example, those skilled in the art can set a first time length t between the rising edge of the data polarity inversion control signal POL and the rising edge of the data transmission control signal LOAD in the timing controller. SET The time interval tLD_RST between the rising edge of the data transmission control signal LOAD and the reset signal is used to calculate the time length t between the rising edge of the data polarity reversal control signal POL and the reset signal. HD Alternatively, those skilled in the art can directly set the time length t between the rising edge of the data polarity reversal control signal POL and the reset signal. HD .

[0125] After providing a pattern recognition signal to the source driver, the controller provides row configuration data to the source driver. Then, it provides row image data to the source driver.

[0126] In some embodiments of this disclosure, the row configuration data may be, for example, a row data packet including 16 bits, such as the row data packet including the 0th bit data LPC[0], the 1st bit data LPC[1], ..., the 15th bit data LPC

[15] .

[0127] Table 1 illustrates the definition of an exemplary row data packet provided in at least one embodiment of this disclosure.

[0128] Table 1

[0129]

[0130] As shown in Table 1, in one type of row configuration data provided in this disclosure, the row configuration data includes a frame start indication signal. For example, the 0th bit LPC[0] of the row data packet is the frame start indication signal. In the row configuration data of the first display row of each frame, LPC[0] is, for example, high.

[0131] As shown in Table 1, in a row configuration data provided in this disclosure, the row configuration data includes a data polarity inversion control signal. For example, the first bit of the row data packet LPC[1] is the data polarity inversion control signal POL; the second bit of the row data packet LPC[2] is the data polarity inversion control signal POLC; and the third bit of the row data packet LPC[3] is the data polarity inversion control signal POL2.

[0132] As shown in Table 1, in a row configuration data provided in this disclosure, the row configuration data includes charge sharing function control signals. For example, bits 4 to 7 of the row data packet, i.e., LPC[4:7], are charge sharing control bits used to control charge sharing.

[0133] As shown in Table 1, the row configuration data provided in this disclosure also includes reserved bits, which are used to flexibly add some row configurations and improve configuration flexibility. For example, bits 8 to 15, namely LPC[8:15], are reserved bits.

[0134] It should be noted that Table 1 is merely an example of a row data packet definition and is not intended to limit the embodiments of this disclosure. Those skilled in the art can design other row data packet definitions. For example, row data packets can also be 8-bit, 32-bit, 64-bit, etc.

[0135] For example, if the display sub-signal is provided to the source driver in frame configuration mode, then during time length t... HD Subsequently, the controller sequentially provides a reset signal and a frame mode start signal to the source driver as pattern recognition signals for the frame configuration mode. After providing the frame configuration mode pattern recognition signal to the source driver, the controller provides frame configuration data to the source driver.

[0136] In some embodiments of this disclosure, the frame configuration data may be, for example, a 256-bit frame data packet, such as a frame data packet including the 0th bit data FPC[0], the 1st bit data FPC[1], ..., the 255th bit data FPC

[255] .

[0137] Table 2 shows a definition of an exemplary frame data packet provided in at least one embodiment of this disclosure.

[0138] Table 2

[0139]

[0140]

[0141] As shown in Table 2, in a frame configuration data provided in this disclosure, the frame configuration data includes receiver offset setting, receiver enable setting, display data inversion, shift direction selection, amplification (AMP) offset control, channel amplifier chopping control, gamma buffer chopping control, channel number control, and source driver identifier (ID).

[0142] For example, in some embodiments of this disclosure, the frame configuration data further includes the configuration of differential signal pairs. For example, in the example in Table 2, the 21st bit of the frame configuration data, FPC

[21] , represents the configuration of differential signal pairs. For example, if FPC

[21] is 0, it indicates that 3 pairs of differential signal pairs are used to transmit the display signal; if FPC

[21] is 1, it indicates that 6 pairs of differential signal pairs are used to transmit the display signal. In embodiments of this disclosure, for example, "1" represents a high level and "0" represents a low level.

[0143] For example, in the example in Table 2, the 22nd bit of the frame configuration data, FPC

[22] , represents the number of bits transmitted per cycle. For example, if FPC

[22] is 0, it means 6 bits are transmitted per cycle; if FPC

[22] is 1, it means 8 bits are transmitted per cycle.

[0144] It should also be noted that Table 2 is merely an example of a frame data packet definition and is not intended to limit the embodiments of this disclosure. Those skilled in the art can design other frame data packet definitions. For example, frame data packets can also be 8-bit, 32-bit, 64-bit, etc.

[0145] For example, if the display sub-signal is provided to the source driver in a calibration configuration mode, then during time length t... HD Subsequently, the controller provides a logic invalid level to the source driver as a pattern recognition signal to correct the configuration mode. After providing the logic invalid level to the source driver, a correction signal is provided to the source driver. The duration of this logic invalid level is, for example, the same as the duration of the reset signal. Those skilled in the art can set the duration of the logic invalid level as needed.

[0146] Figure 6A A timing diagram of a display sub-signal provided in a row configuration mode according to at least one embodiment of the present disclosure is shown.

[0147] like Figure 6A As shown, this timing diagram includes a clock signal CLK, a data transmission control signal LOAD, a data polarity inversion control signal POL, and low-voltage differential signals. Only one signal transmission channel, LV0, of the low-voltage differential signals is shown in the diagram.

[0148] like Figure 6A As shown, the controller provides the data transmission control signal LOAD and the data polarity reversal control signal POL to the source driver according to the set timing relationship as trigger signals.

[0149] After providing a trigger signal to the source driver, the interval length t HD Then, a reset signal RESET and a row mode start signal LPC Start are provided to the source driver as mode recognition signals for the row configuration mode. For example... Figure 6A As shown, the row mode start signal LPC Start can be a digital logic signal 0. In embodiments of this disclosure, for example, a low-level signal is used to represent digital logic signal 0.

[0150] like Figure 6A As shown, the controller provides a reset signal RESET to the source driver for N clock cycles, where N>=1.

[0151] After the controller provides the source driver with the RESET signal and the LPC Start signal, the controller provides the source driver with a row data packet, which may include 16 bits, for example.

[0152] After the controller finishes providing row data packets to the source driver, the controller provides row image data to the source driver, such as image data D0, image data D1, image data D2, and image data D3.

[0153] Figure 6B A timing diagram of a display sub-signal provided by a frame configuration mode according to at least one embodiment of the present disclosure is shown.

[0154] like Figure 6B As shown, this timing diagram includes a clock signal CLK, a data transmission control signal LOAD, a data polarity inversion control signal POL, and low-voltage differential signals. Only one signal transmission channel, LV0, of the low-voltage differential signals is shown in the diagram.

[0155] like Figure 6B As shown, the controller provides the data transmission control signal LOAD and the data polarity reversal control signal POL to the source driver according to the set timing relationship as trigger signals.

[0156] After providing a trigger signal to the source driver, the interval length t HD Subsequently, a reset signal RESET and a frame mode start signal FPC Start are provided to the source driver as mode identification signals for the frame configuration mode. For example... Figure 6BAs shown, the frame mode start signal FPC Start can be digital logic signal 1. In embodiments of this disclosure, for example, a high-level signal is used to represent digital logic signal 1.

[0157] like Figure 6B As shown, the controller provides a reset signal RESET to the source driver for N clock cycles, where N>=1.

[0158] After the controller provides the source driver with the RESET signal and the FPC Start signal, the controller provides the source driver with a frame data packet, which may include 256 bits, for example.

[0159] After the controller finishes providing frame packets to the source driver, it provides invalid data IDLE0 to the source driver.

[0160] like Figure 6B As shown, after the controller provides invalid data IDLE0 to the source driver, the controller again provides at least one trigger sub-signal PSI to the source driver to indicate that the source driver enters a low-power operating state.

[0161] In some embodiments of this disclosure, the duration of the combined data of frame configuration data and invalid data IDLE0 is the same as the duration of the combined data provided in row configuration mode.

[0162] In some embodiments of this disclosure, the signal transmission method is applied to a display device. During the power-on process of the display device, the display signals transmitted between the controller and the source driver are, in sequence, display sub-signals provided by the calibration configuration mode and display sub-signals provided by the frame configuration mode; and after the display device enters the working state, the display signals transmitted between the controller and the source driver are, in sequence, display sub-signals provided by the row configuration mode, display sub-signals provided by the frame configuration mode, and display sub-signals provided by the calibration configuration mode.

[0163] During the power-on process of the display device, the controller first provides a calibration signal to the source driver, and then provides frame configuration data to the source driver, enabling the controller to prepare for image display in advance. No image display occurs during the power-on process, therefore, it is not necessary to provide display sub-signals to the source driver in line configuration mode. After the source driver is configured according to the calibration signal and the frame configuration data, the display device enters the operating state. After the display device enters the operating state, the controller provides multiple display sub-signals to the source driver in line configuration mode, frame configuration mode, and calibration configuration mode.

[0164] For example, the controller first provides row configuration data and row image data to the source driver in row configuration mode, causing the display device to sequentially display the image data of each row to display a complete frame of image. After the display device displays a complete frame of image, it enters the vertical blanking period. During the vertical blanking period, the controller first provides frame configuration data to the source driver in frame configuration mode, causing the source driver to perform frame configuration. For example, the source driver enters a low-power state based on the frame configuration data, and then the controller provides a logic invalid level to the source driver in correction configuration mode. During the vertical blanking period, the source driver is configured according to the frame configuration data and correction configuration data to prepare for the display of the next frame of image.

[0165] Figure 7A A flowchart of another signal transmission method provided by at least one embodiment of the present disclosure is shown.

[0166] like Figure 7A As shown, the signal transmission method includes steps S710 to S730. Figure 7A The signal transmission method shown is, for example, by Figure 1A The source driver SD-IC performs this operation. For example, this signal transmission method is used for the source driver SD-IC to receive display signals transmitted from the timing controller TCON.

[0167] Step S710: Receive display signals from the controller in at least two modes within a display period via a low-voltage differential signal interface. The display signals include multiple display sub-signals, each of which includes a pattern recognition signal.

[0168] Step S720: For each display sub-signal, determine the mode to which each display sub-signal belongs based on the pattern recognition signal.

[0169] Step S730: Process each display sub-signal according to the mode to which each display sub-signal belongs.

[0170] For step S710, for example in Figure 1B In the example, the controller TCON sends the display signal for one display cycle to the source drivers SD#1, SD#2, etc., via its own low-voltage differential signal interface. The source drivers SD#1, SD#2, etc., receive the display signal from the controller TCON via their own low-voltage differential signal interfaces. Please refer to the description above for at least two modes and one display cycle.

[0171] For a description of the pattern recognition signal in step S720, please refer to the above text.

[0172] For example, the pattern recognition signal is Figure 3B The pattern recognition signal A shown indicates that the sub-signal belongs to the row configuration mode.

[0173] For example, the pattern recognition signal is Figure 3B The pattern recognition signal B shown indicates that the sub-signal belongs to the frame configuration mode.

[0174] For example, the pattern recognition signal is Figure 3B The pattern recognition signal C shown indicates that the sub-signal belongs to the correction configuration mode.

[0175] After determining the mode to which the display sub-signal belongs based on the pattern recognition signal, the source driver parses the display sub-signal according to the mode to which the display sub-signal belongs. For example, parsing a display sub-signal provided in a row configuration mode yields row configuration data and row image data; parsing a display sub-signal provided in a frame configuration mode yields frame configuration data; and parsing a display sub-signal provided in a correction configuration mode yields a correction signal.

[0176] For example, extract the pattern recognition signal from the display signal. For example, if the pattern recognition signal is "RESET+000 000", then the display sub-signal belongs to the row configuration mode.

[0177] For step S730, for example, if the mode to which the display sub-signal belongs is the row configuration mode, then the row configuration data and row image data are obtained from the display sub-signal according to the signal format of the row configuration mode.

[0178] In some embodiments of this disclosure, each display sub-signal further includes a data signal, and step S710 includes: sequentially receiving multiple display sub-signals using a low-voltage differential signal interface, and for each display sub-signal, after receiving a pattern recognition signal through the low-voltage differential signal interface, receiving a data signal through the low-voltage differential signal interface.

[0179] In some embodiments of this disclosure, the controller receives display signals in at least two modes within a display period via a low-voltage differential signal interface, and further includes receiving a trigger signal before receiving each display sub-signal to perform transmission operations in at least two modes in response to the trigger signal.

[0180] In some embodiments of this disclosure, the trigger signal includes at least one trigger sub-signal, and receiving the trigger signal includes: sequentially receiving the at least one trigger sub-signal, each trigger sub-signal including a set timing relationship between a data transmission control signal and a data polarity reversal control signal.

[0181] Figure 7B A flowchart illustrating another signal transmission method provided by at least one embodiment of this disclosure is shown. Figure 7BAs shown, the signal transmission method includes steps S701 to S709 and steps S711 to S713. Steps S701 to S709 and steps S711 to S713 can be executed by the source driver, for example.

[0182] Step S701: Power on the source driver.

[0183] Step S702: Determine whether a trigger signal PSI has been acquired. For example, determine whether the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD within the same cycle. If the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD, then the trigger signal PSI has been acquired. If the rising edge of the data polarity inversion control signal POL is earlier than the rising edge of the data transmission control signal LOAD, then a non-trigger signal (e.g., the single-mode indicator signal described above) has been acquired.

[0184] If the trigger signal PSI is obtained, proceed to step S703; if the trigger signal PSI is not obtained, proceed to step S711 to execute.

[0185] Step S703: Determine whether the display sub-signal includes a reset signal. If the display sub-signal does not include a reset signal, then the display sub-signal is provided in the calibration configuration mode. If the display sub-signal includes a reset signal, then continue to determine whether the display sub-signal is provided in the frame configuration mode or the line configuration mode. That is, if the display sub-signal includes a reset signal, then execute step S704; if the display sub-signal does not include a reset signal, then jump to step S711.

[0186] Step S704: Determine whether the line mode start signal (LPC Start) and the frame mode start signal (FPC Start) have been received. That is, determine whether the display sub-signal includes the line mode start signal (LPC Start) or the frame mode start signal (FPC Start).

[0187] If a line mode start signal (LPC Start) is received, proceed to step S708; if a frame mode start signal (FPC Start) is received, proceed to step S705.

[0188] Step S705: Continue to receive frame configuration data using the low-voltage differential signal interface.

[0189] Step S706: Determine whether the low-power operating state is enabled. For example, the source driver enters the low-power operating state based on the frame configuration data.

[0190] If the frame configuration data enables the low-power operating state, then proceed to step S707; if the frame configuration data does not enable the low-power operating state, then return to proceed to step S702.

[0191] Step S707: The source driver enters a low-power operating state. For example, in the low-power operating state, at least a portion of the source driver's circuitry is powered down, thereby reducing the source driver's power consumption at least during vertical blanking. At least a portion of the circuitry may be configured in the frame configuration data.

[0192] Step S708: Continue to receive row configuration data using the low-voltage differential signal interface.

[0193] Step S709: Continue to receive line image data using the low-voltage differential signal interface.

[0194] Step S711: Receive the calibration signal provided by the controller in calibration configuration mode.

[0195] Step S712: Receive reset signal.

[0196] Step S713: Receive image data.

[0197] For example, in steps S701 to S709 and step S711, the reset signal and image data provided by the controller to the source driver conform to the first signal transmission protocol. In steps S712 and S713, for example, the reset signal and image data provided by the controller to the source driver conform to the second signal transmission protocol.

[0198] Figure 7A and Figure 7B The signal transmission method performed by the source driver shown is similar to Figure 1C The signal transmission method performed by the controller shown corresponds to the signal transmission method performed by the source driver. Please refer to the signal transmission method performed by the controller described above. This disclosure will not repeat the details.

[0199] Figure 8 A schematic block diagram of a controller 800 provided in at least one embodiment of the present disclosure is shown. The controller 800 is used to transmit display signals to a source driver.

[0200] For example, such as Figure 8 As shown, the controller 800 includes a display signal acquisition unit 810 and a low-voltage differential signal interface 820.

[0201] The display signal acquisition unit 810 is configured to acquire display signals. For example, the display signal acquisition unit 810 generates display signals that are provided to the source driver in at least two modes.

[0202] The display signal acquisition unit 810 can, for example, perform... Figure 1CStep S10 is described.

[0203] The low-voltage differential signal interface 820 is configured to provide the display signal to the source driver in at least two modes within a display frame period. The display signal includes a plurality of display sub-signals, each of which includes a mode recognition signal. The mode recognition signal is used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs.

[0204] The low-voltage differential signal interface 820 can, for example, perform... Figure 1C Step S20 is described.

[0205] The controller 800 enables multi-mode transmission between the controller and the source driver through pattern recognition signals, thereby realizing the multiplexing of the low-voltage differential signal interface. This allows it to be used to provide both image data and configuration data to the source driver, thereby reducing the number of interfaces used for signal transmission and ensuring that various control functions can be flexibly embedded into the source driver.

[0206] Figure 9 A schematic block diagram of a source driver 900 provided in at least one embodiment of the present disclosure is shown. The source driver 900 is used to acquire display signals from a controller.

[0207] For example, such as Figure 9 As shown, the source driver 900 includes a low-voltage differential signal interface 910, a mode determination unit 920, and a processing unit 930.

[0208] The low-voltage differential signal interface 910 is configured to receive display signals provided by the controller within a display period in at least two modes, wherein the display signals include a plurality of display sub-signals, each of the display sub-signals including a pattern recognition signal.

[0209] The low-voltage differential signal interface 910 can, for example, perform... Figure 7A Step S710 is described.

[0210] The mode determination unit 920 is configured to determine the mode to which each display sub-signal belongs based on the mode recognition signal for each display sub-signal.

[0211] The pattern determination unit 920 can, for example, execute... Figure 7A Step S720 is described.

[0212] The processing unit 930 is configured to process each display sub-signal according to the mode to which each display sub-signal belongs.

[0213] Processing unit 930 can, for example, execute Figure 7AStep S730 is described.

[0214] The source driver 900 identifies the mode to which the display sub-signal belongs through a pattern recognition signal, enabling multi-mode transmission operations between the controller and the source driver. This achieves the multiplexing of the low-voltage differential signal interface, allowing it to be used to provide both image data and configuration data to the source driver. This reduces the number of interfaces used for signal transmission and ensures that various control functions can be flexibly embedded into the source driver.

[0215] For example, the display signal acquisition unit 810, the mode determination unit 920, and the processing unit 930 can be hardware, software, firmware, or any feasible combination thereof. For example, the display signal acquisition unit 810, the mode determination unit 920, and the processing unit 930 can be dedicated or general-purpose circuits, chips, or devices, or a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the above-mentioned units.

[0216] It should be noted that in the embodiments of this disclosure, each unit of the controller 800 and the source driver 900 corresponds to each step of the aforementioned signal transmission method. For the specific functions of the controller 800 and the source driver 900, please refer to the relevant description of the signal transmission method, which will not be repeated here. Figure 8 The controller 800 shown and Figure 9 The components and structure of the source driver 900 shown are merely exemplary and not limiting. The controller 800 and the source driver 900 may also include other components and structures as needed.

[0217] Figure 10 A schematic block diagram of an electronic device 1000 provided in at least one embodiment of this disclosure is shown. For example... Figure 10 As shown, the electronic device 1000 includes a controller 1010, a source driver 1020, and a display panel 1030.

[0218] Controller 1010 executes the above. Figure 1C The described signal transmission method. The source driver 1020, for example, executes the above... Figure 7A The described signal transmission method involves a source driver 1020 connected to a controller 1010 via a low-voltage differential signal interface to receive display signals. A display panel 1030, such as a liquid crystal display panel, receives drive signals (i.e., grayscale voltage signals) from the source driver 1020 to display images; these drive signals are generated based on the display signals.

[0219] Electronic device 1000 can be any electronic device with image display function, including but not limited to smartphones, tablets, laptops, monitors, televisions, etc.

[0220] This electronic device enables multi-mode transmission between the controller and the source driver through pattern recognition signals, thereby achieving the multiplexing of the low-voltage differential signal interface. This allows it to be used to provide both image data and configuration data to the source driver, thereby reducing the number of interfaces used for signal transmission and ensuring that various control functions can be flexibly embedded into the source driver.

[0221] Although the above points have been made, the following points still need to be clarified:

[0222] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0223] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0224] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A signal transmission method for a controller to transmit a display signal to a source driver, the method comprising: Within one frame display cycle, the display signal is provided to the source driver in at least two modes via a low-voltage differential signal interface, wherein the display signal includes multiple display sub-signals. Each of the plurality of display sub-signals includes a pattern recognition signal, which is used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs. The provision of the display signal to the source driver via a low-voltage differential signal interface in at least two modes includes: Before providing each of the display sub-signals to the source driver, a trigger signal is provided to the source driver to notify the source driver to perform the transmission operation of the at least two modes, wherein the trigger signal includes at least one trigger sub-signal, and providing the trigger signal to the source driver includes: At least one trigger sub-signal is sequentially provided to the source driver, wherein each trigger sub-signal includes a set timing relationship between a data transmission control signal and a data polarity inversion control signal. The timing relationship between the data transmission control signal and the data polarity reversal control signal includes: The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least a portion of the time.

2. The method according to claim 1, wherein, Each display sub-signal also includes a data signal. The step of sequentially providing the display signal to the source driver via a low-voltage differential signal interface in at least two modes further includes: The plurality of display sub-signals are sequentially provided to the source driver in at least two modes using the low-voltage differential signal interface. Specifically, for each display sub-signal, after providing the pattern recognition signal to the source driver through the low-voltage differential signal interface, the data signal is then provided to the source driver through the low-voltage differential signal interface.

3. A signal transmission method for a source driver to receive a display signal from a controller, the source driver including a low-voltage differential signal interface, the method comprising: The controller provides display signals within a display period in at least two modes through the low-voltage differential signal interface, wherein the display signals include multiple display sub-signals, and each display sub-signal includes a pattern recognition signal; For each of the display sub-signals, the mode to which each display sub-signal belongs is determined based on the pattern recognition signal; and Each display sub-signal is processed according to the mode to which it belongs. The step of receiving the display signal provided by the controller in at least two modes within one frame display period through the low-voltage differential signal interface includes: Before receiving each of the display sub-signals, a trigger signal is received to perform the transmission operation of the at least two modes in response to the trigger signal, wherein the trigger signal includes at least one trigger sub-signal, and receiving the trigger signal includes: The at least one trigger sub-signal is received sequentially, wherein each trigger sub-signal includes a predetermined timing relationship between a data transmission control signal and a data polarity inversion control signal. The timing relationship between the data transmission control signal and the data polarity reversal control signal includes: The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least a portion of the time.

4. The method according to claim 3, wherein, Each display sub-signal also includes a data signal. The step of receiving the display signal provided by the controller in at least two modes within a display period through the low-voltage differential signal interface further includes: The plurality of display sub-signals are received sequentially using the low-voltage differential signal interface. Specifically, for each display sub-signal, after receiving the pattern recognition signal through the low-voltage differential signal interface, the data signal is then received through the low-voltage differential signal interface.

5. The method according to any one of claims 1-4, wherein, The at least two modes include: At least two of the following: line configuration mode, frame configuration mode, and correction configuration mode. The display sub-signal provided by the row configuration mode is used to configure the source driver for displaying a row of pixels. The display sub-signals provided by the frame configuration mode are used to configure the source driver for displaying a frame of image. The display sub-signal provided by the calibration configuration mode is used to calibrate the timing of the clock signal of the source driver and the display signal.

6. The method according to claim 5, wherein, The pattern recognition signals for the row configuration mode include a reset signal and a row mode start signal. The pattern recognition signal for the frame configuration mode includes the reset signal and the frame mode start signal. The pattern recognition signal for the corrected configuration mode does not include the reset signal.

7. The method according to claim 5, wherein, The display sub-signals provided by the row configuration mode also include row configuration data and row image data. The row configuration data is used to configure the source driver to process the row image data.

8. The method according to claim 7, wherein, The row configuration data includes a frame start indication signal, used to indicate whether the row image data is the first image display row in a frame.

9. The method according to claim 8, wherein, The row configuration data also includes: a data polarity reversal control signal and a charge sharing function control signal.

10. The method according to claim 5, wherein, The display sub-signals provided by the frame configuration mode also include frame configuration data, used to configure the source driver for displaying a frame of image.

11. The method according to claim 10, wherein, The frame configuration mode includes a power consumption control sub-mode. The power consumption control sub-mode is used to provide the source driver with processing signals at least during vertical blanking.

12. The method according to claim 5, wherein, The sub-signals provided by the calibration configuration mode include a calibration signal, which is used to correct the timing of the clock signal of the source driver and the display signal.

13. A controller for transmitting display signals to a source driver, the controller comprising: A low-voltage differential signal interface is configured to provide the display signal to the source driver in at least two modes within a single display frame period, wherein the display signal includes a plurality of display sub-signals. Each of the plurality of display sub-signals includes a pattern recognition signal, which is used to indicate to the source driver the mode to which the display sub-signal belongs, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs. The provision of the display signal to the source driver in at least two modes includes: Before providing each of the display sub-signals to the source driver, a trigger signal is provided to the source driver to notify the source driver to perform the transmission operation of the at least two modes, wherein the trigger signal includes at least one trigger sub-signal, and providing the trigger signal to the source driver includes: At least one trigger sub-signal is sequentially provided to the source driver, wherein each trigger sub-signal includes a set timing relationship between a data transmission control signal and a data polarity inversion control signal. The timing relationship between the data transmission control signal and the data polarity reversal control signal includes: The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least a portion of the time.

14. A source driver for acquiring a display signal from a controller, the source driver comprising: A low-voltage differential signal interface is configured to receive a display signal provided by the controller in at least two modes within a display period of one frame, wherein the display signal includes a plurality of display sub-signals, each display sub-signal including a pattern recognition signal; The mode determination unit is configured to determine the mode to which each display sub-signal belongs based on the mode recognition signal, for each display sub-signal; and The processing unit is configured to process each display sub-signal according to the mode to which each display sub-signal belongs. The step of receiving the display signal provided by the controller within one frame display period in at least two modes includes: Before receiving each of the display sub-signals, a trigger signal is received to perform the transmission operation of the at least two modes in response to the trigger signal, wherein the trigger signal includes at least one trigger sub-signal, and receiving the trigger signal includes: The at least one trigger sub-signal is received sequentially, wherein each trigger sub-signal includes a predetermined timing relationship between a data transmission control signal and a data polarity inversion control signal. The timing relationship between the data transmission control signal and the data polarity reversal control signal includes: The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least a portion of the time.

15. An electronic device comprising: The controller according to claim 13; The source driver of claim 14, wherein the source driver is connected to the controller via the low-voltage differential signal interface to receive the display signal; as well as A display panel is connected to the source driver to receive drive signals provided by the source driver, wherein the drive signals are generated based on the display signals.

Images