Mram device and method of determining its external magnetic field and influence

Abstract

A magnetoresistive random access memory (MRAM) device and a method of determining an external magnetic field and impact thereof are provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array including a plurality of memory cells configured to store memory data and a reference MTJ array including a plurality of reference cells having an MTJ structure. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a total resistance of the reference MTJ array related to an external magnetic field strength, determine whether the external magnetic field is fatal based on the received total resistance of the reference MTJ array and a predetermined threshold, and provide a notification indicating that the memory data stored in the main MTJ array is not trustworthy if it is determined that the external magnetic field around the MRAM device is fatal.

Description

Technical Field

[0001] Embodiments of the present invention relate to MRAM devices and methods for determining their external magnetic fields and their effects. Background Technology

[0002] Many modern electronic devices include electronic memory. Electronic memory can be volatile memory or non-volatile memory (NVM). Non-volatile memory can store data without power, while volatile memory cannot. Magnetoresistive random access memory (MRAM) is a promising candidate for next-generation non-volatile memory technology because of its relatively simple and compact structure and compatibility with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a method is provided for determining the influence of an external magnetic field on a magnetoresistive random access memory (MRAM) device operatively associated with the controller, the method comprising: reading memory data and corresponding error correction redundancy from the MRAM device; determining a bit error rate by performing error correction code (ECC) verification based on the memory data and the error correction redundancy, the bit error rate indicating a retention failure rate of the MRAM device; comparing the retention failure rate with a predetermined failure rate threshold; and if the retention failure rate is greater than the failure rate threshold, providing a notification signal indicating that the retained failed memory data is unreliable.

[0004] According to one aspect of an embodiment of the present invention, a magnetoresistive random access memory (MRAM) device is provided, comprising: a primary magnetic tunnel junction (MTJ) array including a plurality of memory cells configured to store memory data; a reference MTJ array including a plurality of reference cells having MTJ structures; and a controller operatively associated with the primary MTJ array and the reference MTJ array, wherein the controller is configured to: receive the total resistance of the reference MTJ array in relation to the strength of an external magnetic field; determine whether the external magnetic field is lethal based on the received total resistance of the reference MTJ array and a predetermined threshold; and if it is determined that the external magnetic field around the MRAM device is lethal, provide a notification indicating that the memory data stored in the primary MTJ array is unreliable.

[0005] According to one aspect of an embodiment of the present invention, a method is provided for determining an external magnetic field around a magnetoresistive random access memory (MRAM) device operatively associated with the controller, the MRAM device including a magnetic tunnel junction (MTJ) array, the MTJ array including a plurality of memory cells and a reference MTJ array including a plurality of reference cells, the method comprising: reading or writing memory data stored in the MTJ array; detecting a reference MTJ array signal from the reference MTJ array; comparing the reference MTJ array signal with a predetermined threshold; and if the reference MTJ array signal exceeds the predetermined threshold, providing a notification signal indicating that the memory data is unreliable. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 The diagram illustrates a block diagram of an MRAM device configured to detect an external magnetic field by processing data read from an MTJ array, according to some embodiments.

[0008] Figure 2 The illustration shows a flowchart of a method for detecting an external magnetic field of an MRAM device by processing data read from an MTJ array, according to some embodiments.

[0009] Figure 3 The diagram illustrates a block diagram of an MRAM device configured to detect an external magnetic field by processing data read from a reference MTJ array, according to some additional embodiments.

[0010] Figure 4 The illustration shows a flowchart of a method for detecting an external magnetic field of an MRAM device by processing data read from a reference MTJ array, according to some additional embodiments.

[0011] Figure 5A The illustration shows a block diagram of an MRAM device configured to detect an external magnetic field by processing data from a reference MTJ array, according to some additional embodiments.

[0012] Figure 5B An example diagram is shown illustrating the resistance of a reference MTJ array in response to the strength of an external magnetic field around an MRAM device, according to some embodiments.

[0013] Figure 5CThe illustration shows an example graph of the retention failure rate of the master MTJ array and the state switching rate of the reference MTJ array 308 in response to the external magnetic field strength around the MRAM device, according to some embodiments.

[0014] Figure 6 The illustration shows a cross-sectional view of an MRAM device configured to detect an external magnetic field by processing data read from a reference MTJ array, according to some embodiments.

[0015] Figure 7 The illustration shows a top view of an MRAM device configured to detect an external magnetic field by processing data read from a reference MTJ array.

[0016] Figure 8 The illustration shows some examples of additional device structures for an MRAM device according to some additional embodiments.

[0017] Figure 9 Examples of additional device structures for an MRAM device according to some other additional embodiments are shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0020] Magnetoresistive random access memory (MRAM) devices are promising candidates for next-generation non-volatile memory technology due to their relatively simple and compact structure and compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. However, a drawback of MRAM devices is that the data state stored within them can be affected by strong external magnetic fields. External magnetic fields not only affect the retention and write windows of the MRAM device but can also cause unwanted state flips in the stored digital data, leading to data loss or tampering. One current approach to detecting and / or mitigating the effects of external magnetic fields on MRAM devices is to use sensors, such as Hall sensors, to detect the strength of the external magnetic field near the MRAM device. However, this requires significant additional space to accommodate Hall sensors or similar devices. Hall sensors placed separately from the MRAM device occupy a large area and are difficult to integrate into the MRAM device.

[0021] In view of the above, this disclosure relates to a method for performing external magnetic field detection and data protection on MRAM devices and related devices. In some embodiments, the strength of the external magnetic field around the MRAM device is determined by processing measurement data of the MRAM device, without involving a separate direct measurement of the external magnetic field. In some embodiments, existing functions of the controller, such as error correction code (ECC) processing of memory data read from the MRAM device, are used to derive the strength of the external magnetic field. For example, the error correction redundancy (redundant bits) corresponding to the memory data is obtained through ECC processing and represents the data retention failure rate, which is positively correlated with the strength of the external magnetic field around the MRAM device, thereby representing the strength of the external magnetic field around the MRAM device. In some embodiments, the failure rate is compared with a predetermined failure rate threshold. A notification signal is then determined based on the comparison result and provided to indicate the strength of the external magnetic field.

[0022] In some further embodiments, in addition to the main MTJ array used for writing, storing, and reading memory data from the memory device, a reference magnetic tunnel junction (MTJ) array is integrated into the MRAM device and used to detect the strength of an external magnetic field around the MRAM device. In some aspects, the MTJ cells of the reference MTJ array are preset to a resistive state that can flip to the opposite resistive state under the influence of an external magnetic field. Therefore, the resistance change of the reference MTJ array can be used to indicate the strength of the external magnetic field. By integrating the reference MTJ array with the MRAM device on the same substrate, significant additional space is not required compared to using separate, independent magnetic sensors, and the fabrication process is not complex because the reference MTJ array can be formed together with the main MTJ array.

[0023] Figure 1Block diagram 100 is shown, illustrating an MRAM device 102 configured, according to some embodiments, to detect an external magnetic field by processing memory data read from an MTJ array 106. The memory data can be written to, read from, and processed by a controller 104 operatively coupled to the MTJ array 106. In some embodiments, the MTJ array 106 and the controller 104 are integrated on a single chip, while in some alternative embodiments, the MTJ array controller 106 and the controller 104 are arranged on separate chips and operatively coupled to each other via various wired or wireless signal transmission buses, such as conductor rails, optical fibers, wireless, or other signal transmission media.

[0024] In some embodiments, the MTJ array 106 includes a plurality of MTJ cells, each consisting of two magnetic layers separated by a tunnel barrier layer. One of the magnetic layers has a free magnetization that can switch between two stable directions, while the other layer, serving as a reference layer, has a fixed magnetization direction. For an MTJ cell with positive tunneling magnetoresistance (TMR), if the magnetization directions of the reference layer and the free layer are parallel, electrons are more likely to tunnel through the tunnel barrier layer, resulting in a low-resistance state for the MTJ. Conversely, if the magnetization directions of the reference layer and the free layer are antiparallel, electrons are less likely to tunnel through the tunnel barrier layer, resulting in a high-resistance state for the MTJ. Therefore, the MTJ can switch between two resistive states, namely a first state with low resistance (R0). P (The magnetization directions of the reference layer and the free layer are parallel) and a second state with high resistance (R AP (Note: The magnetization direction of the reference layer is antiparallel to that of the free layer.) It is worth noting that MTJ cells can also have negative TMR, for example, lower resistance for antiparallel orientation and higher resistance for parallel orientation. Due to its binary nature, MTJ cells are used to store digital data, where the low-resistance state R... P Corresponding to the first digital data state (e.g., logic "0"), while the high resistance state R AP This corresponds to the second digital data state (e.g., logic "1").

[0025] When digital data is stored in MRAM device 102, error correction codes (ECC) can be used to better guarantee data reliability. ECC blocks can be implemented to correct errors in the digital data. As an example, an ECC block can be multiple additional bits encoded after data bits from the original data, instructions, variables, or messages during write / programming operations. ECC blocks can be encoded using various error correction algorithms, such as single error correction (SEC) Hamming codes, single error correction-double error correction (SEC-DED) improved Hamming codes, and SEC-DED Schott codes. For example, the memory contents of MTJ array 106 can include a block of k data bits that can be encoded by an error correction algorithm to generate a block of m parity bits as an ECC block, where m and k are positive integrals. Over time, the memory contents of MTJ array 106 may suffer data degradation. When the original message is reconstructed, the ECC block can be decoded to check and correct a certain number of error bits. In some examples, the m parity bits can correct a number of bit errors and / or detect a number of bit errors. The number of bit errors detected can be greater than the number of bit errors corrected.

[0026] When a strong external magnetic field is present, the memory contents of the MTJ array 106 may be interfered with or attacked, and converted to contain additional error bits. If the number or proportion of error bits increases but remains within a repairable range, error correction codes can be used to correct these error bits. If the number or proportion of error bits exceeds a repairable range and / or the error correction codes are also altered and become unusable, the memory contents will suffer irreparable damage. In either case, a check is performed on the number or proportion of error bits and the conditions of the correction process to indicate the effects of the external magnetic field. In some embodiments, when the number or proportion of error bits exceeds a predetermined threshold, the controller 104 or other components of the MRAM device 102 can detect and notify the user that such an event has occurred. Further actions may also be taken based on the number or scale of the error bits acquired, such as erasing and / or rewriting the memory data for security purposes.

[0027] Figure 2 A flowchart 200 is illustrated, which shows a method according to some embodiments for detecting an external magnetic field of an MRAM device by processing data read from an MTJ array. The method may be stored in an electronic medium and executed by computer-related devices, such as the controller 104 of the MTJ array 106 and the MRAM device 102, as described above. Figure 1 As shown and described.

[0028] As shown in action 201, in some embodiments, memory data is written to and stored in the MTJ array. The memory data may include bits of raw data, instructions, variables, or messages. Error-correcting redundancy bits (ECC bits) are generated based on the memory data. Before writing the memory data to the MTJ array, the ECC bits can be encoded using various error correction algorithms. The error correction algorithm can be any suitable algorithm, such as single error correction (SEC) Hamming codes, single error correction-double error correction (SEC-DED) improved Hamming codes, and SEC-DED Shaw codes. The ECC bits can be written to and stored in the MTJ array along with the memory data, or they can be stored separately outside the MTJ array.

[0029] At action 202, in some embodiments, memory data is read from the MTJ array. ECC bits may be read along with the memory data, and the ECC bits include N additional bits (e.g., N = 1, 2, 3...) encoded before, after, or within each bit sequence of the memory data. The ECC bits may also include additional ECC bits stored in a separate memory separate from the MTJ array, such as a set of security or hash bits for security verification.

[0030] At action 204, in some embodiments, an ECC check is performed based on memory data and ECC bits, and the bit error rate is determined based on the ECC check. For example, the ECC bits can be decoded to detect the number or proportion of erroneous bits (such as the bit error rate (BER)) and the detected data can be used to determine the data retention failure rate. For example, the bit error rate can be approximated as the data retention failure rate of an MRAM device. As another example, the data retention failure rate can be calculated based on the bit error rate or the number or proportion of detected erroneous bits by subtracting the average write / read bit error rate or by calculating other factors.

[0031] At action 206, in some embodiments, the data retention failure rate is compared to a predetermined failure rate threshold. The failure rate threshold can be preset in a specification. The failure rate threshold can be determined by retrieving and / or obtaining a pre-stored value from memory. In some embodiments, the failure rate threshold can be preset based on ECC block coverage, such as 60% to 80% of ECC block coverage. For example, when ECC blocks can cover 10 ppm, the failure rate threshold can be set to 6 to 8 ppm (0.0006%-0.0008%). Additionally or alternatively, the failure rate threshold can be determined based on test results. An external magnetic field that could have a fatal impact on the MRAM device can be provided as a threshold strength of the external magnetic field to determine the failure rate threshold that the MRAM device cannot withstand. The test can be performed independently of the fabrication and / or operation of the MRAM device.

[0032] Additionally or alternatively, ECC checks can indicate conditions of the error correction process, such as whether the number or proportion of faulty bits is still within the repairable range, whether it is outside the repairable range, and / or whether the error correction code has been altered and become unusable. In the latter two cases, where the number or proportion of faulty bits exceeds the repairable range and / or has been altered and become unusable, the memory contents will suffer irreparable damage. In some cases, the repairable range may be equivalent to the coverage area of ​​the ECC block.

[0033] At action 208, in some embodiments, if the data retention failure rate is less than or no greater than the failure rate threshold determined in action 206, an error correction operation can be performed to correct erroneous bits. For example, ECC bits can be decoded to correct multiple erroneous bits. Alternatively, the MTJ array can be partially or completely rewritten using the corrected bits of the memory data.

[0034] At action 210, in some embodiments, a notification signal is provided if the data retention failure rate is greater than or not less than a failure rate threshold determined in action 204. A data retention failure rate exceeding the failure rate threshold may indicate a strong external magnetic field around the MRAM device and that the stored memory data is unreliable. Upon receiving the notification signal, further actions can be taken, such as clearing the memory data stored in the MTJ array and / or reloading or requesting the rewriting of refreshed data to the MTJ array. In some further aspects, a destroy command can be given to protect secure data. Because existing ECC processing is used, no additional hardware is required to detect the magnetic field strength around the MRAM.

[0035] Figure 3 The illustration shows a block diagram of an MRAM device 302 configured to detect an external magnetic field by processing data read from a reference MTJ array 308, according to some additional embodiments. Memory data can be written to, read from, and processed by a controller 304 operatively coupled to both the main MTJ array 306 and the reference MTJ array 308. In some embodiments, the main MTJ array 306, the reference MTJ array 308, and the controller 304 are integrated on a single chip, while in some alternative embodiments, the main MTJ array 306 and the reference MTJ array 308 may be arranged on a separate chip from the controller 304 and operatively coupled to each other via various wired or wireless signal transmission buses, such as conductor rails, optical fibers, wireless, or other signal transmission media.

[0036] MRAM device 302, controller 304, and main MTJ array 306 may share common components with MRAM device 102, controller 104, and MTJ array 106 as described above. Additionally or alternatively, in some embodiments, MRAM device 302 also includes a reference MTJ array 308 configured to detect and indicate the strength of an external magnetic field around MRAM device 302. Reference MTJ array 308 may include a plurality of reference MTJ cells. In some aspects, the reference MTJ cells are preset to a resistive state. Reference MTJ cells may flip to the opposite resistive state under the influence of an external magnetic field, with more reference MTJ cells flipping under a stronger external magnetic field. Therefore, the total resistance of reference MTJ array 308 is detected and used to indicate the strength of the external magnetic field. In some other aspects, additional reference MTJ array signals are detected and used to indicate the strength of the external magnetic field. The following is in conjunction with... Figure 5A For more details on the MTJ array 308 and its operation, please refer to the description.

[0037] Figure 4 A flowchart 400 is shown, illustrating a method for detecting an external magnetic field of an MRAM device by processing data read from a reference MTJ array, according to some additional embodiments. This method can be stored in an electronic medium and executed by computer-related devices, such as a controller 304 for the main MTJ array 306 and the MRAM device 302, as described above. Figure 3 As shown and described.

[0038] At action 402, in some embodiments, a reference MTJ array signal is read from or detected from the reference MTJ array. In some embodiments, the plurality of reference MTJ cells comprise MTJs connected in series, in parallel, or a combination of series and parallel connections. In some embodiments, the reference MTJ array signal is the total resistance of the reference MTJ array.

[0039] At action 404, in some embodiments, a reference MTJ array signal is processed and compared with a predetermined threshold. The reference MTJ array signal is positively correlated with the strength of an external magnetic field around the MRAM device and thus indicates the strength of the external magnetic field. In some aspects, the reference MTJ array signal is the total resistance of the reference MTJ array 308, indicating the amount of MTJ cells flipped under an external magnetic field and used to indicate the strength of the external magnetic field. In some aspects, a change in the resistance of the reference MTJ array is detected. The resistance change is related to the strength of the external magnetic field and thus used to indicate the strength of the external magnetic field. In some other aspects, a resistance threshold can be used to compare with the total resistance of the reference MTJ array 308. The resistance threshold can be preset in a specification and can be based on application needs. The resistance threshold can be retrieved from memory. During operation, data processing is performed on the master MTJ array 306. The resistance of the reference MTJ array 308 can be initialized by setting a plurality of MTJ cells of the reference MTJ array 308 to a first state. If an external magnetic field is present, the resistance of the reference MTJ array 308 can change, and the resistance change is related to the strength of the external magnetic field.

[0040] In some other respects, the reference MTJ array signal can be other parameters of the reference MTJ array 308. For example, the reference MTJ array signal can be a failure rate compared to a predetermined failure rate threshold, similar to the above. Figure 2 As described.

[0041] If the reference MTJ array signal is less than or not greater than a predetermined threshold, the MRAM device can continue to operate. Alternatively, the reference MTJ array signal can be checked again, for example, periodically or upon request, if the reference MTJ array signal is less than or not greater than the predetermined threshold.

[0042] At action 406, in some embodiments, a notification signal is provided if the reference MTJ array signal is greater than or not less than a predetermined threshold. The notification signal may indicate that the stored memory data is unreliable. In some embodiments, further actions are taken upon receiving the notification signal, such as clearing the memory data stored in the main MTJ array 306 and / or reloading or requesting that refreshed data be rewritten to the main MTJ array 306. In some further aspects, to protect the data, a destruction command may be given to destroy the data. In some further embodiments, an initialization bias may be applied to the reference MTJ array 308 to preset or reset the reference cell 108' for the next detection of an external magnetic field. Since the reference MTJ array 308 can be formed together with the main MTJ array 306, the manufacturing process is not complex compared to forming different types of magnetic sensors.

[0043] Figure 5ABlock diagram 500a is shown, illustrating a configuration according to some embodiments for detecting an external magnetic field using a reference MTJ array 308. Figure 3 The circuit diagram of the MRAM device 302. However, Figure 5A The circuit diagram shown can be used to perform with Figures 1-4 The aforementioned functions are related. Optionally, Figure 5A The MRAM device shown can utilize magnetic elements affected by an external magnetic field to perform other functions.

[0044] In some embodiments, the main MTJ array 306 includes a plurality of memory cells C11-C33. The memory cells C11-C33 may be arranged in rows and / or columns within the main MTJ array 306. The main MTJ array 306 may have any number of memory cells, although... Figure 5A The memory cells are shown as having 3 rows and 3 columns. One of the memory cells C11-C33 may include a memory cell 108 coupled to a selector 118. The selector 118 is configured to selectively provide access to the selected memory cell 108 while suppressing leakage current through the unselected memory cell.

[0045] Memory cells C11-C33 can be controlled via bit lines BL1-BL3, word lines WL1-WL3, and source lines SL1-SL3. Word lines WL1-WL3 can be used to operate selector 118 corresponding to memory cells C11-C33. When selector 118 for memory cell 108 is enabled, a voltage can be applied to that memory cell. Bit line decoder 119 applies a read voltage or write voltage to one of the bit lines BL1-BL3. Word line decoder 127 applies another voltage to one of the word lines WL1-WL3, which enables selector 118 for memory cells C11-C33 in the corresponding row. These operations together result in a read voltage or write voltage being applied to the selected memory cell among memory cells C11-C33.

[0046] Applying a voltage to the selected memory cell 108 generates a current. During a read operation, a sense amplifier 117 determines the programming state of the selected memory cell based on the current. The sense amplifier 117 may be connected to source lines SL1-SL3. Alternatively or additionally, the sense amplifier 117 may be connected to bit lines BL1-BL3. The sense amplifier 117 can determine the programming state of the memory cell 108 based on the current. In some embodiments, the sense amplifier 117 determines the programming state of the memory cell 108 by comparing the current to one or more reference currents. The sense amplifier 117 can transmit the programming state determination to an I / O buffer, which may be coupled to driver circuitry to enable write and write verification operations. The driver circuitry is configured to select a voltage to be applied to the selected memory cell for read, write, and write verification operations.

[0047] In some embodiments, the reference MTJ array 308 includes a plurality of magnetic reference cells R11-R33. The magnetic reference cells R11-R33 may be arranged in rows and / or columns or in any other suitable pattern within the reference MTJ array 308. The reference MTJ array 308 may have any number of reference cells 108'. The number of reference cells 108' in the reference MTJ array 308 is related to the resolution of the external magnetic field detection. In some aspects, the reference MTJ array 308 may have at least 1 / r of reference cells 108', where r is a failure rate that may be listed in the specification. For example, the reference MTJ array 308 may have at least 10 6 Each reference unit 108' can generate 10 corresponding to a failure rate of 1 ppm (1E-6 bit error rate). 6 Resolution. In some respects, the reference cell 108' is preset to a resistive state and can be flipped to the opposite resistive state under the influence of an external magnetic field.

[0048] Figure 5B The response of MRAM device 302 according to some embodiments is shown (see Figure 5A Example Figure 500b shows the resistance of the reference MTJ array 308 to the external magnetic field H surrounding it. In some embodiments, all reference cells 108' of the reference MTJ array 308 can be initially preset to a high resistance state (R). ap ) and can be preset to a high resistance state (R) ap More reference cells 108' are flipped under a stronger external magnetic field. The total resistance of the reference MTJ array 308 decreases as the number of reference cells 108' that have changed to a flip-resistance state increases, and therefore decreases as the strength of the external magnetic field H around the MRAM device 302 increases. Alternatively, all reference cells 108' of the reference MTJ array 308 can be initially preset to a low-resistance state (R). p) and can be preset to a low resistance state (R) p Then, the total resistance of the reference MTJ array 308 increases with the increase in the number of reference cells 108' that change to a flip-flop resistance state, and therefore increases with the increase in the strength of the external magnetic field H around the MRAM device 302. Thus, the resistance change of the reference MTJ array 308 can be used to indicate the strength of the external magnetic field H. By integrating the reference MTJ array 308 with the MRAM device 302, no significant additional space is required compared to using a separate magnetic sensor, and the fabrication process is not complex because the reference MTJ array 308 can be formed together with the main MTJ array 306.

[0049] Figure 5C Some embodiments are shown in response to an external magnetic field H around the MRAM device 302 (see [link]). Figure 5A Example curves for the retention failure rate of the primary MTJ array 306 and the state flip rate of the reference MTJ array 308 are shown in Figure 500c (see...). Figure 5A The retention failure rate of the main MTJ array 306 increases with increasing external magnetic field H around the MRAM device 302. The state transition rate of the reference MTJ array 308 also increases with increasing external magnetic field H. In some respects, the reference MTJ array 308 is more sensitive to external magnetic field H than the main MTJ array 306, and is therefore better suited for detecting external magnetic field H. In some embodiments, the reference cell 108' has an MTJ cell with the same or similar composition as the memory cell 108, but with a smaller lateral dimension. Further details of the memory cell 108 and the reference cell 108' are also related to the following. Figure 6 and Figure 7 describe.

[0050] Figure 6 and Figure 7 Some additional device structure examples of the MRAM device 302 are shown above, as related to... Figure 3 -As shown in Figure 5. Figure 6A cross-sectional view 600 is shown, illustrating a main MTJ array 306 including representative memory cells C11, C12, and a reference MTJ array 308 including magnetic reference cells R11, R12, R13. An interconnect structure 604 is disposed above a substrate 602. The interconnect structure 604 includes, as an example, stacked interconnect metal layers 606a, 606b, 606c disposed within stacked interlayer dielectric (ILD) layers 608a, 608b, 608c, as examples. The stacked interconnect metal layers 606a, 606b, 606c may each include one or more interconnect metal lines. The stacked ILD layers 608a, 608b, 608c may each include one or more dielectric layers. Memory cells C11 and C12 each include memory cells 108 disposed within the interconnect structure 604. Magnetic reference cells R11, R12, R13 each include reference cells 108' also disposed within the interconnect structure 604. In some embodiments, memory cell reference cell 108 and reference cell 108' may have the same composition.

[0051] As an example, memory cell 108 and reference cell 108' may each include an MTJ structure, the MTJ structure including a bottom electrode 110, a data storage structure 112 disposed above the bottom electrode 110, and a top electrode 114 disposed above the data storage structure 112. An upper interconnect metal layer 606c extends through the upper ILD layer 608c to reach the top electrode 114. In some embodiments, the bottom electrode 110 and top electrode 114 may include tantalum nitride, titanium nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, etc. In some embodiments, the data storage structure 112 is a magnetic tunnel junction (MTJ), a spin valve, or other data storage structure containing magnetic materials. Other structures for the data storage structure 112 and / or other memory cell types for memory cell 108 and reference cell 108' are also acceptable.

[0052] In some embodiments, the data storage structure 112 includes a reference ferromagnetic element 132 and free ferromagnetic elements 136 stacked and separated by tunneling barrier elements 134. The reference ferromagnetic element 132 has a fixed magnetization direction, while the free ferromagnetic element 136 has a variable magnetization intensity that can switch between two stable directions. In some embodiments, the reference ferromagnetic element 132 is or includes cobalt iron (e.g., CoFe), cobalt iron boron (e.g., CoFeB), or some other suitable ferromagnetic material or any combination thereof. In some embodiments, the reference ferromagnetic element 132 is adjacent to or otherwise adjacent to a portion of an antiferromagnetic element (not shown) and / or a synthetic antiferromagnetic (SAF) element (not shown). In some embodiments, the free ferromagnetic element 136 is or includes cobalt iron (e.g., CoFe), cobalt iron boron (e.g., CoFeB), or some other suitable ferromagnetic material or any combination thereof. In some embodiments, the tunneling barrier element 134 is a tunneling barrier that selectively allows electron quantum mechanical tunneling through the tunneling barrier element 134. The tunneling barrier element 134 may be, for example, or include an amorphous barrier, a crystalline barrier, or some other suitable barrier, such as aluminum oxide (Al₂O₃). x Titanium oxide (TiO) x Manganese oxide (MgO), spinel (MgAl2O4), or some other suitable barrier material. Although the present invention is primarily described according to MTJ, it should be understood that the present invention is applicable to spin valve memory elements that may use a soft magnetic layer as a free ferromagnetic element 136 and a hard magnetic layer as a reference ferromagnetic element 132, and a nonmagnetic barrier separating the hard magnetic layer and the soft magnetic layer.

[0053] Depending on whether the magnetization of the reference ferromagnetic element 132 and the free ferromagnetic element 136 is parallel or antiparallel, the data storage structure 112 has low or high resistance. For example, the data storage structure 112 may have low resistance when the magnetization of the reference ferromagnetic element 132 and the free ferromagnetic element 136 is parallel, and may have high resistance when the magnetization is antiparallel. During operation, the memory cell 108 can be written to, read from, and used to store digital data, wherein a low-resistance state corresponds to a first digital data state (e.g., logic "0"), and a high-resistance state corresponds to a second digital data state (e.g., logic "1"). The reference cell 108' can be used to indicate the strength of an external magnetic field, and the switching between the low-resistance and high-resistance states of the reference cell 108' causes a change in the total resistance of the reference MTJ array 308.

[0054] In some embodiments, selector 118 is electrically coupled to the bottom electrode 110 of memory cell 108 via interconnect metal layers 606a, 606b and is used to control access to memory cell 108 in main MTJ array 306. Interconnect metal layers 606a, 606b may include metal line layers connected by metal vias disposed between metal lines. Bottom electrode 110 may be directly connected to the lower metal line or connected via bottom electrode vias. Top electrode 114 may be directly connected to or connected via top electrode vias to the upper metal line. Bit line BL may be connected to top electrode 114. Selector 118 may include a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Selector 118 may include a first source / drain region 120 and a second source / drain region 122, the first source / drain region 120 and the second source / drain region 122 being disposed in or on substrate 602 on opposite sides of gate structure 124. Word line WL may be connected to gate structure 124. The source line SL can be connected to the first source / drain region 120, and the second source / drain region 122 can be coupled to the memory cell 108 via an interconnect metal layer such as interconnect metal layers 606a, 606b. The first source / drain region 120 and the second source / drain region 122 can be, for example, heavily doped semiconductor regions. The gate structure can include, for example, polysilicon or a metallic material such as aluminum, tungsten, titanium, or another suitable conductive material separated from the substrate 602 by a dielectric layer, which can be or include, for example, oxides, high-k dielectric materials, or other suitable dielectric materials. During operation, signals (e.g., voltage and / or current) can be selectively applied to the word line WL, the source line SL, and the bit line BL to read data from and write data to the memory cell 108.

[0055] In some embodiments, no selector is present in the reference MTJ array 308. A reference bias may be applied to the reference MTJ array 308 to measure the total resistance of the reference cells 108'. As an example, a reference line RL may be connected to the top electrode 114 of one or more reference cells 108' for conveying the total resistance. During operation, a reference bias may be applied between the reference line RL and the lower metal line connected to the lower interconnect metal layer 606b of the bottom electrode 110. It is understood that the reference MTJ array 308 may be flipped such that the reference line RL may be connected to the bottom electrode 110 of one or more reference cells 108', and a reference bias may be applied between the reference line RL and the upper metal line connected to the upper interconnect metal layer 606c of the top electrode 114. In some embodiments, an initialization bias may be applied to the reference MTJ array 308 to preset or reset the reference cells 108'.

[0056] Figure 7 The figures illustrate top views 700a and 700b according to some embodiments, showing the above... Figures 3-6Some further device structure examples associated with the disclosed MRAM device 302, Figures 3-6 Includes the main MTJ array 306 and the reference MTJ array 308. See top view 700a and... Figure 5A As shown, in some embodiments, the main MTJ array 306 includes a plurality of memory cells C11-C33 having memory cells 108 in rows and / or columns, with any number of memory cells. Memory cells C11-C33 may be composed of interleaved bit lines BL1-BL3 and word lines WL1-WL3. Word lines WL1-WL3 can be used to control and select memory cells C11-C33. When a memory cell 108 is selected, a read voltage or a write voltage can be applied to that memory cell.

[0057] Such as top view 700b and Figure 5A As shown, in some embodiments, the reference MTJ array 308 includes a plurality of magnetic reference cells R11-R33. The magnetic reference cells R11-R33 may be arranged in rows and / or columns or in any other suitable pattern within the reference MTJ array 308. The reference MTJ array 308 may have any number of reference cells 108'. The reference cells 108' of the reference MTJ array 308 may be connected in series, in parallel, or in a combination thereof. Top view 700b and Figure 6 An example of a series connection is shown. The bottom electrodes of the first magnetic reference cell R11 and the second magnetic reference cell R12 can be connected together via metal lines in the lower interconnect metal layer 606b, and the top electrodes of the second magnetic reference cell R12 and the third magnetic reference cell R13 can be connected together via metal lines in the upper interconnect metal layer 606c. The remaining magnetic reference cells can also be arranged in a similar manner. In some aspects, reference cell 108' is preset to a resistive state and can be flipped to the opposite resistive state under the influence of an external magnetic field around the MRAM device.

[0058] In some embodiments, the reference cell 108' has the same or similar dimensions as the memory cell 108 to ensure manufacturing consistency. In some alternative embodiments, the lateral dimension of the reference cell 108' is smaller than that of the memory cell 108. In some aspects, the diameter or lateral dimension of the reference cell 108' of the reference MTJ array 308 is about 70% to 90% of the diameter or lateral dimension of the memory cell 108 of the main MTJ array 306. In some other aspects, the diameter or lateral dimension of the reference cell 108' of the reference MTJ array 308 is about 5 nm to 10 nm smaller than that of the memory cell 108 of the main MTJ array 306. For example, the diameter of each reference cell 108' of the reference MTJ array 308 may be 15-90 nm, while the diameter of each memory cell 108 of the main MTJ array 306 may be 20-100 nm. The smaller MTJ size of the reference MTJ array 308 makes it more susceptible to external magnetic fields, thus providing more sensitive external magnetic field detection. Meanwhile, the MTJ size of the reference MTJ array 308 is 70% smaller than that of the main MTJ array 306 or 5-10 nm smaller, which may lead to manufacturing difficulties for scaling nodes with small critical sizes.

[0059] Furthermore, although memory cell 108 and reference cell 108' are in Figure 7 Both are shown as having a circle, but they can be of various shapes. For example, memory cell 108 and reference cell 108' can be other centrally symmetric shapes, such as squares or other regular polygons. In some alternative embodiments, memory cell 108 and / or reference cell 108' can have an axisymmetric shape that is longer in the length direction than in the width direction, such that the area of ​​memory cell 108 can be increased by arranging it to have a longer length or the area of ​​reference cell 108' can be reduced by arranging it to have a shorter width. Examples of memory cell 108 and / or reference cell 108' include elliptical, rectangular, or other suitable shapes.

[0060] Figure 8 and Figure 9 Examples of additional device structures for the MRAM device 302 are shown above, as related to... Figures 3-7As disclosed, as shown in block diagrams 800a, 900a and top views 800b, 900b, the reference cells 108' of the reference MTJ array 308 can be coupled in series, in parallel, or in a combination thereof. For example, as shown in block diagrams 800a and top view 800b, the first set of magnetic reference cells R11, R12, R13, the second set of magnetic reference cells R21, R22, R23, and the third set of magnetic reference cells R31, R32, R33 are connected in series and then in parallel to the reference line RL, respectively. As another example shown in block diagrams 900a and top view 900b, all magnetic reference cells R11-R33 can be connected in parallel and connected to the reference line RL. During operation, a bias voltage VR can be applied to the reference cell 108' to measure the total resistance of the reference MTJ array 308 and thus indicate the strength of the external magnetic field around the MRAM device 302.

[0061] Therefore, in some embodiments, this disclosure relates to a method implemented by a controller to determine the influence of an external magnetic field on a magnetoresistive random access memory (MRAM) device operatively associated with the controller. The method includes reading memory data and corresponding error correction redundancy from the MRAM device, determining a bit error rate by performing error correction code (ECC) checks based on the memory data and the error correction redundancy, the bit error rate indicating the retention failure rate of the MRAM device. The method also includes comparing the retention failure rate to a predetermined failure rate threshold, and providing a notification signal indicating that the memory data is unreliable if the retention failure rate is greater than the failure rate threshold.

[0062] The above method also includes performing an error correction operation and rewriting the MRAM device with the corrected bits of the memory data if the retention failure rate is less than the failure rate threshold.

[0063] The above method also includes providing a destroy command to protect secure data if the memory data stored in the MRAM device is untrusted.

[0064] In the above method, the failure rate threshold is determined by obtaining a pre-stored value from memory.

[0065] In the above method, a failure rate threshold is determined by performing a test process that provides an external magnetic field with a threshold strength that has a fatal impact on the MRAM device.

[0066] In the above method, the failure rate threshold is determined to be 60% to 80% of the coverage of the error correction code (ECC) block of the MRAM device.

[0067] In other embodiments, this disclosure relates to a magnetoresistive random access memory (MRAM) device. The MRAM device includes a primary magnetic tunnel junction (MTJ) array and a reference MTJ array. The primary MTJ array includes a plurality of memory cells configured to store memory data, and the reference MTJ array includes a plurality of reference cells having an MTJ structure. The MRAM device also includes a controller operatively associated with the primary MTJ array and the reference MTJ array. The controller is configured to receive the total resistance of the reference MTJ array in relation to an external magnetic field strength, determine whether the external magnetic field is lethal based on the received total resistance of the reference MTJ array and a predetermined threshold, and if it is determined that the external magnetic field around the MRAM device is lethal, provide a notification indicating that the memory data stored in the primary MTJ array is unreliable.

[0068] In the aforementioned MRAM device, the reference cells of the reference MTJ array each have the same composition as the memory cells of the main MTJ array.

[0069] In the aforementioned MRAM device, the reference cells of the reference MTJ array each have a smaller lateral dimension than the memory cells of the main MTJ array.

[0070] In the aforementioned MRAM device, multiple memory cells of the main MTJ array each include an MTJ structure connected to a selector, wherein the selector is not present in the reference MTJ array.

[0071] In the MRAM device described above, the top or bottom electrode of the MTJ structure of the reference MTJ array is connected to a reference line, which is configured to convey the total resistance of the reference MTJ array.

[0072] In the MRAM device described above, the reference cells of the reference MTJ array are connected in series with each other and connected to the reference lines.

[0073] In the MRAM device described above, the reference cells of the reference MTJ array are connected in parallel to each other and connected to the reference lines.

[0074] In the aforementioned MRAM devices, the reference cells have lateral dimensions that are 5nm to 10nm smaller than those of the memory cells.

[0075] In the aforementioned MRAM device, the reference MTJ array is disposed within the interconnect structure above the substrate.

[0076] In another embodiment, this disclosure relates to a method implemented by a controller for determining an external magnetic field around a magnetoresistive random access memory (MRAM) device operatively associated with the controller. The MRAM device includes a magnetic tunnel junction (MTJ) array comprising a plurality of memory cells and a reference MTJ array comprising a plurality of reference cells. The method includes reading or writing memory data stored in the MTJ array and detecting a reference MTJ array signal from the reference MTJ array. The method further includes comparing the reference MTJ array signal with a predetermined threshold, and if the reference MTJ array signal exceeds the predetermined threshold, providing a notification signal indicating that the memory data is unreliable.

[0077] In the above method, detecting the reference MTJ array signal from the reference MTJ array includes: initializing the total resistance of the reference MTJ array by setting multiple memory cells of the reference MTJ array to a first state; and detecting the resistance change of the reference MTJ array, the resistance change being related to the strength of the external magnetic field.

[0078] In the above method, the method further includes applying an initialization bias to the reference MTJ array to reset multiple reference cells for the next detection of the external magnetic field.

[0079] In the above method, the predetermined threshold is determined by performing a test procedure that provides an external magnetic field with a threshold strength that has a fatal effect on the MRAM device.

[0080] In the above method, the predetermined threshold is retrieved from memory.

[0081] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method implemented by a controller to determine the influence of an external magnetic field on an MRAM device operatively associated with the controller, the method comprising: An MRAM device is provided, the MRAM device including a magnetic tunnel junction array, the magnetic tunnel junction array including a plurality of memory cells and a reference magnetic tunnel junction array, the reference magnetic tunnel junction array including a plurality of reference cells, wherein the plurality of memory cells and the plurality of reference cells are formed together in an interconnect structure disposed above a substrate, and the plurality of reference cells each have a smaller lateral dimension than the plurality of memory cells; Read or write memory data stored in the magnetic tunnel junction array; Detect the reference magnetic tunnel junction array signal from the reference magnetic tunnel junction array; The reference magnetic tunnel junction array signal is compared with a predetermined threshold; and If the reference magnetic tunnel junction array signal exceeds the predetermined threshold, a notification signal indicating that the memory data is unreliable is provided.

2. The method according to claim 1, wherein, The lateral dimension of the reference cell is 70% to 90% of the lateral dimension of the memory cell.

3. The method according to claim 1, wherein, The reference cells each have a lateral dimension that is 5 nm to 10 nm smaller than that of the memory cells.

4. The method according to claim 1, wherein, Each of the multiple reference cells has the same composition as the multiple memory cells.

5. The method according to claim 1, wherein, The predetermined threshold is determined by performing a test procedure that provides an external magnetic field with a threshold strength that would have a fatal effect on the MRAM device.

6. The method according to claim 1, wherein, The predetermined threshold is retrieved from the memory.

7. An MRAM device, comprising: The main magnetic tunnel junction array includes multiple memory cells configured to store memory data. A reference magnetic tunnel junction array includes a plurality of reference cells having magnetic tunnel junction structures, wherein each of the plurality of reference cells in the reference magnetic tunnel junction array has a smaller lateral dimension than the plurality of memory cells in the main magnetic tunnel junction array; and A controller, operatively associated with the main magnetic tunnel junction array and the reference magnetic tunnel junction array, wherein the controller is configured to: Receive the total resistance of the reference magnetic tunnel junction array in relation to the external magnetic field strength; The external magnetic field is determined to be lethal based on the total resistance of the received reference magnetic tunnel junction array and a predetermined threshold; and If it is determined that the external magnetic field around the MRAM device is lethal, a notification is provided indicating that the memory data stored in the main magnetic tunnel junction array is unreliable.

8. The MRAM device according to claim 7, wherein, The plurality of reference cells of the reference magnetic tunnel junction array each have the same composition as the plurality of memory cells of the main magnetic tunnel junction array.

9. The MRAM device according to claim 7, wherein, The lateral dimension of the reference cell is 70% to 90% of the lateral dimension of the memory cell.

10. The MRAM device according to claim 7, wherein, The plurality of memory cells of the main magnetic tunnel junction array each include a magnetic tunnel junction structure connected to a selector, wherein the selector is not present in the reference magnetic tunnel junction array.

11. The MRAM device according to claim 7, wherein, The top or bottom electrode of the magnetic tunnel junction structure of the reference magnetic tunnel junction array is connected to a reference line configured to convey the total resistance of the reference magnetic tunnel junction array.

12. The MRAM device according to claim 11, wherein, The reference cells of the reference magnetic tunnel junction array are connected in series with each other and connected to the reference line.

13. The MRAM device according to claim 11, wherein, The reference cells of the reference magnetic tunnel junction array are connected in parallel to each other and connected to the reference line.

14. The MRAM device according to claim 7, wherein, The reference cells each have a lateral dimension that is 5 nm to 10 nm smaller than that of the memory cells.

15. The MRAM device according to claim 7, wherein, The reference magnetic tunnel junction array is disposed within an interconnect structure above the substrate.

16. A method implemented by a controller for determining an external magnetic field around an MRAM device operatively associated with the controller, the MRAM device comprising a magnetic tunnel junction array including a plurality of memory cells and a reference magnetic tunnel junction array including a plurality of reference cells, wherein, The plurality of reference cells each have a smaller lateral dimension than the plurality of memory cells, and the method includes: Read or write memory data stored in the magnetic tunnel junction array; Detect the reference magnetic tunnel junction array signal from the reference magnetic tunnel junction array; The reference magnetic tunnel junction array signal is compared with a predetermined threshold; and If the reference magnetic tunnel junction array signal exceeds the predetermined threshold, a notification signal indicating that the memory data is unreliable is provided.

17. The method according to claim 16, wherein, Detecting the reference magnetic tunneling junction array signal from the reference magnetic tunneling junction array includes: The total resistance of the reference magnetic tunnel junction array is initialized by setting the plurality of memory cells of the reference magnetic tunnel junction array to a first state; and The resistance change of the reference magnetic tunnel junction array is detected, and the resistance change is related to the strength of the external magnetic field.

18. The method according to claim 16, wherein, The method further includes applying an initialization bias to the reference magnetic tunnel junction array to reset the plurality of reference cells for the next detection of the external magnetic field.

19. The method of claim 16, wherein, The predetermined threshold is determined by performing a test procedure that provides an external magnetic field with a threshold strength that would have a fatal effect on the MRAM device.

20. The method of claim 16, wherein, The predetermined threshold is retrieved from the memory.

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