Semiconductor device manufacturing method and semiconductor device

Abstract

The present application provides a process method for a semiconductor device and a semiconductor device. The process method for the semiconductor device includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor substrate; forming a doped buried layer in the semiconductor substrate; performing a first epitaxial growth on the interface of the doped buried layer to form a first epitaxial layer; performing oxidation diffusion of the doped buried layer on the semiconductor substrate and the first epitaxial layer; and performing a second epitaxial growth on the semiconductor substrate to form a second epitaxial layer; wherein the deposition thickness of the second epitaxial layer is equal. The process method forms a first epitaxial layer on the interface of the doped buried layer in advance through two epitaxial growths, and forms a second epitaxial layer of equal deposition thickness on the semiconductor substrate through the second epitaxial growth, thereby precisely controlling the morphology of the second epitaxial layer, ensuring the uniformity of the second epitaxial layer, avoiding the formation of steps, and effectively solving the problem of the step height affecting the exposure process window in the subsequent process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a process method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration technology capable of fabricating bipolar, CMOS, and DMOS devices on the same chip. Because the BCD process combines the advantages of all three devices, it enables the integration of complex control functions in BCD-based products, making it a mainstream process technology for power integrated circuits. Within the BCD platform process, doped buried layers or deep wells are typically fundamental steps in the BCD process flow.

[0003] Currently, ion implantation is commonly used in the related art doping buried layer process. Compared to deep well processes, ion implantation can achieve a higher implant concentration and deeper implant depth by adjusting the ion implantation process parameters. Therefore, the doping buried layer process is superior to the deep well process in terms of latch-up suppression and isolation performance. After doping ions are implanted into the substrate, the ion concentration in the substrate portion corresponding to the ion implantation is higher than that in other parts of the substrate. This results in a faster oxidation rate for silicon in the substrate portion corresponding to the ion implantation area during the subsequent oxidation process, forming a partial oxide layer in the doped buried layer. When this oxide layer is stripped and epitaxial growth is performed, steps are formed in the epitaxial layer, i.e., step heights are present. This step height can affect the exposure process window in subsequent processes. Summary of the Invention

[0004] The semiconductor device and the manufacturing method thereof provided in the present application are intended to solve the problem in existing semiconductor devices where the step height affects the exposure process window.

[0005] To solve the above-mentioned technical problems, the present application adopts a technical solution: providing a process method for manufacturing a semiconductor device. The process method for manufacturing a semiconductor device comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor substrate; forming a doped buried layer within the semiconductor substrate; performing a first epitaxial growth on the interface of the doped buried layer to form a first epitaxial layer; performing oxidation diffusion of the doped buried layer on the semiconductor substrate and the first epitaxial layer; and performing a second epitaxial growth on the semiconductor substrate to form a second epitaxial layer; wherein the deposition thickness of the second epitaxial layer is equal.

[0006] In some embodiments, a surface of the second epitaxial layer away from the semiconductor substrate is planar.

[0007] In some embodiments, performing a first epitaxial growth on the interface of the doped buried layer to form the first epitaxial layer includes: defining a first epitaxial growth region on the interface of the doped buried layer; and performing epitaxial growth in the first epitaxial growth region so that the first epitaxial layer is formed on the interface of the doped buried layer.

[0008] In some embodiments, before forming the doped buried layer on the semiconductor substrate and the first epitaxial layer, the process method of the semiconductor device further includes: patterning the first epitaxial layer.

[0009] In some embodiments, the semiconductor base material also includes a pad oxide layer formed on the semiconductor substrate; before forming the doped buried layer in the semiconductor substrate, the process method of the semiconductor device also includes: forming a mask layer on the semiconductor substrate having the pad oxide layer; and patterning the mask layer and the pad oxide layer to use the patterned mask layer and the pad oxide layer as a mask to form the doped buried layer in the semiconductor substrate.

[0010] In some embodiments, a top surface of the first epitaxial layer is formed to be higher than a top surface of the pad oxide layer.

[0011] In some embodiments, the thickness of the pad oxide layer ranges from The thickness of the first epitaxial layer is in the range of The thickness of the second epitaxial layer is in the range of 2 to 8 μm.

[0012] In some embodiments, forming a doped buried layer in the semiconductor substrate includes: performing ion implantation on the semiconductor substrate based on the patterned mask layer and the pad oxide layer to form the doped buried layer.

[0013] In some embodiments, the process conditions of the ion implantation are: the implanted impurity is arsenic or antimony; the implantation energy range is 10Kev to 200Kev; and the dose range is 2E12cm -2 ~5E16cm -2 .

[0014] In some embodiments, patterning the mask layer and the pad oxide layer to form the doped buried layer in the semiconductor substrate using the patterned mask layer and the pad oxide layer as a mask includes: etching the mask layer and the pad oxide layer through a wet etching process.

[0015] In some embodiments, before performing the first epitaxial growth on the interface of the doped buried layer to form the first epitaxial layer, the process method of the semiconductor device further includes: removing the mask layer.

[0016] In some embodiments, the doped buried layer is an N-type doped buried layer, and the first epitaxial layer and / or the second epitaxial layer is a P-type semiconductor layer.

[0017] To solve the above technical problems, another technical solution adopted in this application is to provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; and a second epitaxial layer disposed on the semiconductor substrate, the second epitaxial layer being prepared using the above-described process method; wherein the second epitaxial layers are deposited to a uniform thickness.

[0018] Beneficial effects of the present application: The process method for a semiconductor device provided by an embodiment of the present application forms a first epitaxial layer on the interface of a doped buried layer in advance through a first epitaxial growth without adding an additional mask layer, so that during the process of oxidation diffusion of the doped buried layer by the semiconductor substrate and the first epitaxial layer, the first epitaxial layer can be oxidized to prevent the doped buried layer from being oxidized, and then a second epitaxial growth is performed on the semiconductor substrate to form a second epitaxial layer with an equal deposition thickness on the semiconductor substrate. Thus, the process method forms a first epitaxial layer on the interface of the doped buried layer in advance through two epitaxial growths and forms a second epitaxial layer with an equal deposition thickness on the semiconductor substrate through a second epitaxial growth, which not only accurately controls the morphology of the second epitaxial layer, ensures the uniformity of the second epitaxial layer, and avoids the formation of steps in the epitaxial layer, but also effectively solves the problem of the step height affecting the exposure process window in the subsequent process, thereby effectively improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of an epitaxial layer of a semiconductor device in a comparative embodiment.

[0020] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device in an embodiment of the present application is shown.

[0021] Figure 3 A schematic structural diagram of a semiconductor substrate in an embodiment of the present application is shown.

[0022] Figure 4 Shown Figure 3 A schematic structural diagram of forming a mask layer on a semiconductor substrate in the embodiment shown is shown.

[0023] Figure 5 Shown Figure 4 A schematic structural diagram of a patterned mask layer and a pad oxide layer in the embodiment shown.

[0024] Figure 6 Shown Figure 5 The structure diagram of forming a doped buried layer on a semiconductor substrate in the embodiment shown is shown.

[0025] Figure 7 Shown Figure 6 A schematic structural diagram of a semiconductor substrate with the mask layer removed in the embodiment shown.

[0026] Figure 8 Shown Figure 7 A schematic structural diagram of a first epitaxial layer formed on the interface of the doped buried layer in the embodiment shown.

[0027] Figure 9 Shown Figure 8 A schematic structural diagram of the semiconductor substrate undergoing oxidation diffusion in the illustrated embodiment.

[0028] Figure 10 Shown Figure 9 A schematic structural diagram of the semiconductor substrate after the oxide layer is removed in the embodiment shown.

[0029] Figure 11 Shown Figure 10 The schematic diagram of the structure in which the second epitaxial layer is formed on the semiconductor substrate in the embodiment shown is shown. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0032] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] The BCD process integrates bipolar, CMOS, and high-voltage DMOS devices into a single monolithic IC. Deep well or doped buried layer processes are fundamental steps in the BCD process flow.

[0034] The deep well process involves forming a first-doping type well region, such as an N-type well region, in a provided substrate; forming a second-doping type well region, such as a P-type well region, on the side of the first-doping type well region facing away from the lower surface of the substrate; and then forming various semiconductor devices on the side of the second-doping type well region facing away from the lower surface of the substrate. The substrate has the same doping type as the second-doping type well region, such as a P-type substrate. The first-doping type well region and the second-doping type well region are formed in the substrate, and the first-doping type well region is located between the remaining substrate and the second-doping type well region to provide a barrier between the remaining substrate and the second-doping type well region.

[0035] The doped buried layer process involves forming a doped buried layer of a first doping type, such as an N-type buried layer, in a provided substrate; oxidizing and diffusing the doped buried layer; growing an epitaxial layer on one side of the substrate where the doped buried layer is located to serve as a second doping type well region, such as a P-type doped epitaxial layer; and then forming various semiconductor devices on the side of the epitaxial layer serving as the second doping type well region away from the substrate. The substrate has the same doping type as the second doping type well region, such as a P-type substrate. The doped buried layer is formed in the substrate, while the second doping type well region is the grown epitaxial layer.

[0036] Therefore, in the deep well process, the first doping type well region and the second doping type well region are both formed in the substrate. That is to say, the depth of the first doping type well region and the second doping type well region is greatly affected by the thickness of the substrate itself. Therefore, the thickness of the first doping type well region and the second doping type well region cannot be made very thick.

[0037] The doped buried layer process, on the other hand, uses an epitaxial layer grown epitaxially on a substrate as a second doped type well region. It is not formed in the substrate; only the doped buried layer needs to be formed in the substrate. Therefore, during oxidation diffusion, the doped buried layer can diffuse greatly from one side of the substrate to the other side of the substrate. In other words, the thickness of the doped buried layer can be set relatively thick, effectively blocking the remaining substrate from the epitaxially grown epitaxial layer. Therefore, compared to the deep well process, the doped buried layer using ion implantation can achieve a higher implant concentration and a deeper implant depth by adjusting the ion implantation process parameters. As a result, the doped buried layer process is superior to the deep well process in terms of latch-up suppression and isolation performance.

[0038] Specifically, ion implantation utilizes an ion implanter to dope semiconductors. This involves injecting specific impurity atoms into semiconductor materials using accelerated ionization, altering their conductive properties and ultimately forming the desired semiconductor device. During the ion implantation process, the dosage or amount of specific impurity atoms doped into the semiconductor substrate can be precisely controlled. Therefore, one of the key features of ion implantation is the ability to precisely control the amount and depth of doping. However, during the ion implantation process, the incident ions may disrupt the semiconductor crystal lattice. This means that the substrate's crystal structure may be compromised in the ion implanted area. Furthermore, the ion concentration in the substrate portion corresponding to the ion implanted area is higher than in other areas of the substrate. This results in accelerated silicon oxidation in the substrate portion corresponding to the ion implanted area during the subsequent oxidation diffusion process, leading to excessive oxidation in the substrate portion corresponding to the ion implanted area. This means that during the subsequent oxidation process, a partial oxide layer forms within the doped buried layer. The first step in epitaxial growth is to strip the oxide layer. During this process, the stripping of the oxide layer from the doped buried layer leaves a recess in the doped buried layer area. Epitaxial growth is carried out along the original lattice. Since there are grooves in the doped buried layer area, the epitaxial layer will form steps, that is, the epitaxial layer has step heights. Figure 1 shown. Figure 1 Schematic diagram of the structure of the epitaxial layer of a semiconductor device in a comparative embodiment of the related art.

[0039] Specifically, in the comparative embodiment, the process for preparing the epitaxial layer of the semiconductor device generally includes the following steps:

[0040] A mask layer is coated on the surface of the semiconductor substrate 10, and after the mask layer is exposed and developed, an ion implantation window is formed on the surface of the semiconductor substrate 10. Through the ion implantation window, an ion implantation method is used to form a doped buried layer in the semiconductor substrate 10. Furthermore, the doped buried layer is subjected to oxidation diffusion. During the oxidation diffusion process, the oxidation rate of silicon in the substrate portion corresponding to the ion implantation area is accelerated relative to other parts of the semiconductor substrate 10, and a partial oxide layer is formed in the doped buried layer. In addition, the oxide layer needs to be stripped off before the epitaxial layer 11 is formed. Therefore, after the partial oxide layer in the doped buried layer is stripped off, a groove will be left in the doped buried layer area. As a result, the epitaxial layer 11 formed by growth along the original crystal lattice will have a step height.

[0041] Specifically, if Figure 1As shown, the epitaxial layer of the semiconductor device formed using the preparation process in the comparative embodiment has steps. That is, the height of the formed epitaxial layer 11 at the doped buried layer location is inconsistent with the height elsewhere, resulting in a step difference or step height. The step height of the epitaxial layer significantly affects the exposure process window in subsequent processes, thereby affecting the performance of the semiconductor device.

[0042] In order to solve the problems existing in the process of preparing the epitaxial layer of semiconductor devices in the related art, the present application provides a process method for manufacturing semiconductor devices. The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0043] See also Figure 2 , Figure 2 It is a flow chart of a process method for a semiconductor device provided in one embodiment of the present application. In this embodiment, the semiconductor device may be a Bipolar device, a CMOS device, or a DMOS device. The process method for a semiconductor device provided in some embodiments of the present application adopts a process flow of two epitaxial growths, wherein a first epitaxial layer is formed in advance on the interface of the doped buried layer through the first epitaxial growth, and a second epitaxial layer with equal deposition thickness is formed on a semiconductor substrate with a roughly flat surface through the second epitaxial growth, which not only accurately controls the morphology of the second epitaxial layer, ensures the uniformity of the second epitaxial layer, avoids the formation of steps on the second epitaxial layer, and effectively solves the problem of the exposure process window in the subsequent process affected by the step height, thereby effectively improving the performance of the semiconductor device. The process method specifically includes:

[0044] Step S11: providing a semiconductor substrate.

[0045] In some embodiments, the semiconductor substrate may include a semiconductor substrate, and may further include a semiconductor substrate and a pad oxide layer formed on the semiconductor substrate. Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of a semiconductor substrate in one embodiment of the present application. Figure 3As shown, the material of the semiconductor substrate 21 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, etc., and can also be silicon on insulator (SOI) or germanium on insulator (GOI), or can also be other materials, such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP, etc., or can also be a combination of the above materials. The present application does not specifically limit the material of the semiconductor substrate 21. In some embodiments of the present application, the semiconductor substrate 21 can be a silicon substrate. Specifically, the semiconductor substrate 21 includes a top surface and a bottom surface arranged opposite to each other. It will be understood by those skilled in the art that, in the present application, the top surface of the semiconductor substrate 21 refers to the surface of the semiconductor substrate 21 on which the epitaxial layer is formed, that is, through this surface of the semiconductor substrate 21, related semiconductor devices, such as bipolar devices, CMOS devices or DMOS devices, etc., can be formed in the semiconductor substrate 21. In some embodiments, the pad oxide layer 22 formed on the semiconductor substrate 21 can be used to capture defects on the surface of the semiconductor substrate 21. Specifically, the pad oxide layer 22 can be a silicon oxide layer grown by oxidation on the surface of the semiconductor substrate 21 to capture defects on the surface of the silicon semiconductor substrate 21. In this embodiment, the thickness of the pad oxide layer 22 is generally thin. Optionally, the thickness of the pad oxide layer 22 is approximately Preferably, the thickness of the pad oxide layer 22 is in the range of

[0046] Step S12: forming a doped buried layer in the semiconductor substrate.

[0047] In some embodiments, a doped buried layer is formed on a side of the semiconductor substrate 21 where the top surface is located.

[0048] Specifically, Figure 4-6 A schematic structural diagram of forming a doped buried layer in a semiconductor substrate according to an embodiment of the present application is shown.

[0049] In a specific implementation, a pad oxide layer 22 is provided on the semiconductor substrate 21. The pad oxide layer 22 may be located on the top surface of the semiconductor substrate 21. Before forming the doped buried layer in the semiconductor substrate, the process method of the semiconductor device further includes the following steps:

[0050] Step S12a: forming a mask layer on the semiconductor substrate having the pad oxide layer.

[0051] Specifically, see Figure 4 , Figure 4 for Figure 3 The schematic diagram of the structure of forming a mask layer on a semiconductor substrate in the embodiment shown is shown. Figure 4As shown, in step S12a, a mask layer 23 is formed on the semiconductor substrate 21 having the pad oxide layer 22 by coating a photoresist on the surface of the semiconductor substrate 21 having the pad oxide layer 22 (specifically, on the surface of the pad oxide layer 22).

[0052] In this embodiment, the mask layer 23 may be a photoresist layer.

[0053] Step S12b: patterning the mask layer and the pad oxide layer, and using the patterned mask layer and the pad oxide layer as masks to form a doped buried layer in the semiconductor substrate.

[0054] Specifically, see Figure 5 , Figure 5 for Figure 4 The schematic diagram of the structure of the patterned mask layer and the pad oxide layer in the embodiment shown is shown. Figure 5 As shown, the mask layer 23 and the pad oxide layer 22 can be patterned through steps such as exposure, development, and etching, and the ion implantation window can be defined. Figure 5 In the illustrated embodiment, notches or openings may be formed in the patterned mask layer 23 and pad oxide layer 22, and the notches or openings terminate at the surface of the semiconductor substrate 21 adjacent to the pad oxide layer 22, thereby forming an ion implantation window. In other words, after patterning the mask layer 23 and pad oxide layer 22, portions of the pad oxide layer are removed from the regions corresponding to the ion implantation windows, while the pad oxide layer remains except for the regions corresponding to the ion implantation windows.

[0055] In this embodiment, the mask layer 23 and the pad oxide layer 22 may be patterned by wet etching.

[0056] Furthermore, during the wet etching process, the mask layer 23 and the pad oxide layer 22 are etched. Furthermore, a suitable etchant, such as phosphoric acid or hydrofluoric acid, can be selected based on the material being etched. In a specific implementation, the mask layer 23 and the pad oxide layer 22 are wet-etched simultaneously to form an ion implantation window.

[0057] Further, see Figure 6 , Figure 6 for Figure 5 The structure diagram of the semiconductor substrate forming the doped buried layer in the embodiment shown is shown. Figure 6 As shown, in this embodiment, the patterned mask layer 23 and the pad oxide layer 22 are used as masks to form a doped buried layer 24 in the semiconductor substrate 21 .

[0058] Specifically, the doping process of the buried layer can be selected from melt doping, gas phase doping, neutron doping, ion implantation doping and surface coating doping. In this embodiment, an ion implantation doping process is adopted. Among them, the ion implantation method may include the following three methods: direct implantation, indirect implantation and multiple implantation. Among them, direct implantation refers to the direct injection of ions into the silicon substrate through the ion implantation window. Indirect implantation refers to the injection of ions into the substrate crystal after passing through a dielectric film or photoresist. Multiple implantation can be performed by multiple injections of doping ions so that the longitudinal distribution of the doping ions is precisely controllable, or it can be performed by multiple injections of doping ions of different energies and doses into the silicon substrate so that the distribution of the doping ions is the desired design shape. In this embodiment, the ion implantation method can be any one of direct implantation, indirect implantation and multiple implantation.

[0059] Specifically, if Figure 5 and Figure 6 As shown, after the mask layer 23 and the pad oxide layer 22 are patterned, an ion implantation window is formed on the semiconductor substrate 21. Furthermore, through the ion implantation window, an ion implantation method is used to form a doped buried layer 24 in the semiconductor substrate 21 below the bottom of the ion implantation window. Specifically, in some embodiments, the doped buried layer 24 is an N-type doped buried layer, and the process conditions of the ion implantation are: the implanted impurities can be arsenic, antimony, or other pentavalent elements, the implantation energy range is 10Kev to 200Kev, preferably, the implantation energy range is 10Kev to 100Kev, and the dose range is 2E12 cm -2 ~5E16cm -2 , preferably, the dose range is 5E14 cm -2 ~5E15cm -2 The ion implantation method may be direct implantation, indirect implantation, or multiple implantations. Thus, in this embodiment, an N-type doped buried layer is formed in the semiconductor substrate 21 by using the patterned mask layer 23 and the pad oxide layer 22 as masks and employing an ion implantation process.

[0060] Step S13: performing a first epitaxial growth on the interface of the doped buried layer to form a first epitaxial layer.

[0061] See also Figure 7 , Figure 7 for Figure 6 The schematic structural diagram of the semiconductor substrate 21 with the mask layer removed in the embodiment shown is shown. Figure 7As shown, before forming the first epitaxial layer 25 on the interface of the doped buried layer 24, the process method may further include removing the mask layer. Specifically, the photoresist formed on the pad oxide layer 22 is removed. For example, the photoresist may be removed by dry plasma etching or wet cleaning. The specific etching method can be selected according to the type of photoresist and is not specifically limited in this application.

[0062] See also Figure 8 , Figure 8 for Figure 7 A schematic structural diagram of a first epitaxial layer formed on the interface of the doped buried layer in the embodiment shown.

[0063] Specifically, epitaxial growth processes primarily include vapor phase epitaxy, liquid phase epitaxy, solid phase epitaxy, and molecular beam epitaxy. Of these, vapor phase epitaxy is the most mature and easily controls epitaxial layer thickness, impurity concentration, and lattice integrity. Therefore, vapor phase epitaxy has long been a dominant technology in silicon epitaxy. In this embodiment, vapor phase epitaxy is preferably used for the initial epitaxial growth on the interface of the doped buried layer.

[0064] like Figure 8 As shown, in a specific implementation, a first epitaxial growth region is defined on the interface of the doped buried layer 24, wherein the first epitaxial growth region may correspond to the region defined by the ion implantation window (i.e., the region where the pad oxide layer is partially removed). Furthermore, by controlling the gas concentration, the first epitaxial layer 25 may be formed on the interface of the doped buried layer 24 within the first epitaxial growth region through an epitaxial growth process. In this embodiment, the first epitaxial layer 25 is self-alignedly grown along the original lattice direction of the semiconductor substrate 21 within the first epitaxial growth region. The original lattice includes the single crystal silicon of the substrate. Therefore, in some embodiments, the first epitaxial growth process may also be referred to as selective epitaxial growth, i.e., epitaxial growth performed within a defined region on the semiconductor substrate 21. Specifically, the first epitaxial growth region corresponds to the region defined by the ion implantation window, i.e., the first epitaxial growth region corresponds to the growth region of the doped buried layer 24 or the region where the pad oxide layer is partially removed. Therefore, the first epitaxial layer 25 is formed on the interface of the doped buried layer 24, while the corresponding areas on the semiconductor substrate 21 where the pad oxide layer 22 is retained cannot form an epitaxial layer due to the presence of the pad oxide layer 22. In other words, the first epitaxial layer 25 is formed by epitaxial growth aligned with the corresponding lattice of the doped buried layer 24.

[0065] In this embodiment, the top surface of the formed first epitaxial layer 25 is higher than the top surface of the pad oxide layer 22, that is, the deposition thickness of the first epitaxial layer 25 is slightly greater than the thickness of the pad oxide layer 22. Specifically, the thickness range of the first epitaxial layer 25 is Preferably, the thickness of the first epitaxial layer 25 is in the range of Of course, those skilled in the art can also set it according to design requirements. Here, the "top surface of the first epitaxial layer 25" refers to the surface of the first epitaxial layer 25 away from the semiconductor substrate 21. Similarly, the "top surface of the pad oxide layer 22" refers to the surface of the pad oxide layer 22 away from the semiconductor substrate 21.

[0066] The first epitaxial layer 25 is a P-type semiconductor layer corresponding to the type of the doped buried layer 24. Of course, those skilled in the art will understand that when an N-type substrate and a P-type doped buried layer are used, the first epitaxial layer 25 can also be an epitaxially grown N-type semiconductor layer.

[0067] Step S14: performing oxidation diffusion on the doped buried layer in the semiconductor substrate and the first epitaxial layer.

[0068] See also Figure 9 , Figure 9 for Figure 8 A schematic diagram of the structure of the semiconductor substrate undergoing oxidation diffusion in the illustrated embodiment. In a specific implementation process, a semiconductor substrate 21 having a first epitaxial layer 25 formed on the interface of the doped buried layer 24 is subjected to a thermal oxidation treatment, so that the doped buried layer 24 undergoes oxidation diffusion between the semiconductor substrate 21 and the first epitaxial layer 25. During the oxidation diffusion process, the first epitaxial layer 25 and the pad oxide layer 22 are oxidized to form an oxide layer 26. Specifically, the semiconductor substrate 21 having the first epitaxial layer 25 can be placed in a sealed reaction chamber; the reaction chamber is heated, for example, to 1000°C-1200°C; oxygen is introduced into the reaction chamber and the oxygen flow rate is controlled, and the reaction is carried out for a period of time to prepare the oxide layer 26; the reaction chamber is cooled, and the semiconductor substrate 21 having the oxide layer 26 formed thereon is removed from the reaction chamber for standby use.

[0069] In some embodiments, further Figure 9 As shown, the oxide layer 26 may include: an oxide layer formed by oxidation of the region corresponding to the first epitaxial layer 25, and an oxide layer that continues to grow after oxidation of the region corresponding to the pad oxide layer 22. The thickness of the oxide layer that continues to grow after oxidation of the region corresponding to the pad oxide layer 22 is at least 10 times the thickness of the pad oxide layer 22 before oxidation. Specifically, the thickness of the oxide layer that continues to grow after oxidation of the region corresponding to the pad oxide layer 22 is approximately Preferably, the thickness of the oxide layer that continues to grow after oxidation in the area corresponding to the pad oxide layer 22 is in the range of

[0070] In some embodiments, the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 is approximately flush with the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22 and is adjacent to the top surface of the semiconductor substrate 21. Furthermore, the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 is higher than the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22, that is, after the oxidation diffusion process in step S14 above, the thickness of the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 is greater than the thickness of the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22. It is understandable that after the oxidation diffusion process in step S14 above, the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 and the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22 can be fused into one.

[0071] In some embodiments, the semiconductor substrate 21 can be divided into a first region and a second region. The first region is the region where the oxide layer formed by oxidation of the region corresponding to the first epitaxial layer 25 is located. The second region is the remaining region on the semiconductor substrate 21 except the first region, that is, the region where the oxide layer continues to grow after oxidation of the region corresponding to the pad oxide layer 22 is located. Therefore, after the processing of step S14, the top surface of the semiconductor substrate 21 (the surface for the subsequent formation of the second epitaxial layer) is roughly planar; that is, the top surface of the first region (the surface of the oxide layer formed by oxidation of the region corresponding to the adjacent first epitaxial layer 25) is roughly flush with the top surface of the second region (the surface of the oxide layer continued to grow after oxidation of the region corresponding to the adjacent pad oxide layer 22).

[0072] Thus, in this embodiment, a first epitaxial layer 25 is pre-formed on the interface of the doped buried layer 24 through step S13. Therefore, in the step of performing oxidation diffusion on the doped buried layer 24, since the first epitaxial layer 25 is pre-formed on the interface of the doped buried layer 24, the first epitaxial layer 25 can be oxidized first, thereby preventing the silicon in the doped buried layer 24 from being oxidized. Therefore, compared to the preparation process in the comparative embodiment, in the oxidation diffusion step of this embodiment, the first epitaxial layer 25 formed on the doped buried layer 24 can replace the doped buried layer 24 in the oxidation reaction, and the deposited oxide layer formed by oxidation in the corresponding area of the first epitaxial layer 25 is thicker, thereby preventing the silicon in the doped buried layer 24 from forming a partial oxide layer. As a result, after removing the oxide layer 26, it is possible to avoid leaving grooves on the semiconductor substrate 21.

[0073] Furthermore, before oxidizing and diffusing the doped buried layer in the semiconductor substrate and the first epitaxial layer, the process method further includes patterning the first epitaxial layer. This is because part of the original lattice is lost during the ion implantation process. Patterning the first epitaxial layer 25 allows the first epitaxial layer 25 to be aligned with the ion implantation window, thereby allowing the oxide layer formed by subsequent oxidation of the corresponding region of the first epitaxial layer 25 to be aligned with the ion implantation window.

[0074] Step S15: performing a second epitaxial growth on the semiconductor substrate to form a second epitaxial layer, and the deposition thickness of the second epitaxial layer is equal.

[0075] In a specific implementation, before performing the second epitaxial growth on the semiconductor substrate 21 , the process method further includes: removing the oxide layer 26 formed by oxidation diffusion in step S14 .

[0076] See also Figure 10 , Figure 10 for Figure 9 A schematic diagram of the structure of the semiconductor substrate after the oxide layer is removed in the illustrated embodiment. In one specific implementation, a wet etching process can be used to remove the oxide layer 26. Since the surface of the oxide layer 26 formed by oxidation in the region corresponding to the first epitaxial layer 25 adjacent to the semiconductor substrate 21 is approximately flush with the surface of the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22 adjacent to the semiconductor substrate 21, the top surface of the semiconductor substrate 21 obtained after removing the oxide layer 26 is approximately flat. Therefore, during the oxidation diffusion step of the doped buried layer 24, since the first epitaxial layer 25 is formed on the doped buried layer 24 in step S13, the first epitaxial layer 25 can undergo an oxidation reaction to form an oxide layer, thereby preventing the silicon in the doped buried layer 24 from being oxidized to form a partial oxide layer. As a result, before forming the second epitaxial layer, after removing the oxide layer 26, no grooves are left in the region of the doped buried layer 24. That is, the top surface of the semiconductor substrate 21 after removing the oxide layer 26 is approximately flat.

[0077] See also Figure 11 , Figure 11 for Figure 10 The second epitaxial layer 27 is formed on the semiconductor substrate in the embodiment shown. Figure 10 and Figure 11As shown, after removing the oxide layer 26, the top surface of the semiconductor substrate 21 obtained is substantially planar. Through the epitaxial growth process, a second epitaxial growth is performed on the top surface of the semiconductor substrate 21, that is, growth continues along the original crystal lattice to form a second epitaxial layer 27 on the semiconductor substrate 21, and the surface of the second epitaxial layer 27 on the side away from the semiconductor substrate 21 is planar. Optionally, the specific method of the second epitaxial growth process in this step can refer to the epitaxial growth processing method in the related art, and this application does not limit it.

[0078] In some embodiments, the thickness of the second epitaxial layer 26 is approximately in the range of 2 to 8 um. Preferably, the thickness of the second epitaxial layer 26 is in the range of 3 to 6 um.

[0079] Here, "the surface of the second epitaxial layer 27 facing away from the semiconductor substrate 21 is planar" means that all locations on the surface of the second epitaxial layer 27 facing away from the semiconductor substrate 21 are at the same level, with virtually no grooves or pits. The second epitaxial layer 27 generally includes a first portion corresponding to the first region and a second portion corresponding to the second region. The surface of the first portion facing away from the semiconductor substrate 21 is substantially flush with the surface of the second portion facing away from the semiconductor substrate 21.

[0080] In this embodiment, because the first epitaxial layer 25 is pre-formed on the doped buried layer 24 in step S13, and the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 in step S14 is relatively thick, oxidation of the silicon in the doped buried layer 24 to form a partial oxide layer is avoided. Furthermore, before forming the second epitaxial layer 27, after removing the oxide layer 26, no grooves are left in the region of the doped buried layer 24, that is, the formation of grooves on the semiconductor substrate 21 is avoided. As a result, the surface of the oxide layer formed by oxidation in the region corresponding to the first epitaxial layer 25 on the side adjacent to the semiconductor substrate 21 is roughly flush with the surface of the oxide layer that continues to grow by oxidation in the region corresponding to the pad oxide layer 22 on the side adjacent to the semiconductor substrate 21. After removing the oxide layer 26, since the top surface of the semiconductor substrate 21 is roughly planar, during the second epitaxial growth of the semiconductor substrate 21, the deposition thickness of the second epitaxial layer 27 formed along the original crystal lattice of the semiconductor substrate 21 that is roughly flush with the top surface is equal, and the surface of the second epitaxial layer 27 on the side away from the semiconductor substrate 21 is planar, thereby precisely controlling the morphology of the second epitaxial layer 27, avoiding affecting the exposure process window in subsequent processes, and effectively improving the performance of the semiconductor device.

[0081] In some embodiments, the second epitaxial layer 27 may also be a P-type semiconductor layer corresponding to the type of the doped buried layer 24. Of course, those skilled in the art will appreciate that when an N-type substrate and a P-type doped buried layer are used, the second epitaxial layer 27 may also be an epitaxially grown N-type semiconductor layer.

[0082] It should be noted that, in step S15, the dopant ions in the doped buried layer 24 will also diffuse toward the second epitaxial layer 27. Specifically, during the formation of the second epitaxial layer 27, the dopant ions in the doped buried layer 24 will also diffuse toward the second epitaxial layer 27, so that part of the second epitaxial layer 27 also constitutes part of the doped buried layer 24 due to doping, that is, forming the following: Figure 11 The structure shown.

[0083] The above describes in detail the preparation method of the embodiment of the present application. In addition, the present application also provides a semiconductor device formed by the above method. The semiconductor device may include: a semiconductor substrate 21, and a second epitaxial layer 27. The second epitaxial layer 27 is provided on the semiconductor substrate 21. The second epitaxial layer 27 can be prepared by the process method as described above. The deposition thickness of the second epitaxial layer 27 is equal. In some embodiments, the surface of the side of the second epitaxial layer 27 away from the semiconductor substrate 21 is flat, that is, the contact interface between the semiconductor substrate 21 and the second epitaxial layer 27 is flat, and there are almost no pits or grooves.

[0084] In the semiconductor device provided by the present application, the semiconductor substrate 21 is subjected to two epitaxial growths to form a first epitaxial layer 25 in advance on the interface of the doped buried layer 24 of the semiconductor substrate 21, and a second epitaxial layer 27 of equal deposition thickness is formed on the semiconductor substrate 21 through a second epitaxial growth. This not only accurately controls the morphology of the second epitaxial layer 27 and ensures the uniformity of the second epitaxial layer 27, but also avoids the formation of steps in the epitaxial layer, effectively solves the problem of the step height affecting the exposure process window in the subsequent process, thereby effectively improving the performance of the semiconductor device.

[0085] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor base material, wherein the semiconductor base material comprises a semiconductor substrate and a pad oxide layer formed on the semiconductor substrate; forming a doped buried layer in the semiconductor substrate; Performing a first epitaxial growth on the interface of the doped buried layer to form a first epitaxial layer; performing oxidation diffusion on the doped buried layer in the semiconductor substrate and the first epitaxial layer, wherein during the oxidation diffusion process, the first epitaxial layer and the pad oxide layer are oxidized to form an oxide layer; removing the oxide layer; and performing a second epitaxial growth on the semiconductor substrate to form a second epitaxial layer; Wherein, the deposition thickness of the second epitaxial layer is equal.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A surface of the second epitaxial layer away from the semiconductor substrate is flat.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Performing a first epitaxial growth on the interface of the doped buried layer to form the first epitaxial layer includes: defining a first epitaxial growth region on the interface of the doped buried layer; and Epitaxial growth is performed in the first epitaxial growth region so that the first epitaxial layer is formed on the interface of the doped buried layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the oxidation diffusion of the doped buried layer on the semiconductor substrate and the first epitaxial layer, the process method of the semiconductor device further includes: patterning the first epitaxial layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the doped buried layer in the semiconductor substrate, the process method for the semiconductor device further includes: forming a mask layer on the semiconductor substrate having the pad oxide layer; and The mask layer and the pad oxide layer are patterned to form the doped buried layer in the semiconductor substrate using the patterned mask layer and the pad oxide layer as masks.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The top surface of the formed first epitaxial layer is higher than the top surface of the pad oxide layer.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The thickness of the oxygen pad layer is in the range of The thickness of the first epitaxial layer is in the range of The thickness of the second epitaxial layer ranges from 2 to 8 μm.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The forming of a doped buried layer in the semiconductor substrate comprises: Based on the patterned mask layer and the pad oxide layer, ion implantation is performed on the semiconductor substrate to form a doped buried layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The process conditions of the ion implantation are: The impurities injected are arsenic or antimony; The implantation energy range is 10Kev to 200Kev; and Dose range 2E12 cm -2 ~5E16cm -2 .

10. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of patterning the mask layer and the pad oxide layer to form the doped buried layer in the semiconductor substrate using the patterned mask layer and the pad oxide layer as masks includes etching the mask layer and the pad oxide layer through a wet etching process.

11. The method for manufacturing a semiconductor device according to claim 5, wherein: Before performing the first epitaxial growth on the interface of the doped buried layer to form the first epitaxial layer, the process method of the semiconductor device further includes: removing the mask layer.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: The doped buried layer is an N-type doped buried layer, and the first epitaxial layer and / or the second epitaxial layer is a P-type semiconductor layer.

13. A semiconductor device, characterized in that: include: semiconductor substrates; A second epitaxial layer is provided on the semiconductor substrate, wherein the second epitaxial layer is prepared by the process method according to any one of claims 1 to 12; Wherein, the deposition thickness of the second epitaxial layer is equal.

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