Semiconductor device and method of forming the same

Abstract

This invention discloses a semiconductor device and a method for forming the same. The semiconductor device includes: a substrate, a current collector layer on the substrate, a base layer on the current collector layer, and an emitter layer on the base layer; wherein the current collector layer, the base layer, and the emitter layer include doped ions; a dielectric layer covering a first common layer, the first common layer being one of the current collector layer, the base layer, and the emitter layer; a resistive layer located on the dielectric layer; and a first connection portion, one end of which is electrically connected to one end of the resistive layer, and the other end of which is electrically connected to the first common layer. Using this technical solution, a resistor with a larger resistance value can be formed within a unit area of ​​the semiconductor device, thereby reducing the area of ​​the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for forming the same. Background Technology

[0002] Resistors are indispensable components in electronic circuits, playing a crucial role. During chip manufacturing, resistors are produced to meet the required resistance values ​​according to design specifications.

[0003] In existing technologies, when forming resistors in semiconductor devices, it is usually necessary to increase the length of the resistor to achieve the desired resistance value. However, increasing the resistance value by increasing the resistor length results in an excessively large area occupied by the resistor, making the semiconductor device relatively large. Summary of the Invention

[0004] The technical problem solved by this invention is how to form a resistor with a larger resistance value within a unit area of ​​a semiconductor device, so as to reduce the area of ​​the semiconductor device.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device comprising: a substrate, a current collector layer on the substrate, a base layer on the current collector layer, and an emitter layer on the base layer; wherein the current collector layer, the base layer, and the emitter layer comprise doped ions; a dielectric layer covering a first common layer, wherein the first common layer is one of the current collector layer, the base layer, and the emitter layer; a resistive layer located on the dielectric layer; and a first connection portion, one end of which is electrically connected to one end of the resistive layer, and the other end of which is electrically connected to the first common layer.

[0006] Optionally, the semiconductor device further includes: a first resistive electrode and a second resistive electrode, wherein the first resistive electrode is located at the other end of the resistive layer and is electrically connected to the resistive layer, and the second resistive electrode is located on the first common layer and is electrically connected to the first common layer.

[0007] Optionally, the first connection portion is located near one end of the resistive layer, and the second resistive electrode is located near the other end of the resistive layer.

[0008] Optionally, the first common layer is a base layer.

[0009] Optionally, the semiconductor device further includes: a second connection portion, one end of which is electrically connected to the first common layer, and the other end of which is electrically connected to a second common layer, wherein the second common layer is one of the collector layer, the base layer, and the emitter layer, and the second common layer is different from the first common layer.

[0010] Optionally, the semiconductor device further includes: a third connection portion, one end of which is electrically connected to the second common layer, and the other end of which is electrically connected to the third common layer. The third common layer is one of the collector layer, the base layer, and the emitter layer. The third common layer is different from the first common layer and different from the second common layer.

[0011] Optionally, the semiconductor device further includes: a heterojunction bipolar transistor, the heterojunction bipolar transistor including the substrate, the collector layer, the base layer, and the emitter layer; the dielectric layer further covers the heterojunction bipolar transistor; and the resistive layer is placed next to the heterojunction bipolar transistor.

[0012] Accordingly, the present invention also provides a method for forming a semiconductor device, the method comprising: providing a substrate; forming a current collector layer, a base layer, and an emitter layer on the substrate; wherein the current collector layer, the base layer, and the emitter layer include doped ions; forming a dielectric layer covering a first common layer, the first common layer being one of the current collector layer, the base layer, and the emitter layer; forming a resistive layer on the dielectric layer; and forming a first connection portion, one end of the first connection portion being electrically connected to one end of the resistive layer, and the other end of the first connection portion being electrically connected to the first common layer.

[0013] Optionally, the method for forming the semiconductor device further includes: forming a first resistive electrode and a second resistive electrode, wherein the first resistive electrode is located at the other end of the resistive layer and electrically connected to the resistive layer, and the second resistive electrode is located on the first common layer and electrically connected to the first common layer.

[0014] Optionally, the method for forming the semiconductor device further includes: forming a second connection portion, one end of the second connection portion being electrically connected to the first common layer, and the other end of the second connection portion being electrically connected to a second common layer, wherein the second common layer is one of the collector layer, the base layer, and the emitter layer, and the second common layer is a different layer from the first common layer.

[0015] Optionally, a third connection portion is formed, one end of which is electrically connected to the second common layer, and the other end of which is electrically connected to the third common layer. The third common layer is one of the current collector layer, the base layer, and the emitter layer. The third common layer is different from the first common layer and different from the second common layer.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] An embodiment of the present invention provides a semiconductor device comprising a substrate, a collector layer on the substrate, a base layer on the collector layer, and an emitter layer on the base layer, wherein the collector layer, base layer, and emitter layer include doped ions; a dielectric layer covering a first common layer, the first common layer being one of the collector layer, base layer, and emitter layer; a resistive layer on the dielectric layer; and a first connection portion, one end of which is electrically connected to one end of the resistive layer, and the other end of which is electrically connected to the first common layer. Since the collector layer, base layer, and emitter layer are doped with ions and have a certain resistance value, the current can be increased by connecting the resistive layer in series with the first common layer, allowing current to flow through both the first common layer and the resistive layer, thereby increasing the current transmission path. By connecting the resistive layer in series with the first common layer, the current transmission path can be increased without increasing the semiconductor device area, or even by reducing the semiconductor device area, thereby increasing the resistance value per unit area of ​​the semiconductor device.

[0018] Furthermore, by connecting the second common layer, the third common layer, the resistive layer, and the first common layer in series, the current transmission path can be further increased without changing the area of ​​the semiconductor device, thereby further increasing the resistance value per unit area of ​​the semiconductor device.

[0019] Furthermore, the first connection portion can be disposed at one end near the resistive layer, and the second resistive electrode can be disposed at the other end near the resistive layer. This allows full utilization of the extension length of the first common layer, enabling current to flow through the first common layer as completely as possible, thereby increasing the resistance value per unit area of ​​the semiconductor device. Attached Figure Description

[0020] Figure 1 This is an overall flowchart of a method for forming a semiconductor device provided in an embodiment of the present invention;

[0021] Figures 2 to 9 This is a schematic diagram of the steps in a method for forming a semiconductor device according to an embodiment of the present invention;

[0022] Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0023] Figure 11 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0024] Figure 12 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0025] Figure 13 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, in existing technologies, when forming resistors in semiconductor devices, it is usually necessary to increase the length of the resistor to achieve the desired resistance value. However, increasing the resistance value by increasing the resistor length results in an excessively large area occupied by the resistor, making the area of ​​the semiconductor device relatively large.

[0027] An embodiment of the present invention provides a semiconductor device comprising a substrate, a collector layer on the substrate, a base layer on the collector layer, and an emitter layer on the base layer, wherein the collector layer, base layer, and emitter layer include doped ions; a dielectric layer covering a first common layer, the first common layer being one of the collector layer, base layer, and emitter layer; a resistive layer on the dielectric layer; and a first connection portion, one end of which is electrically connected to one end of the resistive layer, and the other end of which is electrically connected to the first common layer. Since the collector layer, base layer, and emitter layer are doped with ions and have a certain resistance value, the current can be increased by connecting the resistive layer in series with the first common layer, allowing current to flow through both the first common layer and the resistive layer, thereby increasing the current transmission path. By connecting the resistive layer in series with the first common layer, the current transmission path can be increased without increasing the semiconductor device area, or even by reducing the semiconductor device area, thereby increasing the resistance value per unit area of ​​the semiconductor device.

[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0029] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Figure 1 This is an overall flowchart of a method for forming a semiconductor device provided in an embodiment of the present invention.

[0031] Specifically, such as Figure 1 As shown, a method for forming a semiconductor device may include the following steps:

[0032] In step 101, a substrate is provided, and a current collector layer, a base layer, and an emitter layer are formed on the substrate.

[0033] In step 102, a dielectric layer is formed;

[0034] In step 103, a resistive layer is formed;

[0035] In step 104, a first connecting portion is formed.

[0036] Figures 2 to 9 This is a schematic diagram of the steps in a method for forming a semiconductor device according to an embodiment of the present invention.

[0037] Please refer to Figure 1 and Figure 2 In step 101, a substrate 200 is provided, and an initial current collector layer 201, an initial base layer 202, and an initial emitter layer 203 are formed on the substrate 200 in sequence.

[0038] In a specific embodiment, the semiconductor device may include a heterojunction bipolar transistor, which is formed based on an initial collector layer 201, an initial base layer 202 and an initial emitter layer 203.

[0039] In specific embodiments, the material of the substrate 200 may include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or indium gallium arsenide (InGaAsP).

[0040] In a non-limiting embodiment, the initial emitter layer 203 is doped with a first ion, and the initial base layer 202 is doped with a second ion, the electrical type of the first ion being different from that of the second ion; the initial collector layer 201 is doped with a third ion, the electrical type of the third ion being different from that of the second ion, and the electrical type of the third ion being the same as that of the first ion. Specifically, the doping type of the heterojunction bipolar transistor can be NPN type doping or PNP type doping.

[0041] In a non-limiting embodiment, a transition layer (not shown) may also be formed between the initial current collector layer 201 and the substrate 200 to form a better ohmic contact and reduce resistance.

[0042] Please refer to Figure 1 and Figure 3In step 102, after forming the initial current collector layer 201, the initial base layer 202, and the initial emitter layer 203, a second resistive electrode 204 and a first connecting electrode 205 are formed on the initial emitter layer 203. Specifically, a layer of photoresist can be coated on the initial emitter layer 203 first, and after exposure and development, the second resistive electrode 204 and the first connecting electrode 205 can be formed on the initial emitter layer 203 by vapor deposition. The second resistive electrode 204 and the first connecting electrode 205 respectively cover a portion of the top surface of the initial emitter layer 203. The second resistive electrode 204 and the first connecting electrode 205 can be a single metal layer or multiple metal layers stacked sequentially.

[0043] In a specific embodiment, the contact between the second resistive electrode 204 and the first connecting electrode 205 and the initial emission layer 203 is an ohmic contact.

[0044] In a non-limiting embodiment, the second resistive electrode 204 may be disposed at a first end of the first common layer, and the first connecting electrode 205 may be disposed at a second end of the first common layer. By disposing the second resistive electrode 204 and the first connecting electrode 205 at both ends of the first common layer, the length of the first common layer can be fully utilized, allowing the current to flow a longer distance in the first common layer, thereby increasing the resistance value per unit area.

[0045] In this embodiment, the first common layer is the initial emission layer 203.

[0046] In a non-limiting embodiment, the initial base layer 202 can be used as the first common layer. Since the initial base layer 202 is the thinnest layer, and the resistance of a conductor is inversely proportional to the cross-sectional area of ​​the conductor, using the initial base layer 202 as the first common layer can achieve a higher resistance value per unit area.

[0047] In a specific embodiment, after forming the second resistive electrode 204 and the first connecting electrode 205, a dielectric layer 206 is formed on the top surface of the second resistive electrode 204, the first connecting electrode 205, and the initial emitter layer 203 using a chemical vapor deposition method. The material of the dielectric layer 206 can be a nitride, such as silicon nitride.

[0048] Please refer to Figure 4 After forming the dielectric layer 206, the dielectric layer 206 and the initial emitter layer are etched using a dry etching process. Specifically, a first patterned layer (not shown) is formed on the dielectric layer 206, covering a portion of the top surface of the dielectric layer 206; the dielectric layer 206 and the initial emitter layer are etched using the first patterned layer as a mask until the top surface of the initial base layer 202 is exposed, forming the emitter layer 207. The emitter layer 207 covers a portion of the top surface of the initial base layer 202.

[0049] Furthermore, after forming the emitter layer 207, a dielectric layer is formed on the top surface of the initial base layer 202 using chemical vapor deposition. For simplicity, the dielectric layer in all figures is uniformly identified by reference numeral 206.

[0050] Please refer to Figure 5 The dielectric layer 206 and the initial base layer are etched, for example, using a dry etching process. Specifically, a second patterned layer (not shown) is formed on the dielectric layer 206, covering a portion of the top surface of the dielectric layer 206; the dielectric layer 206 and the initial base layer are etched using the second patterned layer as a mask until the top surface of the initial collector layer 201 is exposed, forming a base layer 208, which covers a portion of the top surface of the initial collector layer 201.

[0051] In a non-limiting embodiment, after forming the base layer 208, ion implantation can be performed on a peripheral portion of the substrate 200 and the initial current collector layer 201 to neutralize the ions in that portion, forming an insulating region 209. The insulating region 209 surrounds the initial current collector layer 201. The electrical type of the implanted ions differs from the electrical type of the doped ions in the substrate 200 and the initial current collector layer 201.

[0052] Furthermore, after forming the insulating region 209, a dielectric layer 206 is formed on the top surface of the initial current collector layer 201 and the top surface of the insulating region 209 using a chemical vapor deposition method.

[0053] It should be noted that the insulating region 209 can be formed by ion implantation or by trench filling, and this application does not limit it.

[0054] Please refer to Figure 1 and Figure 6 In step 103, after forming the insulating region 209, the dielectric layer 206 is etched, for example, using a dry etching process, to form a first dielectric layer opening 220. The bottom of the first dielectric layer opening 220 exposes a portion of the top surface of the second resistive electrode 204 and the first connecting electrode 205.

[0055] Furthermore, a photoresist layer is coated on the dielectric layer 206. After exposure and development, a resistive layer 210 is formed on the dielectric layer 206 by vapor deposition. The resistive layer 210 is located on a portion of the top surface of the dielectric layer 206.

[0056] In a specific embodiment, since a multilayer dielectric layer 206 is formed when the emitter layer 207 and the base layer 208 are formed, a dielectric layer groove can be etched at the same time as the first dielectric layer opening 220 is formed, and a resistor layer 210 is formed in the dielectric layer groove to reduce the height of the semiconductor device.

[0057] It should be noted that the material of the resistive layer 210 can be a metallic element or any other material that can provide a resistance value; this application does not impose any restrictions on this.

[0058] Please refer to Figure 1 and Figure 7 In step 104, a layer of photoresist is first coated onto the first surface. After exposure and development, a first connection portion 211 is formed on the first surface by vapor deposition. The first surface includes a portion of the top surface of the resistive layer 210, a portion of the top surface of the dielectric layer 206, and the exposed portion of the top surface of the first connecting electrode 205. The material of the first connection portion 211 can be copper. The first connection portion 211 can connect the resistive layer 210 and the first connecting electrode 205, allowing current to flow from the emitter layer 207 into the resistive layer 210. Specifically, the first connection portion 211 is located near one end of the resistive layer 210, and the second resistive electrode 204 is located near the other end of the resistive layer 210.

[0059] Furthermore, while forming the first connection portion 211, a first metal interconnect 221 can be formed on the second resistive electrode 204. The first metal interconnect 221 covers a portion of the top surface of the dielectric layer 206 and the exposed portion of the top surface of the second resistive electrode 204, and the first metal interconnect 221 is electrically connected to the second resistive electrode 204. Current can be introduced into the emitter layer 207 through the first metal interconnect 221.

[0060] In a specific embodiment, a third patterned layer (not shown) may be formed on the resistive layer 210, defining the pattern of the first resistive electrode 212 and exposing a portion of the top surface of the resistive layer 210. An initial first resistive electrode (not shown) is formed on the third patterned layer and the exposed resistive layer 210 using a vapor deposition process. The third patterned layer and the initial first resistive electrode on the third patterned layer are removed to form the first resistive electrode 212, which is located at the other end of the resistive layer 210 and electrically connected to the resistive layer 210. Correspondingly, one end of the first connecting portion 211 is electrically connected to one end of the resistive layer 210.

[0061] It should be noted that the initial first resistive electrode can be formed by vapor deposition or by sputtering, and this application does not limit it in this regard.

[0062] Please refer to Figure 8After the first resistive electrode 212 is formed, a dielectric layer 206 is formed on the second surface, for example, by chemical vapor deposition. The second surface includes a portion of the top surface of the resistive layer 210, a first connection portion 211, a first metal interconnect 221, and the top surface of the first resistive electrode 212.

[0063] Furthermore, the dielectric layer 206 is etched using a dry etching process to form a second dielectric layer opening 222, the bottom of which exposes a portion of the top surface of the first resistive electrode 212.

[0064] Please refer to Figure 9 After forming the second dielectric layer opening 222, a third metal interconnect 213 is formed on the third surface, which includes the exposed surface of the first resistive electrode 212 and a portion of the top surface of the dielectric layer 206. Current can be led out to the outside through the third metal interconnect.

[0065] Accordingly, embodiments of the present invention also provide a semiconductor device, please refer to [link / reference needed]. Figure 9 It includes: a substrate 200, an initial collector layer 201 on the substrate 200, a base layer 208 on the initial collector layer 201, and an emitter layer 207 on the base layer 208; a dielectric layer 206 covering a first common layer, the first common layer being one of the initial collector layer 201, the base layer 208, and the emitter layer 207; a resistive layer 210 on the dielectric layer 206; and a first connection portion 211, one end of which is electrically connected to one end of the resistive layer 210, and the other end of which is electrically connected to the first common layer.

[0066] exist Figure 9 In the embodiment shown, the first common layer is specifically the emission layer 207.

[0067] In a specific embodiment, the semiconductor device further includes a first connecting electrode 205, which is located on and in contact with the emitter layer 207. The first connecting electrode 205 is also in contact with one end of the first connecting portion 211. The emitter layer 207 and the first connecting portion 211 are located on both sides of the first connecting electrode 205.

[0068] In a specific embodiment, the semiconductor device further includes a second resistive electrode 204, a first metal interconnect 221, a first resistive electrode 212, and a third metal interconnect 213; the second resistive electrode 204 is located on the emitter layer 207, near the other end of the resistive layer 210, and the second resistive electrode 204 is in contact with the emitter layer 207; one end of the first metal interconnect 221 is electrically connected to the second resistive electrode 204, and the other end is externally connected; the first resistive electrode 212 is located at the other end of the resistive layer 210 and is in contact with the resistive layer 210; one end of the third metal interconnect 213 is electrically connected to the first resistive electrode 212, and the other end is externally connected; the third metal interconnect 213 is located above the first metal interconnect 221, and a portion of the dielectric layer 206 is located between the third metal interconnect 213 and the first metal interconnect 221.

[0069] In this embodiment of the invention, the first common layer is the emitter layer 207, and the resistive layer 210 is connected in series with the emitter layer 207 via the first connecting electrode 205 and the first connection portion 211. Current can flow into the emitter layer 207 through the second resistive electrode 204, and after flowing through the emitter layer 207, it flows into the resistive layer 210 through the first connecting electrode 205 and the first connection portion 211, and then flows out to the outside through the third metal interconnect 213 via the first resistive electrode 212. Compared to current only flowing through the resistive layer 210, this embodiment of the invention, by reusing the epitaxial layer of a heterojunction bipolar transistor and connecting the resistive layer 210 in series with the first common layer, allows current to flow through both the emitter layer 207 and the resistive layer 210, greatly increasing the current transmission path and improving the resistance value per unit area of ​​the semiconductor device. Compared to the prior art, while achieving the desired resistance value, the length of the resistive layer 210 is significantly shortened, reducing the area of ​​the semiconductor device.

[0070] It should be noted that the first common layer can also be the initial collector layer 201 or the base layer 208. For the steps regarding forming the series structure of the first common layer and the resistor layer 210, please refer to [reference needed]. Figures 2 to 9 The structural diagram shown indicates that the first common layer can be selected according to the actual situation, and this application does not impose any restrictions on it.

[0071] Figure 10 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention.

[0072] like Figure 10 The semiconductor device shown includes: a substrate 200; an initial collector layer 201 and a base layer 208 located on the substrate 200; a dielectric layer 206 covering the base layer 208; a resistive layer 210 located on the dielectric layer 206; and a first connection portion 211, one end of which is electrically connected to one end of the resistive layer 210, and the other end of which is electrically connected to a first common layer, wherein the first common layer is one of the initial collector layer 201 and the base layer 208.

[0073] In this embodiment, the first common layer is specifically the base layer 208.

[0074] In a specific embodiment, an initial collector layer 201 and a base layer 208 are covered on the substrate 200, with the base layer 208 serving as the first common layer. Current flows into the base layer 208 through the first metal interconnect and the second resistive electrode 204, and then into the resistive layer 210 through the first connecting electrode 205 and the first connection portion 211. It is then led out to the outside through the first resistive electrode 212 and the third metal layer 213. In the base of a heterojunction bipolar transistor, the current transmission path can be increased by connecting the resistive layer 210 and the base layer 208 in series, thereby increasing the resistance per unit area of ​​the semiconductor device. Simultaneously, the base layer 208 is the thinnest layer among the initial collector layer 201, the base layer 208, and the emitter layer 207. The resistance of a conductor is inversely proportional to its cross-sectional area; therefore, with all layers having the same length, using the base layer 208 as the first common layer maximizes the resistance per unit area.

[0075] It should be noted that the steps for connecting the resistive layer 210 and the base layer 208 in series in the base of a heterojunction bipolar transistor can be found in [reference needed]. Figures 2 to 9 The structural diagram shown is not repeated here.

[0076] Figure 11 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention.

[0077] like Figure 11 The semiconductor device shown includes: a substrate 200; an initial collector layer 201 located on the substrate 200; a dielectric layer 206 covering the initial collector layer 201; a resistive layer 210 located on the dielectric layer 206; and a first connection portion 211, one end of which is electrically connected to one end of the resistive layer 210, and the other end of which is electrically connected to a first common layer.

[0078] In this embodiment, the first common layer is specifically the initial collector layer 201.

[0079] In a specific embodiment, an initial collector layer 201 is covered on the substrate 200, and the first common layer is the initial collector layer 201. At this time, current flows into the initial collector layer 201 through the first metal interconnect and the second resistive electrode 204, and then into the resistive layer 210 through the first connecting electrode 205 and the first connection portion 211. It is then led out to the outside through the first resistive electrode 212 and the third metal layer 213. By connecting the resistive layer 210 and the initial collector layer 201 in series, the current transmission path is increased, thereby improving the resistance value per unit area of ​​the semiconductor device.

[0080] It should be noted that the steps for connecting the resistive layer 210 and the initial collector layer 201 in series in the base of a heterojunction bipolar transistor can be found in [reference needed]. Figures 2 to 9 The structural diagram shown is not repeated here.

[0081] Figure 12 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention.

[0082] like Figure 12 As shown, the semiconductor device includes: a substrate 200; an initial collector layer 201 on the substrate 200, a base layer 208 on the initial collector layer 201, and an emitter layer 207 on the base layer 208; a dielectric layer 206 covering a first common layer; a resistive layer 210 on the dielectric layer 206; and a first connection portion 211, one end of which is electrically connected to one end of the resistive layer 210, and the other end of which is electrically connected to the first common layer, wherein the first common layer is one of the initial collector layer 201, the base layer 208, and the emitter layer 207. Figure 13 In the embodiment shown, the first common layer is specifically the emission layer 207.

[0083] In a specific implementation, with Figure 9 The difference is that the semiconductor device also includes a second common layer. In this case, the first common layer is the emitter layer 207, and the second common layer is the base layer 208. The second resistive electrode 204 is located on the base layer 208 and is electrically connected to the base layer 208. Current can flow into the base layer 208 through the first metal connection 221 and the second resistive electrode 204. Figure 12 In the embodiment shown, the second common layer is specifically the base layer 208.

[0084] The semiconductor device further includes a second connecting electrode 230, a third connecting electrode 231, and a second connection portion 232. The second connecting electrode 230 is located on and in contact with the emitter layer 207; the third connecting electrode 231 is located on and in contact with the base layer 208; one end of the second connection portion 232 is electrically connected to the first common layer, and the other end of the second connection portion 232 is electrically connected to the second common layer. Specifically, one end of the second connection portion 232 is in contact with the second connecting electrode 230, and the other end is in contact with the third connecting electrode 231.

[0085] It should be noted that the first common layer can be one of the initial collector layer 201, the base layer 208, and the emitter layer 207; the second common layer is one of the initial collector layer 201, the base layer 208, and the emitter layer 207, and the second common layer is a different layer from the first common layer. The selection of the first and second common layers can be determined according to the actual situation, and this application does not impose any restrictions on this.

[0086] In this embodiment of the invention, the first common layer and the second common layer are connected in series using the second connecting electrode 230, the third connecting electrode 231, and the second connecting portion 232. This allows current to flow sequentially through the second common layer, the first common layer, and the resistive layer 210. Specifically, the current flows sequentially through the base layer 208, the emitter layer 207, and the resistive layer 210, further increasing the current transmission path and improving the resistance value per unit area of ​​the semiconductor device.

[0087] Figure 13 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention.

[0088] like Figure 13 As shown, the semiconductor device includes: a substrate 200, an initial collector layer 201 on the substrate 200, a base layer 208 on the initial collector layer 201, and an emitter layer 207 on the initial collector layer 201; a dielectric layer 206 covering a first common layer; a resistive layer 210 on the dielectric layer 206; and a first connection portion 211, one end of which is electrically connected to one end of the resistive layer 210, and the other end of which is electrically connected to the first common layer, wherein the first common layer is one of the initial collector layer 201, the base layer 208, and the emitter layer 207. Figure 13 In the embodiment shown, the first common layer is specifically the emission layer 207.

[0089] In a specific implementation, with Figure 9 The difference is that semiconductor devices also include a second common layer and a third common layer. Figure 13 In the illustrated embodiment, the first common layer is the emitter layer 207, the second common layer is the base layer 208, and the third common layer is the initial collector layer 201. The second resistive electrode 204 is located on and in contact with the initial collector layer 201, and current can flow into the initial collector layer 201 through the first metal interconnect 221 and the second resistive electrode 204.

[0090] The semiconductor device further includes a second connecting electrode 230, a third connecting electrode 231, and a second connection portion 232. The second connecting electrode 230 is located on and in contact with the emitter layer 207; the third connecting electrode 231 is located on and in contact with the base layer 208; one end of the second connection portion 232 is electrically connected to the first common layer, and the other end of the second connection portion 232 is electrically connected to the second common layer. Specifically, one end of the second connection portion 232 is in contact with the second connecting electrode 230, and the other end of the second connection portion 232 is in contact with the third connecting electrode 231.

[0091] The semiconductor device further includes a fourth connecting electrode 233, a fifth connecting electrode 234, and a third connection portion 235. The fourth connecting electrode 233 is located on and in contact with the base layer 208; the fifth connecting electrode 234 is located on and in contact with the initial collector layer 201; one end of the third connection portion 235 is electrically connected to the second common layer, and the other end of the third connection portion 235 is electrically connected to the third common layer. Specifically, one end of the third connection portion 235 is in contact with the fourth connecting electrode 233, and the other end is in contact with the fifth connecting electrode 234.

[0092] It should be noted that the first common layer can be one of the initial collector layer 201, the base layer 208, and the emitter layer 207; the second common layer is one of the initial collector layer 201, the base layer 208, and the emitter layer 207, and the second common layer is different from the first common layer; the third common layer is one of the initial collector layer 201, the base layer 208, and the emitter layer 207, and the third common layer is different from the first and second common layers. The selection of the first, second, and third common layers can be determined according to the actual situation, and this application does not impose any restrictions on this.

[0093] In this embodiment of the invention, the first common layer and the second common layer are connected in series using the second connecting electrode 230, the third connecting electrode 231, and the second connecting portion 232, and the second common layer and the third common layer are connected in series using the fourth connecting electrode 233, the fifth connecting electrode 234, and the third connecting portion 235. This allows current to flow sequentially through the third common layer, the second common layer, the first common layer, and the resistive layer 210. Specifically, the current flows sequentially through the initial collector layer 201, the base layer 208, the emitter layer 207, and the resistive layer 210, greatly increasing the current transmission path and maximizing the reuse of each layer in the heterojunction bipolar transistor, thereby improving the resistance value per unit area of ​​the semiconductor device.

[0094] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a current collector layer on the substrate, a base layer on the current collector layer, and an emitter layer on the base layer; wherein the current collector layer, the base layer, and the emitter layer include doped ions; A dielectric layer covers a first common layer, wherein the first common layer is one of the current collector layer, the base layer, and the emitter layer; A resistive layer is located on the dielectric layer; A first connecting portion, one end of which is electrically connected to one end of the resistive layer, and the other end of which is electrically connected to the first common layer; The second connection portion has one end electrically connected to the first common layer and the other end electrically connected to the second common layer. The second common layer is one of the current collector layer, the base layer, and the emitter layer, and the second common layer is a different layer from the first common layer.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A first resistive electrode and a second resistive electrode, wherein the first resistive electrode is located at the other end of the resistive layer and is electrically connected to the resistive layer, and the second resistive electrode is located on the first common layer and is electrically connected to the first common layer.

3. The semiconductor device according to claim 2, characterized in that, The first connection portion is located near one end of the resistive layer, and the second resistive electrode is located near the other end of the resistive layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first common layer is the base layer.

5. The semiconductor device according to claim 1, characterized in that, Also includes: The third connection portion has one end electrically connected to the second common layer and the other end electrically connected to the third common layer. The third common layer is one of the current collector layer, the base layer, and the emitter layer. The third common layer is different from the first common layer and different from the second common layer.

6. The semiconductor device according to claim 1, characterized in that, Also includes: A heterojunction bipolar transistor, comprising a substrate, a collector layer, a base layer, and an emitter layer; a dielectric layer further covering the heterojunction bipolar transistor; and a resistive layer placed beside the heterojunction bipolar transistor.

7. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, and a current collector layer, a base layer, and an emitter layer are formed on the substrate; wherein the current collector layer, the base layer, and the emitter layer include doped ions; A dielectric layer is formed, the dielectric layer covering a first common layer, the first common layer being one of the current collector layer, the base layer, and the emitter layer; A resistive layer is formed on the dielectric layer; A first connection portion is formed, one end of the first connection portion is electrically connected to one end of the resistive layer, and the other end of the first connection portion is electrically connected to the first common layer. A second connection portion is formed, one end of which is electrically connected to the first common layer, and the other end of which is electrically connected to the second common layer. The second common layer is one of the current collector layer, the base layer, and the emitter layer, and the second common layer is a different layer from the first common layer.

8. The method for forming a semiconductor device according to claim 7, characterized in that, Also includes: A first resistive electrode and a second resistive electrode are formed. The first resistive electrode is located at the other end of the resistive layer and is electrically connected to the resistive layer. The second resistive electrode is located on the first common layer and is electrically connected to the first common layer.

9. The method for forming a semiconductor device according to claim 7, characterized in that, Also includes: A third connection portion is formed, one end of which is electrically connected to the second common layer, and the other end of which is electrically connected to the third common layer. The third common layer is one of the current collector layer, the base layer, and the emitter layer. The third common layer is different from the first common layer and different from the second common layer.

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