Thin film transistor, method of manufacturing the same, display substrate, and display device

Abstract

The present disclosure provides a thin film transistor and a preparation method thereof, a display substrate and a display device. The thin film transistor comprises a gate electrode, an active layer and a source electrode arranged on a substrate, the gate electrode is arranged on a side of the active layer away from the substrate; the active layer comprises a first conductive part, a second conductive part and a channel part between the two; the source electrode comprises a first surface facing the substrate, a second surface facing away from the substrate and a first side surface connected between the two and facing the channel part; a buffer layer is arranged on a side of the source electrode away from the substrate, the buffer layer is provided with a containing hole, and the containing hole exposes at least a part of the first side surface; wherein at least a part of the channel part is located on a side wall of the containing hole, and the first conductive part is in contact with the first side surface; a gate insulation layer is arranged between the layer where the active layer is located and the layer where the gate electrode is located.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof, a display substrate and a display device. BACKGROUND

[0002] With the continuous popularity of VR (Virtual Reality) products, the demand for resolution is increasing. Currently, 1000PPI products have appeared in the VR LCD (Liquid Crystal Display) market, and 1200PPI and 1500PPI products will gradually be launched in the next five years. The main reason restricting the further improvement of the resolution of VR LCD products is that the metal ratio in the existing device structure is too high, which leads to a lower aperture ratio as the PPI (Pixel Density) increases. Therefore, there is an increasing demand for new device structures. SUMMARY

[0003] The present disclosure provides a thin film transistor, a preparation method thereof, a display substrate and a display device.

[0004] The present disclosure provides a thin film transistor, comprising:

[0005] a gate electrode, an active layer and a source electrode disposed on a substrate, the gate electrode being disposed on a side of the active layer away from the substrate; the active layer comprising a first conductive part, a second conductive part and a channel part between the two; the source electrode comprising a first surface facing the substrate, a second surface facing away from the substrate and a first side surface connected between the two and facing the channel part;

[0006] a buffer layer disposed on a side of the source electrode away from the substrate, the buffer layer being provided with a receiving hole, the receiving hole exposing at least a part of the first side surface; wherein at least a part of the channel part is located on a sidewall of the receiving hole, and the first conductive part is in contact with the first side surface;

[0007] a gate insulating layer disposed between the layer where the active layer is located and the layer where the gate electrode is located.

[0008] In some embodiments, the channel part comprises a first part located at the bottom of the receiving hole and a second part located on the sidewall of the receiving hole; the first conductive part is connected with the first part, the second conductive part is connected with the second part, and the first conductive part is in contact with the first side surface.

[0009] In some embodiments, the size of the first conductive part in the thickness direction of the substrate is the same as the size of the first part in the thickness direction of the substrate.

[0010] In some embodiments, the size of the first conductive part in the thickness direction of the substrate is greater than or equal to the thickness of the source electrode.

[0011] In some embodiments, the buffer layer includes a first buffer portion, a projection of the first buffer portion on the substrate overlaps with a projection of the source on the substrate, the first buffer portion has a second side facing the accommodation hole;

[0012] The second conductive portion also covers at least a portion of the second side.

[0013] In some embodiments, an area of the first side of the source is less than or equal to 4 / 5 of the second surface area of the source.

[0014] In some embodiments, the second conductive portion is located on a surface of the buffer layer away from the substrate.

[0015] In some embodiments, an opening area of the accommodation hole away from the substrate is greater than an opening area of the accommodation hole close to the substrate.

[0016] In some embodiments, a thickness of the buffer layer is greater than a thickness of the gate insulating layer.

[0017] In some embodiments, the thin film transistor further includes a light shielding layer located on a side of the active layer close to the substrate, a projection of the light shielding layer on the substrate overlaps with a projection of the channel portion on the substrate.

[0018] The present disclosure also provides a method for manufacturing a thin film transistor, comprising:

[0019] forming a source on a substrate, the source including a first surface facing the substrate, a second surface facing away from the substrate, and a first side connecting the two;

[0020] forming a buffer layer on a side of the source away from the substrate, and forming an accommodation hole on the buffer layer, the accommodation hole exposing at least a portion of the first side;

[0021] forming an active layer, the active layer including a first conductive portion, a second conductive portion, and a channel portion located therebetween; wherein the first side faces the channel portion, at least a portion of the channel portion is located on a sidewall of the accommodation hole, and the first conductive portion is in contact with the first side;

[0022] forming a gate insulating layer on a side of the active layer away from the substrate;

[0023] forming a gate on a side of the gate insulating layer away from the substrate.

[0024] The present disclosure also provides a display substrate including at least one thin film transistor as described above.

[0025] In some embodiments, the display substrate further includes a plurality of gate lines and a plurality of data lines disposed on the substrate, the plurality of gate lines and the plurality of data lines intersecting to define a plurality of pixel regions, the gate of the thin film transistor being a part of the gate line, the source of the thin film transistor being a part of the data line, a pixel electrode being disposed in the pixel region, and the pixel electrode being electrically connected to the second conductive portion.

[0026] This disclosure also provides a display device including the above-described display substrate. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0028] Figure 1 This is a schematic diagram of a thin-film transistor provided in some embodiments.

[0029] Figure 2A This is a plan view of a thin-film transistor provided in some embodiments of this disclosure.

[0030] Figure 2B For along Figure 2A A sectional view obtained along line A-A'.

[0031] Figure 3 This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure.

[0032] Figure 4 This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure.

[0033] Figure 5 This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure.

[0034] Figure 6 This is a plan view of the gate lines, data lines, and thin-film transistors in a display substrate provided in some embodiments of this disclosure.

[0035] Figure 7 This is a plan view of the gate lines, data lines, thin-film transistors, and transition electrodes of a display substrate provided in some embodiments of this disclosure.

[0036] Figure 8 This is a plan view of the gate lines, data lines, thin-film transistors, transition electrodes, and pixel electrodes of a display substrate provided in some embodiments of this disclosure.

[0037] Figure 9 This is a cross-sectional view of a display substrate provided in some embodiments of this disclosure.

[0038] Figures 10 to 16 A schematic diagram of a manufacturing process of a thin film transistor provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to explain and illustrate the present disclosure, and are not intended to limit the present disclosure.

[0040] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0041] The terms used herein to describe the embodiments of the present disclosure are not intended to limit and / or restrict the scope of the present disclosure. For example, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings thereof by those having ordinary skills in the art to which the present disclosure belongs. It should be understood that the terms “first”, “second” and the like used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different constituent parts. Unless the context clearly indicates otherwise, the singular forms “a”, “an” and “the” and the like are also intended to represent the “at least one”. The terms “comprise”, “comprises” and the like are intended to mean that the elements or objects appearing before the “comprise” or “comprises” are encompassed by the “comprise” or “comprises” and the like, and do not exclude other elements or objects. The terms “connected” or “connected” and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may also be changed accordingly.

[0042] It should be noted that, for the sake of clarity, the thickness of a layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, i.e. these drawings are not drawn according to the actual proportions. It should also be noted that, for the present disclosure, the numerical range “m1~m2” includes the end values m1 and m2.

[0043] With the continuous popularization of VR (Virtual Reality) products, the demand for resolution is increasing, and currently the VR LCD (Liquid Crystal Display) market has appeared 1000PPI products, and 1200-1500PPI products will gradually appear in the next five years. One of the main reasons restricting the further improvement of the resolution of the VR LCD product is that the metal proportion in the existing device structure is too high. As the PPI (Pixel Density) is higher, the aperture ratio of the product is correspondingly lower, so the demand for new device structures is becoming stronger and stronger. The vertical structure thin film transistor can utilize the longitudinal space to save the area proportion of the thin film transistor in the pixel area, and becomes one of the important technical means to improve the resolution in the future.

[0044] Figure 1 For the schematic diagram of the thin film transistor provided in some embodiments, the thin film transistor is a vertical structure thin film transistor, as shown in Figure 1 The thin film transistor includes a source electrode 11, a gate electrode 13 and an active layer 12 arranged on a substrate 10. In addition, a buffer layer BFL and a gate insulating layer GI are also included. The buffer layer BFL is also arranged on the side of the source electrode 11 away from the substrate 10, and the buffer layer BFL is provided with a containing hole Va corresponding to the position of the source electrode 11, which exposes at least a part of the surface of the source electrode 11 away from the substrate 10. The active layer 12 includes a first active part 12a and a second active part 12b, at least a part of the first active part 12a is located in the containing hole Va and connected with the source electrode 11; the second active part 12b is located on the surface of the buffer layer BFL away from the substrate 10, and is used to connect the pixel electrode. The gate insulating layer GI is located on the side of the active layer 12 away from the substrate 10, and the gate electrode 13 is located on the side of the gate insulating layer GI away from the substrate 10 and opposite to the first active part 12a. When the voltage signal loaded on the gate electrode 13 reaches a certain value, a carrier channel is formed in the first active part 12a, so that the source electrode 11 and the pixel electrode of the thin film transistor are turned on.

[0045] Compared with the thin film transistor commonly used in the prior art, Figure 1 The first active part 12a of the active layer 12 of the thin film transistor in is located in the containing hole Va, and the orthographic projection of the gate electrode 13 and the source electrode 11 on the substrate 10 overlaps, so that the occupied area of the thin film transistor can be reduced under the condition that the channel length of the active layer 12 is constant, thereby facilitating the improvement of the pixel density.

[0046] However, for the thin film transistor in Figure 1 The film layer between the source electrode 11 and the gate electrode 13 is only the gate insulating layer GI, and the thickness of the gate insulating layer GI is usually small, so that a large parasitic capacitance is formed between the source electrode 11 and the gate electrode 13, which further affects the display effect of the display product.

[0047] Figure 2AA plan view of a thin film transistor provided in some embodiments of the present disclosure, Figure 2B A cross-sectional view taken along the direction of line A-A' in Figure 2A FIG. 1, Figure 2A and Figure 2B As shown in FIG. 1, a thin film transistor provided in an embodiment of the present disclosure includes a gate 13, an active layer 12, a source 11, a buffer layer BFL, and a gate insulating layer GI, which are disposed on a substrate 10.

[0048] The substrate 10 can be a substrate made of a transparent material, such as a glass substrate 10 or a flexible substrate 10 made of polyimide (PI) or the like.

[0049] The source 11 is disposed on the substrate 10. The source 11 includes a first surface s1 facing the substrate 10, a second surface s2 facing away from the substrate 10, and a first side surface s3 (right side surface of the source 11 in FIG. 1) connecting the first surface s1 and the second surface s2 and being close to the active layer 12. Figure 2B The source 11 can be a single-layer metal made of Mo, MoNb, MoNbTi, Al, Cu, Ti, or the like, or a laminated metal made of any two or more metals combined with each other.

[0050] The buffer layer BFL is disposed on a side of the source 11 away from the substrate 10. The buffer layer BFL is provided with a receiving hole Va. The receiving hole Va can or can not penetrate the buffer layer BFL. The bottom of the receiving hole Va has no overlap with the source 11 in a normal projection of the substrate 10. The first side surface s3 of the source 11 is a side surface of the source 11 facing the receiving hole Va. At least a part of the first side surface s3 is exposed by the receiving hole Va.

[0051] The active layer 12 is disposed on a side of the buffer layer BFL away from the substrate 10. The active layer 12 includes a first conductive part 121, a second conductive part 122, and a channel part 123 between the first conductive part 121 and the second conductive part 122. The first conductive part 121 is connected to the source 11. The second conductive part 122 can be connected to a drain, or the second conductive part 122 itself can serve as a drain of the thin film transistor. At least a part of the channel part 123 is located on a side wall of the receiving hole Va. The first side surface s3 of the source 11 faces the channel part 123 of the active layer 12. The first conductive part 121 is in contact with the first side surface s3 of the source 11.

[0052] The gate electrode 13 is located on the side of the active layer 12 away from the substrate 10, and the gate insulating layer GI is located between the layer where the active layer 12 is located and the layer where the gate electrode 13 is located, so that the gate electrode 13 and the active layer 12 and the gate electrode 13 and the buffer layer BFL are both separated by the gate insulating layer GI. In an example, the gate electrode 13 can be a single layer of metal, or a metal stack, such as a MoNb / Cu stack, or a MTD / Cu stack, or a MoNb / Cu / MTD stack, or the same as the material and structure used for the source electrode. The thickness of the gate electrode 13 can be between 200-1200 nm.

[0053] In the embodiments of the present disclosure, at least a part of the channel portion 123 is located on the sidewall of the accommodation hole Va, so as to ensure that the occupied area of the channel portion 123 is reduced under the condition that the length of the channel portion 123 is constant, thereby reducing the overall occupied area of the thin film transistor, and the first surface s1 of the source electrode 11 and the gate electrode 13 are not only separated by the gate insulating layer GI but also separated by the buffer layer BFL, so as to reduce the parasitic capacitance formed between the gate electrode 13 and the source electrode 11 in the vertical direction; in addition, although the first side surface s3 of the source electrode 11 and the gate electrode 13 are only separated by the gate insulating layer GI, the area of the first side surface s3 is much smaller than the second surface s2, so the parasitic capacitance between the gate electrode 13 and the source electrode 11 in the lateral direction will not be caused. Therefore, the thin film transistor in the embodiments of the present disclosure can not only save the occupied area but also reduce the parasitic capacitance between the gate electrode 13 and the source electrode 11.

[0054] In some embodiments, the area of the first side surface s3 of the source electrode 11 is less than or equal to 4 / 5 of the area of the second surface s2 of the source electrode 11, so as to reduce the lateral capacitance between the source electrode 11 and the gate line GL as much as possible. For example, the area of the first side surface s3 of the source electrode 11 is less than or equal to 4 / 5, or 3 / 5, or 1 / 2, or 1 / 3, or 1 / 4, or 1 / 5 of the area of the second surface s2 of the source electrode 11.

[0055] In some embodiments, the first side surface s3 can be an inclined plane, and the angle between the inclined plane and the first surface s1 of the source electrode 11 is an acute angle, so as to improve the connection stability of the first conductive portion 121 and the source electrode 11. Of course, the first side surface s3 can also be an arc surface, and when the first side surface s3 is an arc surface, the tangent line of each point on the arc surface and the first surface s1 form an acute angle, so as to improve the connection stability of the first conductive portion 121 and the source electrode 11.

[0056] In some embodiments, the thickness of the buffer layer BFL is greater than the thickness of the gate insulating layer GI, so that the thickness of the insulating medium between the second surface s2 of the source electrode 11 and the gate electrode 13 is increased, and the capacitance between the source electrode 11 and the gate electrode 13 in the vertical direction is reduced. For example, the thickness of the buffer layer BFL is 3-60 times the thickness of the gate insulating layer GI. For example, the thickness of the buffer layer BFL is 3-60 nm, and the thickness of the gate insulating layer GI is 1-2 nm. between 1 nm and 10 nm. between 1 nm and 10 nm.

[0057] In one example, the material of the gate insulating layer GI can be SiO2 or other oxide insulating layer, and the buffer layer BFL can be a SiN / SiO2 stacked structure, or a SiO2 single layer structure or other oxide insulating film layer.

[0058] In some embodiments, as shown in FIG. 1C, the channel portion 123 includes a first portion 123a and a second portion 123b. The first portion 123a is located at the bottom of the accommodation hole Va and is connected with the first conductive portion 121. The second portion 123b is located on the sidewall of the accommodation hole Va and is connected with the second conductive portion 122. The first conductive portion 121 is in contact with the first side surface s3. Figure 2B

[0059] In some embodiments, as shown in FIG. 1C, the channel portion 123 includes a first portion 123a and a second portion 123b. The first portion 123a is located at the bottom of the accommodation hole Va and is connected with the first conductive portion 121. The second portion 123b is located on the sidewall of the accommodation hole Va and is connected with the second conductive portion 122. The first conductive portion 121 is in contact with the first side surface s3. Figure 2B

[0060] In the embodiments of the present disclosure, the channel portion 123 is a semiconductor structure, and the first conductive portion 121 and the second conductive portion 122 are both conductive structures doped or plasma treated on the semiconductor structure. The material of the channel portion 123 can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and in particular can be a high mobility and stable oxide semiconductor, such as a rare earth element doped oxide semiconductor, indium gallium zinc tin oxide (IGZTO), indium gallium oxide (IGO), etc. The thickness of the active layer 12 can be between 1 nm and 10 nm.

[0061] In some embodiments, as shown in FIG. 1C, the channel portion 123 includes a first portion 123a and a second portion 123b. The first portion 123a is located at the bottom of the accommodation hole Va and is connected with the first conductive portion 121. The second portion 123b is located on the sidewall of the accommodation hole Va and is connected with the second conductive portion 122. The first conductive portion 121 is in contact with the first side surface s3. Figure 2B

[0062] In some embodiments, as shown in FIG. 1C, the channel portion 123 includes a first portion 123a and a second portion 123b. The first portion 123a is located at the bottom of the accommodation hole Va and is connected with the first conductive portion 121. The second portion 123b is located on the sidewall of the accommodation hole Va and is connected with the second conductive portion 122. The first conductive portion 121 is in contact with the first side surface s3.

[0063] In some embodiments, the second conductive portion 122 can serve as the drain of the thin film transistor and can be located on the surface of the buffer layer BFL away from the substrate 10 to facilitate connection with the pixel electrode 30.

[0064] Figure 3 ​​​​This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure. Figure 3 The thin-film transistor shown is Figure 2B Similar to the thin-film transistor shown, the difference lies in that... Figure 3 In the active layer 12, the first conductive portion 121 in the thickness direction of the substrate 10 is greater than or equal to the thickness of the source electrode 11. That is, the first conductive portion 121 extends at least from the bottom end of the first side surface s3 to the top end of the first side surface s3, thereby improving the connection stability between the first conductive portion 121 and the source electrode 11.

[0065] Figure 4 This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure, such as... Figure 4 As shown, the buffer layer BFL includes a first buffer portion BF1. The orthographic projection of the first buffer portion BF1 onto the substrate 10 overlaps with the orthographic projection of the source electrode 11 onto the substrate 10. In other words, the first buffer portion BF1 is the portion of the buffer layer BFL located above the source electrode 11. The first buffer portion BF1 has a second side facing the receiving hole Va. Figure 4 (Right side of the first buffer section BF1). Figure 4 In the middle, the first conductive part 121 not only covers the first side s3 of the source electrode 11, but also covers at least a portion of the second side. Figure 4 The other structures of the thin-film transistor shown are all similar to Figure 2B The same applies, so I won't repeat it here.

[0066] exist Figures 2B to 4 In each of the structures shown, there may be no contact between the first conductive part 121 and the second side surface s2 of the source electrode 11.

[0067] Figure 5 This is a schematic diagram of a thin-film transistor provided in some other embodiments of this disclosure. Figure 5 The thin-film transistor shown is Figure 2B Similar to the thin-film transistor shown, the only difference is that... Figure 5 The thin-film transistor further includes a light-shielding layer LS and an insulating spacer layer 15. The light-shielding layer LS is disposed on the substrate 10, and the insulating spacer layer 15 is located on the side of the light-shielding layer LS away from the substrate 10. The source 11, buffer layer BFL, and active layer 12 are all located on the side of the insulating spacer layer 15 away from the substrate 10. The orthographic projection of the light-shielding layer LS on the substrate 10 overlaps with the orthographic projection of the channel portion 123 on the substrate 10. Preferably, the orthographic projection of the channel portion 123 on the substrate 10 is within the range of the orthographic projection of the light-shielding layer LS on the substrate 10. The light-shielding layer LS is used to prevent the channel portion 123 from generating a large amount of leakage current due to light exposure, thereby avoiding the influence of the thin-film transistor characteristics.

[0068] The material of the light-shielding layer LS can include metal. For example, the light-shielding layer LS can be a Mo / Al / Al metal stack, or a MoNb / Cu metal stack, or a MTD / Cu metal stack, or a MoNb / Cu / MTD metal stack.

[0069] It should be noted that, Figure 5 Equivalent to in Figure 4 The thin-film transistor shown is based on the addition of a light-shielding layer LS and an insulating spacer layer 15. Figure 2B and Figure 3 The thin-film transistor shown may also be provided with a light-shielding layer LS and an insulating spacer layer 15.

[0070] This disclosure also provides a display substrate comprising a plurality of thin-film transistors, wherein at least one thin-film transistor is a thin-film transistor as described in the above embodiments.

[0071] Figure 6 This is a plan view of the gate lines, data lines, and thin-film transistors in a display substrate provided in some embodiments of this disclosure. Figure 7 This is a plan view of the gate lines, data lines, thin-film transistors, and transition electrodes of the display substrate provided in some embodiments of this disclosure. Figure 8 This is a plan view of the gate lines, data lines, thin-film transistors, transition electrodes, and pixel electrodes of the display substrate provided in some embodiments of this disclosure. Figure 9 This is a cross-sectional view of a display substrate provided in some embodiments of this disclosure. Figure 9 Corresponding to Figure 8 The B-B' section line in the diagram. For example... Figures 6 to 9 As shown, the display substrate includes multiple gate lines GL and multiple data lines DL, which are arranged in an intersecting manner to define multiple pixel areas. Each pixel area corresponds to at least one thin-film transistor as described in the above embodiment.

[0072] In this design, the gate 13 of the thin-film transistor is part of the gate line GL, and the source 11 of the thin-film transistor is part of the data line DL. A pixel electrode 30 is disposed in the pixel region, and the pixel electrode 30 is connected to the second conductive part 122 of the thin-film transistor.

[0073] like Figure 9As shown, the gate electrode 13 is provided with an interlayer dielectric layer ILD on the side away from the substrate 10, the transfer electrode 20 is provided on the side of the interlayer dielectric layer ILD away from the substrate 10, and is connected with the second conductive part 122 through the first via V1 penetrating the interlayer dielectric layer ILD and the gate insulating layer GI. The planarization layer PLN is provided on the side of the transfer electrode 20 away from the substrate 10, and the pixel electrode 30 is provided on the side of the planarization layer PLN away from the substrate 10, and is connected with the transfer electrode 20 through the second via V2 penetrating the planarization layer PLN. By connecting the pixel electrode 30 with the second conductive part 122 through the transfer electrode 20, the pixel electrode 30 can be prevented from being broken in a via with excessively large depth.

[0074] The first via V1 can have a circular, rectangular, elliptical or other irregular shape in the orthographic projection on the substrate 10. The orthographic projection of the first via V1 on the substrate 10 can be located within the orthographic projection range of the transfer electrode 20 on the substrate 10, so as to ensure stable connection between the pixel electrode 30 and the transfer electrode 20. The second via V2 can have a circular, rectangular, elliptical or other irregular shape in the orthographic projection on the substrate 10. The orthographic projection of the second via V2 on the substrate 10 can be located within the orthographic projection range of the second conductive part 122 on the substrate 10, so as to ensure stable connection between the transfer electrode 20 and the second conductive part 122.

[0075] The material of the interlayer dielectric layer ILD can include at least one of silicon nitride, silicon oxide, silicon oxynitride. The material of the planarization layer PLN can include an organic insulating material, for example, a resin material such as polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone, etc. For example, the organic insulating material includes an elastic material, for example, urethane, thermoplastic polyurethane (TPU), etc.

[0076] The material of the transfer electrode 20 and the transparent electrode both includes a transparent material, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0077] In some embodiments, the display substrate further includes a common electrode 40, as shown in FIG. 4. The common electrode 40 is provided on the side of the substrate 10 away from the pixel electrode 30, and is connected with the second conductive part 122 through the first via V1 penetrating the interlayer dielectric layer ILD and the gate insulating layer GI. The common electrode 40 can be connected with the second conductive part 122 through the transfer electrode 20, so as to prevent the common electrode 40 from being broken in a via with excessively large depth. Figure 9As shown, the common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10, and the common electrode 40 is spaced apart from the pixel electrode 30 by a passivation layer PVX. The material of the common electrode 40 includes a transparent material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The common electrode 40 can include a plurality of strip electrodes. In the liquid crystal display device, when a voltage is loaded on the pixel electrode 30 and the common electrode 40 respectively, an electric field can be generated between the two, thereby driving the liquid crystal to deflect. Of course, the common electrode 40 can also be disposed on the color film substrate opposite the display substrate, or the common electrode 40 can also be disposed in the same layer as the pixel electrode 30, for example, the pixel electrode 30 includes a plurality of first strip electrodes, and the common electrode 40 includes a plurality of second strip electrodes, the first strip electrodes and the second strip electrodes are alternately and spaced apart.

[0078] It should be noted that, in order to clearly show the corresponding relationship between the elements in the plan view and the sectional view, a coordinate system is schematically shown in Figures 2A to 9 each of the above-mentioned drawings is schematically shown under the same coordinate system, wherein the Z axis can be the thickness direction of the substrate 10; the X axis can be the direction from the accommodation hole Va to the source electrode 11, and the Y axis can be the direction from the channel portion 123 to the second conductive portion 122.

[0079] The display device can be a mobile phone, a tablet computer, a navigator, electronic paper, or the like product or component having a display function.

[0080] The display device can be a mobile phone, a tablet computer, a navigator, electronic paper, or the like product or component having a display function.

[0081] S10, forming a source electrode on a substrate, the source electrode including a first surface facing the substrate, a second surface facing away from the substrate, and a first side surface connecting the two.

[0082] S20, forming a buffer layer on the side of the source electrode away from the substrate, and forming an accommodation hole on the buffer layer, the accommodation hole exposing at least a part of the first side surface.

[0083] S30, forming an active layer, the active layer including a first conductive portion, a second conductive portion, and a channel portion located between the two; wherein the first side surface faces the channel portion, at least a part of the channel portion is located on the sidewall of the accommodation hole, and the first conductive portion is in contact with the first side surface.

[0084] S40, forming a gate insulating layer on the side of the active layer away from the substrate.

[0085] S50, forming a gate electrode on the side of the gate insulating layer away from the substrate.

[0086] The preparation method of the thin film transistor is described in detail below with reference to the thin film transistor shown in Figure 4 The preparation method of the thin film transistor is described in detail below with reference to the thin film transistor shown in Figures 10 to 16 The preparation process of the thin film transistor provided in some embodiments of the present disclosure is shown in the schematic diagram, and the preparation process includes:

[0087] S01, cleaning the substrate.

[0088] S10, as shown in Figure 10 The source 11 is formed on the substrate 10. The source metal layer can be formed on the substrate 10, and the pattern including the source 11 is formed by a photoetching patterning process. The source metal layer can be a single-layer metal such as Mo, Al, Cu, or a laminated metal such as Ti / Cu, Ti / Al / Ti. The width of the source 11 can be between 0.5 and 2 um. In step S10, the source 11 does not have to be formed separately, but a data line DL can be formed, and a part of the data line DL serves as the source 11, and the width of the source 11 is the width of the data line DL.

[0089] The source 11 includes a first surface s1 facing the substrate 10, a second surface s2 facing away from the substrate 10, and a first side surface s3 connected between the two.

[0090] S20, as shown in

[0091] The buffer layer BFL can be formed by a chemical vapor deposition (CVD) process, and the material of the buffer layer BFL can include at least one of a carbide of silicon, an oxide of silicon, and a silicon oxynitride. For example, the buffer layer BFL can be a SiN / SiO2 laminated structure, or a SiO2 single-layer structure or other oxide insulating film layer, and the total thickness of the buffer layer BFL is

[0092] S30, forming the active layer 12. The active layer 12 includes a first conductive part 121, a second conductive part 122, and a channel part 123 located between the two, at least a part of the channel part 123 is located on the sidewall of the accommodation hole Va, and the first conductive part 121 is in contact with the first side surface s3.

[0093] Specifically, step S30 includes steps S31 and S32:

[0094] S31, as shown in Figure 12As shown, a semiconductor layer is formed and patterned to create an intermediate pattern 120. The semiconductor layer can be an oxide material, such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), and particularly a high-mobility, photostable oxide semiconductor, such as a rare-earth-doped oxide semiconductor. The thickness of the semiconductor layer is [not specified in the original text]. between.

[0095] S32, such as Figure 13 As shown, the intermediate pattern 120 is made conductive. Specifically, a mask 50 is used to mask the area of ​​the intermediate pattern 120 corresponding to the channel portion 123 (where the masking area 51 of the mask 50 corresponds to the area where the channel portion 123 is to be formed, and the transparent area 52 corresponds to other areas of the intermediate pattern 120). Plasma implantation is performed on the other areas of the intermediate pattern 120. The implanted plasma can be hydrogen ions, argon ions, or B / P plasma, thereby making the unmasked areas of the intermediate pattern 120 conductive, forming the first conductive portion 121 and the second conductive portion 122. The area of ​​the intermediate region masked by the mask 50 is the channel portion 123 (e.g., ...). Figure 14 (As shown).

[0096] S40, such as Figure 15 As shown, a gate insulating layer GI is formed on the side of the active layer 12 away from the substrate 10. The gate insulating layer 13 can be formed by CVD or atomic layer deposition (ALD) processes. The material of the gate insulating layer GI can be SiO2 or other oxide insulating layers, with a thickness of [missing information]. between.

[0097] S50, such as Figure 16 As shown, a gate 13 is formed on the side of the gate insulating layer GI away from the substrate 10. The material of the gate 13 includes metals; for example, the gate 13 can be a MoNb / Cu stack, an MTD / Cu stack, or a MoNb / Cu / MTD stack. The thickness of the gate 13 can be between 200 and 1200 nm.

[0098] The above is based on Figure 4 The fabrication process of a thin-film transistor is illustrated using the thin-film transistor shown as an example. In other embodiments, such as for Figure 5 The thin-film transistor shown includes, in addition to the steps S10 to S50 described above, a light-shielding layer LS and an insulating spacer layer 15 are formed sequentially before step S10.

[0099] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present disclosure, however the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and principle of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure. The embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments without conflict.

Claims

1. A thin-film transistor, characterized in that, include: A gate, an active layer, and a source are disposed on a substrate, wherein the gate is disposed on the side of the active layer away from the substrate; The active layer includes: a first conductive portion, a second conductive portion, and a channel portion located between the two; the source electrode includes: a first surface facing the substrate, a second surface facing away from the substrate, and a first side surface connected between the two and facing the channel portion; the orthographic projection of the source electrode on the substrate does not overlap with the orthographic projection of the second conductive portion on the substrate; A buffer layer is disposed on the side of the source electrode away from the substrate, and a receiving hole is provided on the buffer layer, the receiving hole exposing at least a portion of the first side surface; wherein at least a portion of the channel portion is located on the sidewall of the receiving hole, and the first conductive portion is in contact with the first side surface; A gate insulating layer is disposed between the active layer and the gate layer; The buffer layer includes a first buffer portion, the orthographic projection of the first buffer portion on the substrate overlaps with the orthographic projection of the source electrode on the substrate, the first buffer portion having a second side facing the receiving hole; the first conductive portion also covers at least a portion of the second side.

2. The thin-film transistor according to claim 1, characterized in that, The channel portion includes a first portion located at the bottom of the receiving hole and a second portion located on the side wall of the receiving hole; the first conductive portion is connected to the first portion, the second conductive portion is connected to the second portion, and the first conductive portion is in contact with the first side.

3. The thin-film transistor according to claim 1, characterized in that, The dimension of the first conductive portion in the thickness direction of the substrate is greater than or equal to the thickness of the source electrode.

4. The thin-film transistor according to any one of claims 1 to 3, characterized in that, The area of ​​the first side of the source electrode is less than or equal to 4 / 5 of the area of ​​the second surface of the source electrode.

5. The thin-film transistor according to any one of claims 1 to 3, characterized in that, The second conductive portion is located on the surface of the buffer layer away from the substrate.

6. The thin-film transistor according to any one of claims 1 to 3, characterized in that, The opening area of ​​the receiving hole away from the substrate is larger than the opening area of ​​the receiving hole close to the substrate.

7. The thin-film transistor according to any one of claims 1 to 3, characterized in that, The thickness of the buffer layer is greater than the thickness of the gate insulating layer.

8. The thin-film transistor according to any one of claims 1 to 3, characterized in that, The thin-film transistor further includes a light-shielding layer located on the side of the active layer near the substrate, wherein the orthographic projection of the light-shielding layer on the substrate overlaps with the orthographic projection of the channel portion on the substrate.

9. A method for fabricating a thin-film transistor, characterized in that, include: A source electrode is formed on a substrate, the source electrode including a first surface facing the substrate, a second surface facing away from the substrate, and a first side surface connecting the two; A buffer layer is formed on the side of the source electrode away from the substrate, and a receiving hole is formed on the buffer layer, the receiving hole exposing at least a portion of the first side surface; the buffer layer includes a first buffer portion, the orthographic projection of the first buffer portion on the substrate overlaps with the orthographic projection of the source electrode on the substrate, and the first buffer portion has a second side surface facing the receiving hole; An active layer is formed, the active layer comprising: a first conductive portion, a second conductive portion, and a channel portion located between the two; wherein, the first side faces the channel portion, at least a portion of the channel portion is located on the sidewall of the receiving hole, the first conductive portion is in contact with the first side; the first conductive portion also covers at least a portion of the second side; the orthographic projection of the source electrode on the substrate and the orthographic projection of the second conductive portion on the substrate do not overlap; A gate insulating layer is formed on the side of the active layer away from the substrate; A gate is formed on the side of the gate insulating layer away from the substrate.

10. A display substrate, characterized in that, It includes at least one thin-film transistor according to any one of claims 1 to 8.

11. The display substrate according to claim 10, characterized in that, The display substrate further includes multiple gate lines and multiple data lines disposed on the substrate. The multiple gate lines and multiple data lines intersect to define multiple pixel regions. The gate of the thin-film transistor is part of the gate line, and the source of the thin-film transistor is part of the data line. A pixel electrode is disposed in the pixel region, and the pixel electrode is electrically connected to the second conductive part.

12. A display device, characterized in that, Includes the display substrate as described in claim 10 or 11.

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