Solar cell manufacturing method and solar cell

Abstract

The present application provides a method for preparing a solar cell and a solar cell. The method for preparing a solar cell includes: providing a P-type silicon substrate; performing a first texturing; sequentially forming a tunneling oxide layer, an N+ doped polysilicon layer, and a silicon oxide protective layer on the back side or the back side and the front side of the P-type silicon substrate to obtain a first intermediate cell; removing the other parts of the silicon oxide protective layer except for the part located in the preset N+ doping area to obtain a second intermediate cell; performing an alkali polishing treatment on the second intermediate cell to obtain a third intermediate cell; performing a second texturing; forming a passivation anti-reflection layer on the front side and the back side of the fourth intermediate cell. Metallizing the fourth intermediate cell to form a metal electrode to obtain a solar cell. The solar cell provided in the first aspect of the present application simultaneously achieves optimal passivation effects in the P+ doping area and the N+ doping area, further improving the efficiency of the solar cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] IBC cells (interdigitated back contact) are gaining popularity due to their numerous advantages, including no front-side light blocking and no metal-contact composites. However, the complex and costly manufacturing process for IBC cells hinders large-scale commercial production. Furthermore, further improving the photoelectric conversion efficiency of IBC solar cells remains a pressing challenge.

[0003] Therefore, there is an urgent need for a new method for preparing a solar cell and a solar cell. Summary of the Invention

[0004] In a first aspect, the present application provides a method for preparing a solar cell, comprising:

[0005] Providing a P-type silicon substrate, with preset P+ doping regions and preset N+ doping regions alternately distributed on the back side of the P-type silicon substrate;

[0006] The first texturing is to texturing the P-type silicon substrate so that a first textured surface structure is formed on both the front and back surfaces of the P-type silicon substrate;

[0007] forming a tunneling oxide layer, an N+ doped polysilicon layer, and a silicon oxide protective layer in sequence on the back side or on both the back side and the front side of the P-type silicon substrate to obtain a first intermediate cell;

[0008] removing the portion of the silicon oxide protective layer other than the portion located in the preset N+ doping region to obtain a second intermediate cell;

[0009] After alkali polishing the second intermediate cell, a third intermediate cell is obtained, wherein the front surface of the third intermediate cell and the back surface of the third intermediate cell in the preset P+ doping area are both smooth surfaces;

[0010] A second texturing process is performed on the third intermediate cell to obtain a fourth intermediate cell. The front surface of the fourth intermediate cell and the back surface of the fourth intermediate cell in the predetermined P+ doping region both form a second textured structure, while the back surface of the fourth intermediate cell in the predetermined N+ doping region retains the first textured structure.

[0011] forming a passivation anti-reflection layer on the front and back sides of the fourth intermediate cell;

[0012] The fourth middle cell is metallized to form a metal electrode to obtain a solar cell.

[0013] The first aspect of the present application provides a method for preparing a solar cell. This method cleverly utilizes a silicon oxide protective layer disposed on an N+-doped polysilicon layer as a mask layer during the solar cell preparation process. This ensures that the first textured structure formed in the first texturing process remains unaffected in the pre-set N+-doped region during the alkali polishing process, while the second texturing process forms a second textured structure in the pre-set P+-doped region without affecting the first textured structure. The pre-set P+-doped region and the pre-set N+-doped region have two different surface states due to their different textured structures. The passivation anti-reflection layer grows at different rates in the pre-set P+-doped region and the pre-set N+-doped region, thereby controlling the thickness of the passivation anti-reflection layer in the P+-doped region and the thickness of the passivation anti-reflection layer in the N+-doped region by controlling the surface states of the pre-set P+-doped region and the pre-set N+-doped region. In an IBC cell, the desired optimal thickness of the passivation anti-reflection layer varies due to the different structures of the P+-doped and N+-doped regions. When the passivation anti-reflection layer reaches its optimal thickness, it achieves optimal passivation and minimizes metal recombination, thereby improving the efficiency of the solar cell. In summary, the first aspect of the present application provides a method for preparing a solar cell in which the surface morphology of the P+ doped region and the N+ doped region can be freely adjusted. The free adjustment of the surface morphology of the P+ doped region and the N+ doped region enables the thickness of the portion of the passivation anti-reflection layer corresponding to each doping region to be freely designed and effectively controlled, while achieving the optimal passivation conditions of the P+ doped region and the N+ doped region to improve the battery efficiency.

[0014] A second aspect of the present application provides a solar cell, which is prepared by the method for preparing a solar cell provided by the first aspect of the present application, wherein the P+ doped region and the N+ doped region are alternately distributed on the back side of the solar cell.

[0015] The portion of the solar cell in the P+ doping region has a second velvet structure, and the portion of the solar cell in the N+ doping region has a first velvet structure. The passivation anti-reflection layer on the back of the solar cell includes a first portion and a second portion of unequal thicknesses, wherein the first portion is in the P+ doping region and the second portion is in the N+ doping region.

[0016] In the solar cell provided in the second aspect of the present application, the thickness of the first portion of the passivation anti-reflection layer is adapted to the structure of the P+ doped region, so that the first portion of the passivation anti-reflection layer can achieve an optimal passivation effect in the P+ doped region and minimize metal recombination in the P+ doped region; the thickness of the second portion of the passivation anti-reflection layer is adapted to the structure of the N+ doped region, so that the second portion of the passivation anti-reflection layer can achieve an optimal passivation effect in the N+ doped region and minimize metal recombination in the N+ doped region. The solar cell of the second aspect of the present application improves cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic flow chart of an embodiment of a method for preparing a solar cell provided in the first aspect of the present application;

[0018] Figure 2 This is a schematic structural diagram of a P-type silicon substrate in Example 1 of the first aspect of the present application;

[0019] Figure 3 This is a schematic structural diagram of a P-type silicon substrate after step S20 is completed in Example 1 of the first aspect of the present application;

[0020] Figure 4 This is a schematic structural diagram of the first intermediate battery cell after step S30 is completed in Example 1 of the first aspect of the present application;

[0021] Figure 5 This is a schematic structural diagram of the first intermediate battery cell after step S41 is completed in Example 1 of the first aspect of the present application;

[0022] Figure 6 This is a schematic structural diagram of the second intermediate battery sheet obtained after completing step S42 in Example 1 of the first aspect of the present application;

[0023] Figure 7 This is a schematic structural diagram of a third intermediate cell obtained after completing step S50 in Example 1 of the first aspect of the present application;

[0024] Figure 8 This is a schematic structural diagram of a fourth intermediate cell obtained after completing step S60 in Example 1 of the first aspect of the present application;

[0025] Figure 9 This is a schematic structural diagram of the fourth middle battery cell after completing step S70 in Example 1 of the first aspect of the present application;

[0026] Figure 10 This is a schematic structural diagram of the fourth middle battery cell after completing step S81 in Example 1 of the first aspect of the present application;

[0027] Figure 11 Schematic diagram of the solar cell structure obtained after completing step S82 in Example 1 of the first aspect of the present application;

[0028] Figure 12 This is a schematic structural diagram of the first intermediate battery cell after step S30 is completed in Example 2 of the first aspect of the present application;

[0029] Figure 13 This is a schematic structural diagram of the first intermediate battery cell after step S41 is completed in Example 2 of the first aspect of the present application;

[0030] Figure 14 This is a schematic structural diagram of the second intermediate battery cell obtained after completing step S42 in Example 1 of the first aspect of the present application.

[0031] Description of reference numerals:

[0032] 1-P-type silicon substrate; 2-tunneling oxide layer; 3-N+ doped polysilicon layer; 4-back passivation anti-reflection layer; 41-notch; 5-front passivation anti-reflection layer; 6-metal positive electrode; 7-P+ heavily doped region; 8-metal negative electrode; 9-silicon oxide protective layer.

[0033] A-P+ doping area; A1-second texture structure; A2-preset P+ doping area; B-N+ doping area; B1-first texture structure; B2-preset N+ doping area. DETAILED DESCRIPTION

[0034] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0035] Currently, IBC cells (interdigitated back contact) are gaining popularity due to their numerous advantages, including no light blocking on the front of the cell and no metal contact composites. However, the current IBC cell manufacturing process utilizes a new mask to form alternating P+ and N+ doped regions. This requires multiple masks, increasing production costs. IBC cells also require numerous photolithography processes, which require precise calibration, are complex, and have high production costs, making them unsuitable for large-scale commercial production. Furthermore, further improving the photoelectric conversion efficiency of IBC solar cells remains a pressing issue.

[0036] In view of this, this application is filed.

[0037] like Figure 1 As shown, the first aspect of the present application provides a method for preparing a solar cell, comprising:

[0038] S10: providing a P-type silicon substrate, wherein predetermined P+ doping regions and predetermined N+ doping regions are alternately distributed on the back side of the P-type silicon substrate.

[0039] S20: texturing for the first time, texturing the P-type silicon substrate so that a first textured surface structure is formed on both the front and back surfaces of the P-type silicon substrate.

[0040] S30: forming a tunneling oxide layer, an N+ doped polysilicon layer and a silicon oxide protection layer in sequence on the back side or on the back side and the front side of the P-type silicon substrate to obtain a first intermediate cell.

[0041] S40: removing the other portions of the silicon oxide protection layer except the portion located in the preset N+ doping region to obtain a second middle cell.

[0042] S50: performing alkaline polishing on the second intermediate cell to obtain a third intermediate cell, wherein the front surface of the third intermediate cell and the back surface of the third intermediate cell in the preset P+ doping region are both smooth surfaces.

[0043] S60: The second texturing is performed on the third intermediate cell to obtain the fourth intermediate cell. The front side of the fourth intermediate cell and the back side of the fourth intermediate cell in the preset P+ doping area both form a second texturing structure, and the back side of the fourth intermediate cell in the preset N+ doping area still retains the first texturing structure.

[0044] S70: forming a passivation anti-reflection layer on the front and back surfaces of the fourth intermediate cell.

[0045] S80: Metallizing the fourth middle cell to form a metal electrode to obtain a solar cell.

[0046] The solar cell provided in the first aspect of the present application cleverly utilizes a silicon oxide protective layer disposed on an N+-doped polysilicon layer as its own mask layer during the solar cell fabrication process, thereby ensuring that the predetermined N+-doped region remains unaffected during the alkali polishing process, retaining the first textured structure formed in the first texturing process. A second texturing process forms a second textured structure in the predetermined P+-doped region without affecting the first textured structure. The predetermined P+-doped region and the predetermined N+-doped region have two different surface states due to the formation of different textured structures. The passivation anti-reflection layer grows at different rates on the predetermined P+-doped region and the predetermined N+-doped region, thereby controlling the thickness of the passivation anti-reflection layer in the P+-doped region and the thickness of the passivation anti-reflection layer in the N+-doped region by controlling the surface states of the predetermined P+-doped region and the predetermined N+-doped region. This allows the thickness of the passivation anti-reflection layer in the P+-doped region and the thickness of the passivation anti-reflection layer in the N+-doped region to be freely designed and effectively controlled. Due to the structural differences between the P+-doped region and the N+-doped region, the corresponding passivation anti-reflection layer portions have different thicknesses required to achieve optimal passivation and minimum metal cladding. Compared with the same surface state of the P+ doped region and the N+ doped region under conventional processes, the present application proposes a method for preparing a solar cell in which the surface state, i.e., the surface morphology, of the P+ doped region and the N+ doped region can be freely adjusted, thereby achieving greater freedom of adjustment in the thickness of the passivation anti-reflection layer parts corresponding to the P+ doped region and the N+ doped region, thereby simultaneously achieving the optimal passivation effect of the P+ doped region and the N+ doped region, further improving the efficiency of the solar cell.

[0047] The following combination Figures 2 to 14Example 1 and Example 2 of the first aspect of this application are described in detail.

[0048] [Example 1]

[0049] This embodiment 1 specifically provides a method for preparing a solar cell, where the solar cell is an IBC cell, and specifically includes:

[0050] like Figure 2 As shown, S10: providing a P-type silicon substrate 1, and pre-set P+ doping regions A2A and pre-set N+ doping regions B2B are alternately distributed on the back side of the P-type silicon substrate 1. Figure 2 This is a schematic structural diagram of the P-type silicon substrate 1 in Example 1 of the first aspect of the present application.

[0051] like Figure 3 As shown, S20: first texturing, texturing the P-type silicon substrate 1 so as to form a first textured surface structure B1 on both the front and back surfaces of the P-type silicon substrate 1. Figure 3 This is a schematic structural diagram of the P-type silicon substrate 1 after completing step S20 in Example 1 of the first aspect of the present application.

[0052] like Figure 4 As shown, S30: forming a tunneling oxide layer 2, an N+ doped polysilicon layer 3 and a silicon oxide protection layer 9 in sequence on the back and front sides of the P-type silicon substrate 1 to obtain a first intermediate cell. Figure 4 This is a schematic structural diagram of the first intermediate battery cell after completing step S30 in Example 1 of the first aspect of the present application.

[0053] In some optional embodiments of the first aspect of the present application, the tunneling oxide layer 2 includes silicon oxide, and the thickness of the tunneling oxide layer 2 is 0.5 nm to 3.0 nm.

[0054] In some optional embodiments of the first aspect of the present application, the silicon oxide protective layer 9 contains phosphorus or does not contain phosphorus.

[0055] In some optional embodiments of the first aspect of the present application, in the step of sequentially forming a tunneling oxide layer 2, an N+ doped polysilicon layer 3 and a silicon oxide protective layer 9 on the back and front sides of a P-type silicon substrate 1 to obtain a first intermediate cell:

[0056] The tunnel oxide layer 2, the N+ doped polysilicon layer 3 and the silicon oxide protection layer 9 are formed by low pressure chemical vapor deposition (LPCVD). The LPCVD method can achieve double-sided deposition on the front and back sides of the P-type silicon substrate 1.

[0057] S40: removing the other portions of the silicon oxide protection layer 9 except the portion located in the preset N+ doping region B2B to obtain a second intermediate cell.

[0058] Step S40 further includes:

[0059] Step S41: Patterning and removing the portion of the silicon oxide protection layer 9 on the back surface of the first intermediate cell located in the preset P+ doping area A2A. Figure 5 This is a schematic structural diagram of the first intermediate cell after completing step S41 in Example 1 of the first aspect of the present application. Figure 5 As shown, in some examples, laser is used to remove the portion of the silicon oxide protective layer 9 on the back side of the first intermediate cell located in the preset P+ doping area A2A, while the portion of the silicon oxide protective layer 9 on the back side of the first intermediate cell located in the preset N+ doping area B2B remains.

[0060] Step S42: Perform single-side etching on the front surface of the first intermediate cell to remove the silicon oxide protection layer 9 on the front surface of the first intermediate cell. Figure 6 This is a schematic structural diagram of the second intermediate cell obtained after completing step S42 in Example 1 of the first aspect of the present application. Figure 6 As shown, in some examples, a hydrofluoric acid (HF) solution is used for single-side etching to remove the silicon oxide protective layer 9 on the front side of the first middle cell, so that the stacked tunnel oxide layer 2 and the N+ doped polysilicon layer 3 remain on the front side of the first middle cell.

[0061] S50: performing alkaline polishing on the second intermediate cell to obtain a third intermediate cell. The front side of the third intermediate cell and the back side of the third intermediate cell in the preset P+ doping area A2A are both smooth surfaces. Figure 7 This is a schematic diagram of the structure of the third intermediate cell obtained after completing step S50 in Example 1 of the first aspect of the present application. Figure 7 As shown, the front side of the third intermediate cell is the exposed front side of the silicon substrate, while the back side of the third intermediate cell, located in the predetermined P+ doped region A2A, is the exposed back side of the silicon substrate. The back side of the third intermediate cell, located in the predetermined N+ doped region B2B, has a first textured structure B1, comprising a tunneling oxide layer 2, an N+ doped polysilicon layer 3, and a silicon oxide protective layer 9. During the alkaline polishing process, the silicon oxide protective layer 9 in the predetermined N+ doped region B2B acts as a mask, protecting the tunneling oxide layer 2 and the N+ doped polysilicon layer 3 in the predetermined N+ doped region B2B, eliminating the need to form a new mask layer on the intermediate cell.

[0062] S60: The second texturing is performed, and the third intermediate cell is texturing treated with an alkaline solution to obtain a fourth intermediate cell. The front side of the fourth intermediate cell and the back side of the fourth intermediate cell in the preset P+ doping area A2A both form a second texturing structure A1, and the back side of the fourth intermediate cell in the preset N+ doping area B2B still retains the first texturing structure B1. Figure 8 This is a schematic structural diagram of the fourth intermediate cell obtained after completing step S60 in Example 1 of the first aspect of the present application. Figure 8 As shown, after the second texturing, the front side of the fourth intermediate cell (i.e., the front side of the silicon substrate) and the back side of the fourth intermediate cell located in the preset P+ doping area A2A (i.e., the back side of the silicon substrate located in the preset P+ doping area A2A) both form a second texturing structure A1.

[0063] S70: forming a passivation anti-reflection layer on the front and back surfaces of the fourth intermediate cell. Figure 9 This is a structural diagram of the fourth intermediate cell after completing step S70 in Example 1 of the first aspect of the present application. Figure 9 As shown, a front-side passivation anti-reflection layer 5 is formed on the front side of the fourth intermediate cell, and a back-side passivation anti-reflection layer 4 is formed on the back side of the fourth intermediate cell. The thickness of the back-side passivation anti-reflection layer 4 in the predetermined N+ doped region B2B and the thickness in the predetermined P+ doped region A2A are different due to the formation of the first velvet structure B1 and the second velvet structure A1. In some embodiments, the front-side passivation anti-reflection layer 5 and the back-side passivation anti-reflection layer 4 include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0064] S80: Metallizing the fourth middle cell to form a metal electrode to obtain a solar cell.

[0065] Step S80 further includes:

[0066] Step S81: performing laser grooving processing on the preset P+ doping area A2A on the back surface of the fourth middle cell. Figure 10 This is a schematic structural diagram of the fourth intermediate cell after completing step S81 in Example 1 of the first aspect of the present application. Figure 10 As shown, the back passivation anti-reflection layer 4 in the preset P+ doping area A2A on the back of the fourth middle cell is laser grooved to form a notch 41 , and the P-type silicon substrate 1 is exposed through the notch 41 .

[0067] Step S82 : printing metal paste on the notch 41 of the fourth middle cell and the preset N+ doping region B2B respectively, and sintering to obtain the metal positive electrode 6 and the metal negative electrode 8 . Figure 11 Schematic diagram of the solar cell structure obtained after completing step S82 in Example 1 of the first aspect of the present application. Figure 11 As shown, the metal positive electrode 6 forms a P+ heavily doped region 7 in the area in contact with the P-type silicon substrate 1. After sintering, the metal negative electrode 8 passes through the back passivation anti-reflection layer 4 and contacts and connects with the N+ doped polysilicon layer 3 in the N+ doped region B. The metal paste forming the metal positive electrode 6 is aluminum paste and / or silver aluminum paste, and the metal paste forming the metal negative electrode 8 is silver paste. The portion of the solar cell in the P+ doped region A has a second velvet structure A1, and the portion of the solar cell in the N+ doped region B has a first velvet structure B1. The passivation anti-reflection layer on the back of the solar cell includes a first portion and a second portion of unequal thickness, wherein the first portion is in the P+ doped region A and the second portion is in the N+ doped region B.

[0068] In general, the preparation method of the solar cell provided in the first aspect of the present application forms a silicon oxide protective layer 9 as a mask for the subsequent second texturing when preparing the tunneling oxide layer 2 passivation contact structure (including the tunneling oxide layer 2 and the N+ doped polysilicon layer 3), thereby avoiding the process of forming additional preparation masks in the N+ doped area B and the P+ doped area A, simplifying the IBC battery preparation process, reducing the preparation cost, and facilitating large-scale commercial production; at the same time, the thickness of the passivation anti-reflection layer in the P+ doped area A and the thickness of the passivation anti-reflection layer in the N+ doped area B can be freely designed and effectively controlled, thereby achieving greater adjustment freedom in the thickness of the passivation anti-reflection layer parts corresponding to the P+ doped area A and the N+ doped area B, thereby simultaneously achieving the optimal passivation effect of the P+ doped area A and the N+ doped area B, further improving the efficiency of the solar cell.

[0069] [Example 2]

[0070] The difference between the second embodiment and the first embodiment lies in step S30 and step S40.

[0071] S30: forming a tunneling oxide layer 2, an N+ doped polysilicon layer 3 and a silicon oxide protection layer 9 in sequence on the back side of the P-type silicon substrate 1 to obtain a first intermediate cell. Figure 12 This is a schematic structural diagram of the first intermediate cell after completing step S30 in Example 2 of the first aspect of the present application. Figure 12 As shown, after the tunneling oxide layer 2, the N+ doped polysilicon layer 3 and the silicon oxide protective layer 9 are formed in sequence on the back side of the P-type silicon substrate 1, a side wrap-around plating phenomenon usually occurs. Therefore, a wrap-around plating structure is formed at the side of the front side of the P-type silicon substrate 1. The wrap-around plating structure includes a small-area stacked tunneling oxide layer 2, an N+ doped polysilicon layer 3 and a silicon oxide protective layer 9 located on the front side of the P-type silicon substrate 1.

[0072] In Example 2, at least one deposition method selected from the group consisting of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and plasma-enhanced atomic layer deposition (PEALD) is used to form the tunneling oxide layer 2, the N+-doped polysilicon layer 3, and the silicon oxide protective layer 9.

[0073] In some examples, low-pressure chemical vapor deposition is used to deposit on two closely placed silicon wafers, thereby achieving a single-sided deposition process, that is, a tunneling oxide layer 2, an N+ doped polysilicon layer 3 and a silicon oxide protective layer 9 are sequentially formed on the back side (single side) of the P-type silicon substrate 1.

[0074] In some examples, plasma-enhanced chemical vapor deposition, physical vapor deposition, and plasma-enhanced atomic layer deposition are single-sided deposition processes, that is, a tunneling oxide layer 2, an N+ doped polysilicon layer 3, and a silicon oxide protective layer 9 are sequentially formed on the back side (single side) of a P-type silicon substrate 1.

[0075] In some optional embodiments of the first aspect of the present application, when a low-pressure chemical vapor deposition method is used to form the tunneling oxide layer 2, the N+ doped polysilicon layer 3, and the silicon oxide protective layer 9, the tunneling oxide layer 2 is first formed, and then an intrinsic polysilicon layer is formed on the tunneling oxide layer 2. Then, phosphorus is diffused into the intrinsic polysilicon layer to form the N+ doped polysilicon layer 3 and the silicon oxide protective layer 9. In these embodiments, the silicon oxide protective layer 9 contains phosphorus. In some examples, during the phosphorus diffusion process, P2O5 generated by the decomposition of POCL3 precipitates and accumulates on the surface of the intrinsic polysilicon layer. P2O5 reacts with silicon to generate silicon oxide (SiO2) and phosphorus atoms, and then the phosphorus atoms diffuse into the intrinsic polysilicon layer, ultimately forming the N+ doped polysilicon layer 3 and the silicon oxide protective layer 9.

[0076] In some optional embodiments of the first aspect of the present application, when the tunneling oxide layer 2, the N+ doped polysilicon layer 3 and the silicon oxide protective layer 9 are formed by plasma enhanced chemical vapor deposition,

[0077] A tunneling oxide layer 2, a phosphorus-containing amorphous silicon layer, and a silicon oxide protective layer 9 are sequentially deposited, and annealed to obtain a tunneling oxide layer 2, an N+-doped polysilicon layer 3, and a silicon oxide protective layer 9. The silicon oxide protective layer 9 does not contain phosphorus. In these embodiments, the silicon oxide protective layer 9 is obtained by deposition and therefore does not contain phosphorus.

[0078] In some optional embodiments of the first aspect of the present application, the deposition method includes an annealing step, in which oxygen is supplied to the environment in which the P-type silicon substrate 1 is located to form a silicon oxide protective layer 9.

[0079] In some examples of these embodiments, low-pressure chemical vapor deposition (LPCVD) is used to form the tunneling oxide layer 2, the N+-doped polysilicon layer 3, and the silicon oxide protective layer 9. In the LPCVD method, the tunneling oxide layer 2 is first formed, and then a native polysilicon layer is formed on the tunneling oxide layer 2. Then, the N+-doped polysilicon layer 3 is formed on the native polysilicon layer by ion implantation, and finally, annealing is performed. During the annealing step, oxygen is supplied to the environment surrounding the P-type silicon substrate 1, causing the silicon to react with the oxygen to form the silicon oxide protective layer 9.

[0080] In other examples of these embodiments, low-pressure chemical vapor deposition is used to form the tunneling oxide layer 2, the N+ doped polysilicon layer 3, and the silicon oxide protective layer 9. In the low-pressure chemical vapor deposition method, the tunneling oxide layer 2 is first formed, and the N+ doped polysilicon layer 3 is deposited on the tunneling oxide layer 2. Then, annealing is performed. During the annealing step, oxygen is supplied to the environment of the P-type silicon substrate 1, so that silicon reacts with oxygen to form the silicon oxide protective layer 9.

[0081] In some other examples of these embodiments, plasma-enhanced chemical vapor deposition, physical vapor deposition, or plasma-enhanced atomic layer deposition is used to form the tunneling oxide layer 2, the N+-doped polysilicon layer 3, and the silicon oxide protective layer 9. In these examples, the tunneling oxide layer 2 is first formed, and the N+-doped polysilicon layer 3 is deposited on the tunneling oxide layer 2, and then annealing is performed. During the annealing step, oxygen is supplied to the environment of the P-type silicon substrate 1, so that silicon reacts with oxygen to form the silicon oxide protective layer 9.

[0082] S40: removing the other portions of the silicon oxide protection layer 9 except the portion located in the preset N+ doping region B2B to obtain a second intermediate cell.

[0083] Step S40 further includes:

[0084] Step S41: Patterning and removing the portion of the silicon oxide protection layer 9 on the back surface of the first intermediate cell located in the preset P+ doping area A2A. Figure 13 This is a schematic structural diagram of the first intermediate cell after completing step S41 in Example 2 of the first aspect of the present application. Figure 13 As shown, in some examples, laser is used to remove the portion of the silicon oxide protective layer 9 on the back side of the first intermediate cell located in the preset P+ doping area A2A, while the portion of the silicon oxide protective layer 9 on the back side of the first intermediate cell located in the preset N+ doping area B2B remains.

[0085] Step S42: Perform single-side etching on the front surface of the first intermediate cell to remove the silicon oxide protection layer 9 on the front surface of the first intermediate cell. Figure 14 This is a schematic structural diagram of the second intermediate cell obtained after completing step S42 in Example 1 of the first aspect of the present application. Figure 6 As shown, in some examples, hydrofluoric acid (HF) solution is used for single-sided etching to remove the silicon oxide protective layer 9 on the side of the front side of the first intermediate cell due to the wrap-around plating phenomenon, and the stacked tunnel oxide layer 2 and N+ doped polysilicon layer 3 are retained in the wrap-around plating structure on the front side of the first intermediate cell.

[0086] The remaining steps in Example 2 are the same as those in Example 1 and will not be described again here.

[0087] A second aspect of the present application provides a solar cell, which is prepared by the method for preparing a solar cell provided by the first aspect of the present application, wherein the P+ doped region A and the N+ doped region B are alternately distributed on the back side of the solar cell.

[0088] The portion of the solar cell in the P+ doping region A has a second velvet structure A1, and the portion of the solar cell in the N+ doping region B has a first velvet structure B1. The passivation anti-reflection layer on the back of the solar cell includes a first part and a second part of unequal thicknesses, wherein the first part is in the P+ doping region A and the second part is in the N+ doping region B.

[0089] In the solar cell provided in the second aspect of the present application, the thickness of the first portion of the passivation anti-reflection layer is adapted to the structure of the P+ doped region A, so that the first portion of the passivation anti-reflection layer can achieve an optimal passivation effect in the P+ doped region A and minimize metal recombination in the P+ doped region A. The thickness of the second portion of the passivation anti-reflection layer is adapted to the structure of the N+ doped region B, so that the second portion of the passivation anti-reflection layer can achieve an optimal passivation effect in the N+ doped region B and minimize metal recombination in the N+ doped region B. The solar cell of the second aspect of the present application has improved cell efficiency.

[0090] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a P-type silicon substrate, with predetermined P+ doping regions and predetermined N+ doping regions alternately distributed on the back side of the P-type silicon substrate; a first texturing step of texturing the P-type silicon substrate so as to form a first textured surface structure on both the front and back sides of the P-type silicon substrate; forming a tunneling oxide layer, an N+ doped polysilicon layer and a silicon oxide protection layer in sequence on the back side or on both the back side and the front side of the P-type silicon substrate to obtain a first intermediate cell; removing the portion of the silicon oxide protective layer other than the portion located in the preset N+ doping region to obtain a second intermediate cell; After alkali polishing the second intermediate cell, a third intermediate cell is obtained, wherein the front surface of the third intermediate cell and the back surface of the third intermediate cell in the portion located in the preset P+ doping region are both smooth surfaces; A second texturing process is performed on the third intermediate cell to obtain a fourth intermediate cell, wherein the front surface of the fourth intermediate cell and the back surface of the fourth intermediate cell located in the preset P+ doping region both form a second texturing structure, while the back surface of the fourth intermediate cell located in the preset N+ doping region still retains the first texturing structure; forming a passivation anti-reflection layer on the front and back sides of the fourth intermediate cell; The fourth intermediate cell is metallized to form a metal electrode to obtain a solar cell.

2. The method for preparing a solar cell according to claim 1, wherein: The silicon oxide protective layer contains phosphorus or does not contain phosphorus.

3. The method for preparing a solar cell according to claim 1, wherein: The step of removing the portion of the silicon oxide protection layer other than the portion located in the preset N+ doping region to obtain a second intermediate cell comprises: patterning and removing the portion of the silicon oxide protection layer on the back surface of the first intermediate cell located in the preset P+ doping area; Single-side etching is performed on the front surface of the first intermediate cell to remove the silicon oxide protection layer on the front surface of the first intermediate cell.

4. The method for preparing a solar cell according to claim 1, wherein: The step of metallizing the fourth intermediate cell to form a metal electrode to obtain a solar cell comprises: Grooving the preset P+ doping region of the fourth middle cell to form a grooved region; Printing metal paste to the grooved area and the preset N+ doping area, and then sintering to complete the metallization process to form the metal electrode.

5. The method for preparing a solar cell according to claim 1, wherein: In the step of sequentially forming a tunneling oxide layer, an N+ doped polysilicon layer and a silicon oxide protective layer on the back side of the P-type silicon substrate to obtain a first intermediate cell: The tunneling oxide layer, the N+ doped polysilicon layer and the silicon oxide protective layer are formed by adopting at least one deposition method selected from low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition and plasma enhanced atomic layer deposition.

6. The method for preparing a solar cell according to claim 5, wherein: In the step of sequentially forming a tunneling oxide layer, an N+ doped polysilicon layer and a silicon oxide protective layer on the back and front sides of the P-type silicon substrate to obtain a first intermediate cell: The tunneling oxide layer, the N+ doped polysilicon layer and the silicon oxide protection layer are formed by low pressure chemical vapor deposition.

7. The method for preparing a solar cell according to claim 6, wherein: When the tunneling oxide layer, the N+ doped polysilicon layer and the silicon oxide protective layer are formed by low pressure chemical vapor deposition, The tunnel oxide layer is first formed, and an intrinsic polysilicon layer is formed on the tunnel oxide layer. Then, phosphorus is diffused into the intrinsic polysilicon layer to form the N+ doped polysilicon layer and the silicon oxide protective layer, wherein the silicon oxide protective layer contains phosphorus.

8. The method for preparing a solar cell according to claim 6, wherein: When the tunnel oxide layer, the N+ doped polysilicon layer and the silicon oxide protective layer are formed by plasma enhanced chemical vapor deposition, The tunneling oxide layer, the phosphorus-containing amorphous silicon layer and the silicon oxide protective layer are deposited in sequence, and after annealing, the tunneling oxide layer, the N+ doped polysilicon layer and the silicon oxide protective layer are obtained, wherein the silicon oxide protective layer does not contain phosphorus.

9. The method for preparing a solar cell according to claim 5, wherein: The deposition method includes an annealing step, In the annealing step, oxygen is supplied to the environment of the P-type silicon substrate to form the silicon oxide protection layer.

10. The method for preparing a solar cell according to claim 1, wherein: The tunnel oxide layer includes silicon oxide, and the thickness of the tunnel oxide layer is 0.5 nm to 3.0 nm.

11. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 10, wherein the P+ doped region and the N+ doped region are alternately distributed on the back side of the solar cell. The portion of the solar cell in the P+ doping region has the second velvet structure, and the portion of the solar cell in the N+ doping region has the first velvet structure. The passivation anti-reflection layer on the back of the solar cell includes a first portion and a second portion of unequal thicknesses, wherein the first portion is in the P+ doping region and the second portion is in the N+ doping region.

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