A low-frequency shunt signal generation and detection device

Abstract

The present invention relates to the technical field of low-frequency signal communication devices, and particularly to a low-frequency shunt signal generation and detection device, which includes a signal receiving module, a shunt signal generation module, a signal detection module, and an electro-optical conversion module that are electrically connected in sequence, and an interface module that is electrically connected to the shunt signal generation module and the signal detection module respectively; wherein, the signal receiving module receives an input signal and transmits an output square wave signal to the shunt signal generation module; the shunt signal generation module divides the square wave signal into multiple paths of signals and transmits each path of output signal to the signal detection module; the electro-optical conversion module converts the multiple paths of electrical signals output by the shunt signal generation module into optical signals for output. By converting the signal into a square wave signal and performing signal detection in real time, the present invention solves the problems that the output voltage of the existing solid-state transmitter contains relatively large harmonics and the signal anti-interference ability is poor, and detects the excitation signal, so as to protect the solid-state low-frequency transmitter in a timely manner.

Description

Technical Field

[0001] The present invention relates to the technical field of low-frequency signal communication devices, and particularly to a low-frequency shunt signal generation and detection device. Background Art

[0002] With the rapid development of power electronics technology, solid-state transmitters are widely used in low-frequency communication systems. At present, solid-state low-frequency transmitters generally adopt a switching method to improve the conversion efficiency, and usually consist of multiple H-shaped single-phase inverter bridges connected in parallel or in series through an output transformer; each H-shaped single-phase inverter bridge is composed of four power electronic power devices, and the control signals of the two bridge arms of the H-shaped single-phase inverter bridge are the same, and the gate drive signals of the same bridge arm are two square-wave signals with a dead zone. This form of control signal makes the output voltage of the solid-state low-frequency transmitter contain relatively large harmonics, and a relatively large LC filter must be added at the output end. This measure will increase the scale of the transmitter system, making the system more complex in terms of installation, use, maintenance, etc., and will increase the insertion loss of the transmitter system, ultimately resulting in a reduction in the working efficiency of the system.

[0003] In the actual application process of solid-state transmitters, there are high voltages and large currents in the circuit, and the distributed capacitance and distributed inductance in the loop are both very large. Slight faults in the gate drive signals of power electronic power devices will cause overvoltage (or overcurrent) in the power loop, burning out equipment or devices, posing a hidden danger to the safety performance of the equipment and bringing certain challenges to the maintenance of the equipment.

[0004] In the prior art, such as the invention patent application "Signal Processing Method and Interface Circuit between an Analog Exciter and a Power Amplifier" proposed by Beijing Beiguang Technology Co., Ltd. on March 21, 2009, with the application number 200910080198.8 and the publication number CN101847983A, it has relatively many analog devices, which will cause additional harmonic components, so that the output voltage of the solid-state low-frequency transmitter contains relatively large harmonics; there is also no optoelectronic conversion module, the signal anti-interference ability is relatively poor, and there is no excitation signal detection and protection function, and it cannot protect in time against slight faults in the excitation signal, and cannot effectively cope with the large harmonic situation of the solid-state transmitter and cannot effectively protect the solid-state transmitter. Summary of the Invention

[0005] The present invention provides a low-frequency shunt signal generation and detection device to solve the defects in the above-mentioned prior art. Aiming at the large harmonics of the solid-state transmitter and the need for circuit protection, the input excitation signal is shunted to adapt to the multi-level of the solid-state transmitter, so as to reduce the harmonics. The low-frequency shunt signal detection function is added, so that the transmitter can be protected in time when an abnormality occurs, and the problems that the output voltage of the existing solid-state transmitter contains large harmonics and the signal anti-interference ability is poor are solved. At the same time, the excitation signal is detected to protect the solid-state low-frequency transmitter in time.

[0006] The present invention provides a low-frequency shunt signal generation and detection device, including a signal receiving module, a shunt signal generation module, a signal detection module, and an electro-optical conversion module that are electrically connected in sequence, and an interface module that is electrically connected to the shunt signal generation module and the signal detection module respectively;

[0007] Among them, the signal receiving module receives the input signal and transmits the output square wave signal to the shunt signal generation module;

[0008] The shunt signal generation module divides the square wave signal into multiple paths of signals and transmits each path of output signal to the signal detection module;

[0009] The signal detection module receives the original square wave signal output by the signal receiving module, obtains the pulse width of the square wave signal, determines whether the pulse width of the square wave signal is within a preset pulse width range, and generates a blocking signal; the signal detection module also receives each path of output signal, and performs an AND operation on every two paths of output signals respectively to obtain the corresponding phase detection signal, obtains the pulse width of the phase detection signal, determines whether the pulse width of the phase detection signal is within a preset pulse width range, and generates a blocking signal;

[0010] The electro-optical conversion module converts the multiple paths of electrical signals output by the shunt signal generation module into optical signals for output.

[0011] Specifically, the signal receiving circuit includes a first operational amplifier U1, a second operational amplifier U2, and a first level conversion chip U3;

[0012] Among them, the positive input terminal of the first operational amplifier U1 is grounded through a resistor R2, the negative input terminal is connected to a series of resistor R1 and capacitor C1, and the output terminal is respectively connected to the negative input terminal of the first operational amplifier U1 and the negative input terminal of the second operational amplifier U2 through a resistor R3 and a resistor R4;

[0013] The positive input terminal of the second operational amplifier U2 is grounded through a resistor R5, the output terminal of the second operational amplifier U2 is connected to the high level terminal of the first level conversion chip U3 through a resistor R6, and the low level terminal of the first level conversion chip U3 is connected to a resistor R7.

[0014] Specifically, the shunt signal generation module is composed of an inverting sub-module, a phase shift parameter calculation sub-module, and a plurality of signal generation sub-modules;

[0015] The inverting sub-module inverts the square wave signal output by the signal receiving circuit to obtain an inverted square wave signal;

[0016] The phase shift parameter calculation sub-module receives the frequency value f of the square wave signal input by the interface module c , and generates a phase shift parameter.

[0017] Specifically, each of the signal generation sub-modules has the same structure, and each of the signal generation sub-modules includes a first counter and a second counter.

[0018] Specifically, the signal detection module includes a detection parameter calculation sub-module, a pulse width comparison sub-module, a plurality of detection sub-modules, and an alarm processing sub-module;

[0019] Among them, the detection parameter calculation sub-module calculates the maximum allowable pulse width L max , the minimum allowable pulse width L min , the pulse width X corresponding to the maximum allowable phase difference max , and the pulse width X corresponding to the minimum allowable phase difference min based on the frequency value of the square wave signal and the preset maximum allowable frequency error;

[0020] The pulse width comparison sub-module determines whether the pulse width of the square wave signal satisfies L pulse <T min <L pulse <L max , and if it is satisfied, it outputs a high-level blocking signal to the alarm processing sub-module, otherwise it outputs a low-level blocking signal to the alarm processing sub-module;

[0021] Each of the detection sub-modules performs an AND operation on every two output signals respectively to obtain a corresponding phase detection signal, and obtains the pulse width X n of the phase detection signal, and determines whether the pulse width of the phase detection signal satisfies X min <X n <X max , and if it is satisfied, it outputs a high-level blocking signal to the alarm processing sub-module, otherwise it outputs a low-level blocking signal to the alarm processing sub-module;

[0022] When the alarm processing sub-module receives a low-level blocking signal output by any one of the pulse width comparison sub-module and each of the detection sub-modules, it generates a low-level alarm signal, sets each output signal generated by the shunt signal generation module to a low level, and transmits the low-level alarm signal to the interface module.

[0023] Optionally, calculate the maximum allowable pulse width L max , the minimum allowable pulse width L min , the pulse width X corresponding to the maximum allowable phase difference max and the pulse width X corresponding to the minimum allowable phase difference min , including:

[0024]

[0025]

[0026] In the formula, the maximum allowable frequency error △f max is 400 Hz.

[0027] Specifically, the interface module receives the frequency value f of the square wave signal transmitted externally c and the low-level alarm signal transmitted by the signal detection module, and displays the frequency value f c and the low-level alarm signal, and transmits the frequency value f c to the signal generation module and the signal detection module respectively.

[0028] Specifically, the optoelectronic conversion module includes a second level conversion chip U4, a preset number of signal driver chips, and a preset number of electro-optic conversion chips;

[0029] The output signals of each path output by the split signal generation module are respectively connected to the low-level end of the second level conversion chip U4, and are converted into corresponding high-level signals by the second level conversion chip U4;

[0030] Each high-level signal is respectively sent to the input ends of 2 signal driver chips; the drive signals output by the preset number of signal driver chips are respectively output to the preset number of electro-optic conversion chips, and after electro-optic conversion, they become optical signals with twice the number of electrical signal paths and are output.

[0031] Optionally, the split signal generation module, the signal detection module, and the interface module are all implemented in the FPGA using the HDL language.

[0032] A low-frequency split signal generation and detection device provided by the present invention has the following technical effects:

[0033] By converting the sine excitation signal into a stepped square wave signal suitable for use in a low-frequency solid-state transmitter and converting the electrical signal into an optical signal, it avoids the large harmonics contained in the output voltage of the existing solid-state transmitter, and effectively improves the signal anti-interference ability of the existing solid-state transmitter;

[0034] The excitation signal is detected in real time through the signal detection module, so as to protect the solid-state low-frequency transmitter in a timely manner; the device provided by the present invention has high working efficiency, low cost, intuitive and convenient operation, and convenient maintenance, which not only improves the long-distance ocean communication ability, but also ensures the signal quality of ocean communication. Brief Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of the low-frequency shunt signal generation and detection device provided by the present invention;

[0037] Figure 2 It is a schematic structural diagram of the signal receiving module of the low-frequency shunt signal generation and detection device provided by the present invention;

[0038] Figure 3 It is a schematic diagram of the shunt signal generation of the low-frequency shunt signal generation and detection device provided by the present invention;

[0039] Figure 4 It is a waveform timing diagram of the shunt signal of the low-frequency shunt signal generation and detection device provided by the present invention;

[0040] Figure 5 It is a schematic structural diagram of the signal detection module of the low-frequency shunt signal generation and detection device provided by the present invention;

[0041] Figure 6 It is a schematic structural diagram of the optoelectronic conversion module of the low-frequency shunt signal generation and detection device provided by the present invention. Detailed Embodiments

[0042] To make the objectives, technical solutions and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] As used in the description and claims of this application and the above-mentioned drawings, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally further includes steps or modules not listed, or optionally further includes other steps or modules inherent to these processes, methods, products or devices.

[0044] It should be noted that the terms "first" and "second" related to the present invention are only used to distinguish similar objects and do not represent a specific order for the objects. Understandably, "first" and "second" can be interchanged in a specific order or sequence when permitted. It should be understood that the objects distinguished by "first" and "second" can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those described or illustrated here.

[0045] In one embodiment, as Figure 1 shown, the present invention provides a low-frequency shunt signal generation and detection device, including a signal reception module, a shunt signal generation module, a signal detection module, and an electro-optic conversion module that are electrically connected in sequence, and an interface module that is electrically connected to the shunt signal generation module and the signal detection module respectively;

[0046] Among them, the signal reception module receives an input signal and transmits an output square wave signal to the shunt signal generation module;

[0047] The shunt signal generation module divides the square wave signal into multiple paths of signals and transmits each path of output signal to the signal detection module;

[0048] The signal detection module receives the original square wave signal output by the signal reception module, obtains the pulse width of the square wave signal, determines whether the pulse width of the square wave signal is within a preset pulse width range, and generates a blocking signal; the signal detection module also receives each path of output signal, and respectively performs an AND operation on every two paths of output signals to obtain corresponding phase detection signals, obtains the pulse width of the phase detection signals, determines whether the pulse width of the phase detection signals is within a preset pulse width range, and generates a blocking signal;

[0049] The electro-optic conversion module converts the multiple paths of electrical signals output by the shunt signal generation module into optical signals for output.

[0050] Optionally, the signal reception circuit receives a sine excitation signal and outputs a square wave signal to the shunt signal generation module;

[0051] In a specific embodiment, as Figure 2As shown, the signal receiving circuit includes a first operational amplifier U1, a second operational amplifier U2, and a first level conversion chip U3. The positive input terminal of the first operational amplifier U1 is grounded through a resistor R2. The negative input terminal of the first operational amplifier U1 is connected to a series of resistor R1 and capacitor C1. The output terminal of the first operational amplifier U1 is connected to the negative input terminal of the first operational amplifier U1 and the negative input terminal of the second operational amplifier U2 through a resistor R3 and a resistor R4 respectively. The positive input terminal of the second operational amplifier U2 is grounded through a resistor R5. The output terminal of the second operational amplifier U2 is connected to the high level terminal of the first level conversion chip U3 through a resistor R6. The low level terminal of the first level conversion chip U3 is connected to a resistor R7;

[0052] Optionally, the first operational amplifier U1 and the second operational amplifier U2 use AD8055 chips, the first level conversion chip U3 uses LJ245A, the resistor R1 is 1K, the resistor R2 is 1K, the resistor R3 is 2K, the resistor R4 is 1K, the resistor R5 is 1K, the resistor R6 is 33, the resistor R7 is 33, and the capacitor C1 is 0.1uF.

[0053] In a specific embodiment, the shunt signal generation module is composed of an inverting sub-module, a phase shift parameter calculation sub-module, and a plurality of signal generation sub-modules;

[0054] The inverting sub-module inverts the square wave signal output by the signal receiving circuit to obtain an inverted square wave signal;

[0055] The phase shift parameter calculation sub-module receives the frequency value f of the square wave signal input by the interface module c and generates a phase shift parameter;

[0056] As an example, as Figure 3 shown, the shunt signal generation module includes an inverting sub-module, a phase shift parameter calculation sub-module, and a first to sixth signal generation sub-modules; The first to eighth signals generated by the shunt generation module are as Figure 4 shown;

[0057] The inverting sub-module inverts the square wave signal I1 output by the signal receiving circuit to obtain an inverted square wave signal I2;

[0058] The phase shift parameter calculation sub-module receives the frequency value f of the square wave signal I1 input by the interface module c = 20KHz and calculates the phase shift parameter S0:

[0059]

[0060] In the formula, the parameter f clk = 200MHz;

[0061] Specifically, each of the signal generation sub - modules has the same structure, and each signal generation sub - module includes a first counter and a second counter;

[0062] Among them, in the first signal generation sub - module, when the rising edge of the square - wave signal I1 arrives, the first counter starts counting. When the count value is equal to S0, the first - path signal IN1 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the square - wave signal I1 arrives, the second counter starts counting. When the count value is equal to S0, the first - path signal IN1 is output as low level, and at the same time, the second counter is cleared. The first - path signal IN1 is sent to the second signal generation sub - module;

[0063] In the second signal generation sub - module, when the rising edge of the first - path signal arrives, the first counter starts counting. When the count value is equal to S0, the second - path signal IN2 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the first - path signal arrives, the second counter starts counting. When the count value is equal to S0, the second - path signal IN2 is output as low level, and at the same time, the second counter is cleared. The second - path signal IN2 is divided into two paths, one path is sent to the fifth signal generation sub - module, and the other path is output as the fifth - path signal IN5;

[0064] In the third signal generation sub - module, when the rising edge of the inverted square - wave signal I2 arrives, the first counter starts counting. When the count value is equal to S0, the third - path signal IN3 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the inverted square - wave signal I2 arrives, the second counter starts counting. When the count value is equal to S0, the third - path signal IN3 is output as low level, and at the same time, the second counter is cleared. The third - path signal IN3 is sent to the fourth signal generation sub - module;

[0065] In the fourth signal generation sub - module, when the rising edge of the third - path signal arrives, the first counter starts counting. When the count value is equal to S0, the fourth - path signal IN4 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the third - path signal arrives, the second counter starts counting. When the count value is equal to S0, the fourth - path signal IN4 is output as low level, and at the same time, the second counter is cleared. The fourth - path signal IN4 is divided into two paths, one path is sent to the sixth signal generation sub - module, and the other path is output as the seventh - path signal IN7;

[0066] In the fifth signal generation sub - module, when the rising edge of the second - path signal arrives, the first counter starts counting. When the count value is equal to S0, the sixth - path signal IN6 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the second - path signal arrives, the second counter starts counting. When the count value is equal to S0, the sixth - path signal IN6 is output as low level, and at the same time, the second counter is cleared;

[0067] In the sixth signal generation sub-module, when the rising edge of the fourth signal arrives, the first counter starts counting. When the count value equals S0, the eighth signal IN8 is output as high level, and at the same time, the first counter is cleared. When the falling edge of the fourth signal arrives, the second counter starts counting. When the count value equals S0, the eighth signal IN8 is output as low level, and at the same time, the second counter is cleared.

[0068] In a specific embodiment, the signal detection module includes a detection parameter calculation sub-module, a pulse width comparison sub-module, multiple detection sub-modules, and an alarm processing sub-module.

[0069] As an example, as Figure 5 shown, the signal detection module includes a detection parameter calculation sub-module, a pulse width comparison sub-module, first to fourth detection sub-modules, and an alarm processing sub-module.

[0070] Specifically, the detection parameter calculation sub-module receives the frequency value f of the square wave signal I1 input by the interface module c , and calculates the maximum allowable pulse width L max , the minimum allowable pulse width L min , as well as the pulse width X corresponding to the maximum allowable phase difference max and the pulse width X corresponding to the minimum allowable phase difference min :

[0071]

[0072]

[0073] In the formula, the maximum allowable frequency error △f max is 400 Hz; the frequency value f of the square wave signal I1 c is 20 KHz;

[0074] The pulse width comparison sub-module receives L max , L min and the square wave signal I1 output by the signal receiving circuit, calculates the pulse width T of the square wave signal I1 pulse , and then determines whether L min < T pulse < L max . If so, the output blocking signal is high level, otherwise the output blocking signal is low level.

[0075] The first detection sub-module first ANDs the first signal and the second signal to obtain a first phase detection signal, calculates its pulse width X0, and then determines whether X min < X0 < X max . If so, the output blocking signal is high level, otherwise the output blocking signal is low level.

[0076] The second detection sub-module first ANDs the third signal and the fourth signal to obtain a second phase detection signal, calculates its pulse width X1, and then determines whether X min <X1<X max If so, the output blocking signal is at a high level; otherwise, the output blocking signal is at a low level.

[0077] The third detection sub-module first ANDs the fifth signal and the sixth signal to obtain a third phase detection signal, calculates its pulse width X2, and then determines whether X min <X2<X max If so, the output blocking signal is at a high level; otherwise, the output blocking signal is at a low level.

[0078] The fourth detection sub-module first ANDs the seventh signal and the eighth signal to obtain a fourth phase detection signal, calculates its pulse width X3, and then determines whether X min <X3<X max If so, the output blocking signal is at a high level; otherwise, the output blocking signal is at a low level.

[0079] When the alarm processing sub-module receives that any one of the blocking signals from the pulse width comparison sub-module and the first to fourth detection sub-modules is at a low level, it generates a low-level alarm signal, sets the first to eighth signals output by the signal generation module to a low level, and transmits the low-level alarm signal to the interface module.

[0080] The interface module receives the frequency value f of the square wave signal I1 transmitted externally c and the low-level alarm signal transmitted by the signal detection module, and displays the frequency value f c and the low-level alarm signal; and transmits the frequency value f c to the signal generation module and the signal detection module respectively.

[0081] The signal receiving circuit converts the received sine excitation signal into a square wave signal suitable for digital processing. The split signal generation module generates eight signals according to the requirements of the transmitter from the square wave signal and sends them to the signal detection module. The signal detection module detects the phase and pulse width of the generated eight signals, and at the same time, transmits the device detection and protection status to the interface module in real time. The interface module completes information transmission and display. The optoelectronic conversion module splits and drives the first to eighth signals, and at the same time realizes the conversion of multiple electrical signals into optical signals.

[0082] In one embodiment, as Figure 6As shown in the figure, the optoelectronic conversion module includes a second-level conversion chip U4, 16 signal driving chips, and 16 electro-optical conversion chips. The first to eighth signals output by the branch signal generation module are respectively connected to the low-level terminals of the second-level conversion chip U4, and are converted into eight high-level signals by the second-level conversion chip U4. Each high-level signal is respectively sent to the input terminals of 2 signal driving chips. The driving signals output by the 16 signal driving chips are respectively sent to the 16 electro-optical conversion chips, and are converted into 16 optical signals after electro-optical conversion and then output;

[0083] Optionally, the second-level conversion chip U4 uses LJ245, and the signal driving chips use a total of 8 DS75452 chips from U5 to U12, each of which includes two signal driving chips. Each of the 16 electro-optical conversion chips U13 to U28 uses T-1528;

[0084] Optionally, the branch signal generation module, the signal detection module, and the interface module are all implemented in the FPGA chip of model EP2C35F672 using the HDL language.

[0085] As a further description of the present invention, based on the above embodiments, the branch signal generation module outputs the first to eighth signals, and the optoelectronic conversion module outputs 16 optical signals, which are implemented based on the following connection method:

[0086] As Figure 6As shown, the first to eighth signals output by the shunt signal generation module are respectively connected to the low-level pins 21, 20, 19, 18, 17, 16, 15, and 14 of the second-level conversion chip U4. Pin 3 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U5. Pin 4 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U6. Pin 5 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U7. Pin 6 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U8. Pin 7 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U9. Pin 8 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U10. Pin 9 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U11. Pin 10 of the second-level conversion chip U4 is connected to pins 1 and 6 of the signal driving chip U12. Pins 3 and 5 of the signal driving chip U5 are respectively connected to pin 2 of the electro-optical conversion chip U21 and pin 2 of the electro-optical conversion chip U13. Pins 3 and 5 of the signal driving chip U6 are respectively connected to pin 2 of the electro-optical conversion chip U22 and pin 2 of the electro-optical conversion chip U14. Pins 3 and 5 of the signal driving chip U7 are respectively connected to pin 2 of the electro-optical conversion chip U23 and pin 2 of the electro-optical conversion chip U15. Pins 3 and 5 of the signal driving chip U8 are respectively connected to pin 2 of the electro-optical conversion chip U24 and pin 2 of the electro-optical conversion chip U16. Pins 3 and 5 of the signal driving chip U9 are respectively connected to pin 2 of the electro-optical conversion chip U25 and pin 2 of the electro-optical conversion chip U17. Pins 3 and 5 of the signal driving chip U10 are respectively connected to pin 2 of the electro-optical conversion chip U26 and pin 2 of the electro-optical conversion chip U18. Pins 3 and 5 of the signal driving chip U11 are respectively connected to pin 2 of the electro-optical conversion chip U27 and pin 2 of the electro-optical conversion chip U19. Pins 3 and 5 of the signal driving chip U12 are respectively connected to pin 2 of the electro-optical conversion chip U28 and pin 2 of the electro-optical conversion chip U20. Pin 1 of each of the electro-optical conversion chips U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U23, U24, U25, U26, U27, and U28 is connected to 5V. The output optical signals of the electro-optical conversion chips U13 to U20 are respectively B1 to B8, and the output optical signals of the electro-optical conversion chips U21 to U28 are respectively A1 to A8.

[0087] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0088] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-frequency shunt signal generation and detection device, characterized in that It includes a signal receiving module, a shunt signal generating module, a signal detecting module, and an electro-optical conversion module that are electrically connected in sequence, and an interface module that is electrically connected to the shunt signal generating module and the signal detecting module respectively; Among them, the signal receiving module receives an input signal and transmits an output square wave signal to the shunt signal generating module; The shunt signal generating module divides the square wave signal into multiple paths of signals and transmits each path of output signal to the signal detecting module; The signal detecting module receives the original square wave signal output by the signal receiving module, obtains the pulse width of the square wave signal, determines whether the pulse width of the square wave signal is within a preset pulse width range, and generates a blocking signal; the signal detecting module also receives each path of output signal, and performs an AND operation on every two paths of output signals respectively to obtain corresponding phase detection signals, obtains the pulse width of the phase detection signals, determines whether the pulse width of the phase detection signals is within a preset pulse width range, and generates a blocking signal; The electro-optical conversion module converts the multiple paths of electrical signals output by the shunt signal generating module into optical signals for output.

2. The low-frequency shunt signal generation and detection device according to claim 1, characterized in that The signal receiving module includes a first operational amplifier U1, a second operational amplifier U2, and a first level conversion chip U3; Among them, the positive input terminal of the first operational amplifier U1 is grounded through a resistor R2, the negative input terminal is connected to a series of resistor R1 and capacitor C1, and the output terminal is connected to the negative input terminal of the first operational amplifier U1 and the negative input terminal of the second operational amplifier U2 through a resistor R3 and a resistor R4 respectively; The positive input terminal of the second operational amplifier U2 is grounded through a resistor R5, the output terminal of the second operational amplifier U2 is connected to the high level terminal of the first level conversion chip U3 through a resistor R6, and the low level terminal of the first level conversion chip U3 is connected to a resistor R7.

3. The low-frequency shunt signal generation and detection device according to claim 1, characterized in that, The shunt signal generating module is composed of an inverting sub-module, a phase shift parameter calculation sub-module, and multiple signal generating sub-modules; The inverting sub-module inverts the square wave signal output by the signal receiving circuit to obtain an inverted square wave signal; The phase shift parameter calculation sub-module receives the frequency value f of the square wave signal input by the interface module c , and generates phase shift parameters.

4. The low-frequency shunt signal generation and detection device according to claim 3, wherein, Each of the signal generating sub-modules has the same structure, and each of the signal generating sub-modules includes a first counter and a second counter.

5. The low-frequency shunt signal generation and detection device according to claim 3, characterized in that, The signal detecting module includes a detection parameter calculation sub-module, a pulse width comparison sub-module, multiple detection sub-modules, and an alarm processing sub-module; Among them, the detection parameter calculation sub-module calculates the maximum allowable pulse width L based on the frequency value of the square wave signal and the preset maximum allowable frequency error max , the minimum allowable pulse width L min , the pulse width X corresponding to the maximum allowable phase difference max and the pulse width X corresponding to the minimum allowable phase difference min ; The pulse width comparison sub-module determines whether the pulse width of the square wave signal meets L pulse based on the pulse width T of the square wave signal min <T pulse <L max ; if it meets the condition, a high-level blocking signal is output to the alarm processing sub-module, otherwise a low-level blocking signal is output to the alarm processing sub-module; Each of the detection sub-modules performs an AND operation on every two output signals respectively to obtain corresponding phase detection signals, and obtains the pulse width X of the phase detection signals n , and determines whether the pulse width of the phase detection signal satisfies X min <X n <X max , if it is satisfied, a high-level blocking signal is output to the alarm processing sub-module, otherwise a low-level blocking signal is output to the alarm processing sub-module; When the alarm processing sub-module receives that the blocking signal output by any one of the pulse width comparison sub-module and each of the detection sub-modules is at a low level, it generates a low level alarm signal, sets each path of output signal generated by the shunt signal generating module to a low level, and transmits the low level alarm signal to the interface module.

6. The low-frequency shunt signal generation and detection device according to claim 5, characterized in that, Calculate the maximum allowable pulse width L max , the minimum allowable pulse width L min , the pulse width X corresponding to the maximum allowable phase difference max and the pulse width X corresponding to the minimum allowable phase difference min , It includes: In the formula, the maximum allowable frequency error △f max is 400 Hz.

7. The low-frequency shunt signal generation and detection device according to claim 5, characterized in that, The interface module receives the frequency value f of the square wave signal transmitted externally c and the low-level alarm signal transmitted by the signal detection module, and displays the frequency value f c and the low-level alarm signal, and transmits the frequency value f c to the signal generation module and the signal detection module respectively.

8. The low-frequency shunt signal generation and detection device according to claim 5, characterized in that, The electro-optical conversion module includes a second level conversion chip U4, a preset number of signal driver chips, and a preset number of electro-optical conversion chips; Each path of output signal output by the shunt signal generating module is respectively connected to the low level terminal of the second level conversion chip U4, and is converted into a corresponding high level signal by the second level conversion chip U4; Each high-level signal is sent to the input ends of two signal driver chips respectively; the driving signals output by a preset number of signal driver chips are output to a preset number of electro-optical conversion chips respectively, and after electro-optical conversion, optical signals with twice the number of electrical signal paths are output.

9. A low-frequency shunt signal generation and detection device according to any one of claims 1-8, characterized in that The split signal generation module, signal detection module and interface module are all implemented in the FPGA using the HDL language.

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