Chip cache testing method, device, electronic device and storage medium

Abstract

The invention discloses a chip cache test method, device, electronic device and storage medium, belonging to the field of network communication technology. The method comprises the following steps: enabling the inner loop configuration of all ports of a chip, so that the ports forward received messages after the inner loop; enabling the input CRC detection function of all ports, and prohibiting the output CRC update function of all ports; configuring the message forwarding logic inside the chip; a packet sending module inside the chip sends a message to one of the ports, and forwards the message to other ports according to the configured chip forwarding logic; detecting whether a message received on each port has a CRC check error, and thereby judging whether the chip cache has an abnormality, thereby realizing efficient detection of chip buffer abnormalities.

Description

Technical Field

[0001] The present invention relates to the field of network communication technology, and in particular to a chip cache testing method, device, electronic equipment and storage medium. Background Art

[0002] CRC (Cyclic Redundancy Check) is the most commonly used error checking code in the field of data communication. The basic idea is to treat the transmitted data as a very long number, divide this number by another number (agreed polynomial), and get the remainder as the check data, which is attached to the original data as a cyclic redundancy check code. The receiving device also executes a similar algorithm to ensure the correctness and integrity of data transmission. Its characteristic is that the length of the information field and the check field can be arbitrarily selected.

[0003] In the current Ethernet, the switching mode used in most scenarios is the store-and-forward mode, that is, after the Ethernet device receives the message, it is first saved in the buffer. After the message is searched and edited by the chip, the chip will take out the corresponding message from the buffer, and overwrite the corresponding data in the buffer with the edited result. At the same time, after merging with other data, the message is sent out from the chip. The existence of the buffer can effectively avoid the problem of packet loss caused by untimely chip export processing. At the same time, because the complete message is stored in the buffer, the message can be checked by CRC, that is, the CRC can be recalculated based on the received message at the message entrance to detect whether the received message is correct. The CRC can be recalculated at the message exit to update the original CRC field in the message.

[0004] On the other hand, if there is an error in the buffer, a common error is that a certain bit in the buffer is fixed to 0 or 1 and cannot be rewritten, which will cause errors in the content of the sent message, which will affect the subsequent forwarding behavior at the least, and cause the entire chip to be abnormal at the worst. In actual networking, messages often need to pass through multiple chips to reach the actual destination. For such problems caused by the abnormality of the upstream chip buffer and the downstream forwarding problem, it will be very troublesome to locate it.

[0005] like Figure 1 A chip cache test method shown is to detect whether the chip buffer is abnormal by using a packet test tool. Ports A and B of the tester are connected to ports 0 and 1 of the chip respectively. The forwarding logic is configured on the chip to forward the message received by port 0 to port 1. At the same time, port 1 does not recalculate the CRC. The corresponding test process is as follows:

[0006] Step 1. The tester sends a message from port A;

[0007] Step 2. Chip port 0 receives the message sent by the tester, caches the message into the buffer, and checks the forwarding table at the same time;

[0008] Step 3. Chip port 1 takes the cached message content from the buffer and sends the corresponding content to port B of the tester;

[0009] Step 4. Tester port B receives the message sent from chip port 1. By checking whether there is a CRC check error in the message received by tester port B, it is determined whether there is a problem with the chip buffer.

[0010] Although this detection method can detect whether the buffer is in a normal state, it relies on the detection of a packet tester. If there is no auxiliary packet detection tool in the actual usage scenario, it is impossible to effectively detect whether the buffer is normal. Summary of the invention

[0011] The object of the present invention is to provide a chip cache testing method, device, electronic device and storage medium to overcome one or more technical problems existing in the prior art.

[0012] To achieve the above object, the present invention provides a chip cache testing method, comprising:

[0013] Enable the inner loop configuration of all ports of the chip, so that the ports will forward the received messages after inner looping;

[0014] Enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports;

[0015] Configure the message forwarding logic inside the chip;

[0016] The packet sending module inside the chip sends a message to one of the ports, and forwards the message to other ports according to the configured chip forwarding logic;

[0017] Check whether the message received on each port has CRC check error, and judge whether there is abnormality in the chip cache.

[0018] Preferably, the configuration message forwarding logic inside the chip includes setting the message to be only forwarded without editing inside the chip.

[0019] Preferably, after the packet sending module sends the message to the inbound direction of the first port, the outbound direction of the first port receives the message and loops the message back to the inbound direction of the first port, and the message is cached in a corresponding buffer.

[0020] Preferably, after the other ports except the first port sequentially take out the messages from the buffer, they perform the inner loop of the port and then forward them sequentially.

[0021] Preferably, if a CRC check error that is inconsistent with the CRC stored in the message occurs when a CRC check is performed on the message in the inbound direction of a certain port, it is determined that an abnormality occurs in the chip cache.

[0022] Preferably, the message format sent by the packet sending module includes:

[0023] All bytes in the message are 0.

[0024] All bytes in the message are 0xFF.

[0025] All bytes of the message are 0xAA, or

[0026] All bytes in the message are 0x55.

[0027] The present invention also provides a chip cache testing device, comprising:

[0028] The port inner loop enabling module is used to enable the inner loop configuration of all ports of the chip, so that the ports forward the received messages after inner looping;

[0029] CRC detection enable module, used to enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports;

[0030] The message forwarding logic configuration module is used to configure the message forwarding logic inside the chip;

[0031] A packet sending module, used to send a message to one of the ports of the chip, and the port forwards the message to other ports according to the configured chip forwarding logic;

[0032] The chip cache abnormality judgment module is used to judge whether there is an abnormality in the chip cache based on whether there is a CRC check error in the message received on each port.

[0033] Preferably, the packet sending module is used to send the message to the first port input direction, and after the first port input direction performs CRC check, the message is looped back from the first port output direction to the first port input direction, and the message is cached in the corresponding buffer.

[0034] The present invention further proposes an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the chip cache test method when running the computer program.

[0035] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the chip cache testing method is implemented.

[0036] Compared with the prior art, the chip cache testing method proposed in the present invention utilizes the automatic packet sending engine inside the chip without the aid of an external tester, and by constructing different message formats, the message will not be edited when forwarded inside the chip, that is, the message content remains unchanged, and the CRC is not recalculated in the outbound direction of the port. At the same time, CRC detection is performed in the inbound direction of the port, thereby successfully realizing the detection of chip buffer anomalies. Compared with the traditional testing method using a tester, the chip buffer anomaly detection can be realized more efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a flowchart of an existing chip cache testing method;

[0038] Figure 2 It is a flowchart of an embodiment of a chip cache testing method of the present invention;

[0039] Figure 3 is a flow chart of an embodiment of a chip cache testing method of the present invention;

[0040] Figure 4 It is a schematic block diagram of an embodiment of a chip cache testing device of the present invention. DETAILED DESCRIPTION

[0041] The technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention.

[0042] Combination Figure 1 , Figure 2 As shown, a chip cache test method disclosed in an embodiment of the present invention sends a buffer test message through an automatic packet sending engine inside the chip, constructs different message formats, and prevents the message from being edited when forwarded inside the chip, that is, the message content remains unchanged, and does not recalculate the CRC in the outbound direction of the port. At the same time, a CRC check is performed in the inbound direction of the port, thereby realizing the detection of chip buffer abnormalities. Specifically, the test method includes the following steps:

[0043] S1. Enable the inner loop configuration for all ports of the chip, so that the ports forward the received messages after the inner loop, ensuring that all ports can connect normally and send and receive messages normally.

[0044] like Figure 2The chip in the embodiment is provided with a packet sending engine, a buffer and several ports, such as port 0, port 1, port 2, port 3 and port 4. The packet sending engine can send a message to one of the ports to detect whether there is an abnormality in the state of the buffer corresponding to the port. In this embodiment, the packet sending engine sends a message to port 0, and port 0 forwards the message after looping it in the port, that is, after the inbound direction of port 0 receives the message, it loops back from the outbound direction to the inbound direction again and forwards it after checking the forwarding table, and at the same time caches the message in the corresponding buffer.

[0045] To ensure that all buffers can be detected for abnormalities, enable the inner loop configuration for all ports, that is, after receiving a message in the inbound direction of each port, the outbound direction of the port further loops the message back to the inbound direction of the port, and caches the message in the corresponding buffer. After enabling the inner loop configuration of all ports, all ports can send and receive messages normally and cache the messages in the corresponding buffer.

[0046] S2. Enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports.

[0047] During the test, the CRC detection function of the incoming direction of all ports is enabled, and the CRC update function of the outgoing direction of all ports is disabled, so that after receiving the message in the incoming direction of each port, the CRC check is detected to see whether it is consistent with the CRC stored in the message. If they are consistent, the CRC check passes; if they are inconsistent, a CRC check error occurs.

[0048] After the CRC update function is disabled in the outbound direction of all ports, no further CRC detection will be performed in the outbound direction of the port. In this way, even if the message content changes during the forwarding process, no further CRC recalculation will be performed in the outbound direction of the port.

[0049] S3. Configure the message forwarding logic inside the chip so that the message is only forwarded without editing inside the chip to ensure that when a CRC check error occurs, it is determined that the error is caused by an abnormality in the buffer area. In addition, the export CRC will not be updated, thereby eliminating the error caused by CRC recalculation caused by changes in the message content.

[0050] When configuring the message forwarding logic inside the chip, each port needs to participate in the message forwarding process to complete the complete detection of all buffer fragments. Figure 2 The message forwarding path selection in is: the message is forwarded from port 0, port 1, port 2, port 3, port 4 in sequence until all ports are forwarded. At the same time, the message is only forwarded without editing in the port and buffer to ensure that when the message CRC check error occurs, it is excluded that it is caused by the change of message content or length, so as to further determine the abnormality of the chip buffer.

[0051] S4. Send a message to one of the ports through the internal packet sending module of the chip, and the port forwards the message to other ports according to the configured chip forwarding logic.

[0052] When testing the chip buffer, the chip sends a message to one of the ports through the internal packet engine. Figure 2 In the example, a message is sent to port 0. After receiving the message, port 0 forwards the message in the inner loop and caches the message in the buffer. After the next port receives the message popped out of the buffer, it repeats the inner loop forwarding of the port, and so on until all ports have completed forwarding.

[0053] S5. Detect whether there is a CRC check error in the message received on each port, and thereby determine whether there is an abnormality in the cache of the chip.

[0054] Specifically, the CRC check of the message is performed in the incoming direction of each port. If a check error occurs in the incoming direction of a port where the recalculated CRC is inconsistent with the CRC stored in the message after comparison, it is determined that an abnormality has occurred in the buffer corresponding to the previous port, or that the buffer corresponding to one of the previous ports is the first buffer to have an abnormality.

[0055] Figure 2 In the example, it is assumed that the chip buffer corresponding to port 3 has an abnormality. The packet engine sends the message to port 0, and then forwards it to port 1, port 2, and port 3 in sequence. When the message is forwarded at each port, it needs to be sent after the inner loop according to the inner loop enable configuration, and is cached in the buffer. Since the buffer corresponding to port 3 has an abnormality, the message will be taken out of the buffer by port 4 and a check error will occur when the CRC check is performed in the inbound direction. Therefore, it can be determined that the buffer corresponding to port 3 has an abnormality.

[0056] Since the most common situation when a buffer error occurs is that the data in the buffer is always 0 or 1, the message content sent by the chip internal packet sending engine in this embodiment adopts the following message formats:

[0057] 1) All 0, that is, all bytes in the message are 0;

[0058] 2) All 0xFF, that is, all bytes in the message are 1;

[0059] 3) All 0xAA, that is, all bytes in the message are composed of 1010;

[0060] 4) All 0x55, that is, all bytes in the message are composed of 0101.

[0061] The above four message formats can completely detect all abnormal situations where the data in the buffer is always 0 or 1. Of course, in other embodiments of the present invention, other message formats that can detect buffer data errors can also be selected.

[0062] Based on the above chip cache testing method, the present invention also proposes a chip cache testing device, such as Figure 4 As shown, the test device includes a port inner loop enabling module, a CRC detection enabling module, a message forwarding logic configuration module, a packet sending module and a chip cache abnormality judgment module. The port inner loop enabling module is used to enable the inner loop configuration of all ports of the chip, so that each port forwards the received message after the inner loop of the port, and caches the message in the corresponding buffer.

[0063] The CRC detection enable module is used to enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports, so that the message is only checked for CRC in the incoming direction of the port.

[0064] The message forwarding logic configuration module is used to configure the message forwarding logic inside the chip so that the message is not edited when forwarded in the chip port and buffer, thereby eliminating CRC check errors caused by changes in the message itself.

[0065] A packet sending module, used to send a message to one of the ports of the chip, and the port forwards the message to other ports according to the configured chip forwarding logic;

[0066] The chip cache abnormality judgment module is used to judge whether there is an abnormality in the chip cache according to whether there is a CRC check error in the message received on each port.

[0067] The process of each module of the chip cache test device realizing the chip cache test function can be referred to the introduction of the above-mentioned test method and process, which will not be repeated here.

[0068] The present invention also discloses an electronic device, which may include but is not limited to: a personal computer, a server computer, a workstation, a desktop computer, a laptop computer, a notebook computer, a mobile electronic device, a smart phone, a tablet computer, a cellular phone, a personal digital assistant (PDA), a handheld device, a message transceiver device, a wearable electronic device, a consumer electronic device, etc. The electronic device can implement the chip cache test method described above. Specifically, the electronic device includes at least one memory, at least one processor and a computer program, at least one memory is coupled to the at least one processor, wherein the computer program is stored in the memory and can run the chip cache test method described above in the processor. During implementation, when the processor executes the computer program, each step in the above method can be implemented to achieve judgment.

[0069] It should be noted that the electronic equipment here includes but is not limited to the memory, processor and computer program mentioned above, and may also include others, such as input devices for inputting prediction information (such as keyboards, etc.), display screens, communication interfaces, etc. These components communicate with each other through a bus.

[0070] The present invention also discloses a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, a chip cache test method can be implemented. The computer program includes a computer program code, which can be in source code form, an executable file, or some intermediate form, and the computer-readable medium can include any entity or device, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), etc. that can carry the computer program code.

[0071] The technical contents and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and are covered by the claims of this patent application.

Claims

1. A chip cache testing method, characterized in that: include: Enable the inner loop configuration of all ports of the chip, so that the ports will forward the received messages after inner looping; Enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports; Configure the message forwarding logic inside the chip so that the message is forwarded without editing inside the chip; The packet sending module inside the chip sends a message to one of the ports, and forwards the message to other ports according to the configured forwarding logic inside the chip; Check whether the message received on each port has CRC check error, and judge whether there is abnormality in the chip cache.

2. The chip cache testing method according to claim 1, characterized in that: After the packet sending module sends the message to the first port inbound direction, the first port outbound direction receives the message and loops the message back to the first port inbound direction, the message is cached in a set buffer and is prepared to be forwarded to the next port by checking the forwarding table.

3. The chip cache testing method according to claim 2, characterized in that: After receiving the messages sent by the buffer in sequence, the other ports except the first port perform the inner loop of the port and then forward them in sequence.

4. The chip cache testing method according to claim 1, characterized in that: If a CRC check error that is inconsistent with the CRC in the message occurs when a CRC check is performed on the message in the inbound direction of a certain port, it is determined that an abnormality occurs in the chip cache.

5. The chip cache testing method according to claim 1, characterized in that: The message formats sent by the packet sending module include: All bytes in the message are 0. All bytes in the message are 0xFF. All bytes of the message are 0xAA, or All bytes in the message are 0x55.

6. A chip cache test device, characterized in that: include: The port inner loop enabling module is used to enable the inner loop configuration of all ports of the chip, so that the ports forward the received messages after the inner loop; CRC detection enable module, used to enable the CRC detection function in the incoming direction of all ports and disable the CRC update function in the outgoing direction of all ports; The message forwarding logic configuration module is used to configure the message forwarding logic inside the chip so that the message can be forwarded without editing inside the chip; A packet sending module, used to send a message to one of the ports of the chip, and the port forwards the message to other ports according to the configured chip forwarding logic; The chip cache abnormality judgment module is used to judge whether there is an abnormality in the chip cache based on whether there is a CRC check error in the message received on each port.

7. The chip cache testing device according to claim 6, characterized in that: The packet sending module is used to send the message to the first port input direction. After the first port input direction performs CRC check, the message is looped back to the first port input direction from the first port output direction, and the message is cached in a set buffer.

8. An electronic device, comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 5 when running the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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