Semiconductor device and semiconductor memory device
By using insulating layer structures with different oxygen atom concentrations and optimizing the shape of the oxide semiconductor layer in oxide semiconductor transistors, the problem of characteristic changes after heat treatment was solved, and stable turn-on current and reliable DRAM memory cell switching transistors were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-12-27
- Publication Date
- 2026-06-23
AI Technical Summary
Oxide semiconductor transistors are prone to changes in characteristics after heat treatment, leading to asymmetry in the on-current and affecting their stability as switching transistors in DRAM memory cells.
An insulating layer structure with different oxygen atom concentrations is adopted, especially with the oxygen atom concentration of the upper insulating layer being lower than that of the lower insulating layer. This suppresses the decrease in oxygen vacancy concentration in the upper region after heat treatment. By designing the shape of the oxide semiconductor layer and selecting the material of the insulating layer, the contact resistance and current asymmetry are reduced.
This achieves stable characteristics of oxide semiconductor transistors after heat treatment, reduces the asymmetry of the turn-on current, and improves the reliability of switching transistors in DRAM memory cells.
Smart Images
Figure CN115867025B_ABST
Abstract
Description
[0001] [Citation of relevant applications]
[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-153487 filed on September 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field
[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology
[0004] Oxide semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during disconnection. Therefore, for example, OSTs are studied as switching transistors for use in memory cells of dynamic random access memory (DRAM).
[0005] For example, oxide semiconductor transistors can sometimes exhibit characteristic variations due to heat treatment applied after the transistor structure is formed. Therefore, it is desirable to realize oxide semiconductor transistors with stable characteristics that exhibit minimal characteristic variations even after heat treatment. Summary of the Invention
[0006] One implementation provides a semiconductor device with stable characteristics.
[0007] The semiconductor device of the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode disposed between the first electrode and the second electrode in a first direction from the first electrode toward the second electrode and facing the oxide semiconductor layer; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first insulating layer disposed between the gate electrode and the first electrode; and a second insulating layer disposed between the gate electrode and the second electrode, wherein the oxygen atom concentration is lower than the oxygen atom concentration of the first insulating layer.
[0008] Based on the aforementioned configuration, a semiconductor device with stable characteristics can be provided. Attached Figure Description
[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
[0011] Figure 3This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
[0012] Figure 4 This is a schematic cross-sectional view of a comparative example semiconductor device.
[0013] Figure 5 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.
[0014] Figure 6 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.
[0015] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.
[0016] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.
[0017] Figure 9 This is a schematic cross-sectional view of a variation of the semiconductor device according to the third embodiment.
[0018] Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.
[0019] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.
[0020] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.
[0021] Figure 13 This is a schematic cross-sectional view of a variation of the semiconductor device according to the fifth embodiment.
[0022] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment.
[0023] Figure 15 This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment.
[0024] Figure 16 This is an equivalent circuit diagram of the semiconductor memory device according to the eighth embodiment.
[0025] Figure 17 This is a schematic cross-sectional view of the semiconductor memory device according to the eighth embodiment. Detailed Implementation
[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will sometimes be omitted.
[0027] In addition, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" are merely terms indicating the relative positional relationship within the accompanying drawings, and do not specify the positional relationship relative to gravity.
[0028] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device and semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness of the components constituting the semiconductor device and semiconductor memory device, the distance between components, and the crystal grain size can be performed, for example, by transmission electron microscopy (TEM). Additionally, measurements of the carrier concentration of the components constituting the semiconductor device and semiconductor memory device can be performed, for example, by scanning diffusion resistance microscopy (SSRM).
[0029] (First Embodiment) The semiconductor device of the first embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode disposed between the first electrode and the second electrode in a first direction from the first electrode toward the second electrode and facing the oxide semiconductor layer; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first insulating layer disposed between the gate electrode and the first electrode; and a second insulating layer disposed between the gate electrode and the second electrode, wherein the oxygen atom concentration is lower than the oxygen atom concentration of the first insulating layer.
[0030] Figure 1 , Figure 2 , Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' sectional view. Figure 3 yes Figure 1 BB' sectional view. Figure 1 In this context, the up-down direction is referred to as the first direction. Figure 1 In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.
[0031] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor 100 is a so-called surrounding gate transistor (SGT) in which a gate electrode surrounds an oxide semiconductor layer in which the channel is formed. The transistor 100 is a so-called vertical transistor.
[0032] The transistor 100 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0033] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Lower insulating layer 24 is an example of a first insulating layer. Upper insulating layer 26 is an example of a second insulating layer.
[0034] The silicon substrate 10 is, for example, single-crystal silicon. The silicon substrate 10 is one example of a substrate. The substrate is not limited to a silicon substrate. The substrate can also be, for example, a semiconductor substrate other than a silicon substrate. The substrate can also be, for example, an insulating substrate.
[0035] The lower electrode 12 is disposed on the silicon substrate 10. A substrate insulating layer 22 is disposed between the silicon substrate 10 and the lower electrode 12. The lower electrode 12 is an example of the first electrode.
[0036] The lower electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.
[0037] The lower electrode 12 is a conductor. The lower electrode 12 may contain, for example, an oxide conductor or a metal. The lower electrode 12 may be, for example, an oxide conductor containing indium (In) and tin (Sn). The lower electrode 12 may be, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).
[0038] The lower electrode 12 may also have a multilayer structure of multiple conductors.
[0039] The upper electrode 14 is disposed on the silicon substrate 10. The upper electrode 14 is disposed on the lower electrode 12. The lower electrode 12 is disposed between the silicon substrate 10 and the upper electrode 14. The upper electrode 14 is an example of a second electrode. The direction from the lower electrode 12 toward the upper electrode 14 is a first direction.
[0040] The upper electrode 14 functions as either the source electrode or the drain electrode of the transistor 100.
[0041] The upper electrode 14 is a conductor. The upper electrode 14 may contain, for example, an oxide conductor or a metal. The upper electrode 14 may be, for example, an oxide conductor containing indium (In) and tin (Sn). The upper electrode 14 may also be a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).
[0042] The upper electrode 14 may also have a multilayer structure of multiple conductors.
[0043] An oxide semiconductor layer 16 is disposed on the silicon substrate 10. The oxide semiconductor layer 16 is disposed between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is, for example, connected to the lower electrode 12. The oxide semiconductor layer 16 is, for example, connected to the upper electrode 14.
[0044] A channel is formed in the oxide semiconductor layer 16, which becomes a current path when the transistor 100 is turned on.
[0045] The oxide semiconductor layer 16 is an oxide semiconductor. The oxide semiconductor layer 16 is, for example, amorphous.
[0046] The oxide semiconductor layer 16, for example, contains at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and zinc (Zn). The oxide semiconductor layer 16, for example, contains indium (In), gallium (Ga), and zinc (Zn). The atomic concentration of zinc (Zn) in the oxide semiconductor layer 16 is, for example, more than 5 atomic% and less than 20 atomic%.
[0047] The oxide semiconductor layer 16 may contain at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W). The oxide semiconductor layer 16 may contain titanium oxide, zinc oxide, or tungsten oxide.
[0048] The oxide semiconductor layer 16, for example, has a chemical composition different from that of the lower electrode 12 and the upper electrode 14.
[0049] The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c. The middle region 16c is disposed between the lower region 16a and the upper region 16b. The lower region 16a is disposed between the lower electrode 12 and the middle region 16c. The upper region 16b is disposed between the middle region 16c and the upper electrode 14.
[0050] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.
[0051] For example, the oxygen vacancy concentration in the lower region 16a is higher than that in the middle region 16c. The oxygen vacancies in the lower region 16a are formed, for example, by the absorption of oxygen in the lower region 16a by the lower electrode 12. The lower region 16a is an n-type semiconductor. The carrier concentration in the lower region 16a is higher than that in the middle region 16c. The lower region 16a functions as either the source or drain region of the transistor 100.
[0052] For example, the oxygen vacancy concentration in the upper region 16b is higher than that in the middle region 16c. The oxygen vacancies in the upper region 16b are formed, for example, by the absorption of oxygen in the upper region 16b by the upper electrode 14. The upper region 16b is an n-type semiconductor. The carrier concentration in the upper region 16b is higher than that in the middle region 16c. The upper region 16b functions as either the source or drain region of the transistor 100.
[0053] The intermediate region 16c faces the gate electrode 18. The intermediate region 16c functions as the channel region of the transistor 100.
[0054] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm or more and 200 nm or less. The width of the oxide semiconductor layer 16 in the second direction is, for example, 20 nm or more and 100 nm or less.
[0055] The gate electrode 18 is disposed between the lower electrode 12 and the upper electrode 14 in the first direction. The gate electrode 18 faces the oxide semiconductor layer 16.
[0056] The gate electrode 18 is disposed surrounding the oxide semiconductor layer 16.
[0057] The gate electrode 18 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 18 may contain, for example, tungsten (W).
[0058] The gate length of the gate electrode 18 is, for example, 20 nm or more and 100 nm or less. The gate length of the gate electrode 18 is the length of the gate electrode 18 in the first direction.
[0059] A gate insulating layer 20 is disposed between the oxide semiconductor layer 16 and the gate electrode 18. The gate insulating layer 20 surrounds the oxide semiconductor layer 16.
[0060] The gate insulating layer 20 is, for example, connected to the lower electrode 12. The gate insulating layer 20 is, for example, connected to the upper electrode 14.
[0061] The gate insulating layer 20 is, for example, an oxide or oxynitride. The gate insulating layer 20 may contain, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 20 is, for example, 2 nm or more but less than 10 nm.
[0062] A substrate insulating layer 22 is disposed between the silicon substrate 10 and the lower electrode 12. The substrate insulating layer 22 is, for example, an oxide, a nitride, or an oxide oxynitride. The substrate insulating layer 22 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride.
[0063] The lower insulating layer 24 is disposed above the lower electrode 12. The lower insulating layer 24 is disposed between the gate electrode 18 and the lower electrode 12.
[0064] The lower insulating layer 24 surrounds the lower region 16a of the oxide semiconductor layer 16. The lower insulating layer 24 surrounds the gate insulating layer 20. The gate insulating layer 20 is disposed between the lower insulating layer 24 and the lower region 16a.
[0065] The lower insulating layer 24 is, for example, an oxide or an oxide oxynitride. The lower insulating layer 24 may contain, for example, silicon oxide or silicon oxynitride. The lower insulating layer 24 may contain, for example, a silicon oxide layer or a silicon oxynitride layer. The lower insulating layer 24 may contain, for example, a silicon oxide layer or a silicon oxynitride layer.
[0066] An upper insulating layer 26 is disposed above the gate electrode 18. The upper insulating layer 26 is disposed between the gate electrode 18 and the upper electrode 14.
[0067] The upper insulating layer 26 surrounds the upper region 16b of the oxide semiconductor layer 16. The upper insulating layer 26 surrounds the gate insulating layer 20. The gate insulating layer 20 is disposed between the upper insulating layer 26 and the upper region 16b.
[0068] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the upper insulating layer 26 is less than half that in the lower insulating layer 24.
[0069] The upper insulating layer 26 is, for example, an oxide, a nitride, or an oxynitride. The upper insulating layer 26 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride. The upper insulating layer 26 may contain, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The upper insulating layer 26 may be, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.
[0070] For example, when the lower insulating layer 24 is a silicon oxide layer, the upper insulating layer 26 is a silicon nitride layer. Alternatively, for example, when the lower insulating layer 24 is a silicon oxide layer, the upper insulating layer 26 is a silicon oxynitride layer.
[0071] Alternatively, for example, when the lower insulating layer 24 is a silicon oxide layer, the upper insulating layer 26 is a silicon oxide layer with a relatively lower oxygen concentration than the lower insulating layer 24. For example, when the lower insulating layer 24 is a silicon oxide layer with a silicon (Si) to oxygen (O) atomic ratio (Si / O) of half, the upper insulating layer 26 is a silicon oxide layer with a silicon (Si) to oxygen (O) atomic ratio (Si / O) of more than half.
[0072] Furthermore, when manufacturing the transistor 100, after forming the lower electrode 12 on the silicon substrate 10, the oxide semiconductor layer 16 and the upper electrode 14 are formed sequentially.
[0073] The function and effects of the semiconductor device according to the first embodiment will be explained below.
[0074] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during disconnection. Therefore, for example, research is being conducted on the application of OSTs in switching transistors for DRAM memory cells.
[0075] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, their characteristics can sometimes change due to heat treatment applied after the transistor structure is formed. Therefore, it is desirable to realize oxide semiconductor transistors with stable characteristics that exhibit minimal characteristic changes even after heat treatment.
[0076] Figure 4 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 4 It is the semiconductor device of the first embodiment. Figure 1 The corresponding diagram.
[0077] The comparative example semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor in which the channel is formed in an oxide semiconductor. The difference between transistor 900 and transistor 100 of the first embodiment is that the oxygen atom concentration of the upper insulating layer 26 is equal to the oxygen atom concentration of the lower insulating layer 24. The lower insulating layer 24 and the upper insulating layer 26 are, for example, silicon oxide layers.
[0078] The characteristics of the comparative transistor 900 change due to the heat treatment applied after the transistor structure is formed. In particular, heat treatment in an oxygen-containing environment can lead to an asymmetry problem in the turn-on current. The asymmetry in the turn-on current refers to the difference in the magnitude of the turn-on current when the current flows from the upper electrode 14 to the lower electrode 12 and when the current flows from the lower electrode 12 to the upper electrode 14.
[0079] One reason for the perceived asymmetry in the turn-on current is that the oxygen vacancy concentration in the lower region 16a of the oxide semiconductor layer 16 differs from that in the upper region 16b of the oxide semiconductor layer 16 after the heat treatment applied following the formation of the transistor structure. For example, if the oxygen vacancy concentration in the upper region 16b decreases, the carrier concentration in the upper region 16b will decrease. This decrease in carrier concentration in the upper region 16b leads to an increase in the contact resistance between the upper region 16b and the upper electrode 14. Consequently, an asymmetry in parasitic resistance occurs between the upper and lower parts of the transistor structure, resulting in an asymmetry in the turn-on current of the transistor 900.
[0080] Figure 5 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 5 This indicates the state after the transistor structure of the comparative example transistor 900 is formed, during which heat treatment is performed in an oxygen-containing environment.
[0081] Oxygen is supplied to the lower region 16a and the upper region 16b from the environment. Additionally, oxygen is supplied to the lower region 16a from the lower insulating layer 24 formed of a silicon oxide layer. Furthermore, oxygen is supplied to the upper region 16b from the upper insulating layer 26 formed of a silicon oxide layer.
[0082] Oxygen vacancies are filled using oxygen supplied to both the lower region 16a and the upper region 16b. The amount of oxygen from the environment in the upper region 16b is greater than that in the lower region 16a. Therefore, the oxygen vacancy concentration in the upper region 16b is lower than that in the lower region 16a. Consequently, the carrier concentration in the upper region 16b is lower than that in the lower region 16a, resulting in an increase in the contact resistance between the upper region 16b and the upper electrode 14.
[0083] Figure 6 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 6 This indicates the state after the transistor structure of the transistor 100 of the first embodiment is formed, during which heat treatment is performed in an oxygen-containing environment.
[0084] In the transistor 100 of the first embodiment, the oxygen atom concentration of the upper insulating layer 26 is lower than that of the lower insulating layer 24. For example, when the lower insulating layer 24 is a silicon oxide layer, the upper insulating layer 26 is a silicon oxide layer with a relatively lower oxygen concentration than the lower insulating layer 24.
[0085] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. Therefore, during heat treatment, the amount of oxygen supplied from the upper insulating layer 26 to the upper region 16b is less than the amount of oxygen supplied from the lower insulating layer 24 to the lower region 16a. Consequently, the decrease in oxygen vacancy concentration in the upper region 16b is suppressed. Therefore, the decrease in carrier concentration in the upper region 16b is suppressed, thereby suppressing the increase in contact resistance between the upper region 16b and the upper electrode 14. Therefore, the occurrence of asymmetry in the turn-on current of the transistor 100 after heat treatment is suppressed.
[0086] From the viewpoint of suppressing oxygen supply to the upper region 16b, the upper insulating layer 26 is preferably a silicon nitride layer. From the viewpoint of suppressing oxygen supply to the upper region 16b, the upper insulating layer 26 is preferably a silicon oxide layer with a silicon (Si) to oxygen (O) atomic ratio (Si / O) of more than half.
[0087] From the viewpoint of suppressing the oxygen supply to the upper region 16b, the oxygen atom concentration of the upper insulating layer 26 is preferably less than one-half of the oxygen atom concentration of the lower insulating layer 24, more preferably less than one-tenth, and even more preferably less than one-hundredth.
[0088] According to the first embodiment, the asymmetry of the turn-on current after heat treatment is suppressed, thereby enabling the realization of an oxide semiconductor transistor with stable characteristics.
[0089] (Second Embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second insulating layer includes: a first region; and a second region disposed between the first region and the second electrode, and the oxygen atom concentration is lower than the oxygen atom concentration of the first region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0090] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.
[0091] The semiconductor device in the second embodiment is a transistor 200. The transistor 200 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0092] The transistor 200 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0093] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Lower insulating layer 24 is an example of a first insulating layer. Upper insulating layer 26 is an example of a second insulating layer.
[0094] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the upper insulating layer 26 is less than half that in the lower insulating layer 24.
[0095] The upper insulating layer 26 includes a first region 26a and a second region 26b. The second region 26b is disposed between the first region 26a and the upper electrode 14.
[0096] The oxygen atom concentration in region 26b is lower than that in region 1, 26a. The oxygen atom concentration in region 1, 26a is, for example, less than half of the oxygen atom concentration in region 1, 26a.
[0097] For example, when the lower insulating layer 24 is a silicon oxide layer, the first region 26a is a silicon oxide layer and the second region 26b is a silicon nitride layer. Alternatively, for example, when the lower insulating layer 24 is a silicon oxide layer, the first region 26a is a silicon oxide layer and the second region 26b is a silicon oxynitride layer.
[0098] Additionally, for example, when the lower insulating layer 24 is a silicon oxide layer, the first region 26a is a silicon oxide layer with the same oxygen concentration as the lower insulating layer 24, and the second region 26b is a silicon oxide layer with a relatively lower oxygen concentration than the lower insulating layer 24. For example, when the lower insulating layer 24 and the first region 26a are silicon oxide layers with an atomic ratio of silicon (Si) to oxygen (O) (Si / O) of half, the second region 26b is a silicon oxide layer with an atomic ratio of silicon (Si) to oxygen (O) (Si / O) of more than half.
[0099] According to the second embodiment, the asymmetry of the turn-on current after heat treatment is suppressed by the same action as in the first embodiment, thereby realizing an oxide semiconductor transistor with stable characteristics.
[0100] (Third Embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the thickness of the gate insulating layer in the second direction between the second insulating layer and the oxide semiconductor layer is thinner than the thickness of the gate insulating layer in the second direction between the first insulating layer and the oxide semiconductor layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0101] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.
[0102] The semiconductor device in the third embodiment is a transistor 300. The transistor 300 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0103] The transistor 300 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0104] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Lower insulating layer 24 is an example of a first insulating layer. Upper insulating layer 26 is an example of a second insulating layer.
[0105] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the upper insulating layer 26 is less than half that in the lower insulating layer 24.
[0106] The thickness of the gate insulating layer 20 between the upper insulating layer 26 and the oxide semiconductor layer 16 in the second direction is thinner than the thickness of the gate insulating layer 20 between the lower insulating layer 24 and the oxide semiconductor layer 16 in the second direction. The thickness of the gate insulating layer 20 between the upper insulating layer 26 and the upper region 16b is thinner than the thickness of the gate insulating layer 20 between the lower insulating layer 24 and the lower region 16a.
[0107] According to the transistor 300 of the third embodiment, the decrease in oxygen vacancy concentration in the upper region 16b is suppressed by the same function as that of the transistor 100 of the first embodiment.
[0108] Furthermore, in the transistor 300 of the third embodiment, the gate insulating layer 20 between the upper insulating layer 26 and the upper region 16b is thinner. Therefore, during heat treatment, oxygen is absorbed from the upper region 16b toward the upper insulating layer 26. In particular, when the upper insulating layer 26 is, for example, an oxygen-free layer such as silicon nitride, oxygen absorption from the upper region 16b toward the upper insulating layer 26 is further promoted. Therefore, the decrease in oxygen vacancy concentration in the upper region 16b is further suppressed.
[0109] In the transistor 300 of the third embodiment, from the viewpoint of promoting oxygen absorption from the upper region 16b toward the upper insulating layer 26, the upper insulating layer 26 is preferably a silicon nitride layer.
[0110] (Example of variation) Figure 9 This is a schematic cross-sectional view of a variation of the semiconductor device according to the third embodiment. The variation of the semiconductor device according to the third embodiment is a transistor 301.
[0111] The difference between transistor 301 and transistor 300 of the third embodiment is that at least a portion of the upper insulating layer 26 is in contact with the oxide semiconductor layer 16. The difference between transistor 301 and transistor 300 of the third embodiment is that at least a portion of the upper insulating layer 26 is in contact with the upper region 16b.
[0112] Transistor 301 is connected to upper region 16b via upper insulating layer 26, and oxygen absorption from upper region 16b toward upper insulating layer 26 during heat treatment is further promoted. Therefore, compared with transistor 300, the reduction of oxygen vacancy concentration in upper region 16b is further suppressed.
[0113] According to the third embodiment and its variations, the asymmetry of the turn-on current after heat treatment is further suppressed, thereby enabling the realization of an oxide semiconductor transistor with more stable characteristics.
[0114] (Fourth Embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that, in a cross-section of the oxide semiconductor layer parallel to the first direction, the first width of the oxide semiconductor layer at the first position in the oxide semiconductor layer, perpendicular to the first direction, is smaller than the second width of the oxide semiconductor layer at the second position in the oxide semiconductor layer, which is closer to the second electrode than the first position. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0115] Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.
[0116] The semiconductor device in the fourth embodiment is a transistor 400. The transistor 400 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0117] The transistor 400 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0118] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Lower insulating layer 24 is an example of a first insulating layer. Upper insulating layer 26 is an example of a second insulating layer.
[0119] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the upper insulating layer 26 is less than half that in the lower insulating layer 24.
[0120] In a cross-section of the oxide semiconductor layer 16 parallel to the first direction, the first position in the oxide semiconductor layer 16 ( Figure 10 The first width (P1) of the oxide semiconductor layer 16 perpendicular to the first direction and the second direction (in the first direction) Figure 10 w1 in the oxide semiconductor layer 16 is closer to the second position of the upper electrode 14 than the first position P1 in the oxide semiconductor layer 16. Figure 10 The second width (P2) of the oxide semiconductor layer 16 in the second direction at point P2 Figure 10 w2) is small.
[0121] The width of the oxide semiconductor layer 16 in the second direction decreases, for example, from the upper electrode 14 toward the lower electrode 12. The side surface of the oxide semiconductor layer 16 has a tapered shape.
[0122] According to the fourth embodiment, the asymmetry of the turn-on current after heat treatment is suppressed by the same action as in the first embodiment, thereby realizing an oxide semiconductor transistor with stable characteristics.
[0123] (Fifth Embodiment) The semiconductor device of the fifth embodiment differs from the semiconductor device of the fourth embodiment in that it further includes a third insulating layer, which is surrounded by a second insulating layer and an oxide semiconductor layer, and the oxygen atom concentration is lower than that of the first insulating layer. Hereinafter, some descriptions that are repeated in the first or fourth embodiment will be omitted.
[0124] Figure 11 , Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Figure 12 yes Figure 11 BB' sectional view.
[0125] The semiconductor device in the fifth embodiment is a transistor 500. The transistor 500 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0126] The transistor 500 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, an upper insulating layer 26, and a core insulating layer 28. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0127] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Lower insulating layer 24 is an example of a first insulating layer. Upper insulating layer 26 is an example of a second insulating layer. Core insulating layer 28 is an example of a third insulating layer.
[0128] The oxygen atom concentration in the upper insulating layer 26 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the upper insulating layer 26 is less than half that in the lower insulating layer 24.
[0129] The width of the oxide semiconductor layer 16 in the second direction decreases, for example, from the upper electrode 14 toward the lower electrode 12. The side surface of the oxide semiconductor layer 16 has a tapered shape.
[0130] The core insulating layer 28 is surrounded by the upper insulating layer 26. The core insulating layer 28 is surrounded by the oxide semiconductor layer 16. The core insulating layer 28 is in contact with the oxide semiconductor layer 16. The core insulating layer 28 is in contact with the upper region 16b. The core insulating layer 28 extends along the first direction.
[0131] The width of the core insulating layer 28 in the second direction decreases, for example, from the upper electrode 14 toward the lower electrode 12. The side surface of the core insulating layer 28 has a tapered shape. In addition, for example, the lowermost part of the core insulating layer 28 is positioned higher in the second direction than the upper surface of the gate electrode 18 is positioned in the second direction.
[0132] The oxygen atom concentration in the core insulating layer 28 is lower than that in the lower insulating layer 24. For example, the oxygen atom concentration in the core insulating layer 28 is less than half that in the lower insulating layer 24.
[0133] The core insulating layer 28 is, for example, an oxide, a nitride, or an oxynitride. The core insulating layer 28 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride. The core insulating layer 28 may contain, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The core insulating layer 28 may contain, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.
[0134] The core insulating layer 28 is, for example, made of the same material as the upper insulating layer 26.
[0135] According to the transistor 500 of the fifth embodiment, the decrease in oxygen vacancy concentration in the upper region 16b is suppressed by the same function as that of the transistor 100 of the first embodiment.
[0136] Furthermore, the transistor 500 of the fifth embodiment includes a core insulating layer 28 with a low oxygen atom concentration that is in contact with the upper region 16b of the oxide semiconductor layer 16. Therefore, during heat treatment, oxygen is absorbed from the upper region 16b toward the core insulating layer 28. In particular, when the core insulating layer 28 is, for example, an oxygen-free layer such as silicon nitride, oxygen absorption from the upper region 16b toward the core insulating layer 28 is promoted. Therefore, the decrease in oxygen vacancy concentration in the upper region 16b is further suppressed.
[0137] In the transistor 500 of the fifth embodiment, from the viewpoint of promoting oxygen absorption from the upper region 16b toward the core insulating layer 28, the core insulating layer 28 is preferably a silicon nitride layer.
[0138] (Example of variation) Figure 13 This is a schematic cross-sectional view of a variation of the semiconductor device according to the fifth embodiment. The variation of the semiconductor device according to the fifth embodiment is a transistor 501.
[0139] The difference between transistor 501 and transistor 500 in the fifth embodiment is that the core insulating layer 28 is connected to the lower electrode 12. The core insulating layer 28 is surrounded by a lower region 16a, a middle region 16c, and an upper region 16b.
[0140] Transistor 501 has a core insulating layer 28, thereby suppressing the decrease in oxygen vacancy concentration in the upper region 16b by means of the same function as transistor 500 in the fifth embodiment.
[0141] According to the fifth embodiment and its variations, the asymmetry of the turn-on current after heat treatment is further suppressed, thereby enabling the realization of an oxide semiconductor transistor with more stable characteristics.
[0142] (Sixth Embodiment) The semiconductor device of the sixth embodiment differs from the semiconductor device of the first embodiment in that it includes a substrate in which a second electrode is disposed between the first electrode and the second electrode. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0143] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment.
[0144] The semiconductor device in the sixth embodiment is a transistor 600. The transistor 600 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0145] The transistor 600 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0146] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a second electrode. Upper electrode 14 is an example of a first electrode. Lower insulating layer 24 is an example of a second insulating layer. Upper insulating layer 26 is an example of a first insulating layer.
[0147] The lower insulating layer 24 is disposed above the lower electrode 12. The lower insulating layer 24 is disposed between the gate electrode 18 and the lower electrode 12.
[0148] The lower insulating layer 24 surrounds the lower region 16a of the oxide semiconductor layer 16. The lower insulating layer 24 surrounds the gate insulating layer 20. The gate insulating layer 20 is disposed between the lower insulating layer 24 and the lower region 16a.
[0149] The oxygen atom concentration in the lower insulating layer 24 is lower than that in the upper insulating layer 26. For example, the oxygen atom concentration in the lower insulating layer 24 is less than half that in the upper insulating layer 26.
[0150] The lower insulating layer 24 is, for example, an oxide, a nitride, or an oxynitride. The lower insulating layer 24 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride. The lower insulating layer 24 may contain, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The lower insulating layer 24 may contain, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.
[0151] An upper insulating layer 26 is disposed above the gate electrode 18. The upper insulating layer 26 is disposed between the gate electrode 18 and the upper electrode 14.
[0152] The upper insulating layer 26 surrounds the upper region 16b of the oxide semiconductor layer 16. The upper insulating layer 26 surrounds the gate insulating layer 20. The gate insulating layer 20 is disposed between the upper insulating layer 26 and the upper region 16b.
[0153] The upper insulating layer 26 is, for example, an oxide or an oxide oxynitride. The upper insulating layer 26 may contain, for example, silicon oxide or silicon oxynitride. The upper insulating layer 26 may contain, for example, a silicon oxide layer or a silicon oxynitride layer. The upper insulating layer 26 may be, for example, a silicon oxide layer or a silicon oxynitride layer.
[0154] For example, when the upper insulating layer 26 is a silicon oxide layer, the lower insulating layer 24 is a silicon nitride layer. Alternatively, for example, when the upper insulating layer 26 is a silicon oxide layer, the lower insulating layer 24 is a silicon oxynitride layer.
[0155] Additionally, for example, when the upper insulating layer 26 is a silicon oxide layer, the lower insulating layer 24 is a silicon oxide layer with a relatively lower oxygen concentration than the upper insulating layer 26. For example, when the upper insulating layer 26 is a silicon oxide layer with a silicon (Si) to oxygen (O) atomic ratio (Si / O) of half, the lower insulating layer 24 is a silicon oxide layer with a silicon (Si) to oxygen (O) atomic ratio (Si / O) of more than half.
[0156] For example, sometimes the material of the lower electrode 12 is different from the material of the upper electrode 14. For example, sometimes the material of the lower electrode 12 is less likely to absorb oxygen from the oxide semiconductor layer 16 than the material of the upper electrode 14. When the material of the lower electrode 12 is less likely to absorb oxygen from the oxide semiconductor layer 16, there is concern that the oxygen vacancy concentration in the lower region 16a may decrease after heat treatment. If the oxygen vacancy concentration in the lower region 16a decreases, the contact resistance between the lower region 16a and the lower electrode 12 will increase. Therefore, there is concern about generating asymmetry in the transistor's turn-on current.
[0157] In transistor 600, the oxygen atom concentration in the lower insulating layer 24 is lower than that in the upper insulating layer 26. Therefore, during heat treatment, the amount of oxygen supplied from the lower insulating layer 24 to the lower region 16a is less than the amount supplied from the upper insulating layer 26 to the upper region 16b. Consequently, the decrease in oxygen vacancy concentration in the lower region 16a is suppressed. Therefore, the decrease in carrier concentration in the lower region 16a is suppressed, thereby suppressing the increase in contact resistance between the lower region 16a and the lower electrode 12. Therefore, the occurrence of asymmetry in the turn-on current of transistor 600 after heat treatment is suppressed.
[0158] According to the sixth embodiment, the asymmetry of the turn-on current after heat treatment is suppressed, thereby enabling the realization of an oxide semiconductor transistor with stable characteristics.
[0159] (Seventh Embodiment) The semiconductor device of the seventh embodiment differs from the semiconductor device of the sixth embodiment in that, in a cross-section of the oxide semiconductor layer parallel to the first direction, the first width of the second direction perpendicular to the first direction at the first position in the oxide semiconductor layer is larger than the second width of the second direction at the second position in the oxide semiconductor layer that is closer to the second electrode than the first position. Hereinafter, some descriptions that are repeated in the sixth embodiment will be omitted.
[0160] Figure 15 This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment.
[0161] The semiconductor device in the seventh embodiment is a transistor 700. The transistor 700 is an oxide semiconductor transistor in which an oxide semiconductor channel is formed.
[0162] The transistor 700 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a substrate insulating layer 22, a lower insulating layer 24, and an upper insulating layer 26. The oxide semiconductor layer 16 includes a lower region 16a, an upper region 16b, and a middle region 16c.
[0163] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a second electrode. Upper electrode 14 is an example of a first electrode. Lower insulating layer 24 is an example of a second insulating layer. Upper insulating layer 26 is an example of a first insulating layer.
[0164] The oxygen atom concentration in the lower insulating layer 24 is lower than that in the upper insulating layer 26. For example, the oxygen atom concentration in the lower insulating layer 24 is less than half that in the upper insulating layer 26.
[0165] In a cross-section of the oxide semiconductor layer 16 parallel to the first direction, the first position in the oxide semiconductor layer 16 ( Figure 15 The first width (P1) of the oxide semiconductor layer 16 perpendicular to the first direction and the second direction (in the first direction) Figure 15 w1 in the oxide semiconductor layer 16 is closer to the second position of the lower electrode 12 than the first position P1 in the oxide semiconductor layer 16. Figure 15 The second width (P2) of the oxide semiconductor layer 16 in the second direction at point P2 Figure 15 w2) is large.
[0166] The width of the oxide semiconductor layer 16 in the second direction decreases, for example, from the upper electrode 14 toward the lower electrode 12. The side surface of the oxide semiconductor layer 16 has a tapered shape.
[0167] According to the seventh embodiment, the asymmetry of the turn-on current after heat treatment is suppressed through the same action as in the sixth embodiment, thereby realizing an oxide semiconductor transistor with stable characteristics.
[0168] (Eighth Embodiment) The semiconductor memory device of the eighth embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode disposed between the first electrode and the second electrode in a first direction from the first electrode toward the second electrode and facing the oxide semiconductor layer; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first insulating layer disposed between the gate electrode and the first electrode; a second insulating layer disposed between the gate electrode and the second electrode, and having an oxygen atom concentration lower than that of the first insulating layer; and a capacitor electrically connected to the first electrode or the second electrode.
[0169] The semiconductor memory device of the eighth embodiment is a semiconductor memory 800. The semiconductor memory device of the eighth embodiment is a DRAM. The semiconductor memory 800 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.
[0170] Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0171] Figure 16 This is an equivalent circuit diagram of the semiconductor memory device according to the eighth embodiment. Figure 16 The example illustrates a single storage unit MC, but storage units MC can also be arranged in an array of multiple units.
[0172] The semiconductor memory 800 includes memory cells MC, word lines WL, bit lines BL, and board lines PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 16 In the diagram, the area enclosed by the dashed line is the memory cell MC.
[0173] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source and drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to plate line PL.
[0174] The storage cell MC stores data by storing charge in the capacitor CA. Data writing and reading are performed by turning on the switching transistor TR.
[0175] For example, with the required voltage applied to the bit line BL, the switching transistor TR is turned on to perform data writing to the memory cell MC.
[0176] Alternatively, for example, the switching transistor TR is turned on to detect the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor, and the data of the memory cell MC is read out.
[0177] Figure 17 This is a schematic cross-sectional view of the semiconductor memory device according to the eighth embodiment. Figure 17 This represents a cross-section of the memory cell MC of the semiconductor memory 800.
[0178] Semiconductor memory 800 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, a lower interlayer insulating layer 30, and an upper interlayer insulating layer 32. The silicon substrate 10 is an example of a substrate.
[0179] The switching transistor TR includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a lower insulating layer 24, and an upper insulating layer 26. The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode. The lower insulating layer 24 is an example of a first insulating layer. The upper insulating layer 26 is an example of a second insulating layer.
[0180] The switching transistor TR has the same structure as the transistor 100 in the first embodiment.
[0181] Capacitor CA is disposed between silicon substrate 10 and switching transistor TR. Capacitor CA is disposed between silicon substrate 10 and lower electrode 12. Capacitor CA is electrically connected to lower electrode 12.
[0182] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. For example, the unit electrode 71 is connected to the lower electrode 12.
[0183] The unit electrode 71 and the plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.
[0184] Gate electrode 18 is electrically connected, for example, to word line WL (not shown). Upper electrode 14 is electrically connected, for example, to bit line BL (not shown). Plate electrode 72 is connected, for example, to plate line PL (not shown).
[0185] When manufacturing a semiconductor memory 800, after forming a capacitor CA on a silicon substrate 10, a switching transistor TR is formed. When forming the switching transistor TR, after forming the lower electrode 12, an oxide semiconductor layer 16 and an upper electrode 14 are formed sequentially.
[0186] The semiconductor memory 800 utilizes an oxide semiconductor transistor with extremely low channel leakage current during disconnection in the switching transistor TR. This results in DRAM with excellent charge retention characteristics.
[0187] Furthermore, the asymmetry in the turn-on current that occurs in the switching transistor TR of the semiconductor memory 800 due to the applied heat treatment is suppressed. Therefore, the characteristics of the switching transistor TR are stable, and the characteristics of the semiconductor memory 800 are also stable.
[0188] In embodiments 1 to 7, a transistor with a gate electrode surrounding an oxide semiconductor layer was described as an example. However, the transistor in the embodiments of the present invention may also be a transistor with a gate electrode not surrounding an oxide semiconductor layer. For example, the transistor in the embodiments of the present invention may also be a transistor with an oxide semiconductor layer sandwiched between two gate electrodes.
[0189] In the eighth embodiment, a semiconductor memory using the transistor of the first embodiment was described as an example, but the semiconductor memory of the embodiments of the present invention may also be a semiconductor memory using the transistors of the second to seventh embodiments.
[0190] In the eighth embodiment, a semiconductor memory in which the unit electrode is electrically connected to the lower electrode was described as an example. However, the semiconductor memory in the embodiments of the present invention may also be a semiconductor memory in which the unit electrode is electrically connected to the upper electrode.
[0191] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be replaced or modified with the constituent elements of other embodiments. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.
Claims
1. A semiconductor device comprising: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode disposed between the first electrode and the second electrode in a first direction from the first electrode toward the second electrode and facing the oxide semiconductor layer; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first insulating layer disposed between the gate electrode and the first electrode; and a second insulating layer disposed between the gate electrode and the second electrode, wherein the oxygen atom concentration is lower than the oxygen atom concentration of the first insulating layer.
2. The semiconductor device of claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.
3. The semiconductor device according to claim 1 or 2, wherein the second insulating layer comprises a silicon nitride layer or a silicon oxide layer in which the atomic ratio of silicon (Si) to oxygen (O) (Si / O) is greater than half.
4. The semiconductor device according to claim 1 or 2, wherein the oxygen atom concentration of the second insulating layer is less than half of the oxygen atom concentration of the first insulating layer.
5. The semiconductor device according to claim 1 or 2, wherein the second insulating layer comprises: a first region; and a second region disposed between the first region and the second electrode, wherein the oxygen atom concentration is lower than the oxygen atom concentration of the first region.
6. The semiconductor device according to claim 1 or 2, wherein the thickness of the gate insulating layer between the second insulating layer and the oxide semiconductor layer in a second direction perpendicular to the first direction is thinner than the thickness of the gate insulating layer between the first insulating layer and the oxide semiconductor layer in the second direction.
7. The semiconductor device according to claim 1 or 2, wherein the second insulating layer is in contact with the oxide semiconductor layer.
8. The semiconductor device according to claim 1 or 2, further comprising a third insulating layer, the third insulating layer being surrounded by the second insulating layer and surrounded by the oxide semiconductor layer, and having an oxygen atom concentration lower than that of the first insulating layer.
9. The semiconductor device according to claim 1 or 2, further comprising a substrate having the first electrode disposed between the first electrode and the second electrode.
10. The semiconductor device according to claim 1 or 2, wherein in a cross section of the oxide semiconductor layer parallel to the first direction, the first width of the oxide semiconductor layer at a first position in the oxide semiconductor layer in a second direction perpendicular to the first direction is smaller than the second width of the oxide semiconductor layer at a second position in the oxide semiconductor layer closer to the second electrode than the first position.
11. The semiconductor device according to claim 1 or 2, further comprising a substrate having the second electrode disposed between the first electrode and the second electrode.
12. The semiconductor device of claim 11, wherein in a cross section of the oxide semiconductor layer parallel to the first direction, the first width of a second direction perpendicular to the first direction at a first position in the oxide semiconductor layer is greater than the second width of the second direction at a second position in the oxide semiconductor layer that is closer to the second electrode than the first position.
13. A semiconductor memory device comprising: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode disposed between the first electrode and the second electrode in a first direction from the first electrode toward the second electrode and facing the oxide semiconductor layer; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first insulating layer disposed between the gate electrode and the first electrode; a second insulating layer disposed between the gate electrode and the second electrode, wherein the oxygen atom concentration is lower than the oxygen atom concentration of the first insulating layer; and a capacitor electrically connected to the first electrode or the second electrode.
14. The semiconductor memory device of claim 13, further comprising a substrate, wherein the capacitor is disposed between the substrate and the first electrode.
15. The semiconductor memory device of claim 13 or 14, wherein the gate electrode surrounds the oxide semiconductor layer.
16. The semiconductor memory device according to claim 13 or 14, wherein the second insulating layer comprises a silicon nitride layer or a silicon oxide layer having an atomic ratio of silicon (Si) to oxygen (O) of more than half (Si / O).
17. The semiconductor memory device according to claim 13 or 14, wherein the oxygen atom concentration of the second insulating layer is less than half of the oxygen atom concentration of the first insulating layer.