Photonic integrated circuit

Abstract

The invention relates to a device including a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and monolithically integrated with the substrate. The photodetector is configured to operate at cryogenic temperatures (e.g., below about 50 K or about 20 K). In some embodiments, the monolithic photonic device includes a thermal isolation structure and an optical isolation structure. Techniques for fabricating monolithic photonic devices including a thermal isolation structure and an optical isolation structure are also described.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 039,840, entitled “Photonic Integrated Circuits,” filed June 16, 2020, the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] Photonic integrated circuits (such as those in photonic quantum computing systems) can include a variety of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. Integrating different types of integrated optical components onto a single chip can be challenging because the fabrication processes and materials used for these components differ.

[0004] Integrating different types of integrated optical components onto a single chip can negatively impact the performance of photonic integrated circuits due to noise, such as stray light or heat dissipated from heat-generating components to other components. For example, highly sensitive photodetectors (e.g., single-photon detectors) can be used in many photonic quantum technologies, such as quantum cryptography and quantum computing. Due to their high sensitivity, these photodetectors can be very sensitive to noise, such as unwanted ambient light or stray light that may reach the photodetector via direct or indirect paths. Some thermo-optical components, such as thermal tuners used for tuning filters, can employ heaters. The heat generated by the heaters can dissipate to other areas of the photonic integrated circuit, which may reduce the efficiency of the thermo-optical components and / or increase the temperature of other components that may need to operate at low temperatures (e.g., cryogenic temperatures). Summary of the Invention

[0005] This disclosure generally relates to photonic integrated circuits. More specifically, this disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and / or thermal isolation structures. For example, the monolithic photonic integrated circuit may include optical isolation structures to prevent background light from reaching high-sensitivity photodetectors (e.g., superconducting nanowire single-photon detectors) in the photonic integrated circuit (PIC) to achieve high sensitivity and high signal-to-noise ratio (SNR). The monolithic photonic integrated circuit may also include thermal isolation structures to reduce or prevent heat dissipation from some thermo-optical devices to other areas of the photonic integrated circuit. A combination of various semiconductor processing techniques can be used to fabricate monolithic photonic integrated circuits with optical and / or thermal isolation structures. Various inventive embodiments, including methods, processes, systems, devices, etc., are described herein.

[0006] According to some embodiments, the photonic integrated circuit may include a photonic integrated circuit for optical quantum computing. The photonic integrated circuit may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. For example, the photonic integrated circuit may include a single-photon generator for generating a single photon, filters and switches that can be tuned or controlled by thermo-optical devices or other tuners, and a single-photon detector for detecting a single photon. Different types of integrated optical components can operate at different temperatures. For example, the single-photon detector may include a superconducting nanowire single-photon detector that can operate at low temperatures, while thermo-optical devices can operate at much higher temperatures.

[0007] According to some embodiments, the photonic integrated circuit may include an isolation structure fabricated using a CMOS back-end of line (BEOL) process to prevent ambient light or stray light from directly or indirectly reaching the photodetector. The isolation structure may include, for example, a metal layer, an array of vias, an air gap, or trenches filled with reflective or absorbing materials. The isolation structure can provide local and / or global isolation to the photodetector and / or waveguide at different locations, including the input and output ports of the photonic integrated circuit and the photodetector, such that any scattered, reflected, diffused, or otherwise leaked light from the light source or photonic integrated circuit is partially or completely blocked, thereby preventing it from reaching the photodetector.

[0008] According to some embodiments, a device includes: a substrate; a dielectric layer on the substrate; a waveguide within the dielectric layer; a heater disposed in the dielectric layer; a thermal isolation structure including trenches in the dielectric layer and undercuts in the substrate; and a photodetector disposed above the waveguide and monolithically integrated with the substrate, the photodetector being optically coupled to the waveguide and configured to operate at temperatures below 50 K.

[0009] The systems, apparatus, and methods disclosed herein can improve the signal-to-noise ratio of a photodetector by preventing unwanted light from reaching it. This allows the photodetector to achieve high sensitivity with minimal downtime. The isolation structures can be fabricated using standard CMOS back-end-of-line (BEOL) processes or CMOS-compatible BEOL processes. Some isolation can be localized and may not require additional global layers or materials in the stack-up, thus avoiding additional thermal load on the circuitry and devices.

[0010] According to some embodiments, the photonic integrated circuit may include a thermal isolation structure, such as a trench adjacent to the heating device and a large undercut region. The thermal isolation structure can also be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet / dry etching. The thermal isolation structure can contain heat in a localized area to improve the efficiency of the thermo-optical device and reduce the burden on cooling areas that may need to operate at low temperatures. Attached Figure Description

[0011] Various aspects of this disclosure are illustrated by way of example. Non-limiting and non-exhaustive aspects are described in conjunction with the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in the various figures.

[0012] Figure 1 This is a simplified block diagram illustrating an example of an optical device according to certain embodiments, which includes a photonic integrated circuit (PIC) and a high-sensitivity photodetector.

[0013] Figure 2 An example of stray light isolation at the input and / or output ports of a photonic integrated circuit according to certain embodiments is shown.

[0014] Figure 3 An example of a locally isolated photodetector employing various isolation structures is shown according to certain embodiments.

[0015] Figures 4A to 4D Another example of a locally isolated photodetector employing various isolation structures in an optical device, according to certain embodiments, is shown. Figure 4AThis is a cross-sectional view of an optical device, which includes a photodetector and an optical isolation structure. Figure 4B yes Figure 4A A perspective view of the optical components. Figure 4C yes Figure 4A A top view of the optical components. Figure 4D yes Figure 4A A top view of the cross-section of an optical device.

[0016] Figure 5 This is a flowchart illustrating exemplary methods for fabricating various optical isolation structures in a photonic integrated circuit according to certain embodiments.

[0017] Figure 6 This is a cross-sectional view of an example of a photonic integrated circuit according to certain embodiments, which includes a photodetector and is fabricated using a front-end process.

[0018] Figure 7 This is a cross-sectional view of an example photonic integrated circuit according to certain embodiments, which has vias or trenches etched in an oxide layer using a back-end process.

[0019] Figure 8 This is a cross-sectional view of an example photonic integrated circuit according to certain embodiments, which has vias or trenches etched in an oxide layer and filled with a reflective or absorbing material (e.g., metal).

[0020] Figure 9 This is a cross-sectional view of an example of a photonic integrated circuit according to certain embodiments, which has a metal cap fabricated on a metal layer for locally isolating a photodetector.

[0021] Figure 10 This is a cross-sectional view of an example photonic integrated circuit after an additional BEOL process according to certain embodiments.

[0022] Figure 11 This is a cross-sectional view of an example of a photonic integrated circuit according to certain embodiments, the photonic integrated circuit including deep trenches etched in the substrate of the photonic integrated circuit.

[0023] Figure 12 This is a cross-sectional view of an example of a photonic integrated circuit according to certain embodiments, the photonic integrated circuit including deep trenches filled with reflective or absorbing material in the substrate of the photonic integrated circuit.

[0024] Figure 13 This is a cross-sectional view of an example photonic integrated circuit according to certain embodiments, showing optical isolation implemented by various isolation structures in the photonic integrated circuit.

[0025] Figure 14This is a flowchart illustrating an exemplary method for fabricating a photonic integrated circuit according to certain embodiments.

[0026] Figure 15 An example of a basic PIC according to certain embodiments is shown.

[0027] Figure 16 Examples of additional layers that can be deposited for a three-layer lithography process are shown according to certain embodiments.

[0028] Figure 17 An example of an etched PIC structure according to certain embodiments is shown.

[0029] Figure 18 An example of etching an oxide layer on a PIC according to certain embodiments is shown.

[0030] Figure 19 An example of an etching process for forming a trench structure in a thermally isolated region is shown according to certain embodiments.

[0031] Figure 20 An example of an etching process for forming an undercut structure according to certain embodiments is shown.

[0032] Figure 21 An example of an undercut structure according to certain embodiments is shown.

[0033] Figure 22 Examples of processes for forming oxide layers that seal trench structures and undercut structures, according to certain embodiments, are shown.

[0034] Figure 23 Examples of additional layers that can be deposited for a three-layer lithography process are shown according to certain embodiments.

[0035] Figure 24 An example of a contact hole for forming an electrical contact is shown according to certain embodiments.

[0036] Figure 25 Examples of additional layers that can be deposited for a three-layer lithography process are shown according to certain embodiments.

[0037] Figure 26 An example of a contact hole for forming an electrical contact of a photodetector, according to certain embodiments, is shown.

[0038] Figure 27 An example of an electrical contact of a photonic integrated circuit according to certain embodiments is shown.

[0039] Figure 28 An example of a scattering reduction structure according to certain embodiments is shown. Detailed Implementation

[0040] The technology disclosed herein generally relates to a photonic integrated circuit. More specifically, this disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and / or thermal isolation structures. Various inventive embodiments are described herein, including methods, processes, systems, devices, etc.

[0041] According to some embodiments, the photonic integrated circuit may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. For example, the photonic integrated circuit may include a photonic integrated circuit for optical quantum computing and may include a single-photon generator for generating single photons, filters and switches that can be tuned or controlled by thermo-optical devices or other tuners, and a single-photon detector for detecting single photons. Different types of integrated optical components can operate at different temperatures. For example, the single-photon detector may include a superconducting nanowire single-photon detector that can operate at low temperatures, while the thermo-optical device can operate at much higher temperatures.

[0042] The monolithic photonic integrated circuit (PIC) may include an optical isolation structure to prevent background light from reaching the high-sensitivity photodetector (e.g., a single-photon detector) within the PIC, thereby achieving high sensitivity and a high signal-to-noise ratio (SNR). The PIC may also include a thermal isolation structure to reduce or prevent heat dissipation from some thermo-optical devices to other areas of the PIC. A combination of various semiconductor processing techniques can be used to fabricate a monolithic photonic integrated circuit with optical and / or thermal isolation structures.

[0043] High-sensitivity photodetectors (such as single-photon detectors (SPDs) used in many photonic quantum technologies, including superconducting nanowire SPDs (SNSPDs)) can be highly sensitive to many types of light radiation. In many cases, high-sensitivity photodetectors may fail to achieve their potential sensitivity or signal-to-noise ratio (SNR) due to various noise sources, such as noise caused by background light, including stray light in the system or ambient light entering the system. The techniques disclosed herein can reduce or prevent unwanted background light (e.g., stray light or ambient light) from reaching high-sensitivity photodetectors (e.g., superconducting nanowire single-photon detectors) in photonic integrated circuits to achieve high sensitivity and high signal-to-noise ratio.

[0044] According to some embodiments, to improve the sensitivity and SNR of a photodetector, reflective or absorptive structures can be employed around the photodetector to optically isolate the photodetector (e.g., SNSPD) from background radiation (e.g., ambient light or stray light). In some embodiments, additional isolation structures can be added at any other location in the PIC where background light might otherwise propagate before reaching the photodetector, to reduce the number of stray photons that may reach the photodetector region. For example, since a major source of background light or stray light in a photonic integrated circuit is light reflected, scattered, or diffused at the optical input and / or output ports of the PIC (e.g., input or output waveguide couplers) due to imperfect coupling of light into or out of the PIC (e.g., waveguide), isolation structures can be employed at the optical input and / or output ports to prevent stray light from entering the PIC. This significantly reduces the probability of any stray light or ambient light entering the waveguide or reaching the photodetector region. Furthermore, even if any background light reaches the area where the photodetector is located, the local isolation structure around the photodetector can block the background light to prevent it from being detected by the photodetector. In various embodiments, the optical isolation structure can be fabricated using standard CMOS back-end of line (BEOL) technology or other CMOS-compatible fabrication processes.

[0045] According to some embodiments, the photonic integrated circuit may include a heater for tuning integrated optical components, such as optical filters, optical switches, optical interferometers, etc. The photonic integrated circuit may also include thermal isolation structures, such as trenches and large undercut regions adjacent to the heater. Thermal isolation structures can retain heat in localized areas to improve the efficiency of thermo-optical devices and reduce the burden on cooling areas (including devices) that may need to operate at low temperatures. The thermal isolation structures can also be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet / dry etching.

[0046] Several illustrative embodiments will now be described in conjunction with the accompanying drawings, which form a part of this description. The illustrative description provides only one or more embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the illustrative description of one or more embodiments will provide those skilled in the art with an enabling description of implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent, however, that various embodiments can be practiced without these specific details. The drawings and description are not limiting. The terms “example” or “exemplary” are used herein to mean “as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as being better than or superior to other embodiments or designs.

[0047] Figure 1This is a simplified block diagram illustrating an example of an optical device 100 according to certain embodiments, which includes a photonic integrated circuit (PIC) 120 and a high-sensitivity photodetector 130. The PIC 120 may include a photonic circuit formed by waveguides and other active or passive optical components, such as filters, resonators, beam splitters, optical amplifiers, etc. The optical device may include a light source, such as a laser 110, which may be an ultrafast (e.g., picosecond or femtosecond) pulsed laser. In some embodiments, the light source may be an external light source and may be connected to the PIC 120 via, for example, one or more optical fibers. Light from the light source may be coupled into the waveguide within the PIC 120 via couplers such as grating couplers or edge couplers. However, achieving very high coupling efficiency may be difficult. For example, in many cases, the coupling efficiency may be below 90%, below 75%, below 60%, or below 50%. Therefore, a significant amount of light from the light source may not enter the waveguide in the PIC 120 and may instead be reflected, scattered, or diffused, becoming stray light 140. Stray light 140 may be reflected, refracted, diffracted, or otherwise deflected by structures or components in optical device 100, such as metal layers, interfaces between different materials, etc. Therefore, a portion of stray light 140 may eventually reach photodetector 130. Furthermore, some portions of PIC 120 may leak light out along a desired path. For example, light may couple out of the waveguide instead of being guided within the photonic circuitry to reach photodetector 130, for instance, when the waveguide has a sharp bend or when defects exist in the waveguide or other photonic circuitry. Light leaking from the photonic circuitry may become stray light 150, which may also be at least partially deflected to photodetector 130. In some embodiments, ambient light may also enter PIC 120, for example, through oxide layers and / or reflected by metal layers.

[0048] The photodetector 130 can be a highly sensitive photodetector, such as a single-photon detector. For example, in some embodiments, the photodetector 130 may include a superconducting nanowire single-photon detector capable of detecting a single photon. In one embodiment, the photodetector 130 may include a waveguide coupled to a superconducting nanowire (e.g., a niobium-germanium nanowire, which can have ultra-low resistance in its superconducting state). The superconducting nanowire may be photosensitive or photoactive, such as photon-absorbing. For example, photons passing through the waveguide may be absorbed by the superconducting nanowire, causing the superconducting nanowire to become non-superconducting (i.e., changing its resistance or impedance). The change in resistance or impedance in the nanowire can be converted into an electrical detection signal (e.g., a current or voltage signal) indicating the detection of one or more photons.

[0049] When at least a portion of stray light 140, 150 reaches photodetector 130, it may cause a change in the state of the superconducting nanowire, and photodetector 130 may generate a detection signal indicating the detection of one or more photons even when no photons arrive from the waveguide to the superconducting nanowire, or the amplitude of the detection signal may not correctly indicate the number of photons arriving from the waveguide to the photodetector. Therefore, photodetector 130 may generate erroneous or incorrect (e.g., noisy) detection signals, which may reduce the effective sensitivity or SNR of photodetector 130.

[0050] According to some embodiments, optical isolation structures can be added at different locations on the optics 100 to block stray light or ambient light from reaching the photodetector 130. For example, an isolation structure 160 can be added at the input port of the PIC 120, an isolation structure 170 can be fabricated to surround the photodetector 130, and an isolation structure 180 can be added anywhere in the optics 100 where background light might otherwise propagate. Further details of some embodiments of the optical isolation structures and their fabrication processes are described in the following examples.

[0051] Figure 2 An example of isolating stray light at the input and / or output ports of a photonic integrated circuit 200 according to certain embodiments is shown. Figure 2 A cross-sectional view of a PIC 200 is shown, which may include a waveguide 210 fabricated on a substrate 205 (e.g., a silicon-processed wafer). The PIC 200 may also include an input port 220 and an output port 230 of the waveguide 210. The waveguide 210 may transmit light from the input port 220 into the interior of the PIC 200 (where some photosensitive components may be located), or may export light from the PIC 200 through the output port 230.

[0052] As described above, light may not be perfectly coupled into or out of waveguide 210 at input port 220 or output port 230. A significant portion of the input or output light may enter the PIC 200 through a path outside of waveguide 210. In some cases, approximately 10 12 A single photon can enter the PIC 200 as stray light. To prevent these photons from reaching the interior of the PIC 200, one or more optical isolation structures can be fabricated at the input and / or output ports. For example, such as... Figure 2 As shown, the PIC 200 may include one or more metal trenches 240 and one or more deep trenches 260, which can serve as Figure 1The isolation structure 160 is shown. The metal trench 240 may include a metal layer thick enough to block (e.g., reflect or absorb) incident photons. The metal trench 240 may act as a mirror barrier and may extend downwards from, for example, metal 1 (M1, which may be about 1 μm above waveguide 210) to substrate 205 (which may be about 2-3 μm below waveguide 210) to block light that may propagate in the cladding of waveguide 210 from reaching the interior of PIC 200. A deep trench 260 may extend through substrate 205 of PIC 200 and may be empty (i.e., an air gap) or filled with a reflective or absorbing material to at least partially reflect or absorb incident photons that may propagate in or be scattered from substrate 205, preventing photons from entering the cladding of the waveguide.

[0053] Gap 250 may exist between adjacent metal trenches 240, allowing waveguide 210 to pass through the gap between the metal trenches 240. Gap 270 may exist between adjacent deep trenches 260, allowing waveguide 210 to be supported by the substrate at gap 270. Figure 2 As shown, gaps 250 and 270 may be misaligned and offset from each other by a certain distance, so that gap 250 may not be in the line of sight of stray photons from input port 220. Therefore, stray photons from input port 220 may not pass through gap 250, but may be blocked by metal groove 240.

[0054] Figure 3 An example of a locally isolated photodetector 350 employing various isolation structures in a photonic integrated circuit 300 according to certain embodiments is shown. The PIC 300 may include a substrate 305 (e.g., a silicon-processed wafer). A waveguide 310 may be formed on the substrate 305, wherein the waveguide 310 may include multiple bends to change direction. Optically isolated structures (e.g., a top metal cap 320, a metal trench 330, and a deep trench 340) may be fabricated in the PIC 300 to surround and isolate the waveguide 310 and the photodetector 350. Figure 3 The optical isolation structure shown can be Figure 1 One specific embodiment of the isolation structure 170, and it can form an isolation structure that can be compared to a castle-like structure.

[0055] like Figure 3As shown, waveguide 310 can transmit signal light from photonic circuitry in PIC 300 to photodetector 350 (e.g., SNSPD), where the signal light can be detected. Similar to deep trench 260, deep trench 340 can include an air gap that completely penetrates the substrate 305, or it can be filled with a reflective or absorbing material. In some embodiments, deep trench 340 can partially penetrate the substrate 305. The deep trench can isolate photodetector 350 from light that may propagate in or be scattered from the substrate 305. Metal trench 330 can be similar to metal trench 240 and can be combined as described above. Figure 2 As described above, a mirror-like barrier is created extending downwards from M1 to substrate 305. In some embodiments, the metal trench 330 may include a plurality of nested rings centered on photodetector 350, wherein an inner ring may be surrounded by one or more outer rings. Each ring may include an opening through which waveguide 310 can pass. The opening in each ring may be located on a different side (e.g., opposite side or adjacent side) relative to the opening in an adjacent ring. The metal trench 330 may block light that may propagate in the cladding of waveguide 310 from reaching photodetector 350. The top metal cap 320 may serve as a top cover for the optical isolation structure, analogous to a castle-like structure, and may prevent light from reaching photodetector 350 from the top of PIC 300.

[0056] Figures 4A to 4D Another example of a locally isolated photodetector 470 employing various isolation structures in an optical device 400 according to certain embodiments is shown. Figure 4A This is a cross-sectional view of an optical device 400, which includes a photodetector 470 and an optically isolated structure surrounding the photodetector 470. Figure 4B yes Figure 4A The diagram shows a perspective view of the optical device 400. The optical device 400 may include a substrate 410 (e.g., a silicon wafer), a barrier oxide (BOX) layer 420 (e.g., silicon dioxide), a waveguide 440 formed on top of the BOX layer 420, and a low-temperature oxide (LTO) layer 430 covering the waveguide 440. The optical device 400 may also include an array of vias 450 that can be formed on a metal layer and a top metal cap 460.

[0057] Figure 4C yes Figure 4A A top view of the optical device 400. Figure 4CA top metal cover 460 is shown, which covers the photodetector 470 from the top, so that background light cannot reach the photodetector 470 from the top, wherein the top metal cover 460 may be part of a metal layer 1.

[0058] Figure 4D yes Figure 4A A top view of the cross-section of the optical device 400. Figure 4D The arrangement of via array 450 and photodetector 470 is shown. As shown, via array 450 can be arranged in a two-dimensional array, wherein vias in a row (or column) can be offset from vias in adjacent rows (or columns), so that the via array can effectively form walls. Photodetector 470 may include photoactive nanowires 480 (e.g., niobium-germanium nanowires) on waveguide 440.

[0059] Figure 5 This is a flowchart 500 illustrating an exemplary method for fabricating various optical isolation structures in a photonic integrated circuit according to certain embodiments. Although Figure 5 Operations are described in a sequential flow, but some of these operations may be performed in parallel or simultaneously. Some operations may be performed in a different order. An operation may have additional steps not included in the figures. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with another operation.

[0060] Optionally, at block 510, a waveguide layer can be formed on the barrier oxide layer of the PIC, for example... Figure 4A and Figure 4B The BOX layer 420 shown is illustrated. The waveguide layer can be patterned and etched using techniques such as photolithography to form the waveguide core and / or input / output couplers. At box 520, a photoactive layer (e.g., a niobium-germanium layer) can be deposited on top of the waveguide layer. The photoactive layer can be patterned and etched to form nanowires in a region of the waveguide core. The processing at boxes 510 and 520 can be part of a front-end process in a CMOS process.

[0061] Figure 6This is a cross-sectional view of an example of a photonic integrated circuit 600 according to certain embodiments, which includes photodetectors fabricated using front-end processes at frames 510 and 520. The PIC 600 may include a substrate 610 (e.g., a silicon-processed wafer), a BOX layer 620 formed on the substrate 610, various devices on a device layer (e.g., an optical input / output coupler 640, a waveguide 650, and a photodetector including a waveguide 660 and a nanowire 670 containing photoactive material), and an oxide layer 630 covering the device layer. The optical input / output coupler 640 may include a grating coupler. The oxide layer 630 and the BOX layer 620 may serve as cladding for the waveguide 650. In one example, the oxide layer 630 may have a thickness of approximately 1 μm.

[0062] At frame 530, vias or trenches can be etched down into the substrate in the oxide layer. For example, a patterned mask layer can be formed on the oxide layer (e.g., LTO layer and BOX layer), and vias (holes) or trenches can be etched in the oxide layer using wet or dry etching techniques. These oxide layers can have a total thickness of, for example, 3 μm to 4 μm.

[0063] Figure 7 This is a cross-sectional view of an example photonic integrated circuit 700 according to certain embodiments, which has vias or trenches 710 etched in an oxide layer at frame 530 using a back-end of line (BEOL) process. The PIC 700 may be fabricated from a PIC 600. The vias or trenches 710 may be etched down through the oxide layer 630 and the BOX layer 620 to the substrate 610.

[0064] At frame 540, the via or trench can be filled with a reflective or absorbing material, such as a metallic material. For example, a metallic layer can be deposited on an oxide layer and selectively etched in one or more cycles to form a metal plug in the via or trench.

[0065] Figure 8 This is a cross-sectional view of an example photonic integrated circuit 800 according to certain embodiments, the photonic integrated circuit 800 having vias or trenches etched in an oxide layer at frame 540 using a BEOL process and filled with a reflective or absorbing material (e.g., a metal such as copper, aluminum, cobalt, tungsten, etc.). The PIC 800 may be made from a PIC 700, wherein the vias or trenches 710 may be filled with metal plugs 810.

[0066] At frame 550, a metal layer 1 can be deposited on the oxide layer using standard CMOS BEOL processing techniques, and the metal layer 1 can be etched to leave a top metal cap in a region at the top of the photodetector. This top metal cap can be aligned with a via or trench filled with a reflective or absorbing material (e.g., metal). Therefore, the top metal cap and the via or trench can block background light from at least three (e.g., top, left, and right) or five (e.g., top, left, right, front, and rear) directions.

[0067] Figure 9 This is a cross-sectional view of an example photonic integrated circuit 900 according to certain embodiments, having a top metal cap 910 fabricated as part of a metal layer at frame 550 using a BEOL process for local isolation of a photodetector. The PIC 900 may be fabricated from a PIC 800 and may include an additional top metal cap 910 formed as part of a metal layer. The top metal cap 910 may be located above (e.g., on top of) a photodetector including a waveguide 660 and nanowires 670. The top metal cap 910 may contact a metal plug 810 in a via or trench 710 to block light from the top, left, and right directions in the 2-D cross-sectional view.

[0068] Optionally, at block 560, other BEOL processes can be performed to form, for example, an additional dielectric (e.g., oxide) layer and an upper metal layer (e.g., metal 2, metal 3, etc.). The BEOL process may include a standard CMOS BEOL process.

[0069] Figure 10 This is a cross-sectional view of an example photonic integrated circuit 1000 after an additional BEOL process at block 560 according to certain embodiments. PIC 1000 may be fabricated from PIC 900 and may include an additional metal layer 1010 and an upper metal layer, such as metal layer 1020.

[0070] At frame 570, the substrate can be etched from the back side to form a deep trench in the substrate. The deep trench can reflect photons propagating within the substrate at the interface between the substrate material and the air gap. For example, total internal reflection may occur when photons are incident at an angle at the interface between the substrate material and the air gap.

[0071] Figure 11This is a cross-sectional view of an example of a photonic integrated circuit 1100 according to certain embodiments, which includes a deep trench 1110 etched in the substrate of the photonic integrated circuit at frame 570 using a BEOL process. The PIC 1100 may be fabricated from a PIC 1000 and may include the deep trench 1110 in a substrate 610. The deep trench 1110 may be offset from the metal plug 810. For example, the deep trench 1110 may be slightly further away from the photodetector than the metal plug 810 to prevent light from bypassing the metal plug 810 from the bottom side of the substrate 610 and the BOX layer 620 and reaching the photodetector.

[0072] Optionally, at frame 580, the deep trench may be filled with a reflective or absorbing material that can block light, such as a metallic material.

[0073] Figure 12 This is a cross-sectional view of an example of a photonic integrated circuit 1200 according to certain embodiments, the photonic integrated circuit 1200 including a deep trench in a substrate filled with a reflective or absorbing material using a process at frame 580. PIC 1200 may be fabricated from PIC 1100 and may include a reflective or absorbing material 1210, such as a metallic material, filled in the deep trench 1110.

[0074] Figure 13 This is a cross-sectional view of a photonic integrated circuit 1200 according to certain embodiments, illustrating optical isolation implemented in the photonic integrated circuit by various isolation structures. Light from a laser can be transmitted to the PIC 1200 via an input fiber 1310, which may include a collimator, such as a GRIN lens or a microlens. Input light 1320 from the input fiber 1310 can propagate through an oxide layer and can be partially coupled into a waveguide within the PIC 1200 via an optical input / output coupler 640, which in some embodiments may include a tilting grating.

[0075] Light not coupled into the waveguide by the optical input / output coupler 640 can be scattered in various directions. For example, a portion of the input light 1320 can be reflected as light 1330 at the interface between the substrate 610 and the BOX layer 620. Light 1330 can be further reflected as light 1370 by the metal layer 1020, and light 1370 can be blocked by one of the metal plugs 810. A portion of the input light 1320 can be scattered as light 1335, which can propagate toward and be blocked by the metal plug 810. A portion of the input light 1320 can be scattered at the bottom surface of the substrate 610, where a portion of the scattered light 1350 can be blocked by the reflective or absorptive material 1210 in the deep trench 1110, while another portion of the scattered light 1340 can be blocked by the metal plug 810.

[0076] Light 1360 scattered from waveguide 650 or otherwise leaking may also be blocked by metal plug 810 and unable to reach the photodetector. Ambient light 1380 that may enter the oxide layer from the top or stray light reflected by various metal layers may also be blocked by the top metal cap 910 on top of the photodetector and therefore may also be unable to reach the photodetector. In this way, only photons guided in waveguide 660 can reach the photodetector, thus significantly reducing or essentially eliminating background noise. Thus, the photodetector can achieve high sensitivity and high SNR.

[0077] In various embodiments, other dielectric layers used in CMOS processing can be used to replace one or more of the oxide layers (e.g., silicon dioxide layers). For example, the dielectric layer may include silicon nitride, alkali metal halide, barium titanate, lead titanate, tantalum oxide, tungsten oxide, zirconium oxide, etc.

[0078] The aforementioned high-sensitivity photodetectors can be used to detect individual photons in quantum computing or quantum cryptography. For example, single-photon sources can be used in many photonic quantum technologies. An ideal single-photon source would deterministically produce single photons. One way to achieve a deterministic single-photon source is to employ cascaded (or multiplexed) predictor photon sources based on, for example, spontaneous four-wave mixing (SFWM) or spontaneous parametric down-conversion (SPDC) in a passive nonlinear optical medium. In each predictor photon source (HPS), photons can be produced nondeterministically in pairs (including signal photons and idler photons), where one photon (e.g., the signal photon) predicts the presence of the other photon in the pair (e.g., the idler photon). Therefore, if a high-sensitivity photodetector (e.g., a single-photon detector as described above) detects a signal photon at a predictor photon source, the corresponding idler photon can be used as the output of that single-photon source, while bypassing or shutting down other predictor photon sources in the cascaded (or multiplexed) predictor photon sources of that single-photon source.

[0079] Figure 14 This is a flowchart 1400 illustrating an exemplary method for fabricating a photonic integrated circuit according to certain embodiments. More specifically, Figure 14An example of an integration process for forming thermally isolated structures, light-scattering reduction structures, photodetectors, and metal contacts on and within a basic photonic integrated circuit (PIC) is shown. Other combinations of elements may be possible without departing from the scope of this disclosure. For example, the method may exclude steps for forming thermally isolated structures or other structures (e.g., additional photonic structures formed in one or more additional photonic layers).

[0080] In step 1401, a base PIC is provided. This base PIC can be any integrated circuit structure, and therefore the examples shown herein are not intended to limit the scope of this disclosure. In some embodiments, the base PIC can be provided as the output of any preprocessing step sequence, such as silicon photonics processing steps for processing silicon-on-insulator (SOI) wafers.

[0081] Figure 15 An example of a basic PIC that can be provided in step 1401 is shown. The basic PIC may include a PIC stack 1501. The PIC stack 1501 includes a multilayer photonic integrated circuit stack including a substrate 1524 (e.g., a silicon-processed wafer), a first oxide layer 1520, a waveguide layer 1521, and a spacer / protective cap layer 1522. In some embodiments, a second oxide layer 1518 may be disposed between the waveguide layer 1521 and the spacer / protective cap layer 1522. The waveguide layer 1521 may be patterned to include various photonic components, including one or more input coupler regions 1503, waveguide regions 1505, heater regions 1507, thermal isolation trench regions 1509, photonic switch regions 1511, photonic detector regions 1513, photonic detector contact regions 1515, and / or scattering reduction structure regions 1517. It will be understood by those skilled in the art that the number, order, and location of the various regions and components shown herein are merely illustrative and any arrangement is possible without departing from the scope of this disclosure.

[0082] In some embodiments, the input coupler region 1503 may include one or more photonic input / output structures of any type, such as a grating coupler 1519. The photonic input / output structure may be pre-formed in the waveguide layer 1521, for example, in a Si layer, a SiN layer, or any other material suitable for integrated photonics. The waveguide region 1505 may include one or more waveguides 1523, which may be part of one or more photonic structures and / or photonic components. For example, within the waveguide layer 1521, the waveguide structure may be used to form input / output structures (e.g., grating couplers), optical routing structures (e.g., straight waveguides and waveguide bends), light generation structures (e.g., coupled microring photonic sources), switching structures (e.g., Mach-Zehnder interferometers (MZI)), coupling structures (e.g., directional couplers), optical filters (e.g., wavelength division multiplexed (WDM) wavelength filters), photonic delay line structures, etc.

[0083] exist Figure 15 In the example shown, the structures within the waveguide layer are arranged schematically to illustrate the manufacturing process. Those skilled in the art will understand that the precise arrangement of components (and the interconnections between them) can vary greatly depending on the application the PIC design is intended for. Thus, the waveguide layer 1521 shown is intended to represent any possible combination of photonic components that can be designed using one or more waveguides as building blocks.

[0084] Heater region 1507 may also be part of one or more optical components (e.g., filters, microrings, and MZI (not shown)) and may be used to thermally tune these structures. In some embodiments, heater 1525 (e.g., a strip heater) may be located in heater region 1507. In some embodiments, heater 1525 may be formed in waveguide layer 1521 and may include a doped silicon (n-type or p-type doped silicon) layer 1525a and a cap layer 1525b formed of a silicide such as cobalt silicide, nickel silicide, or any other silicide. Although in Figure 15 The heater region 1507 is shown adjacent to waveguide 1523, but other embodiments may employ silicide and / or metal heaters fabricated on top of waveguide 1523, and may employ doped Si, a metal material such as TiN or TaN, or any other suitable heater material having a silicide top layer.

[0085] In some embodiments, the thermal isolation trench region 1509 is adjacent to the heater region 1507, such that trenches and undercuts (not shown) can be formed in the silicon oxide and silicon regions in subsequent processes to achieve thermal isolation around the heater 1525, as described below. Figure 19 and Figure 20 More specifically, this trench and undercut not only allows the heater 1525 to operate with higher power efficiency (by reducing heating of adjacent oxide layers and the substrate), but also provides thermal isolation between the region in the PIC that includes the heater 1525 (which may have a local temperature of 150K to 200K) and the region in the PIC that includes the photon detector (which may be at ultra-low temperatures, such as having a local temperature of 3K to 20K (e.g., 4K, 10K, etc.)). In some embodiments, a plurality of heaters may be used to tune a plurality of photonic components (e.g., single-photon sources, filters, MZI, etc.) located very close to each other, and the thermally isolated region can prevent crosstalk between component heating, such that a heater used to heat a corresponding component can heat only the adjacent component to a minimum due to the thermal isolation characteristics of the thermal isolation structure formed in the thermally isolated region. In some embodiments, thermal tuning may not be necessary, and therefore heaters and heater regions may be absent.

[0086] In some embodiments, the photonic switching region 1511 includes any suitable photonic switch 1527, such as a pn switch, pin switch, DC Kerr switch, Pockels effect switch, or any other type of optical switch.

[0087] In some embodiments, the photon detector region 1513 and the photon detector contact region 1515 can employ any waveguide-integrated photon detection technology. For example, a superconducting nanowire single-photon detector 1529 is shown here in cross-sectional form. The photon detector region 1513 and the photon detector contact region 1515 may include, for example, an AlN layer 1530, an NbN layer 1532, an amorphous silicon layer 1534, and a silicon oxide layer 1536. Details of the photon detector region 1513 and the photon detector contact region 1515 are described below.

[0088] Surrounding the photon detector region 1513 may be a scattering reduction structure region 1517, which may include one or more scattering reduction structures (not shown) fabricated therein, such as those described above. Figures 1 to 13 The scattering reduction structure is described.

[0089] According to some embodiments, the basic PIC can be Figure 15 The spacer / protective cap layer 1522 (e.g., a SiN layer) shown is covered. The spacer / protective cap layer 1522 may be pre-conformally deposited on top of the base PIC wafer. In other embodiments, without departing from the scope of this disclosure, the base PIC may include a planarized cap layer or any other layer.

[0090] See you again Figure 14In step 1403, a basic PIC is fabricated for the first photolithography process. Although the photolithography process mentioned herein employs three-layer photolithography, any photolithography technique may be used without departing from the scope of this disclosure. Figure 16 Examples of additional layers that can be deposited in a three-layer photolithography process are shown. For example, a planarization layer 1603 can be deposited on a pre-formed spacer layer (e.g., spacer / protective cap layer 1522). Examples of planarization layer 1603 include organic planarization layers, such as spin-on hard masks (SOH), organic planarizing layers (OPL), or any other layer or material that can be used to planarize the top top profile of the underlying PIC. An anti-reflective coating 1605 can be deposited on top of the planarization layer. Examples of anti-reflective coating 1605 include silicon-based anti-reflective coatings (SiARC), bottom anti-reflective coatings (BARC), etc. A photoresist layer 1607 is deposited on top of the anti-reflective coating 1605, which can be photolithographically patterned according to known methods. Figure 16 In the example shown, the photoresist layer 1607 is patterned to protect certain portions of the spacer layer (e.g., a nitride layer) located on top of the contact areas of the heater, switch, and photon detector, as shown. Figure 16 As shown in the image.

[0091] In step 1405, a first etching process is performed to pattern the spacer / protective cap layer 1522 (e.g., a nitride layer). For example, the anti-reflective coating 1605 and the planarization layer 1603 are etched in areas that do not contain photoresist (acting as an etching mask), resulting in... Figure 17 The etched PIC structure 1701 shown has spacers / caps 1705 (e.g., silicon nitride) retained on top of the heater contact region, switch contact region, and photon detector contact region. More generally, photoresist can be photolithographically patterned in any manner that preserves islands of the SiN layer. These islands can be used, for example, as etch terminations in subsequent contact formation etching processes.

[0092] In step 1407, an oxide deposition process (e.g., using middle-of-the-line (MOL) SiO2 deposition) is performed to form an oxide layer 1803 on the etched PIC, such as... Figure 18 As shown in the image.

[0093] In step 1409, a patterned base PIC is fabricated for a second photolithography process. In this process, as in step 1403, another layer of photoresist is deposited and photolithographically patterned.

[0094] In step 1411, a second etching process is performed to create a deep trench 1903 in the thermal isolation region (e.g., thermal isolation trench region 1509), such as Figure 19 As shown herein, the deep trench 1903, referred to herein as a "deep trench," is a trench in the PIC stack that can extend all the way to the substrate 1524. Any suitable etching process can be used to etch the deep trench. Etching processes such as oxide etching processes can be used without departing from the scope of this disclosure. In some embodiments, etching can be selective etching that etches the oxide but not the Si substrate. The etching process can be an anisotropic etching process that etches the deep trench 1903.

[0095] In step 1413, at the bottom of the deep trench 1903, an undercut 2003 is etched in the substrate 1524, as shown. Figure 20 As shown in the diagram. This undercut can be formed using a combination of dry and wet etching processes. Dry etching can be sulfur hexafluoride, chlorine etching, or any other dry etching process, which is a selective etching that etches silicon but not the oxide layer, such that only the silicon at the bottom of the deep trench 1903 is etched, while the overlying oxide layer is retained. Wet etching can then be performed using, for example, tetramethylammonium hydroxide (TMAH), KOH, or any other suitable etchant. In some embodiments, the silicon etching is performed along the 111 crystal plane (e.g., at approximately 54 degrees). This etching results in the undercut 2003 having angled walls due to the silicon etching.

[0096] Figure 21 An example of a heater 2103 and a full undercut structure 2105 according to some embodiments is shown. The full undercut structure 2105 may be... Figure 20 The example shown is a cut in 2003, and the above can be adopted regarding Figure 20 The described etching process is used to form the structure. In some embodiments, the undercut structure 2105 may be located beneath any photonic device 2109 employing a heater. Thermal isolation from the deep trench and the undercut structure 2105 can reduce or prevent heat loss to the surrounding substrate 2107. Examples of photonic devices 2109 include single-photon sources, optical filters, Mach-Zehnder interferometers, microring resonators, or any other structure that can employ thermal tuning and / or switching. Figure 21An example is shown where two deep trenches 2105a and 2105b are formed on the respective sides of the waveguide and heater, respectively, to thermally insulate the heater element from the surrounding area, including the substrate (referred to herein as the silicon processing wafer) and the oxide layer. In some embodiments, the cooling member may be in thermal contact with the substrate to provide a heat sink for the PIC during operation. For circuits operating at cryogenic temperatures, the cooling member may be part of a larger cryostat for cryogenic cooling. In these cases, without a thermal undercut structure between the heater and the cooling structure, a significant amount of heat generated by the heater may be directly diverted to the cooling structure, negatively impacting the heating efficiency of the heater and / or unnecessarily increasing the thermal load on the cryogenic cooling system.

[0097] In step 1415, as Figure 22 As shown, an oxide layer 2210 is deposited on a PIC stack, which includes deep trenches and undercuts formed therein for thermal insulation. The oxide layer 2210 can be planarized, for example, by chemical mechanical polishing (CMP). In some embodiments, the oxide layer 2210 is deposited without disrupting the vacuum, thereby sealing the deep trench undercut regions so that these regions remain sealed under vacuum. By keeping the deep trenches and undercut regions under vacuum, the thermal insulation capability of the deep trench undercut structure can be improved by eliminating the most efficient heat transfer mechanisms within the voids. For example, heat transfer through the deep trenches is primarily radiative, minimizing more efficient processes such as diffusion and convection.

[0098] In step 1417, a patterned photoresist layer 2301 can be formed on the PIC stack for the third photolithography process, such as... Figure 23 As shown in the diagram. In this process, as in step 1403, another layer of photoresist is deposited and photolithographically patterned. For example, a patterned photoresist layer 2301 can be formed on the planarization layer 2305 and the anti-reflective coating 2303. In this case, patterning is performed to form an etch mask for etching silicide contact holes.

[0099] In step 1419, an oxide etching process can be performed to etch the oxide layer 2210, followed by a SiN stamping process to etch the spacer / cap 1705, thereby forming a silicide contact hole 2401 for contacting the silicide layer (e.g., cap layer 1525b), as shown. Figure 24 As shown in the image.

[0100] In step 1421, the photolithography preparation, photolithography, and etching processes are performed in a manner similar to that described above. For example, as... Figure 25As shown, a patterned photoresist layer 2501 can be formed on the planarization layer 2505 and the anti-reflective coating 2503. In this case, the photoresist layer 2501 is patterned to allow etching of the photon detector contact holes, terminating at a suitable layer of the photon detector (e.g., an amorphous silicon layer). Figure 26 As shown, the planarization layer 2505 (e.g., SOH or OPL layer) can be removed to open the silicide contact hole 2401 and the photon detector contact hole 2601.

[0101] In step 1423, metal silicide contacts 2701 are formed, such as Figure 27 As shown in the diagram. For example, an inner liner layer 2703 may first be deposited in the contact holes (e.g., silicide contact hole 2401 and photon detector contact hole 2601). In some embodiments, the inner liner layer 2703 may be formed of tungsten, tungsten carbide, tungsten nitride, or any other suitable liner. After the inner liner layer is deposited, an annealing step may be performed to form a silicide region 2705, such as an amorphous silicon layer 1534, at the bottom of the metal silicide contact 2701 for the detector contact. After the silicide formation, a metallization process is performed to fill the contact holes with a suitable contact metal 2707 (e.g., tungsten, copper, aluminum, cobalt, etc.). In some embodiments, a cleaning step may be performed to clean the amorphous silicon prior to silicide formation. Any suitable cleaning step may be used, such as a chemical cleaning step, argon sputtering, etc.

[0102] In step 1425, a scattering reduction structure 2801 is formed using photolithography and etching processes, such as... Figure 28 As shown in the figure. In some embodiments, the scattering reduction structure 2801 may be formed in a deep trench located on the substrate 1524. In other embodiments, the scattering reduction structure 2801 may be formed in a trench similar to a through-silicon via (TSV), such as... Figure 28 As shown in the diagram. After etching the trench, an oxide liner 2803 is formed to prevent the filler material (which subsequently fills the scattering reduction structure 2801) from reacting with the silicon. Then, before filling the scattering reduction structure with a filler material 2807 (e.g., a metal such as copper), a metal liner layer 2805, such as a Ti-Cu barrier and seed layer, can be formed on the oxide liner 2803. The filler material 2807 can have a coefficient of thermal expansion (CTE) similar to that of the substrate 1524 and / or the oxide. In some embodiments, the TSV-like scattering reduction structure can be approximately 10 micrometers deep, for example, 40 to 60 micrometers deep, thus much deeper than the thermal isolation trench, which can be up to 10 times shallower.

[0103] It will be apparent to those skilled in the art that substantial variations can be made according to specific embodiments. For example, custom hardware may also be used and / or specific elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connectivity to other computing devices, such as network input / output devices, may be employed.

[0104] Referring to the accompanying drawings, components that may include memory may include non-transitory machine-readable media. As used herein, the terms "machine-readable media" and "computer-readable media" refer to any storage medium that participates in providing data that enables a machine to function in a particular manner. In the embodiments provided above, various machine-readable media may involve providing instructions / code to a processor and / or other devices for execution. Additionally or alternatively, machine-readable media may be used to store and / or carry these instructions / code. In many embodiments, computer-readable media are physical and / or tangible storage media. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punched cards, paper tape, any other physical media with a perforated pattern, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash erasable programmable read-only memory (FLASH-EPROM), any other memory chip or cassette memory, carrier waves as described below, or any other medium from which a computer can read instructions and / or code.

[0105] The methods, systems, and devices discussed herein are examples. Various processes or components may be appropriately omitted, substituted, or added in various embodiments. For example, features described with respect to certain embodiments may be incorporated into various other embodiments. Different aspects and elements of embodiments may be combined in a similar manner. The various components in the accompanying drawings provided herein may be implemented in hardware and / or software. Furthermore, technology is evolving, and therefore many elements are examples and are not intended to limit the scope of this disclosure to those specific examples.

[0106] Primarily for general reasons, referring to these signals as bits, information, values, elements, symbols, characters, variables, terms, numbers, numerals, etc., sometimes proves convenient. However, it should be understood that all such terms, or similar terms, are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise specified, as is apparent from the foregoing discussion, it should be understood that throughout the discussion in this specification, the use of terms such as “processing,” “calculating with a computer,” “calculating,” “determining,” “identifying,” “associating,” “measuring,” “executing,” etc., refers to the actions or processes of a specific device, such as a dedicated computer or similar dedicated electronic computing device. Therefore, in the context of this specification, a dedicated computer or similar dedicated electronic computing device is capable of manipulating or converting signals (generally referred to as physical electronic, electrical, or magnetic quantities within the memory, registers, or other information storage devices, transmission devices, or display devices of the dedicated computer or similar dedicated electronic computing device).

[0107] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals used to transmit the messages described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned in all the foregoing descriptions can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0108] The terms “and,” “or,” and “and / or” as used herein can have a variety of meanings, which are expected to depend at least in part on the context in which they are used. Generally, if “or” is used to relate a list (e.g., A, B, or C), then “or” is intended to mean A, B, and C (this is used in the sense of inclusion) and A, B, or C (this is used in the open-ended sense). Furthermore, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular form, or can be used to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Additionally, if the term “at least one” is used to relate a list (e.g., A, B, or C), then “at least one” can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0109] Throughout the specification, references to “an example,” “example,” “some examples,” or “exemplary implementation” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrases “in one example,” “example,” “some examples,” “some implementations,” or other similar phrases throughout the specification does not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0110] In some implementations, operation or processing may involve the physical manipulation of physical quantities. Typically, but not necessarily, these quantities may take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or otherwise manipulated. It is sometimes convenient to refer to these signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, etc., primarily for general reasons. However, it should be understood that all such terms or similar terms are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise specifically stated, as will be apparent from the discussion herein, it should be understood that throughout the discussion in this specification, the use of terms such as “processing,” “calculating with a computer,” “calculating,” “determining,” etc., refers to the action or process of a specific device such as a dedicated computer, dedicated computing device, or similar dedicated electronic computing apparatus. Therefore, in the context of this specification, a dedicated computer or similar dedicated electronic computing apparatus is capable of manipulating or converting signals (generally referred to as physical electronic or magnetic quantities within the memory, registers, or other information storage devices, transmission devices, or display devices of a dedicated computer or similar dedicated electronic computing apparatus).

[0111] In the foregoing detailed description, numerous specific details have been set forth to provide a comprehensive understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those skilled in the art have not been described in detail so as not to obscure the claimed subject matter. Therefore, the claimed subject matter is intended to be limited to the specific examples disclosed, but may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A device comprising: Substrate; A dielectric layer is located on the substrate; The waveguide is located within the dielectric layer; A heater is disposed in the dielectric layer; A thermally insulating structure, comprising trenches in the dielectric layer and undercuts in the substrate; as well as A photodetector is disposed above the waveguide and monolithically integrated with the substrate, the photodetector being optically coupled to the waveguide and configured to operate at temperatures below 50 K.

2. The device according to claim 1, wherein, The heater is located near the waveguide and is configured to thermally tune part of the waveguide.

3. The device according to claim 2, wherein, The waveguide and the heater are components of a single-photon generator, a ring oscillator, an optical filter, an optical switch, or an optical interferometer.

4. The device according to claim 2, wherein, The thermal insulation structure surrounds the heater.

5. The device of claim 4, wherein the undercut extends horizontally in the substrate and is located below the portion of the waveguide.

6. The device of claim 4, wherein the trench and the undercut form a vacuum region.

7. The device according to claim 4, further comprising: A cooling structure is configured to be in thermal contact with the substrate, wherein the undercut is disposed between the heater and the cooling structure.

8. The device according to claim 1, further comprising: Multiple optical isolation structures are located in at least one of the substrate or the dielectric layer, the multiple optical isolation structures being configured to prevent photons from reaching the photodetector without passing through the waveguide.

9. The device of claim 8, wherein the plurality of optical isolation structures comprises at least one of the following: A metal trench located in the dielectric layer and partially extending into the substrate; Metal trenches located in the dielectric layer; An array of metal vias located in the dielectric layer; A metal cap located within the dielectric layer and on top of the photodetector; or A deep trench in the substrate, the deep trench including an air gap or filled with a reflective or absorbing material.

10. The device of claim 8, wherein the plurality of optically isolated structures include at least a metal cap located in the dielectric layer and on top of the photodetector, and a metal trench located at least in the dielectric layer; and The metal cap is aligned or coupled to the metal groove to form a continuous structure around the photodetector.

11. The device of claim 8, wherein the plurality of optically isolated structures at least include a metal cap located in the dielectric layer and on top of the photodetector, and an array of metal vias located in the dielectric layer; and The metal cap is aligned or coupled to the metal via array to form a continuous structure around the photodetector.

12. The device of claim 8, wherein the plurality of optically isolated structures at least include a metal cap located in the dielectric layer and on top of the photodetector; and The metal cap is located within a metal layer, which is situated on the dielectric layer.

13. The device according to claim 9, wherein: The waveguide includes an input port; and The metal trench or the metal via array is located in the region including the input port.

14. The device of claim 1, wherein the photodetector comprises a superconducting nanowire single-photon detector.

15. The device of claim 1, wherein the dielectric layer comprises an oxide layer.

16. A method comprising: Receiving chip, the chip comprising: Substrate; A dielectric layer is located on the substrate; Waveguides are formed in the dielectric layer; A heating structure is disposed in the dielectric layer; and A photodetector is located in the dielectric layer and coupled to the waveguide; A first set of vias or a first trench is etched in the dielectric layer to expose a first portion of the substrate, the first set of vias or the first trench surrounding the photodetector; The substrate is etched through the first set of vias or the first trench to form a second set of vias or a second trench in the substrate; and The first set of vias or the first trench and the second set of vias or the second trench are filled with light-reflecting or light-absorbing materials.

17. The method according to claim 16, wherein, The heating structure is constructed to thermally tune part of the waveguide.

18. The method of claim 17, further comprising: A third set of vias or a third trench is etched in the dielectric layer to expose a second portion of the substrate, the third set of vias or the third trench surrounding the heating structure; The substrate is etched through the third set of vias or the third trench to form an undercut in the substrate, the undercut being located below the second portion of the substrate; as well as An oxide layer is deposited on the dielectric layer to seal the third set of vias or the third trench and the undercut.

19. The method of claim 17, further comprising: The dielectric layer is etched to form contact holes for the heating structure; as well as The contact hole is filled with a conductive material to form an electrical contact for the heating structure.

20. The method of claim 16, further comprising: Prior to the filling, an oxide liner is formed in the second set of vias or the second trench.

21. The method of claim 20, further comprising: Barriers and seed layers are deposited on the oxide liner.

22. The method of claim 16, further comprising: A top metal cap is formed on the dielectric layer and on top of the photodetector.

23. The method according to claim 22, wherein, The top metal cover is located within a metal layer, which is situated on the dielectric layer.

24. The method of claim 16, further comprising: The dielectric layer is etched to form contact holes for the photodetector; as well as The contact hole is filled with a conductive material to form an electrical contact for the photodetector.

25. The method according to claim 24, wherein, Filling the contact hole includes depositing an inner liner layer on the sidewall of the contact hole.

26. The method of claim 25, wherein, The inner lining layer comprises tungsten, tungsten carbide, or tungsten nitride.

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