Selectively write back dirty cache lines while processing

Abstract

The present invention relates to a graphics pipeline (200) comprising a cache (207, 305) having cache lines (310 to 313) configured to store data used to process frames in the graphics pipeline. The graphics pipeline is implemented using a processor (115) that processes frames for the graphics pipeline using the data stored in the cache. The processor processes a first frame and writes dirty cache lines from the cache back to a memory (105) while processing the first frame. The dirty cache lines remain in the cache and are marked as clean after being written back to the memory. In some cases, the processor generates a hint (335) indicating a priority for writing back the dirty cache lines based on a read command occupancy at a system memory controller.

Description

Background Art

[0001] The processing system including the graphics processing unit (GPU) implements a cache hierarchy (or multi-level cache) that uses a cache hierarchy of different speeds to store frequently accessed data. Data requested more frequently is usually cached in a relatively high-speed cache (such as an L1 cache) that is physically (or logically) closer to the processor core or computing unit deployment. Higher-level caches (such as L2 caches, L3 caches, etc.) store less frequently requested data. The last level cache (LLC) is the highest level (and lowest access speed) cache, and LLC reads data directly from the system memory and writes data directly to the system memory. Caches are different from memories because they implement a cache replacement strategy to replace the data in the cache line in response to the need to write new data to the cache line. For example, the least recently used (LRU) strategy replaces the data in the cache line that has not been accessed in the longest time interval by expelling the data in the LRU cache line and writing new data to the LRU cache line. The GPU processes data frame by frame, for example, the graphics pipeline in the GPU renders one frame at a time. Therefore, the cache hierarchy used to cache data for the graphics pipeline evicts dirty data from the cache at the end of one frame and before the start of a subsequent frame. Evicting dirty data requires writing dirty cache lines back to the system memory, which consumes a lot of bandwidth and causes bottlenecks in the traffic between the cache hierarchy and the system memory. Since the bandwidth for reading new data into clean cache lines and writing dirty cache lines back to the system memory is limited, these bottlenecks have a significant impact on the performance of the GPU at the start of subsequent frames. Summary of the invention

[0002] According to some embodiments, a device includes a cache including cache lines configured to store data used to process frames in a graphics pipeline. The device also includes a processor implementing the graphics pipeline, wherein the processor is configured to process a first frame and write dirty cache lines from the cache back to a memory while processing the first frame, wherein the data in the dirty cache lines remains in the cache and is marked as clean after being written back to the memory. The apparatus may also have one or any combination of the following aspects: the processor is configured to selectively write dirty cache lines back to memory based on a read command occupancy at a system memory controller (SMC); the processor is configured to transmit data in the dirty cache lines to the SMC in response to the read command occupancy being less than a first threshold, wherein the SMC is configured to write data received from the processor back to memory; the processor is configured to transmit the data in the dirty cache lines to the SMC with a hint indicating that writing the data back to memory is a low priority in response to the read command occupancy being greater than the first threshold and less than a second threshold; the SMC is configured to provide pending read requests before writing the data back to memory in response to receiving the hint; the processor is configured to bypass transmitting the data in the dirty cache lines to the SMC in response to the read command occupancy being greater than the second threshold. The apparatus may further include one or any combination of the following aspects: the processor is configured to bypass writing dirty cache lines back to memory during a transition from a first frame to a second frame in response to the dirty cache lines being marked as clean; and the processor is configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of the second frame.

[0003] According to some embodiments, a method includes processing a first frame in a graphics pipeline using data stored in a cache line of a cache associated with the graphics pipeline. The method also includes writing a dirty cache line from the cache back to a memory while processing the first frame, and retaining the data in the dirty cache line in the cache. The method also includes marking the dirty cache line as clean after the dirty cache line is written back to the memory. The method may also have one or any combination of the following aspects: wherein writing back the dirty cache line includes selectively writing the dirty cache line back to the memory based on a read command occupancy at a system memory controller (SMC); wherein writing back the dirty cache line includes transmitting the data in the dirty cache line to the SMC in response to the read command occupancy being less than a first threshold; the method also includes writing back the data received from the SMC to the memory; writing back the dirty cache line includes writing back the data in the dirty cache line to the SMC in response to the read command occupancy being greater than a first threshold and less than a second threshold to indicate that writing the data back to the memory is a low priority. The method further comprises providing a pending read request at the SMC before writing the data back to the memory in response to receiving the hint; wherein selectively writing the dirty cache line back to the memory comprises bypassing transmitting the data in the dirty cache line to the SMC in response to the read command occupancy being greater than a second threshold; the method further comprises bypassing writing the dirty cache line back to the memory during a transition from a first frame to a second frame in response to the dirty cache line being marked as clean; or the method further comprises writing back the data in the dirty cache line that is not marked as clean in response to completing processing of the first frame and initiating processing of the second frame.

[0004] According to some embodiments, a device includes a group of computing units configured to implement a graphics pipeline, and also includes a last level cache (LLC) in a cache hierarchy associated with the group of computing units, wherein the computing unit is configured to write dirty cache lines from the LLC back to a memory while processing a first frame based on data stored in the dirty cache lines, and wherein the dirty cache lines are marked as clean after being written back to the memory. The device may also have one or any combination of the following aspects: the computing unit is configured to determine the priority of writing dirty cache lines from the LLC back to the memory based on a read command occupancy of a system memory controller (SMC); or the computing unit is configured to bypass writing dirty cache lines back to the memory during a transition from a first frame to a second frame in response to the dirty cache lines being marked as clean, and wherein the computing unit is configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of the second frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be better understood, and its numerous features and advantages will become apparent to those skilled in the art by referencing the accompanying drawings.The use of the same reference numbers in different drawings indicates similar or identical items.

[0006] Figure 1 is a block diagram of a processing system that selectively writes back dirty cache lines while processing, according to some embodiments.

[0007] Figure 2 Depicted is a graphics pipeline configured to process high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a predetermined resolution, according to some embodiments.

[0008] Figure 3 is a block diagram of a portion of a memory system according to some embodiments.

[0009] Figure 4 is a flow chart of a method of selectively writing back dirty cache lines while processing a frame using data in the cache, according to some embodiments. DETAILED DESCRIPTION

[0010] Figures 1 to 4 Disclosed are systems and techniques for reducing the available bandwidth bottleneck between the last level cache (LLC) and system memory during frame transitions in a graphics processing unit (GPU) by selectively writing back data in dirty cache lines of the LLC based on a read command occupancy rate indicating the number of pending read commands to the system memory. The data written back to the system memory is retained in dirty cache lines that are marked to indicate that the data in the marked cache lines have been written back to the system memory, so that, for example, during a transition from a first frame to a second frame, the marked cache lines can be considered clean cache lines. In some embodiments, the dirty cache lines are selectively written back to the system memory by comparing the read command occupancy rate to one or more thresholds. For example, if the read command occupancy rate is less than a first threshold, the data in the dirty cache lines is transmitted to a system memory controller (SMC) that writes the data back to the system memory. If the read command occupancy rate is greater than a second threshold (the second threshold is greater than the first threshold), a request to write the dirty cache lines back to the system memory is sent to the SMC with a hint indicating that writing the data back to the system memory is a low priority. Therefore, the SMC provides pending read requests before executing low priority writes to system memory.If the read command occupancy is greater than a third threshold (which is greater than the second threshold), a request to write the dirty cache line back to system memory is not transmitted to the SMC.

[0011] Figure 1is a block diagram of a processing system 100 that selectively generates write-back dirty cache lines while processing, according to some embodiments. The processing system 100 includes or has access to a memory 105 or other storage component implemented using a non-transitory computer-readable medium such as a dynamic random access memory (DRAM). However, in some cases, the memory 105 is implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. The memory 105 is referred to as external memory because it is implemented external to the processing units implemented in the processing system 100. The processing system 100 also includes a bus 110 to support communications between entities implemented in the processing system 100, such as the memory 105. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not clearly shown in the figure. Figure 1 Shown in.

[0012] In various embodiments, the techniques described herein are used with any of a variety of parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, etc.). Figure 1 An example of a parallel processor, in particular a graphics processing unit (GPU) 115, is shown according to some embodiments. The graphics processing unit (GPU) 115 renders an image for presentation on a display 120. For example, the GPU 115 renders an object to produce pixel values ​​that are provided to the display 120, which uses the pixel values ​​to display an image representing the rendered object. The GPU 115 implements multiple compute units (CUs) 121, 122, 123 (collectively referred to herein as "compute units 121 to 123") that execute instructions concurrently or in parallel. In some embodiments, the compute units 121 to 123 include one or more single instruction multiple data (SIMD) units and the compute units 121 to 123 are aggregated into workgroup processors, shader arrays, shader engines, etc. The number of compute units 121 to 123 implemented in the GPU 115 is a matter of design choice, and some embodiments of the GPU 115 include more than one CU. Figure 1 105. The GPU 115 may be used to execute instructions, such as program code 125 stored in memory 105, and store information, such as the results of the executed instructions, in memory 105.

[0013] The processing system 100 also includes a central processing unit (CPU) 130 connected to the bus 110, and thus communicates with the GPU 115 and the memory 105 via the bus 110. The CPU 130 implements a plurality of processor cores 131, 132, 133 (collectively referred to herein as "processor cores 131-133") that execute instructions concurrently or in parallel. The number of processor cores 131-133 implemented in the CPU 130 is a matter of design choice, and some embodiments include more than 100 processor cores 131-133. Figure 1 The processor cores 131-133 execute instructions (such as program code 135 stored in memory 105), and the CPU 130 stores information (such as the results of the executed instructions) in the memory 105. The CPU 130 can also initiate graphics processing by issuing draw calls to the GPU 115. Some embodiments of the CPU 130 implement multiple processor cores that execute instructions simultaneously or in parallel (for clarity Figure 1 not shown).

[0014] The input / output (I / O) engine 145 processes input or output operations associated with the display 120 and other elements of the processing system 100, such as a keyboard, a mouse, a printer, an external disk, etc. The I / O engine 145 is coupled to the bus 110 so that the I / O engine 145 communicates with the memory 105, the GPU 115, or the CPU 130. In the illustrated embodiment, the I / O engine 145 reads information stored on an external storage component 150, which is implemented using a non-transitory computer-readable medium, such as a compact disk (CD), a digital video disk (DVD), etc. The I / O engine 145 is also capable of writing information to the external storage component 150, such as a processing result of the GPU 115 or the CPU 130.

[0015] In the illustrated embodiment, the computing units 121 to 123 in the GPU 115 include (or are associated with) one or more caches 151, 152, 153, which are collectively referred to as "caches 151 to 153" herein. Caches 151 to 153 may include L1 caches, L2 caches, L3 caches, or other caches in a cache hierarchy. Portions of caches 151 to 153 are used to implement texture caches for graphics pipelines executed on computing units 121 to 123. In the illustrated embodiment, caches 151 to 153 are (or include) last level caches (LLCs), which are the highest level caches in the cache hierarchy. Therefore, data is read directly from memory 105 into caches 151 to 153, and data is read directly from caches 151 to 153 back into memory 105.

[0016] The processing system 100 also includes a system memory controller (SMC) 155 that receives memory access requests from entities in the processing system. The SMC 155 uses data stored in the memory 105 to provide the memory access requests. In the illustrated embodiment, the computing units 121 to 123 process frames in a graphics pipeline. The processing of the frame includes writing data to cache lines in one or more of the caches 151 to 153. Cache lines that include data written by the computing units 121 to 123 but not yet written back to the memory 105 are referred to as "dirty" cache lines. During transitions between frames processed by the computing units 121 to 123, dirty cache lines are evicted from the caches 151 to 153. Evicting the dirty cache lines includes writing the data in the dirty cache lines back to the memory 105. However, the bandwidth and processing power required to evict all dirty cache lines in the caches 151 to 153 can significantly reduce the bandwidth and processing power available to begin fetching data into the caches 151 to 153 and processing the data for a new frame.

[0017] To address this issue, the computing units 121 to 123 write one or more dirty cache lines from the caches 151 to 153 back to the memory 105 while processing the corresponding frame. The dirty cache lines that have been written back to the memory 105 are also retained in the caches 151 to 153 so that the data in the dirty cache lines are available for processing of the current frame. However, the dirty cache lines are marked as clean after being written back to the memory so that the dirty cache lines do not have to be written back to the memory during the transition between frames, thereby saving memory bandwidth and processing power during the transition. In some cases, the computing units 121 to 123 generate hints indicating the priority of writing back dirty cache lines based on the read command occupancy at the SMC 155.

[0018] Figure 2 A graphics pipeline 200 is depicted that is configured to process high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a predetermined resolution according to some embodiments. The graphics pipeline 200 is Figure 1 1 and 2. The graphics pipeline 200 is implemented in some embodiments of the processing system 100 shown. The illustrated embodiment of the graphics pipeline 200 is implemented according to the DX11 specification. Other embodiments of the graphics pipeline 200 are implemented according to other application programming interfaces (APIs) such as Vulkan, Metal, DX12, etc. The graphics pipeline 200 is subdivided into a geometry portion 201 including the portion of the graphics pipeline 200 before rasterization and a pixel processing portion 202 including the portion of the graphics pipeline 200 after rasterization.

[0019] Graphics pipeline 200 may access storage resources 205, such as a hierarchy of one or more memories or cache memories for implementing buffers and storing vertex data, texture data, etc. In the illustrated embodiment, storage resources 205 include local data storage (LDS) 206 circuits for storing data and cache 207 for caching frequently used data during rendering by graphics pipeline 200. Figure 1 Some embodiments of system memory 105 are shown to implement storage resource 205. As discussed herein, dirty cache lines in cache 207 are selectively written back to system memory while frames are processed using data in the dirty cache lines to save memory bandwidth in graphics pipeline 200.

[0020] Input assembler 210 accesses information from storage resource 205 that defines objects that represent parts of a model of a scene. Examples of primitives are shown in Figure 2 203 is shown as a triangle 211, but other types of primitives are processed in some embodiments of the graphics pipeline 200. A triangle 203 includes one or more vertices 212 connected by one or more edges 214 (for clarity, the edges are not shown in FIG. Figure 2 Only one of each edge is shown in FIG. 2 ). Vertex 212 is shaded during geometry processing portion 201 of graphics pipeline 200 .

[0021] In the illustrated embodiment, the vertex shader 215 implemented in software logically receives a single vertex 212 of a primitive as input and outputs a single vertex. Some embodiments of shaders such as vertex shader 215 implement large-scale single instruction multiple data (SIMD) processing, so that multiple vertices are processed simultaneously. Graphics pipeline 200 implements a unified shader model so that all shaders included in graphics pipeline 200 have the same execution platform on a shared large-scale SIMD computing unit. Therefore, the shaders including vertex shader 215 are therefore implemented using a common resource set referred to herein as unified shader pool 216.

[0022] The hull shader 218 operates on input high-order patches or control points used to define input patches. The hull shader 218 outputs a tessellation factor and other patch data. In some embodiments, the primitives generated by the hull shader 218 are provided to a tessellation device 220. The tessellation device 220 receives an object (such as a patch) from the hull shader 218 and generates information identifying primitives corresponding to the input object, for example, by tessellizing the input object based on a tessellation factor provided to the tessellation device 220 by the hull shader 218. Tessellation subdivides the input high-order primitives (such as patches) into a set of low-order output primitives that represent a finer level of detail, for example, as indicated by a tessellation factor that specifies the granularity of the primitives produced by the tessellation process. Thus, the model of the scene is represented by a smaller number of higher-order primitives (to save memory or bandwidth), and additional details are added by tessellizing the higher-order primitives.

[0023] The domain shader 224 inputs the domain position and (optionally) other patch data. The domain shader 224 operates on the information provided and generates a single vertex for output based on the input domain position and other information. In the illustrated embodiment, the domain shader 224 generates primitives 222 based on the triangles 211 and the tessellation factors. The geometry shader 226 receives the input primitives and outputs up to four primitives generated by the geometry shader 226 based on the input primitives. In the illustrated embodiment, the geometry shader 226 generates output primitives 228 based on the tessellated primitives 222.

[0024] A stream of primitives is provided to one or more scan converters 230, and in some embodiments, up to four streams of primitives are cascaded to a buffer in the storage resource 205. The scan converter 230 performs shading operations and other operations such as clipping, perspective division, shearing, and viewport selection. The scan converter 230 generates a set 232 of pixels that are subsequently processed in the pixel processing portion 202 of the graphics pipeline 200.

[0025] In the illustrated embodiment, pixel shader 234 inputs a pixel stream (eg, including pixel group 232 ) and outputs zero or another pixel stream in response to the input pixel stream. Output merge block 236 performs blending, depth, stencil, or other operations on pixels received from pixel shader 234 .

[0026] Some or all of the shaders in graphics pipeline 200 perform texture mapping using texture data stored in storage resources 205. For example, pixel shader 234 may read texture data from storage resources 205 and use the texture data to shade one or more pixels. The shaded pixels are then provided to a display for presentation to a user. As discussed herein, texture data used by the shaders in graphics pipeline 200 is cached using cache 207. Dirty cache lines in cache 207 are written back while frames in graphics pipeline 200 are being processed using data in cache 207.

[0027] Figure 3 is a block diagram of a portion of a memory system 300 according to some embodiments. The memory system 300 is Figure 1 The processing system 100 and Figure 2 3. The graphics pipeline 200 shown in FIG. 2 is implemented in some embodiments. The memory system 300 includes a cache 305, which includes cache lines 310, 311, 312, 313, which are collectively referred to herein as "cache lines 310 to 313". Data used by the graphics pipeline is extracted into one or more cache lines 310 to 313 using a read / write circuit 320 that sends a request 325 to the SMC 330. The SMC 330 provides the request 325 by obtaining the requested data from the corresponding memory and providing the requested data to the read / write circuit 320, which writes the requested data to one of the cache lines 310 to 313.

[0028] During the transition between frames being processed in the graphics pipeline, the read / write circuit 320 writes the data in the dirty cache lines 310 to 313 back to the memory via the SMC 330. The read / write circuit 320 also writes the data in some of the dirty cache lines 310 to 313 back to the memory via the SMC 330 while processing the frame using the data in the cache 305. The data in the dirty cache lines 310 to 313 is retained in the cache 305, and the dirty cache lines 310 to 313 are marked to indicate that the data has been written back. Therefore, the dirty cache lines 310 to 313 are regarded as clean cache lines that do not need to be written back to the memory during the transition between frames. In the illustrated embodiment, the cache 305 includes a state tag 335 associated with the cache lines 310 to 313. State marker 335 indicates that cache lines 310 and 313 are clean (i.e., the data in cache lines 310 and 313 has not been modified during processing and therefore corresponds to data currently stored at the associated addresses in memory), and that cache line 311 is dirty (i.e., the data in cache line 311 has been modified during processing but has not yet been written back to memory). State marker 335 also indicates that cache line 312 is in a clean / writeback (clean / WB) state, which indicates that cache line 312 is dirty, but the data in cache line 312 has been written back to memory, so it can be considered a clean cache line during frame conversion.

[0029] In some embodiments, the read / write circuit 320 includes a hint with the request 325 to indicate the priority associated with the request to write back data from the dirty cache line. The hint is determined based on the read command occupancy, that is, the occupancy of the queue or buffer in the SMC 330 that includes pending read commands that have not yet been provided by the SMC 330. If the read command occupancy is relatively low, the hint indicates that the request 325 to write data back to the memory from the dirty cache line should be provided as quickly as possible. However, if the read command occupancy is relatively high, the hint indicates that the request 325 has a relatively low priority. Therefore, the SMC 330 provides pending read commands (rather than low priority write requests 325) until the read command occupancy drops below a threshold. If the read command occupancy is above a maximum threshold, the read / write circuit 320 bypasses the transmission of the request 325 to write back the information in the dirty cache lines 310 to 313.

[0030] Figure 4 is a flow chart of a method 400 for selectively writing back dirty cache lines while processing a frame using data in a cache, according to some embodiments. The method 400 is Figure 1 The processing system 100 shown, Figure 2The graphics pipeline 200 shown and Figure 3 embodied in some embodiments of the memory system 300 shown.

[0031] At block 405, the read / write circuitry determines a read command occupancy at an SMC in a memory subsystem including a cache. The read command occupancy indicates that a queue or buffer for holding pending read commands at the SMC is full.

[0032] At decision block 410, the read / write circuit determines whether the read command occupancy is less than a first threshold. If so, the method 400 proceeds to block 415, and the read / write circuit sends a request for SMC writeback data in one or more dirty cache lines in the cache. If the read command occupancy is greater than the first threshold, the method 400 proceeds to decision block 420.

[0033] At decision block 420, the read / write circuit determines whether the read command occupancy is greater than a first threshold and less than a second threshold, the second threshold being greater than the first threshold. If so, the method 400 proceeds to block 425 and the read / write circuit requests the SMC to write back data in one or more dirty cache lines in the cache. These requests include a hint indicating that the priority of the request to write back the data is lower than the priority of continuing to process the request in the read command queue or buffer. If the read command occupancy is greater than the second threshold, the method 400 proceeds to block 430, and the read / write circuit bypasses transmitting the request to write back the dirty cache line to the SMC (i.e., bypasses writing back the dirty cache line).

[0034] Computer-readable storage media may include any non-transitory storage media or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disks (CDs), digital versatile disks (DVDs), Blu-ray disks), magnetic media (e.g., floppy disks, tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache memory), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical system (MEMS)-based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or a flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0035] In some embodiments, certain aspects of the above-mentioned technology can be implemented by one or more processors of a processing system that executes software. Software includes one or more sets of executable instructions, which are stored in or otherwise tangibly embodied on a non-transient computer-readable storage medium. Software may include instructions and certain data, which manipulate one or more processors to perform one or more aspects of the above-mentioned technology when executed by one or more processors. Non-transient computer-readable storage media may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache memory, random access memory (RAM) or other one or more non-volatile memory devices, etc. The executable instructions stored on the non-transient computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0036] It should be noted that not all activities or elements described above in the general description are required, a portion of a particular activity or device may not be required, and one or more additional activities may be performed, or elements may be included in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. In addition, these concepts have been described with reference to specific embodiments. However, it is understood by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the following claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0037] Benefits, other advantages and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage or solution to appear or become more significant should not be interpreted as key, essential or basic features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings herein. Except as described in the following claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is apparent that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the following claims.

Claims

1. A device comprising: a cache memory comprising cache lines configured to store data used in processing frames in a graphics pipeline; as well as a processor implementing the graphics pipeline, wherein the processor is configured to process a first frame and, while processing the first frame, selectively write dirty cache lines from the cache back to memory based on a read command occupancy at a system memory controller (SMC), A dirty cache line includes data written by a computing unit but not yet written back to memory. wherein data in the dirty cache line is retained in the cache and is marked as clean after being written back to the memory, and The read command occupancy rate indicates the number of pending read commands of the memory.

2. The apparatus of claim 1 , wherein the processor is configured to transfer data in the dirty cache line to the SMC in response to the read command occupancy being less than a first threshold, wherein the SMC is configured to write the data received from the processor back to the memory.

3. The apparatus of claim 2 , wherein the processor is configured to transmit the data in the dirty cache line to the SMC with a hint indicating that writing the data back to the memory is a low priority in response to the read command occupancy being greater than the first threshold and less than a second threshold. 4 . The apparatus of claim 3 , wherein the SMC is configured to, in response to receiving the hint, provide pending read requests before writing the data back to the memory. 5 . The apparatus of claim 4 , wherein the processor is configured to bypass transferring the data in the dirty cache line to the SMC in response to the read command occupancy being greater than the second threshold.

6. The apparatus of claim 1, wherein the processor is configured to bypass writing the dirty cache line back to the memory during a transition from the first frame to a second frame in response to the dirty cache line being marked as clean. 7 . The apparatus of claim 6 , wherein the processor is configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of a second frame.

8. A method comprising: processing a first frame in a graphics pipeline using data stored in a cache line of a cache associated with the graphics pipeline; selectively writing dirty cache lines from the cache back to a memory based on a read command occupancy at a system memory controller (SMC), wherein the dirty cache lines include data written by a compute unit but not yet written back to the memory, and wherein the read command occupancy indicates a number of pending read commands for the memory; retaining the data in the dirty cache line in the cache; as well as The dirty cache line is marked as clean after the dirty cache line is written back to the memory. 9 . The method of claim 8 , wherein writing back the dirty cache line comprises transferring data in the dirty cache line to the SMC in response to the read command occupancy being less than a first threshold.

10. The method according to claim 9, further comprising: The data received from the SMC is written back to the memory.

11. The method of claim 9, wherein writing back the dirty cache line comprises transmitting the data in the dirty cache line to the SMC with a hint indicating that writing the data back to the memory is a low priority in response to the read command occupancy being greater than the first threshold and less than a second threshold.

12. The method according to claim 11, further comprising: In response to receiving the hint, a pending read request is provided at the SMC before writing the data back to the memory.

13. The method of claim 12, wherein selectively writing the dirty cache line back to the memory comprises bypassing transferring the data in the dirty cache line to the SMC in response to the read command occupancy being greater than the second threshold.

14. The method according to claim 8, further comprising: Writing the dirty cache line back to the memory is bypassed during a transition from the first frame to a second frame in response to the dirty cache line being marked as clean.

15. The method according to claim 14, further comprising: Data in dirty cache lines that are not marked as clean are written back in response to completing processing of the first frame and initiating processing of a second frame.

16. A device comprising: a set of computing units configured to implement a graphics pipeline; as well as A last level cache LLC in a cache hierarchy associated with the set of compute units, wherein the compute units are configured to selectively write dirty cache lines from the LLC back to a memory based on a read command occupancy at a system memory controller SMC while processing a first frame based on data stored in the dirty cache lines, wherein the dirty cache lines include data written by the compute units but not yet written back to the memory, and wherein the dirty cache lines are marked as clean after being written back to the memory, and wherein the read command occupancy indicates a number of pending read commands for the memory. 17 . The apparatus of claim 16 , wherein the computing unit is configured to determine a priority for writing the dirty cache line back from the LLC to the memory based on the read command occupancy of the SMC.

18. The apparatus of claim 16, wherein the computation unit is configured to bypass writing dirty cache lines back to the memory during transition from the first frame to the second frame in response to the dirty cache lines being marked as clean, and wherein the computation unit is configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of a second frame.

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