Pulsed voltage boosting for substrate processing

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for increasing the voltage of an electrode in a processing chamber. An example plasma processing system includes a processing chamber, a plurality of switches, an electrode disposed in the processing chamber, a voltage source, and a capacitive element. The voltage source is selectively coupled to the electrode via one of the plurality of switches. The capacitive element is selectively coupled to the electrode via one of the plurality of switches. The capacitive element and the voltage source are coupled to the electrode in parallel. The plurality of switches are configured to couple the capacitive element and the voltage source to the electrode during a first phase, couple the capacitive element and the electrode to a ground node during a second phase, and couple the capacitive element to the electrode during a third phase.

Description

[0001] background

[0002] field

[0003] Embodiments of the present disclosure generally relate to systems used in semiconductor device fabrication. More particularly, embodiments of the present disclosure relate to plasma processing systems for processing substrates. Background Art

[0004] Reliably producing high-aspect-ratio features is one of the key technical challenges for next-generation semiconductor devices. One method for forming high-aspect-ratio features uses a plasma-assisted etching process, in which a plasma is formed in a processing chamber and ions from the plasma are accelerated toward a substrate surface to form openings in a material layer beneath a shielding layer formed on the substrate surface.

[0005] In a typical plasma-assisted etching process, a substrate is positioned on a substrate support disposed in a processing chamber, a plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate through the plasma sheath (i.e., an electron-depleted region formed between the plasma and the substrate surface).

[0006] It has been found that pulsed techniques must periodically and suddenly consume a large number of plasma-generated bulk electrons to establish a DC bias, and the amount of consumed bulk electrons is often of the order of magnitude of the number of free electrons found in the generated plasma. Consequently, the consumption of bulk electrons leads to severe perturbations in plasma stability and sometimes to plasma extinction. As an example, assume that a plasma processing system has a 5e10 cm -3 Assume a plasma density of 100 nm, a gap of 2 cm (1 inch gap minus about 0.5 cm shell thickness), and a wafer diameter of 30 cm. In such a system, the total available electrons in the volume above the wafer are 7e13. Further assume a shell capacitance of 200 pF and a shell voltage of 8000 V (typical for high aspect ratio etch applications). The number of electrons used to charge the wafer surface is about 1e13. Therefore, in about tens of nanoseconds, about 15% of the bulk electrons are sucked out of the plasma to establish the DC bias. This depletion is repeated at the pulse frequency, which can be about 400 kHz. Bulk electron depletion is a significant perturbation to the sustainability and stability of the plasma. This situation is only likely to worsen with evolving processes using higher ion energies. During processing, plasma variations caused by plasma instabilities will affect both within-wafer (WIW) and between-wafer (WTW) process performance, thereby affecting device yield and other related process outcomes.

[0007] Therefore, there is a need in the art for plasma processing and biasing methods that can provide desired plasma assisted etching process results. Summary of the Invention

[0008]

[0014] Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms in a processing chamber for plasma processing of substrates.

[0009] One embodiment of the present disclosure is directed to a plasma processing system. The plasma processing system generally includes a processing chamber, a plurality of switches, an electrode disposed in the processing chamber, a voltage source, and a capacitive element. The voltage source is selectively coupled to the electrode via one of the plurality of switches. The capacitive element is selectively coupled to the electrode via one of the plurality of switches. The capacitive element and the voltage source are coupled to the electrode in parallel. The plurality of switches are configured to couple the capacitive element and the voltage source to the electrode during a first phase, couple the capacitive element and the electrode to a ground node during a second phase, and couple the capacitive element to the electrode during a third phase.

[0010] One embodiment of the present disclosure relates to a method for processing a substrate. The method generally includes coupling a capacitive element and a voltage source to an electrode disposed within a processing chamber during a first phase, wherein the capacitive element and the voltage source are coupled to the electrode in parallel. The method further includes coupling the capacitive element and the electrode to a ground node during a second phase. The method further includes coupling the capacitive element to the electrode during a third phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and other equally effective embodiments may be admitted.

[0012] Figure 1 is a schematic cross-sectional diagram of a processing system configured to practice the methods described herein, according to one or more embodiments.

[0013] Figure 2A Voltage waveforms that may be applied to electrodes of a processing chamber are shown in accordance with one or more embodiments.

[0014] Figure 2B The voltage waveform developed across the substrate as a result of the voltage waveform applied to the processing chamber electrodes is shown.

[0015] Figure 3 Example ion energy distributions (IEDs) are shown.

[0016] Figure 4A simplified circuit diagram illustrating the functional equivalent of a plasma processing system that can establish a voltage boost at an electrode according to certain embodiments of the present disclosure is shown.

[0017] Figure 5 is a timing diagram illustrating switching states of a plasma processing system according to certain embodiments of the present disclosure.

[0018] Figures 6A-6C is a diagram of some embodiments according to the present disclosure Figure 5 Circuit diagram depicting the switch states during the corresponding phases.

[0019] Figure 7 is a process flow diagram illustrating a method of establishing a boost voltage at an electrode.

[0020] Figure 8A Additional voltage waveforms that may be established at electrodes of a processing chamber according to certain embodiments of the present disclosure are shown.

[0021] Figure 8B The additional voltage waveform developed on the substrate as a result of the voltage waveform applied to the processing chamber electrodes is shown.

[0022] Figure 9

[0026]

[0027] Additional functionally equivalent simplified circuits of plasma processing systems according to certain embodiments of the present disclosure.

[0023] Figure 10

[0026] Additional functionally equivalent simplified circuits of a plasma processing system having an independent voltage source for a boost capacitor according to certain embodiments of the present disclosure are provided.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0025] As technology nodes advance toward 2nm, the fabrication of smaller features with larger aspect ratios requires the atomic precision of plasma processing. For etching processes where plasma ions play a crucial role, ion energy control is a challenge for the semiconductor equipment industry. Traditionally, RF bias technology uses sinusoidal waves to excite the plasma and accelerate the ions.

[0026] Some embodiments of the present disclosure are generally directed to techniques and apparatus for increasing the wafer surface voltage using charge pump concepts without consuming or reducing the consumption of plasma electrons. In certain aspects, electrons from an external circuit (such as a capacitive element coupled in parallel with an electrode of a processing chamber) can be used to increase the DC bias voltage at the electrode. The techniques and apparatus described herein for increasing the DC bias voltage at the electrode can reduce the load on the plasma electrons and / or facilitate higher energy substrate processing operations.

[0027] Plasma Processing System Examples

[0028] Figure 1 is a schematic cross-sectional view of a plasma processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used with processing systems configured for other plasma-assisted processes, such as plasma-enhanced deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma treatment processes, or plasma-based ion implantation processes, such as plasma doping (PLAD).

[0029] As shown, processing system 10 is configured to form a capacitively coupled plasma (CCP), wherein processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within processing volume 129, the upper electrode facing a lower electrode (e.g., substrate support assembly 136) also disposed within processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source is electrically coupled to one of the upper or lower electrodes, delivering an RF signal configured to ignite and sustain a plasma (e.g., plasma 101), which is capacitively coupled to each of the upper and lower electrodes and disposed within a processing region between the upper and lower electrodes. Typically, the opposing electrode is coupled to ground or to a second RF power source for additional plasma excitation. As shown, processing system 10 includes processing chamber 100, support assembly 136, and system controller 126.

[0030] The processing chamber 100 generally includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which together define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to form a structural support for the elements of the processing chamber 100 and are configured to withstand pressure and added energy applied to the one or more sidewalls 122 and the chamber base 124 when the plasma 101 is generated within the vacuum environment maintained within the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed of a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0031] A gas inlet 128 disposed through the chamber lid 123 is used to deliver one or more process gases to the processing volume 129 from a process gas source 119 in fluid communication with the gas inlet 128. Substrates 103 are loaded into and removed from the processing volume 129 through an opening (not shown) in one of the one or more sidewalls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0032] In some embodiments, a plurality of lift pins (not shown) movably disposed through openings formed in the substrate support assembly 136 are used to facilitate transfer of substrates to and from the substrate support surface 105A. In some embodiments, a plurality of lift pins 132 are disposed above, coupled to, and / or engageable with a lift pin ring (not shown) disposed in the processing volume 129. The lift pin ring can be coupled to a shaft (not shown) that extends sealingly through the chamber base 124. The shaft can be coupled to an actuator (not shown) for raising and lowering the lift pin ring. When the lift pin ring is in a raised position, the lift pin ring engages the plurality of lift pins 132 to raise the upper surface of the lift pins above the substrate support surface 105A, thereby lifting the substrate 103 from the substrate support surface 105A and enabling a handling robot (not shown) to access the inactive (back) surface of the substrate 103. When the lift pin ring is in the lowered position, the plurality of lift pins 132 are flush with or recessed below the substrate supporting surface 105A, and the substrate 103 rests thereon.

[0033] The system controller 126 (also referred to herein as the process chamber controller) includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence for processing the substrate 103, including the substrate biasing and / or boosting methods described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial environment to control the process chamber and its associated subprocessors. The memory 134, as described herein, is typically non-volatile memory and may include random access memory, read-only memory, a floppy disk or hard disk drive, or other suitable form of digital storage, whether local or remote. The support circuitry 135 is conventionally coupled to the CPU 133 and includes cache memory, clock circuitry, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (programs) and data may be encoded and stored in the memory 134 for instructing the processors in the CPU 133. The software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are to be performed by the components in the processing system 10.

[0034] Generally, the program readable by the CPU 133 in the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks associated with the plasma processing schemes described herein. The program may include instructions for controlling the various hardware and electronic components within the processing system 10 to perform the various processing tasks and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions for performing the following in conjunction with Figure 7 Instructions for one or more of the described operations.

[0035] The plasma control system generally includes a first source assembly 196 and a second source assembly 197. The first source assembly 196 is used to bias the electrode 104 (at Figure 4 The first or second PV waveform may be generated using one or more components (e.g., PV sources) within a waveform generator assembly 150, which may correspond to a voltage source and / or a current source, as described herein with reference to Figure 4 In some embodiments, the waveform generator transmits an RF signal to the support base 107 (e.g., a power electrode or cathode) and / or the bias electrode 104, which can be used to generate (maintain and / or ignite) the plasma 101 in the processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, as Figure 1As shown, the individual waveform generator assembly 150 within the third source assembly 198 includes at least an RF source configured to transmit an RF signal to the support substrate 107 (eg, a power electrode or cathode).

[0036] The applied RF signal provided by the first source assembly 196, the second source assembly 197, or the third source assembly 198 can be configured to generate (maintain and / or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal is used to ignite and sustain the process plasma 101 using a process gas disposed in the processing volume 129 and a field generated by RF power (RF signal) delivered to the support base 107 and / or the bias electrode 104. In some aspects, the RF signal can be generated by an RF source (not shown) disposed within the waveform generator assembly 150. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps via the vacuum outlet 120, which maintain the processing volume 129 at a pressure below atmospheric pressure and exhaust process and / or other gases from the processing volume 129. In some embodiments, the substrate support assembly 136 disposed in the processing volume 129 is disposed on a support shaft 138, which is grounded and extends through the chamber base 124. In some embodiments, the RF signal generator may be configured to transmit an RF signal having a frequency greater than 40 MHz, such as between approximately 40 MHz and approximately 200 MHz.

[0037] In some embodiments, the capacitive element 152 may be selectively coupled to the bias electrode 104 and / or the support substrate 107, as described herein with reference to Figure 4 As further described. In some cases, the capacitive element 152 can be electrically coupled to the bias electrode 104 and / or the support substrate 107 via a power transmission line 157. The capacitive element 152 can provide a voltage boost during the ESC recharge phase to reduce the consumption of bulk electrons from the plasma. The voltage boost can reduce or prevent disturbances to the plasma sustainability and stability caused by the consumption of bulk electrons from the plasma.

[0038] As briefly discussed above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an electrostatic chuck (ESC) substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may additionally include an insulating plate 111 and a ground plate 112, as discussed further below. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, with the ground plate 112 interposed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed thereon during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein that are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant source having a relatively high electrical resistance or a water source. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded in the dielectric material of the substrate support 105. Herein, the support base 107 is formed of a corrosion-resistant, thermally conductive material, such as a corrosion-resistant metal, e.g., aluminum, an aluminum alloy, or stainless steel, and is coupled to the substrate support using an adhesive or by mechanical means.

[0039] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In the embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material thereof.

[0040] In one configuration, the bias electrode 104 is a clamping rod that is used to secure (i.e., clamp) the substrate 103 to the substrate supporting surface 105A of the substrate support 105 and bias the substrate 103 relative to the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed from one or more conductive members, such as one or more metal meshes, foils, plates, or combinations thereof.

[0041] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network that uses an electrical conductor, such as a coaxial power transmission line 106 (e.g., a coaxial cable), to provide a clamping voltage, such as a static DC voltage between approximately −5000 V and approximately 5000 V, to the bias electrode 104. As will be discussed further below, the clamping network includes a DC power supply 155 (e.g., a high voltage DC (HVDC) power supply) and a filter 151 (e.g., a low-pass filter).

[0042] The substrate support assembly 136 may further include an edge control electrode 115 positioned below the edge ring 114 and surrounding the bias electrode 104 and / or disposed at a distance from the center of the bias electrode 104. Generally speaking, for a processing chamber 100 configured to process circular substrates, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as Figure 1 As shown, the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments, as shown in FIG. Figure 1 As shown, the edge control electrode 115 comprises a conductive mesh, foil and / or plate disposed at a distance (i.e., in the Z direction) from the substrate supporting surface 105A of the substrate support 105 that is similar to the distance between the bias electrode 104 and the substrate supporting surface 105A of the substrate support 105.

[0043] The edge control electrode 115 can be biased using a waveform generator assembly that is different from the waveform generator assembly 150 that is used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased using a waveform generator assembly 150 that is also used to bias the bias electrode 104 by allocating a portion of power to the edge control electrode 115. In one configuration, the first waveform generator assembly 150 of the first source assembly 196 is configured to bias the bias electrode 104, while the second waveform generator assembly 150 of the second source assembly 197 is configured to bias the edge control electrode 115.

[0044] In one embodiment, a power transmission line 157 electrically connects the output of the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104. Although the following discussion primarily discusses the power transmission line 157 of the first source assembly 196 for coupling the waveform generator assembly 150 to the bias electrode 104, the power transmission line 158 of the second source assembly 197 coupling the waveform generator assembly 150 to the edge control electrode 115 will include the same or similar components. The electrical conductor(s) within each portion of the power transmission line 157 may include: (a) a coaxial cable or a combination of coaxial cables, such as a flexible coaxial cable in series with a rigid coaxial cable, (b) an insulated high voltage corona resistant connecting wire, (c) bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical components in (a)-(e).

[0045] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 to prevent contact between the substrate support 105 and / or the supporting base 107 and the corrosive process gas or plasma, the cleaning gas or plasma, or their byproducts. Typically, the quartz tube 110, the insulating plate 111, and the ground plate 112 are surrounded by a liner 108. In some embodiments, a plasma shield 109 is positioned between the cathode liner 108 and the sidewalls 122 to prevent plasma from forming in the volume below the plasma shield 109 between the liner 108 and one or more sidewalls 122.

[0046] Figure 2A Example voltage waveforms that may be established at electrodes of a processing chamber (eg, bias electrode 104 and / or support substrate 107) are shown. Figure 2B Shows that due to similar Figure 2A 1 and 2. Examples of different types of voltage waveforms 225 and 230 established on a substrate for different voltage waveforms are shown, each of which is established on an electrode within a processing chamber. As shown, the waveform includes two phases: an ion current phase and a shell collapse phase. At the beginning of the ion current phase, a drop in substrate voltage creates a high-voltage shell above the substrate, thereby accelerating positive ions to the substrate. In various aspects, a capacitive element (e.g., capacitive element 152) can be used as a bulk electron source to increase the drop in substrate voltage. The voltage boost can reduce bulk electrons consumed from the plasma and improve the sustainability and stability of the plasma during the etching process.

[0047] Positive ions bombarding the substrate surface during the ion current phase deposit positive charges on the substrate surface which, if not compensated, would cause the substrate voltage to gradually increase during the ion current phase, as shown in FIG. Figure 2B However, the uncontrolled accumulation of positive charge on the substrate surface undesirably causes the shell and clamping capacitors to gradually discharge, slowly reducing the shell voltage drop and bringing the substrate potential closer to zero, as shown in voltage waveform 225. The accumulation of positive charge results in a voltage drop ( Figure 2B ). However, if Figure 2A As shown, a voltage waveform having a negative slope during the ion current phase established at the electrode can be generated to establish a square region (e.g., near zero slope) for the established substrate voltage waveform, as shown in FIG. Figure 2B230 in FIG. Implementing a slope in the waveform established at the electrode during the ion current phase may be referred to as ion current compensation. The voltage difference between the start and end of the ion current phase determines the ion energy distribution function (IEDF) width. The larger the voltage difference, the wider the IEDF width. To achieve monoenergetic ions and a narrower IEDF width, ion current compensation is used to perform an operation to flatten the substrate voltage waveform during the ion current phase. In some embodiments of the present disclosure, the RF signal is superimposed on the substrate voltage waveform. Figure 2A The voltage waveform is shown.

[0048] Figure 3 3 is a graph illustrating an IED function (IEDF) according to certain embodiments of the present disclosure. As shown, the IEDF includes a single energy peak 302 that may be generated at the electrode using a particular waveform during the ion current compensation phase. The energy associated with the energy peak may be less than a few hundred eV (e.g., less than 1 KeV). In some cases, the energy associated with the energy peak may be from a few hundred eV to tens of thousands of eV, depending on the aspect ratio of the feature to be formed in the substrate. For example, in some cases, the energy associated with the energy peak may be between 4keV and 10keV. Some embodiments are directed to methods for implementing Figure 3 The ion energy distribution shown or other suitable ion energy distribution (e.g., Figure 8B depicted) technology.

[0049] Voltage boost for substrate processing

[0050] Certain embodiments of the present disclosure are generally directed to techniques and apparatus for increasing the voltage at an electrode of a processing chamber, such as a bias electrode (e.g., Figure 1 ) and / or a supporting substrate (e.g., Figure 1 ). The voltage boost described herein can reduce consumption of bulk electrons from the plasma and facilitate desirable plasma assisted etching process results.

[0051] Figure 4 4 is a simplified circuit 400 of a plasma processing system (e.g., processing system 10) that can establish a voltage boost at an electrode according to certain embodiments of the present disclosure. As shown, circuit 400 may include switches 402a-402f (collectively referred to as switches 402 and labeled S1-S6), a voltage source 404, a current source 406, a capacitive element 152, an equivalent capacitance of substrate support 105 (labeled C ESC), an input node 408 (representing a bias electrode 104 and / or a support substrate 107 in a processing chamber), and a composite load 410, which can represent a standard plasma model as further described herein. In various aspects, a process can include a substrate support (e.g., substrate support 105) comprising a dielectric layer (e.g., a dielectric material of the substrate support 105) disposed over an electrode (e.g., bias electrode 104 and / or support substrate 107).

[0052] In circuit 400, a waveform (such as Figure 2A During a portion of a process (e.g., the waveform depicted), a capacitor element 152 may be used to establish a voltage boost at an electrode (represented by input node 408) from a pulsed voltage from a voltage source 404 and / or a current source 406. Circuit 400 illustrates a simplified model of the interaction between waveform generator components (represented by voltage source 404 and / or current source 406), capacitor element 152, and certain components within processing chamber 100 (e.g., substrate support and plasma), and generally illustrates the basic components used during operation of processing chamber 100. For clarity, the following definitions are used throughout this disclosure: (1) Unless otherwise specified, all potentials are referenced to ground; (2) the voltage at any physical point (e.g., substrate or bias electrode) is also defined as the potential of that point relative to ground (zero potential); (3) cathode sheath means the sheath that repels electrons and accelerates ions, corresponding to a negative substrate potential relative to the plasma; (4) sheath voltage (sometimes also referred to as "sheath voltage drop"), V sh is defined as the absolute value of the potential difference between the plasma and an adjacent surface (e.g., the surface of the substrate or chamber wall); and (5) the substrate potential is the potential of the substrate surface facing the plasma.

[0053] The composite load 410 is depicted as a standard plasma model that represents the process plasma 101 as three series elements. The first element is the electron-repelling cathode sheath (sometimes also referred to as the "plasma sheath" or simply the "sheath") adjacent to the substrate 103. The cathode sheath is represented by a conventional three-part circuit element, including: (a) a diode D SH , diode D SH When opened, it indicates shell collapse; (b) current source I i , representing the ionic current flowing to the substrate in the presence of the shell; and (c) the capacitor C SH (e.g., about 100-300 pF), capacitor C SH Represents the main part of the bias cycle (e.g. Figure 2A The second element is composed of a single resistor R等离子体 (e.g., resistor 412 = approximately 5-10 ohms) represents the bulk plasma. The third element is the electron repelling shell layer formed on the chamber wall. The shell layer is also represented by a three-part circuit element, including: (a) diode D 壁 (b) Current source I i壁 , representing the ionic current flowing to the wall; and (c) the capacitor C 壁 (e.g., about 5-10nF), capacitor C 壁 The wall shell layer is represented primarily during the ESC recharge phase of the waveform at the electrode. The inner surface of the grounded metal wall may also be coated with a thin layer of dielectric material, which may provide a capacitance (not shown), such as about 300-1000 nF, coupled in series between the composite load 410 and the ground node 414. The parasitic and stray capacitance of the ESC components (e.g., substrate support 105) and the inductance of the ESC components may not be significant for the voltage boost scheme described herein and are not included in the description. Figure 4 In some cases, when determining the value of certain electrical components (such as the capacitance of the capacitor element 152, C ESC These factors (and others) may be considered when evaluating the characteristics of the waveform established at the electrode (e.g., voltage level, duration, and / or RF signal).

[0054] Capacitive element 152 may be implemented as one or more capacitors, such as ceramic capacitors and / or multilayer dielectric capacitors. For example, capacitive element 152 may include multiple capacitors coupled together in a network, such as a parallel network and / or a series network. In some cases, capacitive element 152 may be rated to operate at high voltages (such as voltage levels greater than 10 kV). Capacitive element 152 may have a capacitance in the range of 500 picofarads (pF) to 1 nanofarad (nF). The capacitance value of capacitive element 152 may be close to or greater than C ESC and / or C SH That is, the capacitive element may have a capacitance equal to or greater than the substrate support capacitance of the processing chamber (e.g., C ESC ) or shell capacitance (e.g., C SH ) in the embodiment of the present invention.

[0055] Capacitive element 152 can be selectively coupled to an electrode (e.g., input node 408) of the processing chamber via at least one of switches 402 (e.g., switch 402c). Capacitive element 152 can be selectively coupled to voltage source 404 and ground node 414, for example, via at least one of switches 402 (e.g., switches 402d, 402e, and 402f). Capacitive element 152 and voltage source 404 can be selectively coupled in parallel with the electrode (e.g., input node 408). That is, capacitive element 152 and voltage source 404 can be selectively coupled to the electrode in parallel with each other. In some aspects, capacitive element 152 is coupled to substrate support capacitance (C ESC ) and / or shell capacitance (C SH ) separate electrical components. In some cases, the capacitive element 152 may be integrated and / or co-located with the waveform generator assembly 150 (such as the voltage source 404 and / or the current source 406). In some cases, the capacitive element 152 may be integrated with the substrate support capacitor (C ESC ) and / or shell capacitance (C SH ) integrated and / or co-located to provide a suitable boost voltage as described herein.

[0056] Capacitive element 152 can provide a source of bulk electrons separate from the plasma. In some cases, capacitive element 152 can improve the sustainability and stability of the plasma by reducing the consumption of bulk electrons from the plasma used to establish a DC bias at the electrode.

[0057] Switch 402 can be implemented as a high-voltage solid-state relay. In some cases, switch 402 can be implemented as a high-voltage multiplexer and / or demultiplexer. In this example, switch 402 may include a first switch 402a, a second switch 402b, a third switch 402c, a fourth switch 402d, a fifth switch 402e, and a sixth switch 402f. First switch 402a may be coupled between voltage source 404 and input node 408, which may be electrically coupled to an electrode or a representation electrode. Second switch 402b may be coupled between input node 408 and ground node 414. Third switch 402c may be coupled between first terminal 416 of capacitor element 152 and input node 408. Fourth switch 402d may be coupled between second terminal 418 of capacitor element 152 and input node 408. Fifth switch 402e may be coupled between first terminal 416 of capacitor element 152 and ground node 414. The sixth switch 402 f may be coupled between the second terminal 418 of the capacitive element 152 and the ground node 414 .

[0058] In some cases, the state (e.g., open or closed) of the switches 402 may be controlled by the system controller 126. For example, the system controller 126 may communicate with a control input (not shown) of the switches 402 such that a control signal from the system controller 126 toggles the state of the switches 402. The system controller 126 may control the individual state of each switch 402 using individual control signals applied to the corresponding switches. Figure 5 and Figures 6A-6C As further described, switch 402 can be configured to couple capacitive element 152 and voltage source 404 to an electrode (e.g., input node 408) during a first phase (which can be referred to as an ESC recharge phase), couple capacitive element 152 and the electrode to ground node 414 during a second phase (which can be referred to as a voltage negation phase), and couple capacitive element 152 to the electrode during a third phase (which can be referred to as a voltage boost phase). In various aspects, the second phase can occur after the first phase, and the third phase can occur after the second phase. For certain aspects, switch 402 can decouple the electrode from capacitive element 152 and voltage source 404 during the second phase, and decouple the electrode from the ground node during the third phase.

[0059] Voltage source 404 can be a component of a waveform generator assembly (e.g., waveform generator assembly 150). That is, the waveform generator assembly can include voltage source 404, which can include a pulsed voltage DC waveform generator and / or an RF generator (also referred to as an RF signal generator). Voltage source 404 can be selectively coupled to an electrode (e.g., input node 408) via one of switches 402 (e.g., switch 402a). For example, switch 402a can be coupled in series between voltage source 404 and input node 408.

[0060] Similarly, current source 406 can be a component of the waveform generator assembly. Current source 406 can be used to implement a ramp voltage during the ion current phase, for example, as described herein with reference to Figure 2A The current source may be configured to be in the fourth phase (eg, Figure 2A ion compensation current is applied to the processing chamber (e.g., electrode) during the fourth phase (e.g., the ion current phase depicted). In various aspects, switch 402 can be configured to couple capacitive element 152 to the processing chamber (e.g., electrode) during a fourth phase, which can occur after the third phase. Current source 406 can be coupled to the electrode. In some cases, voltage source 404, current source 406, and capacitive element 152 can be coupled in parallel to the electrode (e.g., input node 408).

[0061] Those skilled in the art will appreciate that circuit 400 is merely an example and that other circuits (such as Figure 9 and Figure 10 For ease of understanding, the examples depicted in this disclosure are described herein with respect to substrate processing using positive voltage pulses, but aspects of the disclosure are also applicable to establishing waveforms at the electrodes using negative voltage pulses.

[0062] According to certain embodiments of the present disclosure, Figure 5 is a timing diagram 500 showing the states of switches 402 (labeled S1-S6, respectively) of circuit 400, and Figures 6A-6C It shows that Figure 5 A circuit diagram depicting the state of switch 402 during the corresponding phases is depicted.

[0063] refer to Figure 5 The waveform at the electrode can be established in a first phase 502, a second phase 504, a third phase 506, and a fourth phase 508. The first phase 502 can take 20 nanoseconds (ns) to 2000 ns to allow sufficient electrons to be collected on the wafer surface. The second phase 504 and / or the third phase 506 can take tens of nanoseconds to hundreds of nanoseconds, such as 20 nanoseconds to 500 nanoseconds. The fourth phase 508 can take more than 50% of the waveform period, such as 85-90% of the waveform period. The frequency of the voltage function can vary from 50 kHz to 5000 kHz.

[0064] During the first phase 502, switches 402a, 402d, and 402e (S1, S4, and S5) are closed to activate the substrate support 105 (C ESC ) and (multiple) plasma sheath capacitances (C SH and C 壁 ) and capacitor element 152 (C 升压 ) charging, such as Figure 6A These capacitors may take longer to charge than Figure 5 During the first phase 502, the first switch 402a is configured to be closed; the second switch 402b is configured to be open; the third switch 402c is configured to be open; the fourth switch 402d is configured to be closed; the fifth switch 402e is configured to be closed; and the sixth switch 402f is configured to be open.

[0065] During the first phase 502, the capacitive elements 152, C ESC and C SH Can be charged to voltage V 升压 .because Figure 5At the rising edge of the waveform shown, plasma electrons are attracted to the wafer surface. For example, due to an equal amount of positive charge on the other electrode, the electrons may not yet have established a negative DC shell potential. Depicted as C ESC An equivalent capacitance can be formed between the wafer surface and the electrode, and there can be an equal amount of positive charge on the electrode to cancel the field generated by those electrons.

[0066] During the second phase 504, the second switch 402b and the sixth switch 402f are closed. Figure 6B The first switch 402a, the fourth switch 402d, and the fifth switch 402e are configured to be open during the second phase 504, and the second switch 402b and the sixth switch 402f are configured to be closed during the second phase to couple the second terminal 418 of the capacitive element 152 and the input node 408 to the ground node 414. Effectively, the substrate supports the capacitance C ESC Coupled to ground node 414 .

[0067] When the second switch 402b is closed, the potential at the electrode can be forced to the voltage level at the ground node 414 (such as 0 volts). Since the voltage drop across the capacitor cannot change instantaneously, the voltage on the wafer surface becomes negative, thereby establishing a negative V on the wafer surface. dc For example, with the second switch 402b in a closed state, the voltage at the electrode may decrease to the first voltage level.

[0068] The sixth switch 402f is closed and pulls the potential of the connected capacitive element 152 to ground. The potential of the capacitive element 152 becomes a negative voltage. During the second phase 504, the capacitive element 152 may not be coupled to the input node 408 and the substrate support. The negative DC voltage (V dc ) can be calculated by using the magnitude of the falling edge ΔV and C ESC and shell capacitance C 壳层 The ratio between them is approximated as:

[0069]

[0070] Among them, C 壳层 Is the capacitance with the ground shell (C 壁 )The chip shell capacitance (C SH ) capacitance. In some cases, due to the ground shell capacitance (C 壁 ) is much larger, so C 壳层 It can be approximated as the chip shell capacitance (C SH ).

[0071] During the third phase 506, the third switch 402c and the sixth switch 402f are closed. Figure 6CDuring the third phase, the second switch 402b is configured to be open and the third switch 402c is configured to be closed, so that the first terminal 416 of the capacitor element 152 is coupled to the input node 408. With the third switch 402c closed, the capacitor element 152 can further reduce the voltage at the electrode to a second voltage level that is less than the first voltage level. The third switch 402c connects the capacitor element 152 to the input node 408, which can further enhance the V dc And V dc Pull more negative.

[0072] The voltage at the electrode is given by:

[0073]

[0074] In some cases, |V 升压 | may be higher than |ΔV|. For example, |V 升压 | might be 1750 volts, and |ΔV| might be 1000 volts. In this example, for the same amount of V dc , capacitor element 152 can reduce the number of electrons required to accumulate on the chip surface to 4 / 11.

[0075] The fourth stage 508 is the ion current compensation stage, which can be referred to herein as Figure 2A and Figure 2B During the fourth phase 508, the electrode voltage may have a negative slope to compensate for the ion current. The state of the switch 402 may remain the same as that established at the end of the third phase 506. That is, during the fourth phase 508, the third switch 402c and the sixth switch 402f may remain closed.

[0076] The incoming ion current neutralizes the negative discharge on the wafer surface and causes the shell capacitor (e.g., C SH ) discharge. The chip voltage can be maintained at a constant voltage to provide the reference herein. Figure 2B and Figure 3 The single-peak IED described above. Current source 406 can be used to pump electrons into the circuit to compensate for the ion current. In doing so, the current source forms a voltage waveform with a negative slope at the electrode. In the fourth phase 508, the plasma ions bombard the wafer surface and initiate an etching reaction. The fourth phase 508 can be considered an etching period and can be made as long as possible to promote the desired etching (e.g., 1000 ns to 10,000 ns). This length may be limited by the charging rate of the wafer surface or the maximum voltage of the current source (if current compensation is performed).

[0077] Ion energy / flux diagnostics can be used to calibrate the ion compensation current (I 离子), or by sampling the electrode voltage (V0) (e.g., for calculating the time derivative of V0) and the shell capacitance to calculate the ion compensation current (I 离子 ):

[0078]

[0079] Among them C 升压 is the capacitance of the capacitive element 152. For example, the first tens to hundreds of cycles can be used to sample the electrode voltage and calculate the ion current compensation I 离子 . Current compensation may then be implemented for subsequent cycles. Current source 406 may be configured to adjust the ion compensation current in response to a change in the voltage measured at the electrode over time based at least in part on the capacitance of the capacitive element, for example, as given by equation (3). The increased capacitance of capacitive element 152 may slow down V dc C can be used within the range allowed by the rated voltage. 升压 As big as possible.

[0080] Figure 7 is a process flow diagram illustrating a method 700 of increasing a voltage at an electrode. The method 700 may be performed by a plasma processing system, such as the processing system 10.

[0081] At activity 702, during a first phase (e.g., first phase 502), a capacitive element (e.g., capacitive element 152) and a voltage source (e.g., voltage source 404) may be coupled to an electrode (e.g., represented by input node 408) disposed within a processing chamber (e.g., processing chamber 100). For example, Figure 4 As depicted, capacitive element 152 and voltage source 404 can be coupled to the electrodes in parallel. As an example, for circuit 400, first switch 402a, fourth switch 402d, and fifth switch 402e can be closed during the first phase. Second switch 402b, third switch 402c, and sixth switch 402f can be open during the first phase.

[0082] At activity 704, capacitive element 152 and the electrode can be coupled to a ground node (e.g., ground node 414) during a second phase (e.g., second phase 504). During the second phase, the electrode can be decoupled from the voltage source and the capacitive element. As an example, for circuit 400, first switch 402a, fourth switch 402d, and fifth switch 402e are open during the second phase. Second switch 402b and sixth switch 402f are closed during the second phase to couple the capacitive element to an input node (e.g., input node 408). With second switch 402b closed, the voltage at the electrode can decrease to a first voltage level.

[0083] At activity 706, capacitive element 152 can be coupled to the electrode during a third phase (e.g., third phase 506). During the third phase, the electrode can be decoupled from the ground node. As an example, for circuit 400, second switch 402b can be opened during the third phase, and third switch can be closed to couple first terminal 416 of capacitive element 152 to input node 408. With third switch 402c closed, the voltage at the electrode can decrease to a second voltage level that is less than the first voltage level.

[0084] At activity 708, a current source (e.g., current source 406) can apply an ion compensation current to the electrode during a fourth phase (e.g., fourth phase 508). In various aspects, capacitive element 152 can be coupled to the electrode during the fourth phase. For certain aspects, the current source can adjust the ion compensation current based at least in part on the capacitance of the capacitive element in response to a change in voltage measured at the electrode over time, e.g., as given by Equation (3).

[0085] In certain aspects, the method 700 may further include generating a plasma above a substrate supporting surface (e.g., substrate supporting surface 105A) of a substrate support (e.g., substrate support 105) disposed in the processing chamber. Plasma and ion current compensation may facilitate substrate etching as described herein.

[0086] In certain aspects, the timing of coupling the charged capacitive element to the electrode can be adjusted, for example, to produce a variety of ion energies and / or to adjust the width of the ion energy during an etch cycle.

[0087] Figure 8A 1 shows example voltage waveforms that may be established at electrodes of a processing chamber (e.g., bias electrode 104 and / or support substrate 107) according to certain embodiments of the present disclosure. Figure 2A and Figure 5 The closing of the third switch 402c in the third phase may be delayed compared to the waveform depicted. For example, the second phase may have a Figure 2A and Figure 5 The duration depicted is longer. By utilizing the delayed coupling of the capacitive elements, it is possible to produce Figure 8B The IEDF with two ion energies is depicted. As shown, the IEDF includes a low energy peak 802 and a high energy peak 804.

[0088] For certain aspects, the current source may be coupled in series with the capacitive element. For example, Figure 91 is an additional functionally equivalent simplified circuit 900 for a plasma processing system (e.g., processing system 10) that can establish a voltage boost at an electrode according to certain embodiments of the present disclosure. A current source 406 can be selectively coupled to a processing chamber (e.g., an electrode) via a switch 402 (e.g., third switch 402c), which can be configured to couple the current source to the processing chamber during a fourth phase. In this example, a capacitive element 152 can be selectively coupled in series between the current source 406 and the electrode (e.g., input node 408). In circuit 900, the sixth switch 402f can be eliminated.

[0089] The ion current can be adjusted according to the following expression:

[0090]

[0091] As a result, circuit 900 may achieve lower ion current compared to circuit 400 .

[0092] In some aspects, a separate voltage source may be used to charge the capacitive element. For example, Figure 10 1 is an additional functionally equivalent simplified circuit 1000 for a plasma processing system (e.g., processing system 10) that can establish a voltage boost at an electrode according to certain embodiments of the present disclosure. In circuit 1000, the voltage source can include a first voltage source 404a selectively coupled to the electrode (e.g., input node 408) and a second voltage source 404b selectively coupled to capacitive element 152. In this example, a sixth switch 402f can be coupled in parallel with second voltage source 404b and fourth switch 402d. A fifth switch 402e can be coupled in series between capacitive element 152 and ground node 414.

[0093] During the first phase, the first switch 402a, the fourth switch 402d, and the fifth switch 402e may be closed, while the second switch 402b, the third switch 402c, and the sixth switch 402f may be open. During the second phase, the sixth switch 402f and the second switch 402b may be closed, while the first switch 402a, the third switch 402c, and the fourth switch 402d may be open. During the third phase, the third switch 402c and the sixth switch 402f may be closed, while the first switch 402a, the second switch 402b, and the fifth switch 402e may be open.

[0094] In some cases, the capacitive element 152 and the second voltage source 404b can be used to compensate for the ion current. For example, the third switch 402c can be closed in the middle of the fourth phase to generate a step down in voltage during the ion current compensation phase.

[0095] Similar to the concept of voltage triplers and quadruplers, multiple stages of boost capacitors can be used to further increase the wafer DC voltage. Such embodiments can use more switches and / or relays.

[0096] It will be appreciated that the techniques and apparatus described herein can reduce the number of plasma electrons consumed to establish a DC bias. Thus, the techniques and apparatus described herein can improve plasma stability and extend the maximum achievable ion energy for substrate processing.

[0097] As used herein, the term "coupled" refers to a direct or indirect coupling between two objects. For example, if object A physically contacts object B and object B contacts object C, then objects A and C can still be considered coupled to each other—even if objects A and C are not in direct physical contact with each other. For example, a first object can be coupled to a second object even if the first object has never been in direct physical contact with the second object.

[0098] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for processing a substrate, comprising the following steps: During a first stage, coupling a capacitive element and a voltage source to an electrode disposed within a processing chamber, wherein the capacitive element and the voltage source are coupled to the electrode in parallel; coupling the capacitive element and the electrode to a ground node during a second phase; as well as During a third phase, the capacitive element is coupled to the electrode and the electrode is decoupled from the ground node.

2. The method of claim 1, further comprising the steps of: generating a plasma above a substrate supporting surface of a substrate support disposed in the processing chamber, the substrate support comprising the electrode and a dielectric layer disposed between the electrode and the substrate supporting surface; Wherein the coupling step during the second phase further comprises decoupling the electrode from the voltage source and the capacitive element.

3. The method of claim 1 , wherein the coupling step during the first phase comprises the following steps: closing a first switch coupled between the voltage source and an input node electrically coupled to the electrode; closing a second switch coupled between the first terminal of the capacitive element and the input node; as well as A third switch coupled between the second terminal of the capacitive element and the ground node is closed.

4. The method of claim 3, wherein the coupling step during the first phase further comprises the following steps: disconnecting a fourth switch coupled between the input node and the ground node; opening a fifth switch coupled between the first terminal of the capacitive element and the ground node; as well as A sixth switch coupled between the second terminal of the capacitive element and the input node is opened.

5. The method of claim 4, wherein the coupling step during the second phase comprises the following steps: turning off the first switch, the second switch and the third switch; as well as The fourth switch and the fifth switch are closed to couple the first terminal of the capacitive element and the input node to the ground node.

6. The method of claim 5, wherein the coupling step during the third phase comprises the following steps: turning off the fourth switch; as well as The sixth switch is closed to couple the second terminal of the capacitive element to the input node.

7. The method of claim 1, further comprising the steps of: During the fourth phase an ion compensation current is applied to the electrodes using a current source.

8. The method of claim 7, wherein during the fourth phase, the capacitive element is coupled to the electrode.

9. The method of claim 7, further comprising the steps of: generating a plasma above a substrate supporting surface of a substrate support disposed in the processing chamber, the substrate support comprising the electrode and a dielectric layer disposed between the electrode and the substrate supporting surface; as well as Wherein applying the ion compensation current comprises adjusting the ion compensation current in response to a change in a voltage measured at the electrode over time based at least in part on a capacitance of the capacitive element.

10. The method of claim 1, wherein: The coupling step during the second phase includes reducing the voltage at the electrode to a first voltage level; as well as The coupling step during the third phase includes reducing the voltage at the electrode to a second voltage level that is less than the first voltage level.

11. A plasma processing system comprising: Multiple switches; an electrode disposed in the processing chamber; a voltage source selectively coupled to the electrode via one of the plurality of switches; as well as a capacitive element selectively coupled to the electrode via the one of the plurality of switches, wherein the capacitive element and the voltage source are coupled to the electrode in parallel, and wherein the plurality of switches are configured to: coupling the capacitive element and the voltage source to the electrode during a first phase, coupling the capacitive element and the electrode to a ground node during a second phase, and During a third phase, the capacitive element is coupled to the electrode and the electrode is decoupled from the ground node.

12. The plasma processing system of claim 11 , wherein: The processing chamber includes a substrate support including a dielectric layer disposed over the electrode; wherein the plurality of switches are configured to: During the second phase, the electrode is decoupled from the capacitive element and the voltage source.

13. The plasma processing system of claim 12, wherein said plurality of switches comprises: a first switch coupled between the voltage source and an input node electrically coupled to the electrode, wherein the first switch is configured to be closed during a first phase; a second switch coupled between the first terminal of the capacitive element and the input node, wherein the second switch is configured to be closed during the first phase; as well as A third switch is coupled between the second terminal of the capacitive element and the ground node, wherein the third switch is configured to be closed during the first phase.

14. The plasma processing system of claim 13 wherein said plurality of switches comprises: a fourth switch coupled between the input node and the ground node, wherein the fourth switch is configured to be open during the first phase; a fifth switch coupled between the first terminal of the capacitive element and the ground node, wherein the fifth switch is configured to be open during the first phase; as well as A sixth switch is coupled between the second terminal of the capacitive element and the input node, wherein the sixth switch is configured to be open during the first phase.

15. The plasma processing system of claim 14, wherein: The first switch, the second switch, and the fifth switch are configured to be open during the second phase; and The fourth switch and the fifth switch are configured to be closed during the second phase to couple the first terminal of the capacitive element and the input node to the ground node.

16. The plasma processing system of claim 15, wherein: The fourth switch is configured to be open during the third phase; as well as The sixth switch is configured to be closed during the third phase to couple the second terminal of the capacitive element to the input node.

17. The plasma processing system of claim 11, further comprising: a current source coupled to the electrode; as well as The current source is configured to apply an ion compensation current to the processing chamber during a fourth stage.

18. The plasma processing system of claim 17 wherein said plurality of switches are configured to couple said capacitive element to said processing chamber during said fourth phase.

19. The plasma processing system of claim 17, wherein: The processing chamber includes a substrate support including a dielectric layer disposed over the electrode; as well as The current source is configured to adjust the ion compensation current in response to a change in voltage measured at the electrode over time based at least in part on the capacitance of the capacitive element.

20. The plasma processing system of claim 11, wherein the plurality of switches are configured to: coupling the electrode to the ground node during the second phase to reduce the voltage at the electrode to a first voltage level; and The capacitive element is coupled to the electrode during the third phase to reduce the voltage at the electrode to a second voltage level that is less than the first voltage level.

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