Display substrate, display panel and display device

Abstract

A display substrate includes: a substrate (1); a plurality of pixel circuits disposed on the substrate (1); a plurality of pixels (2) arranged in an array and located on the side of the pixel circuits facing away from the substrate (1); each pixel (2) includes a first sub-pixel (21), a second sub-pixel (220), and a third sub-pixel (221); the orthographic projections of the first sub-pixel (21), the second sub-pixel (220), and the third sub-pixel (221) on the substrate do not overlap; the first sub-pixel (21), the second sub-pixel (220), and the third sub-pixel (221)... Sub-pixels (221) are electrically connected to pixel circuits in a one-to-one correspondence; a first spacing is set between the first sub-pixel (21) and the second sub-pixel (220) along the first direction (Y), and a first via (41) is set in the first spacing; a second spacing is set between the first sub-pixel (21) and the third sub-pixel (221) along the first direction (Y), and a first via (41) is set in the second spacing; a third spacing is set between the second sub-pixel (220) and the third sub-pixel (221) along the first direction (Y).

Description

Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a display substrate, a display panel, and a display device. Background Technology

[0002] Currently, OLED (Organic Light-Emitting Diode) display panels, also known as organic light-emitting diode display panels or organic light-emitting semiconductor display panels, have color gamut as an important indicator for evaluating OLED display panels. High color gamut displays provide users with a better visual experience and are a key indicator pursued in the development of new products. Summary of the Invention

[0003] This disclosure provides a display substrate, a display panel, and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate;

[0005] Multiple pixel circuits are disposed on the substrate;

[0006] Multiple pixels are arranged in an array and located on the side of the pixel circuit that is away from the substrate;

[0007] The pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the orthographic projections of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate do not overlap; the first sub-pixel, the second sub-pixel, and the third sub-pixel are electrically connected to the pixel circuit in a one-to-one correspondence;

[0008] A first spacing is set between the first sub-pixel and the second sub-pixel along a first direction, and a first via is set in the first spacing;

[0009] A second spacing is set between the first sub-pixel and the third sub-pixel along a first direction, and a first via is set in the second spacing;

[0010] A third spacing is set between the second and third sub-pixels along the first direction.

[0011] In some embodiments, the pixel circuit includes a driving transistor and an insulating layer; the first sub-pixel, the second sub-pixel, and the third sub-pixel each include an anode; the driving transistor, the insulating layer, and the anode are sequentially disposed away from the substrate.

[0012] The pixel circuit also includes auxiliary electrodes;

[0013] The auxiliary electrode includes a first conductive layer, which is located on the same film as the anode, and the orthographic projection of the first conductive layer on the substrate does not overlap with the orthographic projection of the anode on the substrate.

[0014] The auxiliary electrode also includes a second conductive layer, which is located on the same film as the first and second electrodes of the driving transistor, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the first and second electrodes of the driving transistor on the substrate.

[0015] In some embodiments, in a pixel, the second sub-pixel and the third sub-pixel are located on the same side of the first sub-pixel; and the second sub-pixel and the third sub-pixel are arranged along a second direction;

[0016] The first spacing is equal to the second spacing;

[0017] The third spacing is smaller than the first spacing.

[0018] In some embodiments, the first sub-pixel and the third sub-pixel are arranged along a first direction;

[0019] The first direction is perpendicular to the second direction.

[0020] In some embodiments, in a pixel, the size of the first sub-pixel along the second direction is equal to the sum of the sizes of the second sub-pixel, the third sub-pixel, and the interval between them along the second direction;

[0021] The size of the first sub-pixel along the first direction is smaller than the size of either the second or third sub-pixel along the first direction.

[0022] In some embodiments, the orthographic projection of the first conductive layer onto the substrate lies in the gap between at least partially adjacent pixels along a first direction.

[0023] In some embodiments, the dimension of the first conductive layer along the second direction is equal to the sum of the dimensions of two adjacent pixels along the second direction and the spacing between them;

[0024] The dimension of the first conductive layer along the first direction is smaller than the dimension of the first sub-pixel along the first direction.

[0025] In some embodiments, the first spacing is equal to the second spacing;

[0026] The third spacing is equal to the sum of the first spacing, the second spacing, and the width of the first sub-pixel along the first direction.

[0027] In some embodiments, the second sub-pixel, the first sub-pixel, and the third sub-pixel are arranged sequentially along a first direction.

[0028] In some embodiments, the dimension of the first conductive layer along the first direction is greater than the sum of the dimensions of the first sub-pixel and the second sub-pixel along the first direction; or, the dimension of the first conductive layer along the first direction is greater than the sum of the dimensions of the first sub-pixel and the third sub-pixel along the first direction;

[0029] The dimension of the first conductive layer along the second direction is smaller than the dimension of the first sub-pixel along the second direction.

[0030] In some embodiments, the first spacing is smaller than the second spacing;

[0031] The second spacing is equal to the sum of the first spacing, the width of the second sub-pixel along the first direction, and the third spacing.

[0032] In some embodiments, in a pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel are arranged sequentially along a first direction.

[0033] In some embodiments, in a pixel, the size of the first sub-pixel along the second direction is smaller than the size of either the second sub-pixel or the third sub-pixel along the second direction;

[0034] The size of the first sub-pixel along the first direction is smaller than the size of either the second sub-pixel or the third sub-pixel along the first direction;

[0035] The first direction is perpendicular to the second direction.

[0036] In some embodiments, the orthographic projection of the first conductive layer onto the substrate lies in the gap between at least partially adjacent pixels along the second direction.

[0037] In some embodiments, the dimension of the first conductive layer along the first direction is smaller than the first spacing or the second spacing;

[0038] The dimension of the first conductive layer along the second direction is smaller than the dimension of the first sub-pixel along the second direction.

[0039] In some embodiments, any two adjacent rows of pixels arranged along the second direction are mirror-symmetric.

[0040] Alternatively, any two adjacent columns of pixels arranged along the first direction are mirror-symmetric.

[0041] In some embodiments, in the pixel array, each row of pixels is arranged along the second direction;

[0042] The second sub-pixels in each row of pixels are arranged along the second direction;

[0043] The third sub-pixel in each row of pixels is arranged along the second direction;

[0044] The first sub-pixel in each row is arranged along the second direction.

[0045] In some embodiments, in the pixel array, each row of pixels is arranged along the second direction;

[0046] The first sub-pixels of the pixels in the (2n+1)th and (2n+2)th rows are arranged along the second direction; where n is an integer, n = 0, 1, 2, ...

[0047] In some embodiments, the first sub-pixel is a blue sub-pixel; the second sub-pixel is a red sub-pixel; and the third sub-pixel is a green sub-pixel.

[0048] Alternatively, the first sub-pixel is a blue sub-pixel; the second sub-pixel is a green sub-pixel; and the third sub-pixel is a red sub-pixel.

[0049] In some embodiments, the first via is formed in the insulating layer and is used to connect the anodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel to the first pole of the driving transistor in their respective pixel circuits.

[0050] In some embodiments, a second via is further provided in the insulating layer for connecting the first conductive layer to the second conductive layer;

[0051] The orthographic projection of the second via on the substrate lies between two adjacent pixels along the second direction.

[0052] In some embodiments, the spacing range of the first spacing and the second spacing in a pixel is 7-25 μm, respectively.

[0053] In some embodiments, the orthographic projections of the first via and the second via in the first direction do not overlap.

[0054] In some embodiments, the orthographic projections of the first via and the second via in the first direction at least partially overlap.

[0055] In some embodiments, a pixel defining layer is further included, located on the side of the insulating layer opposite to the substrate;

[0056] The first sub-pixel, the second sub-pixel, and the third sub-pixel are located in the regions defined by the pixel boundary layer;

[0057] The first sub-pixel, the second sub-pixel, and the third sub-pixel each further include a light-emitting functional layer and a cathode; the light-emitting functional layer and the cathode are disposed sequentially away from the anode; and the orthographic projections of the light-emitting functional layer and the cathode on the substrate at least partially overlap with the orthographic projections of the anode on the substrate;

[0058] The pixel defining layer has an opening in the region corresponding to the first conductive layer; the light-emitting functional layer and the cathode also extend into the opening, and the portions of the light-emitting functional layer and the cathode located inside the opening are disconnected from the portions located outside the opening at the edge of the opening.

[0059] The portion of the cathode outside the opening covers the broken edge of the light-emitting functional layer at the edge of the opening, and the portion of the cathode outside the opening also extends to contact at least a portion of the edge end face of the first conductive layer.

[0060] In some embodiments, the first conductive layer includes a first sublayer, a second sublayer, and a third sublayer stacked sequentially along a direction away from the substrate;

[0061] The cross-sectional shape of the first conductive layer perpendicular to the substrate includes an "I" shape or an inverted trapezoidal shape;

[0062] The portion of the cathode outside the opening is in contact with at least the edge faces of the second and third sublayers.

[0063] In some embodiments, the aperture ratio of the second sub-pixel, the third sub-pixel, and the first sub-pixel in a pixel ranges from 2:2:1 to 3:2:1.

[0064] In some embodiments, the orthographic projection shapes of the second sub-pixel, the third sub-pixel, and the first sub-pixel on the substrate include rectangles.

[0065] In some embodiments, the first sub-pixel, the second sub-pixel, and the third sub-pixel each further include a color conversion layer located on the side of the cathode away from the light-emitting functional layer;

[0066] The luminescent functional layer emits blue light;

[0067] The color conversion layer is used to convert the color of blue light.

[0068] In some embodiments, the color conversion layer includes a first color conversion unit, a second color conversion unit, and a first transmission unit;

[0069] The orthographic projection of the first color conversion unit onto the substrate covers the orthographic projection of the second sub-pixel onto the substrate;

[0070] The orthographic projection of the second color conversion unit onto the substrate covers the orthographic projection of the third sub-pixel onto the substrate;

[0071] The orthographic projection of the first transmission unit on the substrate covers the orthographic projection of the first sub-pixel on the substrate.

[0072] In some embodiments, the system further includes a barrier and a first black matrix located on the side of the pixel delimiting layer away from the substrate, with the first black matrix and the barrier disposed sequentially away from the pixel delimiting layer.

[0073] The orthographic projections of the retaining wall and the first black matrix onto the substrate at least partially overlap with the orthographic projections of the pixel defining layer onto the substrate.

[0074] In some embodiments, the first sub-pixel, the second sub-pixel, and the third sub-pixel each further include a color resist layer located on the side of the color conversion layer away from the substrate;

[0075] The color resist layer includes a first color resist, a second color resist, and a third color resist;

[0076] The orthographic projection of the first color block on the substrate falls within the orthographic projection of the first color conversion unit on the substrate;

[0077] The orthographic projection of the second color block onto the substrate falls within the orthographic projection of the second color conversion unit onto the substrate;

[0078] The orthographic projection of the third color block on the substrate falls within the orthographic projection of the first transmission unit on the substrate.

[0079] In some embodiments, a second black matrix is ​​also included, located on the side of the retaining wall away from the base;

[0080] The orthographic projection of the second black matrix onto the substrate falls within the orthographic projection of the first black matrix onto the substrate.

[0081] In some embodiments, the projected areas of the multiple pixel circuits on the substrate are equal.

[0082] In some embodiments, the orthographic projections of the first sub-pixel, the second sub-pixel, and the third sub-pixel onto the substrate and the orthographic projections of the pixel circuits electrically connected thereto onto the substrate do not overlap at least partially.

[0083] In some embodiments, the system further includes a first encapsulation layer, a second encapsulation layer, and an anti-reflective layer;

[0084] The first encapsulation layer is located on the side of the cathode away from the substrate and on the side of the color conversion layer closer to the cathode;

[0085] The second encapsulation layer is located on the side of the color conversion layer away from the substrate and on the side of the color resist layer close to the color conversion layer;

[0086] The anti-reflective layer is located on the side of the color resist layer that faces away from the substrate.

[0087] Secondly, embodiments of this disclosure also provide a display panel, including the aforementioned display substrate.

[0088] Thirdly, embodiments of this disclosure also provide a display device, including the aforementioned display panel. Attached Figure Description

[0089] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0090] Figure 1 This is a schematic diagram of the pixel arrangement in an OLED display panel in the disclosed technology;

[0091] Figure 2a This is a schematic diagram illustrating the optical crosstalk caused by a blue subpixel to its surrounding red and green subpixels in the disclosed technology.

[0092] Figure 2bThis is a schematic diagram illustrating the optical crosstalk caused by red and green subpixels to their surrounding blue subpixels in the disclosed technology.

[0093] Figure 2c This is a schematic diagram illustrating optical crosstalk between red and green sub-pixels in the disclosed technology.

[0094] Figure 3 This is a schematic diagram of a pixel arrangement in a display substrate according to an embodiment of the present disclosure.

[0095] Figure 4 For along Figure 3 A structural cross-sectional view along section AA.

[0096] Figure 5 This is an improved diagram showing the spacing between the first and second sub-pixels.

[0097] Figure 6 This is a schematic diagram showing the spacing between the first and second sub-pixels after the improvement.

[0098] Figure 7 For along Figure 3 A structural cross-sectional view along the BB section line.

[0099] Figure 8 This is a schematic diagram showing the arrangement of the first and second vias in an embodiment of this disclosure.

[0100] Figure 9 This is a schematic diagram showing another arrangement of the first and second vias in an embodiment of this disclosure.

[0101] Figure 10 This is a schematic diagram of another pixel arrangement in the display substrate according to an embodiment of the present disclosure.

[0102] Figure 11 This is a schematic diagram of another pixel arrangement in the display substrate according to an embodiment of the present disclosure.

[0103] Figure 12 This is a schematic diagram of another pixel arrangement in the display substrate according to an embodiment of the present disclosure.

[0104] Figure 13 This is a schematic diagram of another pixel arrangement in the display substrate according to an embodiment of the present disclosure.

[0105] Figure 14 This is a schematic diagram of another pixel arrangement in the display substrate according to an embodiment of the present disclosure.

[0106] Figure 15a This is a conductive layer pattern of a plate located on a substrate in a multi-pixel circuit, used to form one of the plates of a capacitor in the pixel circuit, as well as patterns of connecting vias and signal traces.

[0107] Figure 15b For multiple pixel circuits located in Figure 15a The pattern of the active layer of the transistor is opposite to the pattern of the conductive layer.

[0108] Figure 15c This refers to the pattern of vias in an insulating layer located on the side of the active layer pattern away from the substrate in a multi-pixel circuit.

[0109] Figure 15d This is a pattern of the transistor source / drain electrode layer, the second conductive layer, and other conductive structures located on the side of the insulating layer away from the substrate in a multi-pixel circuit.

[0110] Figure 15e for Figure 15a , Figure 15b , Figure 15c and Figure 15d A top view of multiple pixel circuits after the various film layers are stacked in sequence.

[0111] Figure 16a This is a pattern of an anode, a first conductive layer, and a via formed in an insulating layer on a display substrate, located on the side of the transistor source / drain electrode layer pattern facing away from the substrate.

[0112] Figure 16b This is a pattern of an opening formed in the pixel defining layer on the display substrate, located on the side opposite to the anode.

[0113] Figure 16c This is a pattern of a barrier wall and a first black matrix located on the pixel defining layer of a display substrate, facing away from the substrate.

[0114] Figure 16d This is a pattern of a color conversion layer on a display substrate located within the area separated by the barrier.

[0115] Figure 16e for Figures 15a-15d as well as Figures 16a-16d The top view of the display substrate after the various film layers are stacked in sequence.

[0116] Figure 17a This is a conductive layer pattern of a plate located on a substrate in a multi-pixel circuit, used to form one of the plates of a capacitor in the pixel circuit, as well as patterns of connecting vias and signal traces.

[0117] Figure 17b For multiple pixel circuits located in Figure 15a The pattern of the active layer of the transistor is opposite to the pattern of the conductive layer.

[0118] Figure 17c This refers to the pattern of vias in an insulating layer located on the side of the active layer pattern away from the substrate in a multi-pixel circuit.

[0119] Figure 17d This is a pattern of the transistor source / drain electrode layer, the second conductive layer, and other conductive structures located on the side of the insulating layer away from the substrate in a multi-pixel circuit.

[0120] Figure 18a This is a pattern of an anode, a first conductive layer, and a via formed in an insulating layer on a display substrate, located on the side of the transistor source / drain electrode layer pattern facing away from the substrate.

[0121] Figure 18b This is a pattern of an opening formed in the pixel defining layer on the display substrate, located on the side opposite to the anode.

[0122] Figure 18c This is a pattern of a barrier wall and a first black matrix located on the pixel defining layer of a display substrate, facing away from the substrate.

[0123] Figure 18d This is a pattern of a color conversion layer on a display substrate located within the area separated by the barrier.

[0124] Figure 18e for Figures 17a-17d as well as Figures 18a-18d The top view of the display substrate after the various film layers are stacked in sequence. Detailed Implementation

[0125] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the display substrate, display panel and display device provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0126] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0127] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0128] In publicly available technologies, OLED display panels (i.e., QD-OLED display panels) that use quantum dots (QD) as the color conversion layer and OLEDs as the light-emitting elements can achieve high color gamut display while exhibiting relatively good color bias. (See reference...) Figure 1In a large-size QD-OLED display panel, multiple pixels 2 are arranged in an array. Each pixel may contain adjacent red sub-pixels 151, green sub-pixels 152, and blue sub-pixels 153. Pixel 2 includes a vertically arranged light-emitting element and a color conversion layer. The light-emitting element emits blue light, and the color conversion layer includes a first color conversion unit, a second color conversion unit, and a first transmission unit. Specifically, the blue light emitted by the light-emitting element is converted into red light by the first color conversion unit and emitted; the blue light emitted by the light-emitting element is converted into green light by the second color conversion unit and emitted; the first transmission unit may contain scattering particles, and the blue light emitted by the light-emitting element, after passing through the first transmission unit, can still be emitted as blue light after being scattered by the scattering particles. However, the blue sub-pixel 153, due to its thicker cell, may crosstalk to adjacent sub-pixels emitting other colors of light, causing light leakage between adjacent sub-pixels, ultimately resulting in a poor color gamut for the OLED display panel.

[0129] Specifically, the optical crosstalk between adjacent sub-pixels is referenced. Figure 2a , Figure 2b and Figure 2c Because OLED display panels have a relatively thick cell (the cell thickness is the distance between the surface of the encapsulation layer near the light-emitting layer of the subpixel and the pixel circuit substrate of the OLED display panel), under a certain cell thickness, the blue light emitted by the light-emitting element in the blue subpixel will illuminate the quantum dot color conversion units of the adjacent red and green subpixels, exciting the first color conversion unit to emit red light and the second color conversion unit to emit green light, causing optical crosstalk. (Refer to...) Figure 2a In this case, since some of the blue light emitted by the light-emitting element of the blue sub-pixel is converted through the first transmission unit, crosstalk will affect the light conversion efficiency. Simultaneously, the blue light emitted by the light-emitting elements in the red and green sub-pixels will also illuminate the first transmission unit of the blue sub-pixel. The light scattered by the first transmission unit causes optical crosstalk, but in this case, there is no impact on the crosstalk light conversion efficiency. (Refer to...) Figure 2b Furthermore, the blue light emitted by the light-emitting elements in the red sub-pixel and the blue light emitted by the light-emitting elements in the green sub-pixel will also illuminate each other's quantum dot conversion layers, causing optical crosstalk. (Refer to...) Figure 2c .

[0130] The actual test revealed that the light crosstalk between the red and green sub-pixels was relatively small, while the light crosstalk between the blue sub-pixel and other color sub-pixels was the most serious, which could easily lead to serious light leakage between sub-pixels. This was not conducive to improving the color gamut of the OLED display panel, and thus would seriously affect the display effect of the OLED display panel.

[0131] To address the severe optical crosstalk problem between blue subpixels and other color subpixels in QD-OLED display panels, this disclosure provides the following technical solution.

[0132] Firstly, referring to Figure 3 , Figures 10-14 This disclosure provides a display substrate, including: a substrate 1; a plurality of pixel circuits disposed on the substrate 1; a plurality of pixels 2 arranged in an array and located on the side of the pixel circuits facing away from the substrate 1; each pixel 2 includes a first sub-pixel 21, a second sub-pixel 220, and a third sub-pixel 221; the orthographic projections of the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 on the substrate 1 do not overlap; the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 are electrically connected to the pixel circuits one-to-one; a first spacing is provided between the first sub-pixel 21 and the second sub-pixel 220 along a first direction Y, and a first via 41 is provided in the first spacing; a second spacing is provided between the first sub-pixel 21 and the third sub-pixel 221 along the first direction Y, and a first via 41 is provided in the second spacing; a third spacing is provided between the second sub-pixel 220 and the third sub-pixel 221 along the first direction Y.

[0133] In some embodiments, refer to Figure 3 and Figure 4 The pixel circuit includes a driving transistor 3 and an insulating layer 4; the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 each include an anode 201; the driving transistor 3, the insulating layer 4, and the anode 201 are sequentially disposed away from the substrate 1. A first via 41 is formed in the insulating layer 4 for connecting the anodes 201 of the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 to the first pole of the driving transistor 3 in their respective pixel circuits.

[0134] In some embodiments, by positioning the first via 41 within the first and second spacing, the first and second spacings can be increased from approximately 10 μm in the disclosed technology to 15–25 μm. This significantly improves or avoids light crosstalk between the first sub-pixel 21 and the second and third sub-pixels 220, thereby significantly improving or avoiding light leakage between the first sub-pixel 21 and the second and third sub-pixels 221. This is beneficial for improving the color gamut of the display substrate and ultimately enhancing the display effect of the display substrate. (Referring to...) Figure 5 and Figure 2aBefore the improvement, the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 was the spacing between the adjacent edges of adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221. For example, the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 was the sum of the following dimensions along the first direction Y: the size b1 of the overlapping region between the anode of the first sub-pixel 21 and the orthogonal projection of the pixel boundary layer located between adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221, the size b2 of the portion of the pixel boundary layer that does not overlap with the anodes of adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221, and the size b3 of the overlapping region between the anode of the second sub-pixel 220 or third sub-pixel 221 and the orthogonal projection of the pixel boundary layer located between adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221; for example: b1 + b2 + b3 = 3.5 + 4 + 3.5 = 11 μm. (Refer to...) Figure 6 and Figure 4 After the improvement, the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 is the spacing between the adjacent edges of the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 along the first direction Y plus the size p of the first via 41 along the first direction Y. For example, if the first via 41 is a 6×6μm square via, the size p of the first via 41 along the first direction Y is 6μm; then the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 after the improvement is: b1+b2+b3+p=3.5+4+3.5+6=17μm.

[0135] In this embodiment, while keeping the thickness of the display substrate constant, the arrangement of the pixel circuits remains unchanged. By changing the arrangement of the sub-pixels, the first via 41, which is at least partially located in the area where the sub-pixels are located in the disclosed technology, is completely located in the first spacing area between the first sub-pixel 21 and the second sub-pixel 220 and the second spacing area between the first sub-pixel 21 and the third sub-pixel 221. Compared with the arrangement of sub-pixels in the disclosed technology, the first spacing between the first sub-pixel 21 and the second sub-pixel 220 and the second spacing between the first sub-pixel 21 and the third sub-pixel 221 can be increased. This can greatly improve or avoid light crosstalk between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221, and thus greatly improve or avoid light leakage between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221. This is beneficial to improving the color gamut of the display substrate and ultimately improving the display effect of the display substrate.

[0136] In some embodiments, refer to Figure 3 , Figure 4 and Figure 7The pixel circuit also includes an auxiliary electrode 6; the auxiliary electrode 6 includes a first conductive layer 61, which is located on the same film layer as the anode 201, and the orthographic projection of the first conductive layer 61 on the substrate 1 does not overlap with the orthographic projection of the anode 201 on the substrate 1; the auxiliary electrode 6 also includes a second conductive layer 62, which is located on the same film layer as the first electrode 31 and the second electrode 32 of the driving transistor 3, and the orthographic projection of the second conductive layer 62 on the substrate 1 does not overlap with the orthographic projection of the first electrode 31 and the second electrode 32 of the driving transistor 3 on the substrate 1.

[0137] In some embodiments, the insulating layer 4 is further provided with a second via 42 for connecting the first conductive layer 61 to the second conductive layer 62; the orthographic projection of the second via 42 on the substrate 1 is located between two adjacent pixels 2 along the second direction X.

[0138] Specifically, by positioning the orthographic projection of the second via 42 onto the substrate 1 between two adjacent pixels 2 along the second direction X, compared to the arrangement of subpixels in the disclosed technology where the second via 42 is at least partially located in the subpixel region, the first and second spacings can be further increased. This can significantly improve or avoid light crosstalk between the first subpixel 21 and the second and third subpixels 220, thereby significantly improving or avoiding light leakage between the first subpixel 21 and the second and third subpixels 221. This is beneficial for improving the color gamut of the display substrate and ultimately enhancing the display effect of the display substrate.

[0139] In some embodiments, refer to Figure 8 The orthographic projections of the first via 41 and the second via 42 in the first direction Y do not overlap. This ensures that the spacing between adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221 not only increases the dimension p of the first via 41 along the first direction Y, but also increases the dimension n of the second via 42 along the first direction Y. This further increases the spacing between adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221, thereby significantly improving or preventing light crosstalk between the first sub-pixels 21 and the second and third sub-pixels 221.

[0140] In some embodiments, refer to Figure 9The orthographic projections of the first via 41 and the second via 42 in the first direction Y at least partially overlap. Specifically, if the orthographic projections of the first via 41 and the second via 42 in the first direction Y partially overlap, the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 will increase. If the orthographic projections of the first via 41 and the second via 42 completely overlap, and the orthographic projection size of the first via 41 in the first direction Y is larger than the orthographic projection size of the second via 42 in the first direction Y, the spacing between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 will also increase. This further increases the spacing between adjacent first sub-pixels 21 and second sub-pixels 220 or third sub-pixels 221, thereby significantly improving or preventing light crosstalk between the first sub-pixel 21 and the second and third sub-pixels 220 and 221.

[0141] In some embodiments, the spacing range of the first spacing and the second spacing in pixel 2 is 7-25μm. By setting the first via 41 and the second via 42 within the first spacing and the second spacing as described above, the first spacing and the second spacing can be increased from the smaller spacing before the sub-pixel arrangement was improved to the larger spacing after the sub-pixel arrangement was improved, thereby greatly improving or avoiding light crosstalk between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221.

[0142] In this embodiment, by adjusting the arrangement of sub-pixels, the first via 41 and the second via 42 are located within the first spacing and the second spacing. The distribution position of the first via 41 and the second via 42 ensures that it will not affect the aperture ratio of the sub-pixels and the resolution of the display substrate. That is, the resolution of the display substrate and the aperture ratio of the sub-pixels will not change due to the change in the distribution position of the first via 41 and the second via 42.

[0143] In some embodiments, refer to Figure 4 and Figure 7The display substrate also includes a pixel defining layer 5, located on the side of the insulating layer 4 facing away from the substrate 1; the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 are respectively located in the area defined by the pixel defining layer 5; the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 also include a light-emitting functional layer 202 and a cathode 203; the light-emitting functional layer 202 and the cathode 203 are sequentially disposed away from the anode 201; and the orthographic projections of the light-emitting functional layer 202 and the cathode 203 on the substrate 1 are at least partially the same as the orthographic projections of the anode 201 on the substrate 1. The overlapping portions constitute light-emitting elements; the pixel defining layer 5 forms an opening in the region corresponding to the first conductive layer 61; the light-emitting functional layer 202 and the cathode 203 also extend into the opening, and the portions of the light-emitting functional layer 202 and the cathode 203 located inside the opening and the portions located outside the opening are disconnected from each other at the edge of the opening; the portion of the cathode 203 located outside the opening covers the disconnected edge of the light-emitting functional layer 202 at the edge of the opening, and the portion of the cathode 203 located outside the opening also extends to contact at least a portion of the edge end face of the first conductive layer 61.

[0144] In this design, the cathode 203 contacts the first conductive layer 61 at the edge of the opening in the pixel defining layer 5, thus establishing a connection between the two. The first conductive layer 61 is also connected to the second conductive layer 62 via the second via 42, thereby achieving interconnection between the cathode 203 and the first and second conductive layers 61, and consequently, interconnection between the cathode 203 and the auxiliary electrode 6. In top-emitting OLED display substrates, due to the light transmittance requirement for the cathode 203, the cathode 203 typically has a thinner film and higher resistance. The auxiliary electrode 6 can increase the cross-sectional area of ​​the cathode 203, thereby reducing its resistance. This results in a smaller voltage drop across the cathode 203 and a more uniform voltage distribution across the entire cathode 203, improving the display uniformity and brightness of the display substrate and ultimately enhancing its display performance.

[0145] In some embodiments, refer to Figure 7 The first conductive layer 61 includes a first sublayer 611, a second sublayer 612, and a third sublayer 613 stacked sequentially along a direction away from the substrate 1; the cross-sectional shape of the first conductive layer 61 perpendicular to the substrate 1 includes an "I" shape or an inverted trapezoidal shape; the portion of the cathode 203 located outside the opening is in contact with at least the edge faces of the second sublayer 612 and the third sublayer 613. Wherein, if the cross-sectional shape of the first conductive layer 61 is an "I" shape, refer to... Figure 7If the cross-sectional shape of the first sublayer 611 and the third sublayer 613 is greater than the cross-sectional width of the second sublayer 612, then the width of the third sublayer 613 is greater than the width of the second sublayer 612, and the width of the second sublayer 612 is greater than the width of the first sublayer 611. The width of any sublayer in cross-section refers to its dimension perpendicular to the direction away from the substrate 1. The cross-sectional shape of the first conductive layer 61 is due to conventional fabrication processes and will not be elaborated upon here; it is sufficient to ensure that the cathode 203 can make good contact with the edge face of the first conductive layer 61.

[0146] In some embodiments, the anode 201 and the first conductive layer 61 have the same sublayer stacked structure, that is, the anode 201 is also composed of three sublayers stacked together. This reduces the resistance of the anode 201 and improves the display effect. The first sublayer 611 and the third sublayer 613 can be made of materials such as indium tin oxide, and the second sublayer 612 can be made of materials such as aluminum. The three sublayer materials of the anode 201 are the same as the three sublayer materials of the first conductive layer 61, thus allowing it to be fabricated in a single patterning process, simplifying the fabrication process. The anode 201 is opaque and can reflect light incident upon it, thereby realizing a top-emitting OLED display substrate. Of course, the anode 201 can also be transparent. In this case, a reflective layer can be provided on the side of the anode 201 near the substrate 1 to reflect light incident upon it, thereby realizing a top-emitting OLED display substrate. Top-emitting OLED display substrates can achieve a larger display aperture ratio.

[0147] In some embodiments, refer to Figure 3 , Figure 10 and Figure 11 In pixel 2, the second sub-pixel 220 and the third sub-pixel 221 are located on the same side of the first sub-pixel 21; and the second sub-pixel 220 and the third sub-pixel 221 are arranged along the second direction X; the first spacing is equal to the second spacing; and the third spacing is less than the first spacing.

[0148] In some embodiments, refer to Figure 3 The first sub-pixel 21 and the third sub-pixel 221 are arranged along the first direction Y; the first direction Y is perpendicular to the second direction X.

[0149] In some embodiments, refer to Figure 3 In pixel 2, the size of the first sub-pixel 21 along the second direction X is equal to the sum of the sizes of the second sub-pixel 220, the third sub-pixel 221 and the interval between them along the second direction X; the size of the first sub-pixel 21 along the first direction Y is smaller than the size of either the second sub-pixel 220 or the third sub-pixel 221 along the first direction Y.

[0150] In the design of sub-pixel apertures, a balance needs to be struck between the luminous efficiency and lifetime of the quantum pixels. Since the first sub-pixel 21 accounts for a small proportion in color mixing and does not involve the excitation and conversion of the quantum dot color conversion layer, its relative luminous efficiency is high, its sub-pixel current is low, and its lifetime is long. In contrast, the second sub-pixel 220 and the third sub-pixel 221 convert blue light to red and green light respectively through the excitation of the quantum dot color conversion layer, resulting in relatively lower luminous efficiency, higher sub-pixel current, and shorter lifetimes. The sub-pixel aperture ratio and its lifetime ratio can be calculated using the following formula.

[0151] LTpixel=LTltc×(Jltc / Jpixel) a …Formula (1)

[0152] Jpixel=Ipixel / (S×AR)…Formula (2)

[0153] Where a is the acceleration factor, which is a fixed value; LTpixel is the subpixel lifetime; LTltc is the measurable lifetime of the OLED light-emitting element (including the anode, light-emitting functional layer, and cathode); Jpixel is the subpixel current density; Jltc is the current density of a given OLED light-emitting element; Ipixel is the subpixel current; S is the subpixel aperture area; and AR is the subpixel aperture ratio.

[0154] When the color point efficiency and other data of a sub-pixel are fixed, the lifespan of the sub-pixel depends on its aperture ratio AR. In an OLED display substrate using a quantum dot color conversion layer, the minimum aperture required for the first sub-pixel can be calculated using the above formula. For example, when the current efficiencies of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 are 2.3cd / A, 5.8cd / A, and 1.7cd / A, respectively, and combined with the white point or color point information of their respective pixel 2, if the lifespans of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 are allocated in a ratio of 1:1:1.5, then according to the above formulas (1) and (2), the aperture ratio ratio of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 can be calculated to be 2.75:2.4:1, that is, the minimum aperture required for the first sub-pixel 21; the actual aperture ratio can be adjusted according to the white point target of the pixel 2 to which the sub-pixel belongs and the color point and efficiency data achieved by the actual process.

[0155] In some embodiments, refer to Figure 3 and Figure 7 The orthographic projection of the first conductive layer 61 onto the substrate 1 is located in the gap between at least partially adjacent pixels 2 along the first direction Y.

[0156] In some embodiments, refer to Figure 3 and Figure 7 The dimension of the first conductive layer 61 along the second direction X is equal to the sum of the dimensions of two adjacent pixels 2 along the second direction X and the spacing between them; the dimension of the first conductive layer 61 along the first direction Y is smaller than the dimension of the first sub-pixel 21 along the first direction Y. The size of the projected area of ​​the first conductive layer 61 on the substrate 1 affects both the resistance of the cathode and the aperture ratio of the sub-pixels and the resolution of the display substrate. In this embodiment, the distribution of the first conductive layer 61 ensures that it does not affect the aperture ratio of the sub-pixels and the resolution of the display substrate; that is, the resolution of the display substrate and the aperture ratio of the sub-pixels will not change because the first conductive layer 61 occupies a portion of the area.

[0157] In some embodiments, sub-pixels can also be as follows: Figure 10 and Figure 11 Arranged in the middle. Figure 10 and Figure 11 Neutron pixel arrangement and Figure 3 The arrangement of neutron pixels is similar.

[0158] In some embodiments, refer to Figure 12 and Figure 14 The first spacing is equal to the second spacing; the third spacing is equal to the sum of the first spacing, the second spacing, and the width of the first sub-pixel 21 along the first direction Y.

[0159] In some embodiments, the subpixels may also be arranged as follows: (See reference...) Figure 12 and Figure 14 The second sub-pixel 220, the first sub-pixel 21, and the third sub-pixel 221 are arranged sequentially along the first direction Y.

[0160] In some embodiments, refer to Figure 12 The size of the first conductive layer along the first direction Y is greater than the sum of the sizes of the first sub-pixel 21 and the second sub-pixel 220 along the first direction Y; or, the size of the first conductive layer along the first direction Y is greater than the sum of the sizes of the first sub-pixel 21 and the third sub-pixel 221 along the first direction Y; the size of the first conductive layer along the second direction X is less than the size of the first sub-pixel 21 along the second direction X.

[0161] In some embodiments, refer to Figure 13 The first spacing is less than the second spacing; the second spacing is equal to the sum of the first spacing, the width of the second sub-pixel 220 along the first direction Y, and the third spacing.

[0162] In some embodiments, in pixel 2, the second sub-pixel 220, the third sub-pixel 221 and the first sub-pixel 21 are arranged sequentially along the first direction Y.

[0163] In some embodiments, refer to Figure 12 , Figure 13 and Figure 14 In pixel 2, the size of the first sub-pixel 21 along the second direction X is smaller than the size of either the second sub-pixel 220 or the third sub-pixel 221 along the second direction X; the size of the first sub-pixel 21 along the first direction Y is smaller than the size of either the second sub-pixel 220 or the third sub-pixel 221 along the first direction Y; the first direction Y is perpendicular to the second direction X.

[0164] In some embodiments, the orthographic projection of the first conductive layer onto the substrate is located in the gap region between at least a portion of adjacent pixels 2 along the second direction X.

[0165] In some embodiments, refer to Figure 10 , Figure 13 and Figure 14 The size of the first conductive layer along the first direction Y is smaller than the first spacing or the second spacing; the size of the first conductive layer along the second direction X is smaller than the size of the first sub-pixel 21 along the second direction X.

[0166] In some embodiments, refer to Figure 10 Any two adjacent rows of pixels arranged along the second direction X are mirror-symmetric. (Refer to...) Figure 13 and Figure 14 Any two adjacent columns of pixels arranged along the first direction Y are mirror-symmetric.

[0167] In some embodiments, refer to Figure 12 , Figure 13 and Figure 14 In the pixel array 2, each row of pixels 2 is arranged along the second direction X; the second sub-pixels 220 in each row of pixels 2 are arranged along the second direction X; the third sub-pixels 221 in each row of pixels 2 are arranged along the second direction X; and the first sub-pixels 21 in each row of pixels 2 are arranged along the second direction X. This simplifies and makes the subsequent fabrication of the first transmission unit corresponding to the first sub-pixel 21 and the color conversion units corresponding to the second sub-pixels 220 and third sub-pixels 221 through printing or coating processes.

[0168] In some embodiments, refer to Figure 11 and Figure 13 In the pixel array 2, each row of pixels 2 is arranged along the second direction X; the first sub-pixels 21 of pixels 2 in the (2n+1)th and (2n+2)th rows are arranged along the second direction X; where n is an integer, n = 0, 1, 2... This makes the subsequent fabrication of the scattering particle layer corresponding to the first sub-pixel 21 through printing or coating processes simpler and easier to implement.

[0169] In some embodiments, the first sub-pixel 21 is a blue sub-pixel; the second sub-pixel 220 is a red sub-pixel; and the third sub-pixel 221 is a green sub-pixel.

[0170] In some embodiments, refer to Figure 3 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 In pixel 2, the aperture ratio of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 ranges from 2:2:1 to 3:2:1. For example, in pixel 2, the aperture ratio of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 is 2.75:2.4:1. Thus, according to the aforementioned formula for calculating the aperture ratio and lifespan of sub-pixels, this aperture ratio can achieve a lifespan ratio of 1:1:1.5 for the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21. This ensures a balance between the aperture ratio and lifespan of the sub-pixels, thereby improving the display effect of the display substrate while ensuring the longest possible display lifespan.

[0171] In some embodiments, refer to Figure 3 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 In pixel 2, the orthographic projection shapes of the second sub-pixel 220, the third sub-pixel 221, and the first sub-pixel 21 on the substrate 1 include rectangles. This simplifies and makes the subsequent fabrication of the first transmission unit corresponding to the first sub-pixel 21 and the color conversion units corresponding to the second sub-pixel 220 and the third sub-pixel 221 through printing or coating processes.

[0172] In some embodiments, refer to Figure 4 The first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 each also include a color conversion layer 7, located on the side of the cathode 203 away from the light-emitting functional layer 202; the light-emitting functional layer 202 emits blue light; the color conversion layer 7 is used to convert the blue light.

[0173] In some embodiments, refer to Figure 4The color conversion layer 7 includes a first color conversion unit 71, a second color conversion unit 72, and a first transmission unit 73. The orthographic projection of the first color conversion unit 71 onto the substrate 1 covers the orthographic projection of the second sub-pixel 220 onto the substrate 1. The orthographic projection of the second color conversion unit 72 onto the substrate 1 covers the orthographic projection of the third sub-pixel onto the substrate 1. The orthographic projection of the first transmission unit 73 onto the substrate 1 covers the orthographic projection of the first sub-pixel 21 onto the substrate 1. The first color conversion unit 71 converts the blue light emitted by the light-emitting functional layer 202 in its corresponding sub-pixel into red light by exciting the quantum dots therein. The second color conversion unit 72 converts the blue light emitted by the light-emitting functional layer 202 in its corresponding sub-pixel into green light by exciting the quantum dots therein. The first transmission unit 73 further scatters the blue light emitted by the light-emitting functional layer 202 in its corresponding sub-pixel through the scattering particles therein.

[0174] In some embodiments, refer to Figure 4 The display substrate also includes a barrier 8 and a first black matrix 9, located on the side of the pixel defining layer 5 facing away from the substrate 1, with the first black matrix 9 and the barrier 8 sequentially positioned away from the pixel defining layer 5; the orthographic projections of the barrier 8 and the first black matrix 9 onto the substrate 1 at least partially overlap with the orthographic projection of the pixel defining layer 5 onto the substrate 1. The barrier 8 separates the color conversion layers 7 corresponding to different color sub-pixels to prevent crosstalk between the light rays of adjacent sub-pixels during color conversion by the color conversion layers 7. The first black matrix 9 also blocks the light emitted from adjacent sub-pixels from shining onto their corresponding color conversion layers 7, thereby preventing crosstalk between the light rays of adjacent sub-pixels during color conversion by the color conversion layers 7.

[0175] In some embodiments, refer to Figure 4 The first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 each further include a color resist layer 10, located on the side of the color conversion layer 7 away from the substrate 1; the color resist layer 10 includes a first color resist 101, a second color resist 102, and a third color resist 103; the orthographic projection of the first color resist 101 on the substrate 1 falls within the orthographic projection of the first color conversion unit 71 on the substrate 1; the orthographic projection of the second color resist 102 on the substrate 1 falls within the orthographic projection of the second color conversion unit 72 on the substrate 1; and the orthographic projection of the third color resist 103 on the substrate 1 falls within the orthographic projection of the first transmission unit 73 on the substrate 1. The color of the first color resist 101 is the same as the color converted by the first color conversion unit 71; the color of the second color resist 102 is the same as the color converted by the second color conversion unit 72; the color of the third color resist 103 is the same as the light emission color of the light emission functional layer of the first sub-pixel 21; the color resist layer 10 can filter the light color that has not been converted after being converted by the color conversion layer 7, thereby further improving the purity of the display color of each sub-pixel, and thus improving the display effect.

[0176] In some embodiments, based on Figure 4 The structure of the display substrate is configured such that the light-emitting principle of each sub-pixel is as follows: a battery or power source applies a voltage to the anode 201 and cathode 203 of the sub-pixel; current flows from the cathode 203 to the anode 201 and passes through the light-emitting functional layer 202; the light-emitting functional layer 202 includes an organic molecule emitting layer and an organic molecule conductive layer; the cathode 203 outputs electrons to the organic molecule emitting layer in the light-emitting functional layer 202; the anode 201 absorbs electrons from the organic molecule conductive layer in the light-emitting functional layer 202 (this can be regarded as the anode outputting holes to the conductive layer, and the two effects are equal); at the junction of the emitting layer and the conductive layer, electrons combine with holes; when an electron encounters a hole, it fills the hole (it falls into a certain energy level in an atom that is missing electrons); when this process occurs, the electron releases energy in the form of photons; the light-emitting functional layer 202 emits light. In this embodiment, the light-emitting functional layer 202 of each sub-pixel emits blue light. In this embodiment, the light-emitting functional layer 202 is made of an organic blue-emitting material and is laid out in one layer. The size of the anode pattern of each sub-pixel determines the size of the opening area of ​​each sub-pixel. After passing through the color conversion layer 7 in the pixel, the blue light is converted into other colors, such as red, green, and blue. The color conversion layer 7 is made of quantum dot material. Quantum dots are semiconductor nanocrystals that can produce pure monochromatic red, green, and blue light, thereby enabling the color display of the display substrate. A color resist layer 10 is provided on the side of the color conversion layer 7 facing away from the substrate 1, which can further improve the purity of the displayed color of each sub-pixel and improve the display effect.

[0177] In some embodiments, refer to Figure 4 The display substrate also includes a second black matrix 11, located on the side of the barrier 8 facing away from the substrate 1; the orthographic projection of the second black matrix 11 on the substrate 1 falls within the orthographic projection of the first black matrix 9 on the substrate 1. The second black matrix 11 separates the color resist layers 10 of different colors and blocks light emitted from adjacent sub-pixels from passing through their respective color conversion layers 7 and then illuminating their corresponding color resist layers 10, thereby preventing crosstalk between the light from adjacent sub-pixels. The orthographic projection of the second black matrix 11 on the substrate 1 falling within the orthographic projection of the first black matrix 9 on the substrate 1 further prevents crosstalk between adjacent sub-pixels, improving the display effect.

[0178] In some embodiments, refer to Figures 15a-15e The projected areas of multiple pixel circuits on the substrate are equal. Figure 15a This is a conductive layer pattern located on a substrate in a multi-pixel circuit. The conductive layer pattern includes a pattern of one of the plates for forming capacitors in the pixel circuit, as well as patterns of connecting vias and signal traces. Figure 15b For multiple pixel circuits located in Figure 15aThe pattern of the active layer of the transistor is opposite to the pattern of the conductive layer. Figure 15c This refers to the via pattern in an insulating layer (such as a gate insulating layer, intermediate dielectric layer, etc.) located on the side of the active layer pattern away from the substrate in a multi-pixel circuit. Figure 15d This is a pattern of the transistor source / drain electrode layer, the second conductive layer, and other conductive structures located on the side of the insulating layer away from the substrate in a multi-pixel circuit. Figure 15e for Figure 15a , Figure 15b , Figure 15c and Figure 15d The image shows a top view of multiple pixel circuits formed by sequentially stacking the various film layers. In this embodiment, the design and arrangement of the pixel circuits remain unchanged.

[0179] In some embodiments, refer to Figures 16a-16e , Figure 16a This is a pattern of an anode, a first conductive layer, and a via formed in an insulating layer (such as a passivation layer or a planarization layer) on a display substrate, located on the side of the transistor source / drain electrode layer opposite to the substrate. Figure 16b The pattern is a pixel definition layer formed on the substrate on the side opposite to the anode, where the sub-pixel and the orthogonal projection of the first conductive layer on the substrate are located in the opening. Figure 16c This is a pattern of a barrier wall and a first black matrix located on the pixel defining layer of a display substrate, facing away from the substrate. Figure 16d This is a pattern of a color conversion layer on a display substrate located within the area separated by the barrier. Figure 16e for Figures 15a-15d as well as Figures 16a-16d The top view of the display substrate after the various film layers are sequentially stacked. In this embodiment, the arrangement of the sub-pixels is changed so that the orthographic projections of the first via 41 and the second via 42 on the substrate are located in the region between the orthographic projections of the first sub-pixel 21 and the second sub-pixel 22 on the substrate, thereby improving or avoiding light crosstalk between adjacent first sub-pixels 21 and second sub-pixels 22. Figures 15a-15d as well as Figures 16a-16d For the corresponding Figure 3 The pattern of each film layer on the display substrate with neutron pixel arrangement.

[0180] In some embodiments, refer to Figure 16eThe orthographic projections of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate and the orthographic projections of the pixel circuits electrically connected to them on the substrate do not overlap at least partially. In the disclosed technology, each sub-pixel and the orthographic projection of its electrically connected pixel circuit on the substrate correspond one-to-one, and the overlapping areas are regular and consistent. However, in this embodiment, the orthographic projections of each sub-pixel and its electrically connected pixel circuit on the substrate do not correspond one-to-one, and the overlapping areas are also irregular and inconsistent, i.e., they correspond randomly. Thus, on the one hand, by changing the arrangement of the sub-pixels so that the first via 41 and the second via 42 are located in the area between the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221, the spacing between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221 is increased, thereby improving or avoiding light crosstalk between them. On the other hand, space can be utilized more effectively and rationally, so that the change in the sub-pixel arrangement does not reduce the aperture ratio of the sub-pixels, nor does it reduce the display resolution of the display substrate.

[0181] In some embodiments, refer to Figures 17a-17d as well as Figures 18a-18d For the corresponding Figure 12 The pattern of each film layer on the display substrate with neutron pixel arrangement. Figure 17a This is a conductive layer pattern located on a substrate in a multi-pixel circuit. The conductive layer pattern includes a pattern of one of the plates for forming capacitors in the pixel circuit, as well as patterns of connecting vias and signal traces. Figure 17b For multiple pixel circuits located in Figure 15a The pattern of the active layer of the transistor is opposite to the pattern of the conductive layer. Figure 17c This refers to the via pattern in an insulating layer (such as a gate insulating layer, intermediate dielectric layer, etc.) located on the side of the active layer pattern away from the substrate in a multi-pixel circuit. Figure 17d This is a pattern of the transistor source / drain electrode layer, the second conductive layer, and other conductive structures located on the side of the insulating layer away from the substrate in a multi-pixel circuit.

[0182] In some embodiments, refer to Figures 18a-18e , Figure 18a This is a pattern of an anode, a first conductive layer, and a via formed in an insulating layer (such as a passivation layer or a planarization layer) on a display substrate, located on the side of the transistor source / drain electrode layer opposite to the substrate. Figure 18b The pattern is a pixel definition layer formed on the substrate on the side opposite to the anode, where the sub-pixel and the orthogonal projection of the first conductive layer on the substrate are located in the opening. Figure 18c This is a pattern of a barrier wall and a first black matrix located on the pixel defining layer of a display substrate, facing away from the substrate. Figure 18d This is a pattern of a color conversion layer on a display substrate located within the area separated by the barrier. Figure 18e for Figures 17a-17d as well as Figures 18a-18d The top view of the display substrate after the various film layers are stacked in sequence. In this embodiment, the arrangement of the sub-pixels is changed so that the orthographic projections of the first via 41 and the second via 42 on the substrate are located in the area between the orthographic projections of the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 on the substrate, thereby improving or avoiding light crosstalk between adjacent first sub-pixel 21 and second sub-pixel 220 and third sub-pixel 221.

[0183] In some embodiments, refer to Figure 4 The display substrate further includes a first encapsulation layer 12, a second encapsulation layer 13, and an anti-reflection layer 14. The first encapsulation layer 12 is located on the side of the cathode 203 facing away from the substrate 1 and on the side of the color conversion layer 7 near the cathode 203. The second encapsulation layer 13 is located on the side of the color conversion layer 7 facing away from the substrate 1 and on the side of the color resist layer 10 near the color conversion layer 7. The anti-reflection layer 14 is located on the side of the color resist layer 10 facing away from the substrate 1. The first encapsulation layer 12 encapsulates the light-emitting functional layer 202 and the cathode 203 of the sub-pixel, preventing external moisture and oxygen from entering the light-emitting functional layer 202 and causing damage. The second encapsulation layer 13 encapsulates the color conversion layer 7, thus protecting it, and simultaneously providing multiple layers of protection for the light-emitting functional layer 202 and the cathode 203 of the sub-pixel. The anti-reflection layer 14 can be a polarizer, preventing external light incident on the display surface of the display substrate from being reflected, thereby ensuring that the display substrate can display normally.

[0184] In some embodiments, the first encapsulation layer 12 may be composed of a stack of inorganic film layers, organic film layers, and inorganic film layers. The second encapsulation layer 13 may be composed of an inorganic film layer.

[0185] Secondly, embodiments of this disclosure also provide a display panel, including the display substrate described in the above embodiments.

[0186] Thirdly, embodiments of this disclosure also provide a display device, including the display panel described in the above embodiments.

[0187] The display device provided in this disclosure can be any product or component with display function, such as an OLED panel, OLED TV, monitor, mobile phone, or navigator.

[0188] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, include: Base; Multiple pixel circuits are disposed on the substrate; Multiple pixels are arranged in an array and located on the side of the pixel circuit that is away from the substrate; The pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the orthographic projections of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate do not overlap; the first sub-pixel, the second sub-pixel, and the third sub-pixel are electrically connected to the pixel circuit in a one-to-one correspondence. A first spacing is provided between the first sub-pixel and the second sub-pixel along a first direction, and a first via is provided in the first spacing; A second spacing is provided between the first sub-pixel and the third sub-pixel along a first direction, and a first via is provided in the second spacing; The first via can increase the size of the first via along the first direction by increasing the first spacing and the second spacing; A third spacing is provided between the second sub-pixel and the third sub-pixel along the first direction; The pixel circuit includes a driving transistor and an insulating layer; the first sub-pixel, the second sub-pixel, and the third sub-pixel each include an anode; the driving transistor, the insulating layer, and the anode are sequentially disposed away from the substrate; The pixel circuit also includes auxiliary electrodes; The auxiliary electrode includes a first conductive layer, which is located on the same film as the anode, and the orthographic projection of the first conductive layer on the substrate does not overlap with the orthographic projection of the anode on the substrate. The auxiliary electrode further includes a second conductive layer, which is located on the same film as the first and second electrodes of the driving tube, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the first and second electrodes of the driving tube on the substrate. The first sub-pixel is a blue sub-pixel; the second sub-pixel is a red sub-pixel; and the third sub-pixel is a green sub-pixel. Alternatively, the first sub-pixel is a blue sub-pixel; the second sub-pixel is a green sub-pixel; and the third sub-pixel is a red sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel each further include a light-emitting functional layer and a cathode; the light-emitting functional layer and the cathode are disposed sequentially away from the anode; and the orthographic projections of the light-emitting functional layer and the cathode on the substrate at least partially overlap with the orthographic projections of the anode on the substrate; The first sub-pixel, the second sub-pixel, and the third sub-pixel each include a color conversion layer located on the side of the cathode opposite to the light-emitting functional layer; The light-emitting functional layer emits blue light; The color conversion layer is used to convert the blue light color, and the color conversion layer is made of quantum dot material; The first via is formed in the insulating layer and is used to connect the anodes of the first sub-pixel, the second sub-pixel and the third sub-pixel to the first pole of the driving transistor in their respective pixel circuits; The insulating layer also has a second via for connecting the first conductive layer to the second conductive layer; The orthographic projection of the second via on the substrate is located between two adjacent pixels along the second direction; The second via is located between the first spacing and the second spacing, and the orthographic projection size of the first via in the first direction is larger than the orthographic projection size of the second via in the first direction; The first via and the second via can increase the size of the first via along the first direction by at least the first spacing and the second spacing, and at most the sum of the sizes of the first via and the second via along the first direction.

2. The display substrate according to claim 1, characterized in that, In the pixel, the second sub-pixel and the third sub-pixel are located on the same side of the first sub-pixel; and the second sub-pixel and the third sub-pixel are arranged along the second direction; The first spacing is equal to the second spacing; The third spacing is smaller than the first spacing.

3. The display substrate according to claim 2, characterized in that, The first sub-pixel and the third sub-pixel are arranged along a first direction; The first direction is perpendicular to the second direction.

4. The display substrate according to claim 3, characterized in that, In the pixel, the size of the first sub-pixel along the second direction is equal to the sum of the sizes of the second sub-pixel, the third sub-pixel, and the interval between them along the second direction; The size of the first sub-pixel along the first direction is smaller than the size of either the second sub-pixel or the third sub-pixel along the first direction.

5. The display substrate according to claim 4, characterized in that, The orthographic projection of the first conductive layer onto the substrate lies in the gap between at least partially adjacent pixels along the first direction.

6. The display substrate according to claim 5, characterized in that, The dimension of the first conductive layer along the second direction is equal to the sum of the dimensions of two adjacent pixels along the second direction and the interval between them; The dimension of the first conductive layer along the first direction is smaller than the dimension of the first sub-pixel along the first direction.

7. The display substrate according to claim 1, characterized in that, The first spacing is equal to the second spacing; The third spacing is equal to the sum of the first spacing, the second spacing, and the width of the first sub-pixel along the first direction.

8. The display substrate according to claim 7, characterized in that, In the pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel are arranged sequentially along the first direction.

9. The display substrate according to claim 8, characterized in that, The dimension of the first conductive layer along the first direction is greater than the sum of the dimensions of the first sub-pixel and the second sub-pixel along the first direction; or, the dimension of the first conductive layer along the first direction is greater than the sum of the dimensions of the first sub-pixel and the third sub-pixel along the first direction; The dimension of the first conductive layer along the second direction is smaller than the dimension of the first sub-pixel along the second direction.

10. The display substrate according to claim 1, characterized in that, The first spacing is smaller than the second spacing; The second spacing is equal to the sum of the first spacing, the width of the second sub-pixel along the first direction, and the third spacing.

11. The display substrate according to claim 10, characterized in that, In the pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel are arranged sequentially along the first direction.

12. The display substrate according to claim 8 or 11, characterized in that, In the pixel, the size of the first sub-pixel along the second direction is smaller than the size of either the second sub-pixel or the third sub-pixel along the second direction; The size of the first sub-pixel along the first direction is smaller than the size of either the second sub-pixel or the third sub-pixel along the first direction; The first direction is perpendicular to the second direction.

13. The display substrate according to claim 12, characterized in that, The orthographic projection of the first conductive layer onto the substrate lies in the interval region between at least partially adjacent pixels along the second direction.

14. The display substrate according to claim 5, 8, or 11, characterized in that, The dimension of the first conductive layer along the first direction is smaller than the first spacing or the second spacing; The dimension of the first conductive layer along the second direction is smaller than the dimension of the first sub-pixel along the second direction.

15. The display substrate according to claim 3, 8, or 11, characterized in that, The pixels in any two adjacent rows arranged along the second direction are mirror-symmetric; Alternatively, any two adjacent columns of pixels arranged along the first direction are mirror-symmetric.

16. The display substrate according to claim 13, characterized in that, In the pixel array, the pixels in each row are arranged along the second direction; The second sub-pixels in each row of pixels are arranged along the second direction; The third sub-pixels in each row of pixels are arranged along the second direction; The first sub-pixels in each row of pixels are arranged along the second direction.

17. The display substrate according to claim 3, 8, or 11, characterized in that, In the pixel array, the pixels in each row are arranged along the second direction; The first sub-pixels of the pixels in rows 2n+1 and 2n+2 are arranged along the second direction; where n is an integer, n=0,1,2….

18. The display substrate according to claim 1, characterized in that, In the pixels, the spacing ranges of the first spacing and the second spacing are 7-25μm, respectively.

19. The display substrate according to claim 18, characterized in that, The orthographic projections of the first via and the second via in the first direction do not overlap.

20. The display substrate according to claim 18, characterized in that, The orthographic projections of the first via and the second via in the first direction at least partially overlap.

21. The display substrate according to claim 19 or 20, characterized in that, It also includes a pixel defining layer located on the side of the insulating layer opposite to the substrate; The first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively located in the area defined by the pixel boundary layer; The pixel defining layer has an opening in the region corresponding to the first conductive layer; the light-emitting functional layer and the cathode also extend into the opening, and the portions of the light-emitting functional layer and the cathode located inside the opening are disconnected from the portions located outside the opening at the edge of the opening; The portion of the cathode outside the opening covers the broken edge of the light-emitting functional layer at the edge of the opening, and the portion of the cathode outside the opening also extends to contact at least a portion of the edge end face of the first conductive layer.

22. The display substrate according to claim 21, characterized in that, The first conductive layer includes a first sublayer, a second sublayer, and a third sublayer stacked sequentially along a direction away from the substrate; The cross-sectional shape of the first conductive layer perpendicular to the substrate includes an "I" shape or an inverted trapezoidal shape; The portion of the cathode outside the opening is in contact with at least the edge faces of the second and third sub-layers.

23. The display substrate according to claim 1, characterized in that, In the pixel, the aperture ratio of the second sub-pixel, the third sub-pixel, and the first sub-pixel ranges from 2:2:1 to 3:2:

1.

24. The display substrate according to claim 23, characterized in that, In the pixel, the orthographic projection shape of the second sub-pixel, the third sub-pixel, and the first sub-pixel on the substrate includes a rectangle.

25. The display substrate according to claim 21, characterized in that, The color conversion layer includes a first color conversion unit, a second color conversion unit, and a first transmission unit; The orthographic projection of the first color conversion unit onto the substrate covers the orthographic projection of the second sub-pixel onto the substrate; The orthographic projection of the second color conversion unit onto the substrate covers the orthographic projection of the third sub-pixel onto the substrate; The orthographic projection of the first transmission unit on the substrate covers the orthographic projection of the first sub-pixel on the substrate.

26. The display substrate according to claim 25, characterized in that, It also includes a barrier and a first black matrix, located on the side of the pixel defining layer away from the substrate, and the first black matrix and the barrier are arranged sequentially away from the pixel defining layer; The orthographic projections of the retaining wall and the first black matrix onto the substrate at least partially overlap with the orthographic projections of the pixel defining layer onto the substrate.

27. The display substrate according to claim 26, characterized in that, The first sub-pixel, the second sub-pixel, and the third sub-pixel each further include a color resist layer, located on the side of the color conversion layer opposite to the substrate; The color resist layer includes a first color resist, a second color resist, and a third color resist; The orthographic projection of the first color resist on the substrate falls within the orthographic projection of the first color conversion unit on the substrate; The orthographic projection of the second color resist on the substrate falls within the orthographic projection of the second color conversion unit on the substrate; The orthographic projection of the third color resist on the substrate falls within the orthographic projection of the first transmission unit on the substrate.

28. The display substrate according to claim 27, characterized in that, It also includes a second black matrix, located on the side of the retaining wall away from the base; The orthographic projection of the second black matrix onto the substrate falls within the orthographic projection of the first black matrix onto the substrate.

29. The display substrate according to claim 1, characterized in that, The projected areas of the plurality of pixel circuits on the substrate are equal.

30. The display substrate according to claim 29, characterized in that, The orthographic projections of the first sub-pixel, the second sub-pixel, and the third sub-pixel onto the substrate and the orthographic projections of the pixel circuit electrically connected thereto onto the substrate do not overlap at least partially.

31. The display substrate according to claim 28, characterized in that, It also includes a first encapsulation layer, a second encapsulation layer, and an anti-reflective layer; The first encapsulation layer is located on the side of the cathode away from the substrate and on the side of the color conversion layer close to the cathode; The second encapsulation layer is located on the side of the color conversion layer away from the substrate and on the side of the color resist layer close to the color conversion layer; The anti-reflective layer is located on the side of the color resist layer that is away from the substrate.

32. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1-31.

33. A display device, characterized in that, Includes the display panel as described in claim 32.

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