Circuits, methods, and soc chips for accessing memory

Abstract

The application discloses a circuit, a method and an SOC chip for accessing a memory. The circuit for accessing the memory comprises a clock switching circuit and an arbitration circuit. The clock switching circuit is configured to perform clock switching according to a preset scene clock, and provide a working clock after the switching to the arbitration circuit. The arbitration circuit is configured to receive access requests of a plurality of hosts, and control the hosts to access the memory in an order by using the working clock. The application can improve the efficiency of the hosts in accessing the memory in the SOC chip, and improve the access effect.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically to a circuit, method, and SOC chip for accessing memory. Background Technology

[0002] In System-on-Chip (SoC) design, it's common for multiple masters to access a single memory location simultaneously. Since a memory location can only respond to one master's access at a time, traditional solutions often use an asynchronous FIFO (First Input First Output) handshake mechanism, coordinated by an arbitration circuit, to access the memory sequentially. This access method suffers from reduced efficiency due to the asynchronous handshake of control signals and the need for asynchronous FIFO buffering for data reading and writing. Summary of the Invention

[0003] In view of this, this application provides a circuit, method and SOC chip for accessing memory to solve the problem of low efficiency of host access to memory in existing SOC chips.

[0004] This application provides a circuit for accessing a memory, including a clock switching circuit and an arbitration circuit;

[0005] The clock switching circuit is used to switch the clock according to the preset scene clock and provide the switched working clock to the arbitration circuit.

[0006] The arbitration circuit is used to receive access requests from multiple hosts and uses the operating clock to control the orderly access of each host to the memory.

[0007] Optionally, the scene clock includes a first clock and a second clock, wherein the first clock is the clock before the switch and the second clock is the clock after the switch;

[0008] The clock switching circuit is used to turn off the first selection signal corresponding to the first clock at a preset clock switching time, so that the first clock domain signal corresponding to the first selection signal is turned off, and turn on the second selection signal corresponding to the second clock, so that the second clock domain signal corresponding to the second selection signal is turned on, and the clock provided to the arbitration circuit is switched to the second clock.

[0009] Optionally, the first clock domain signal is turned off on the falling edge of the first clock; and / or, the second clock domain signal is turned on on the falling edge of the second clock.

[0010] Optionally, the clock switching circuit includes a first OR gate and clock switching units corresponding to each scene clock; the output terminal of each clock switching unit is connected to one input terminal of the first OR gate, and the output terminal of the first OR gate is the output terminal of the clock switching circuit.

[0011] Each clock switching unit is used to access the corresponding scene clock and selection signal.

[0012] Optionally, the clock switching unit is further configured to set other clock switching units to an asynchronous reset state when the corresponding clock domain signal is enabled.

[0013] Optionally, the clock switching unit includes a first D flip-flop, a second D flip-flop, and a first AND gate;

[0014] The first input terminal of the first D flip-flop is connected to the corresponding selection information, the second input terminal is connected to the corresponding scene clock, and the output terminal is connected to the first input terminal of the second D flip-flop; the second input terminal of the second D flip-flop is connected to the corresponding scene clock, and the output terminal is connected to the first input terminal of the first AND gate; the second input terminal of the first AND gate is connected to the corresponding scene clock, and the output terminal is connected to one input terminal of the first OR gate.

[0015] Optionally, the clock switching unit further includes a first NOR gate; each input terminal of the first NOR gate is connected to the output terminal of a second D flip-flop in another clock switching unit, and the output terminal is connected to the asynchronous reset terminal of the first D flip-flop and the second D flip-flop respectively.

[0016] Optionally, the arbitration circuit is further configured to use the operating clock to control the current host to access the memory, and to determine the target host for the next access to the memory, and to switch the host accessing the memory to the target host when the target host is inconsistent with the current host.

[0017] Optionally, the arbitration circuit is further configured to pre-store the access order corresponding to each host, and when receiving an access request from the first host, determine whether the first host is the next host to access the memory based on the access order; if so, the first host is determined as the target host.

[0018] Optionally, the arbitration circuit is further configured to pre-store the access priority corresponding to each host, and when receiving an access request from the first host, determine whether the first host has access rights based on the access priority and the currently received access request; if so, the first host is identified as the target host.

[0019] Optionally, the arbitration circuit is further configured to, after determining the target host, send an access preparation signal to the target host, switch the read / write clock of the memory to the host read / write clock of the target host, and send an access occupancy signal to each of the other hosts.

[0020] Optionally, the arbitration circuit includes an access state determination unit, a signal feedback unit, and a clock configuration unit;

[0021] The access status determination unit is used to determine the access status of each host and the target host; the signal feedback unit is used to feed back an access preparation signal to the target host and an access occupancy signal to the other hosts; the clock configuration unit is used to switch the read / write clock of the memory to the host read / write clock of the target host.

[0022] Optionally, the circuit for accessing the memory may further include a protocol conversion circuit corresponding to each host; the protocol conversion circuit is used to convert the data read / write interface of the corresponding host to the interface that matches the memory.

[0023] And / or, the circuit for accessing the memory described above also includes a synchronization circuit corresponding to each host; the synchronization circuit is used to synchronize the information between the corresponding host and the arbitration circuit.

[0024] This application also provides a method for accessing memory, including:

[0025] The clock is switched according to the preset scene clock, and the working clock used to control the host to access the memory is switched to the target clock.

[0026] It receives access requests from multiple hosts and uses the target clock to control the orderly access of each host to the memory.

[0027] This application also provides a SOC chip, including a memory, a plurality of hosts, and any of the above-described circuits for accessing the memory.

[0028] In the aforementioned circuits, methods, and SOC chips for accessing memory, the clock switching circuit can seamlessly switch clocks according to a preset scenario clock, providing the switched operating clock to the arbitration circuit. This allows the arbitration circuit to use a stable and effective operating clock to control the orderly access of memory by each host, improving memory access efficiency and performance. Furthermore, since the memory is accessed using the clock of the corresponding host, the operating clock of the arbitration circuit can be switched at any time. This means that even when the operating clock of the arbitration circuit is switched, the corresponding host can still access the memory normally, enhancing the flexibility of memory access by each host. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the SOC chip structure;

[0031] Figure 2 This is a schematic diagram of the circuit structure for accessing the memory according to an embodiment of this application;

[0032] Figure 3 This is the clock switching timing diagram of a traditional arbitration circuit;

[0033] Figure 4a , Figure 4b and Figure 4c This is a schematic diagram of the clock switching circuit structure according to an embodiment of this application;

[0034] Figure 5a and Figure 5b This is a schematic diagram of the clock switching circuit operation according to an embodiment of this application;

[0035] Figure 6a , Figure 6b and Figure 6c This is a schematic diagram of the host access status according to an embodiment of this application;

[0036] Figure 7a , Figure 7b and Figure 7c This is a partial structural schematic diagram of the arbitration circuit in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of the circuit structure for accessing the memory according to an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of the first sub-synchronization circuit in the embodiments of this application;

[0039] Figure 10 This is a schematic diagram of the SOC chip structure according to an embodiment of this application. Detailed Implementation

[0040] For some applications, the SOC chip used can be referenced. Figure 1 As shown, Figure 1 In this context, Masteri (i = 1, 2, ..., N) represents the i-th master, Mem represents the memory, and Arbit represents the arbitration circuit. (See reference...) Figure 1As shown in the background section, if each host accesses the memory sequentially under the coordination of the arbitration circuit using an asynchronous FIFO (First Input First Output) handshake method, the access efficiency will be reduced because the control signals need to be asynchronously handshaked and the read and write data needs to be cached by the asynchronous FIFO.

[0041] To address the aforementioned issues, the circuit, method, and SOC chip for accessing memory provided in this application allow the clock switching circuit to seamlessly switch clocks according to a preset scenario clock, providing the switched operating clock to the arbitration circuit. This enables the arbitration circuit to use a stable and effective operating clock to control the orderly access of memory by each host, thereby improving the efficiency of multiple hosts accessing memory.

[0042] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0043] The first aspect of this application provides a circuit for accessing a memory, with reference to... Figure 2 As shown, the circuit includes a clock switching circuit 100 and an arbitration circuit 300;

[0044] The clock switching circuit 100 is used to switch the clock according to the preset scene clock and provide the switched working clock to the arbitration circuit 300.

[0045] The arbitration circuit 300 is used to receive access requests from multiple hosts 210 and uses the working clock to control the orderly access of each host 210 to the memory 220.

[0046] The aforementioned clock switching circuit 100 can pre-store at least one scene clock based on the characteristics of the response work of each host 210 and / or the order of access to the memory 220 by each host 210, and pre-store the clock switching timing of each scene clock. At the corresponding clock switching timing, it switches to the target scene clock, which is then provided as the working clock to the arbitration circuit 300. This allows the arbitration circuit 300 to use an accurate working clock to control the orderly access to the memory 220 by each host 210, improving access efficiency. Each host 210's working scene has a corresponding scene clock, and the clock switching timing of each scene clock matches the timing of the corresponding host's access to the memory. Typically, this can be set at a certain moment before the corresponding host's access to the memory (e.g., 1 second prior), so that the clock switching circuit 100 switches the working clock in advance at the clock switching timing. This allows the arbitration circuit 300 to use an accurate working clock to execute the control work for the corresponding host's access to the memory, improving control effectiveness.

[0047] Specifically, the arbitration circuit 300 can use the operating clock provided by the clock switching circuit 100 to control the current host's access to the memory 220 and determine the target host for the next access to the memory. If the target host is different from the current host, the operating clock provided by the clock switching circuit 100 is used to switch the host accessing the memory 220 to the target host to update the current host and enable the target host to access the memory 220 quickly. Optionally, if the target host is the same as the current host, the arbitration circuit 300 can continue to use the aforementioned operating clock to control the current host's access to the memory 220 so that the current host can continue to perform read and write operations on the memory 220.

[0048] In one embodiment, the scene clock includes multiple clocks, each with a corresponding selection signal and a clock domain signal. The selection signal indicates whether the corresponding clock is currently enabled, and the clock domain signal indicates whether the corresponding clock is a working clock. For example, the scene clock includes a first clock and a second clock, where the first clock is the clock before switching and the second clock is the clock after switching. The clock switching circuit 100 is used to deactivate the first selection signal corresponding to the first clock at a preset clock switching time, thereby deactivating the first clock domain signal corresponding to the first selection signal and activating the second selection signal corresponding to the second clock, thus enabling the clock provided to the arbitration circuit 300 to be the second clock. Here, the clock switching circuit 100 can preset a corresponding clock switching time based on the timing of each host accessing the memory. This clock switching time can be set at a certain moment before the timing of the corresponding host accessing the memory (e.g., 1 second prior), so that the clock switching circuit 100 switches the working clock in advance at the clock switching time, improving the accuracy of the provided working clock.

[0049] In practical applications, a typical SOC chip corresponds to multiple clock sources, such as clock sources CLK_SRC1, CLK_SRC2, and CLK_SRC3. Each clock source has a corresponding clock. In application scenario 1, clock source CLK_SRC1 is required, while in application scenario 2, clock source CLK_SRC2 is required. Therefore, when switching from application scenario 1 to 2, the operating clock of the arbitration circuit 300 needs to be switched from CLK_SRC1 (the first clock) to CLK_SRC2 (the second clock) in advance so that the arbitration circuit 300 can continue to respond to the work of the corresponding application scenario. In this embodiment, the clock switching circuit 100 adopts the method of turning off the first selection signal corresponding to the first clock and turning on the second selection signal corresponding to the second clock. This turns off the first clock domain signal corresponding to the first selection signal and turns on the second clock domain signal corresponding to the second selection signal, so that the arbitration circuit 300 can quickly and stably switch to the second clock.

[0050] Specifically, this embodiment can use level signals to control the on and off of various signals (such as a first selection signal and a second selection signal). For example, a first level signal can be used to represent on, and a second level signal different from the first level signal can be used to represent off. Optionally, the first level signal is high and the second level signal is low. At this time, the clock switching circuit 100 changes the first selection signal from high to low to turn off the first selection signal, thereby turning off the first clock domain signal; it changes the second selection signal from low to high to turn on the second selection signal, turning on the second clock domain signal, so that the clock of the arbitration circuit 300 is switched to the second clock.

[0051] refer to Figure 3 As shown, in traditional memory access schemes within SOC chips, control signals require asynchronous handshaking, and read / write data requires asynchronous FIFO buffering, leading to reduced efficiency. Furthermore, since the memory uses the clock of its corresponding arbitration circuit, the arbitration circuit cannot change its own clock as long as a host is accessing the memory; otherwise, it will... Figure 3 As shown, the clock mismatch caused by the change in clock caused an error, resulting in an error in the access process of the corresponding host.

[0052] To address the aforementioned issues, in this embodiment, the first clock domain signal is turned off on the falling edge of the first clock; and / or, the second clock domain signal is turned on on the falling edge of the second clock.

[0053] Here, the first clock domain signal changes at the falling edge of the first clock, ensuring that the first clock provided by the clock switching circuit 100 will not have glitches. The second clock domain signal changes at the falling edge of the second clock, ensuring that the second clock provided by the clock switching circuit 100 will not have glitches. In this way, even when there is host access to memory, the arbitration circuit 300 can still achieve seamless switching of clocks in various scenarios, so that the working clock after each switch matches the corresponding host access to memory process, improving access effect and increasing access efficiency.

[0054] Specifically, refer to Figure 4a As shown, the clock switching circuit 100 includes a first OR gate 110 and a clock switching unit 120 corresponding to each scene clock; the output terminal of each clock switching unit 120 is connected to one input terminal of the first OR gate 110, and the output terminal of the first OR gate 110 is the output terminal of the clock switching circuit 110.

[0055] Each clock switching unit 120 is used to access the corresponding scene clock and selection signal, so as to turn on or off the corresponding clock domain signal according to the accessed scene clock and selection signal, and provide the arbitration circuit 300 with the scene clock corresponding to the turned-on clock domain signal.

[0056] Furthermore, when the aforementioned clock switching unit 120 activates the corresponding clock domain signal and provides the scene clock corresponding to the clock domain signal, it also sets the other clock switching units to an asynchronous reset state so that the other clock switching units can prepare for the subsequent clock switching process.

[0057] In one example, reference Figure 4b As shown, the clock switching unit includes a first D flip-flop 121, a second D flip-flop 122, and a first AND gate 123; the first input of the first D flip-flop 121 is connected to the corresponding selection information, the second input is connected to the corresponding scene clock, and the output is connected to the first input of the second D flip-flop 122; the second input of the second D flip-flop 122 is connected to the corresponding scene clock, and the output is connected to the first input of the first AND gate 123; the second input of the first AND gate 123 is connected to the corresponding scene clock, and the output is connected to one input of the first OR gate 110. Figure 4bIn this context, CKi-1 represents the i-th scene clock, Seli-1 represents the selection signal corresponding to the i-th scene clock, CKi-1_Sel represents the clock domain signal corresponding to the i-th scene clock, Li-1 represents the output clock corresponding to the i-th scene clock, and CK represents the output clock of the corresponding clock switching circuit 100 (provided to the arbitration circuit as the working clock), i = 1, ..., n; for example, CK0 represents the first scene clock, the selection signal corresponding to the first scene clock is Sel0, the clock domain signal is CK0_Sel, and the output clock is L0; CKn-1 represents the n-th scene clock, the selection signal corresponding to the n-th scene clock is Seln-1, the clock domain signal is CKn-1_Sel, and the output clock is Ln-1.

[0058] Specifically, Figure 4c The clock switching units corresponding to the four scene clocks are shown, such as... Figure 4c As shown, the clock switching unit 120 also includes a first NOR gate 124; each input terminal of the first NOR gate 124 is connected to the output terminal of a second D flip-flop 122 in another clock switching unit, and the output terminal is connected to the asynchronous reset terminal of the first D flip-flop 121 and the second D flip-flop 122 respectively. Figure 4c In this context, CKi-1_rst_n represents the asynchronous reset signal corresponding to the i-th scene clock, such as CK0_rst_n representing the asynchronous reset signal corresponding to the first scene clock, and CK1_rst_n representing the asynchronous reset signal corresponding to the second scene clock. The first NOR gate 124 of a certain clock switching unit is used to perform NOR operation on the clock domain signals output by other clock switching units to release the asynchronous reset signal of the clock switching unit, so that the signals connected to the asynchronous reset terminals of each D flip-flop in the clock switching unit match the clock domain signals of other clock switching units, ensuring the accuracy of the clock switching process.

[0059] In one example, using Figure 5a The timing diagram shown is explained below. Figure 4c The clock switching circuit shown illustrates the clock switching process in a scenario. Figure 5aIn the scene clock, there are four clocks: CK0, CK1, CK2, and CK3. CK0 has a selection signal of Sel0, a clock domain signal of CK0_Sel, an output clock of L0, and an asynchronous reset signal of CK0_rst_n. CK1 has a selection signal of Sel1, a clock domain signal of CK1_Sel, an output clock of L1, and an asynchronous reset signal of CK1_rst_n. CK2 has a selection signal of Sel2, a clock domain signal of CK2_Sel, an output clock of L2, and an asynchronous reset signal of CK2_rst_n. CK3 has a selection signal of Sel3, a clock domain signal of CK3_Sel, an output clock of L3, and an asynchronous reset signal of CK3_rst_n. If high and low levels are used to control the on / off state of each signal, with 1 representing high level and 0 representing low level, the continuous switching process from CK0 to CK3 includes:

[0060] (1) Currently operating under CK0 clock, when the select signal Sel0 of CK0 configuration register changes from 1 to 0, CK0 generates its clock domain signal CK0_sel (clock domain select signal) after being synchronized by two falling edges of the clock, and the clock domain signal CK0_sel changes from 1 to 0.

[0061] (2) After CK0_sel is 0, the intermediate output clock L0 of CK0 is set to 0. Since CK0_sel changes on the falling edge of CK0, it will not cause glitches in L0. When CK0_sel is 1, L0 outputs CK0. At this time, the output clock CK is equivalent to CK0. At the same time, CK0_sel will set the asynchronous reset signals (CK1_rst_n, CK2_rst_n, CK3_rst_n) of the synchronous circuits of CK1, CK2, and CK3 to 0, so that all other clock switching units are in the reset state.

[0062] (3) When CK0_sel changes from 1 to 0, the asynchronous reset signal (CK1_rst_n) of the synchronous circuit of CK1 is released;

[0063] (4) When Sel0 changes from 1 to 0, the selection signal Sel1 of CK1 changes from 0 to 1. After CK1_rst_n is released, CK1 generates its clock domain signal CK1_sel after being synchronized by two falling edges of the clock. The clock domain signal CK1_sel changes from 0 to 1.

[0064] (5) After the CK1_sel signal changes from 0 to 1, the intermediate output clock L1 of CK1 is set to be the same as CK1. At this time, CK is equivalent to L1. At the same time, CK1_sel will set the asynchronous reset signals (CK0_rst_n, CK2_rst_n, CK3_rst_n) of the synchronous circuit of CK0, CK2, and CK3 to 0, so that the other clock switching units are in the reset state.

[0065] (6) The circuit working process and principle of switching from CK1 to CK2 and from CK2 to CK3 are the same as those of switching from CK0 to CK1. From these switching processes, it can be seen that when switching from CK0 to CK1, it is not related to whether CK2 and CK3 exist. When switching from CK1 to CK2, it is not related to whether CK0 and CK3 exist. The same applies to switching between any two other clocks.

[0066] Furthermore, Figure 5b The timing diagram shows the switching process when there is no initial clock. In this diagram, CK0 is low, indicating that there is no initial clock. When the register configuration is changed to switch the clock, the switching process proceeds according to... Figure 5a The method shown for switching from CK0 to CK1 can be used to switch to the target clock CK1 as long as the target clock CK1 exists. It can be seen that the clock switching circuit 100 provided in this application can support fast and seamless switching between any two clocks in multiple scene clocks. The absence of a half-cycle sampling circuit will not increase the circuit operating frequency. The clock switching only requires the existence of the target clock and does not require a transition clock, resulting in high switching flexibility.

[0067] In one embodiment, the arbitration circuit may include at least one logic element such as AND gate, OR gate, and NOT gate. These logic devices form a corresponding logic circuit to provide an access channel between the current host and the memory. The operating clock provided by the clock switching circuit controls the current host's access to the memory. It can also process received access requests, arbitrate the target host for the next memory access according to certain rules, and switch the host accessing the memory to the target host if the target host is inconsistent with the current host, ensuring the target host can successfully access the memory. The arbitration circuit may include logic circuits implementing rules such as polling, fixed priority, configurable priority, and / or emergency priority. When multiple host access requests are received, these rules can be used to determine the target host for the next memory access, or to determine the access order of each host, so that each host accesses the memory in an orderly manner. Optionally, the rules by which the arbitration circuit determines the target host or the access order of each host are matched with the scenario clocks provided by the clock switching circuit. For example, when the clock switching circuit provides a scenario clock, the arbitration circuit determines a host associated with that scenario clock as the target host according to the corresponding rules, etc., so that the various parts of the circuit in the corresponding memory access circuit operate more harmoniously.

[0068] In one example, the arbitration circuit pre-stores the access order for each host. When it receives an access request from the first host, it determines whether the first host is the next host to access the memory based on the access order. If so, the first host is identified as the target host, so that each host can access the memory according to the access order. The access order can record the order in which each host accesses the memory.

[0069] In one example, the arbitration circuit pre-stores the access priorities corresponding to each host. When receiving an access request from a first host, it determines whether the first host has access rights based on the access priority and the currently received access request. If so, the first host is identified as the target host. The currently received access requests include access requests from the first host and access requests currently sent by other hosts. In this example, when receiving an access request from the first host, the arbitration circuit can identify the access priorities of the first host and the other hosts corresponding to the currently received access request, and obtain the host with the highest access priority. If the host with the highest access priority is the first host, it is determined that the first host has access rights; otherwise, it is determined that the first host does not have access rights.

[0070] In one example, the arbitration circuit described above can also arbitrate the target host using a combination of fixed priority and round-robin. In this method, each host has an initial priority. After a host finishes accessing the memory, its priority is updated to the lowest priority, so that other hosts have priority to access the memory after that host has finished accessing it. The following uses three hosts as an example to illustrate this arbitration method. The corresponding state transition diagram can be found in the provided diagram. Figure 6a As shown, MASTER1 represents the first host, MASTER2 represents the second host, and MASTER3 represents the third host. When the arbitration circuit is in an idle state, if no host requests access, the priority order (initial priority) can be: MASTER1 > MASTER2 > MASTER3. After the first host MASTER1 completes its access and returns to the idle state, the current priority becomes: MASTER2 > MASTER3 > MASTER1. If the second host MASTER2 completes its access and returns to the idle state, the priority becomes MASTER1 > MASTER3 > MASTER2. If the third host MASTER3 completes its access and returns to the idle state, the priority becomes MASTER1 > MASTER2 > MASTER3.

[0071] Furthermore, after identifying the target host, the arbitration circuit sends an access preparation signal to the target host, switches the memory's read / write clock to the target host's host read / write clock (i.e., the host clock), and sends access occupancy signals to other hosts to synchronize the current access to the corresponding memory among the hosts. This ensures that the memory responds to the target host's read / write operations using the host read / write clock. Thus, while the arbitration circuit switches between different scenario clocks, the memory access operation can still proceed normally. (See reference...) Figure 6a As shown, after responding to an access request from a host, a readiness signal (as shown in the diagram master1_req, master2_req, and master2_req) is sent back to the corresponding host, notifying it that it is authorized to access the memory. Simultaneously, a memory occupancy signal is generated to inform other hosts that the memory is in an accessed state. Then, the access command from the corresponding host is sent to the memory port. Optionally, refer to... Figure 6b As shown, Figure 6b The diagram illustrates the clock signal selection channels corresponding to the three hosts, where master1_clk represents the host clock of the first host, master2_clk represents the host clock of the second host, and master3_clk represents the host clock of the third host. The arbitration circuit can also send a clock selection signal to the memory's clock switching module to switch the memory's clock to the corresponding host clock, enabling the corresponding host to effectively access the memory. Figure 6b The corresponding memory clock selection truth table can be found by referring to... Figure 6c As shown.

[0072] In one example, the arbitration circuit includes an access state determination unit, a signal feedback unit, and a clock configuration unit; the access state determination unit is used to determine the access state of each host and the target host; the signal feedback unit is used to feed back an access preparation signal to the target host and an access occupancy signal to the other hosts; the clock configuration unit is used to switch the read / write clock of the memory to the host read / write clock of the target host.

[0073] The access status determination unit uses various logic devices to determine the access status of each host and the target host for the next access to the memory according to certain rules. Its specific structure is matched with the number of hosts accessing the memory and / or the corresponding arbitration rules. Figure 7a It shows Figure 6aThe circuit corresponding to the access status determination unit of the first host includes a first inverter 301, a second inverter 302, a third inverter 303, a second AND gate 304, a third AND gate 305, a second OR gate 306, a fourth inverter 307, a fourth AND gate 308, a fifth AND gate 309, a third OR gate 311, a third D flip-flop 312, and a fourth D flip-flop 313; the input terminal of the first inverter 301 is connected to the access status signal ram_arb_sav[0] of the first host, and the output terminal is connected to the first input of the second AND gate 304. The input terminal of the second inverter 302 is connected to the access status signal ram_arb_sav[1] of the second host, and the output terminal is connected to the second input terminal of the second AND gate 304 and the second input terminal of the third AND gate 305 respectively. The input terminal of the third inverter 303 is connected to the access status signal ram_arb_sav[2] of the third host, and the output terminal is connected to the third input terminal of the second AND gate 304 and the third input terminal of the third AND gate 305 respectively. The first input terminal of the third AND gate 305 is connected to the input terminal of the first inverter 301, and the second AND gate 303 is connected to the second input terminal of the third host. The fourth inputs of 304 and the third AND gate 305 are respectively connected to the access request signal of the first host, and the outputs are respectively connected to one input of the second OR gate 306. The output of the second OR gate 306 is connected to the first input of the fifth AND gate 309 so as to input the processed first host access request information ram_arb_req[0] into the fifth AND gate 309. The first input of the fourth AND gate 308 is connected to the second input of the fifth AND gate 309 through the fourth inverter 307. The second input is connected to the output of the third D flip-flop 312. The output is connected to the first input of the third OR gate 311. The output of the fifth AND gate 309 is connected to the second input of the third OR gate 311. The output of the third OR gate 311 is connected to the first input of the third D flip-flop 312. The second input of the third D flip-flop 312 is connected to the working clock of the arbitration circuit. The output is connected to the first input of the fourth D flip-flop 313 so as to input the first host access status signal ram_arb_sav[0] into the fourth D flip-flop 313. The second input of the fourth D flip-flop 313 is connected to the working clock of the arbitration circuit. Here, the circuit corresponding to the access status determination unit of the first host can arbitrate whether the first host has access rights based on the access status of other hosts and the corresponding arbitration rules. This access rights can be represented by ram_arb_sav[0]. ram_arb_sav[0] = 1 indicates that the first host has the right to access the memory, and ram_arb_sav[0] = 0 indicates that the first host does not have the right to access the memory.

[0074] Optionally, the aforementioned signal feedback unit may include AND and OR gates corresponding to each host; for example, referencing Figure 7bAs shown, the signal feedback unit includes a sixth AND gate 321, a seventh AND gate 322, an eighth AND gate 323, and a fourth OR gate 324. The first input of the sixth AND gate 321 is connected to the access status signal m0_ram_rdy_sync of the first host, the second input is connected to the access permission signal m0_ram_xx of the first host, and the output is connected to the first input of the fourth OR gate 324. The first input of the seventh AND gate 322 is connected to the access status signal m1_ram_rdy_sync of the second host, the second input is connected to the access permission signal m1_ram_xx of the second host, and the output is connected to the second input of the fourth OR gate 324. The first input of the eighth AND gate 323 is connected to the access status signal m2_ram_rdy_sync of the third host, the second input is connected to the access permission signal m3_ram_xx of the third host, and the output is connected to the third input of the fourth OR gate 324. The output of the fourth OR gate 324 outputs the access preparation signal ram_xx of the target host.

[0075] Optionally, the aforementioned clock configuration unit may include structures such as OR gates and channel selectors configured for each host; for example, refer to Figure 7c As shown, the clock configuration unit includes a fifth OR gate 331, a first channel selector 332, a sixth OR gate 332, a second channel selector 334, a seventh OR gate 335, and a third channel selector 336. The first input of the fifth OR gate 331 is connected to the access permission signal m0_ram_rdy_d of the first host. This access permission signal m0_ram_rdy_d can be... Figure 7a The signal output from the fourth D flip-flop 313 is connected to the access status signal m0_ram_rdy of the first host at its second input. Its output is connected to the control terminal of the first channel selector 332. The first input of the first channel selector 332 is connected to the output of the second channel selector 334, whose second input is connected to the clock signal m0_clk of the first host. Its output is the host read / write clock mem_clk of the target host. The first input of the sixth OR gate 332 is connected to the access permission signal m1_ram_rdy_d of the second host, and its second input is connected to the access status signal m1_ram_rd of the second host. The output terminal is connected to the control terminal of the second channel selector 334. The first input terminal of the second channel selector 334 is connected to the output terminal of the third channel selector 336. The second input terminal is connected to the clock signal m1_clk of the second host. The first input terminal of the seventh OR gate 335 is connected to the access permission signal m2_ram_rdy_d of the third host. The second input terminal is connected to the access status signal m2_ram_rdy of the third host. The output terminal is connected to the control terminal of the third channel selector 336. The first input terminal of the third channel selector 336 is connected to the low-level signal 0. The second input terminal is connected to the clock signal m2_clk of the third host.

[0076] In SOC chips, there are various protocols for accessing memory, such as AHB, APB, AXI, OCP, and some custom protocols. However, the memory read / write interface protocol is fixed, and there may be incompatibility between the host's interface protocol and the memory's read / write interface protocol. To address this issue, in one embodiment, refer to... Figure 8 As shown, the circuit for accessing the memory may further include a protocol conversion circuit 410 corresponding to each host 210; the protocol conversion circuit 410 is used to convert the data read / write interface of the corresponding host to the interface that matches the memory. The protocol conversion circuit 410 can be set between the host and various circuits that need to be connected to the host, such as between the host 210 and the arbitration circuit 300, between the host 210 and the synchronization circuit 420, etc., to convert the data read / write interface of the corresponding host to the interface that matches the memory and other circuits, ensuring the effectiveness of each data interaction process.

[0077] In one example, the aforementioned memory access circuit may further include a synchronization circuit 420 corresponding to each host 210. The synchronization circuit 420 is used to synchronize information between the corresponding host and the arbitration circuit 300, such as synchronizing access requests from the corresponding host to the arbitration circuit 300, and synchronizing various types of information generated by the arbitration circuit 300 to the corresponding host, etc., to maintain consistency of relevant information between each host 210 and the arbitration circuit 300. When the memory access circuit includes a protocol conversion circuit 410, the synchronization circuit 420 can be connected between the corresponding protocol conversion circuit 410 and the arbitration circuit 300.

[0078] Specifically, the synchronization circuit 420 configured for each host 210 includes a first sub-synchronization circuit for synchronizing access requests to the arbitration circuit 300 and a second sub-synchronization circuit for synchronizing various types of information generated by the arbitration circuit 300 to the corresponding host. The first sub-synchronization circuit can use multiple D flip-flops to synchronize access requests, and the second sub-synchronization circuit can use multiple D flip-flops and AND gates to synchronize the information generated by the arbitration circuit 300.

[0079] In one example, the first sub-synchronization circuit of the first host can be referenced. Figure 9As shown, the first sub-synchronization circuit includes a fifth D flip-flop 421, a sixth D flip-flop 422, and a seventh D flip-flop 423. The asynchronous reset terminal of the fifth D flip-flop 421 is connected to a first asynchronous reset signal rst_n, which can be the asynchronous reset signal for the entire memory access circuit. The first input terminal is connected to the access request signal m0_ram_req of the first host, and the second input terminal is connected to the clock signal m0_clk (host read / write clock) of the first host. The output terminal is connected to the first input terminal of the sixth D flip-flop 422 to transmit the request signal m0_ram_req_r after information capture of the access request signal m0_ram_req. The second input terminal of the sixth D flip-flop 422 is connected to the working clock aribt_clk of the arbitration circuit, and the output terminal is connected to the first input terminal of the seventh D flip-flop 423. The second input terminal of the seventh D flip-flop 423 is connected to the working clock aribt_clk of the arbitration circuit, and the output terminal outputs the request signal m0_ram_req_sync after information capture of the request signal m0_ram_req_r. The asynchronous reset terminals of the sixth D flip-flop 422 and the seventh D flip-flop 423 are respectively connected to a second asynchronous reset signal async_rst_n_m0. This second asynchronous reset signal async_rst_n_m0 is an asynchronous reset signal generated by the arbitration circuit 300 according to its operating state. Optionally, the arbitration circuit 300 further includes an asynchronous signal generation unit for generating the aforementioned second asynchronous reset signal. Figure 9As shown, the asynchronous signal generation unit includes a fifth inverter 351, a ninth AND gate 352, a tenth AND gate 353, an eighth D flip-flop 354, a ninth D flip-flop 355, a second NOR gate 356, and a sixth inverter 357. The input terminals of the fifth inverter 351 are respectively connected to the output terminal of the fifth D flip-flop 421, the first input terminal of the eighth D flip-flop 354, and the first input terminal of the tenth AND gate 353. The output terminal is connected to the first input terminal of the ninth AND gate 352. The asynchronous reset terminals of the eighth D flip-flop 354 and the ninth D flip-flop 355 are respectively connected to the first asynchronous reset signal rst_n, and the second input... The first input terminal of the ninth D flip-flop 355 is connected to the clock signal m0_clk of the first host. The first input terminal of the ninth D flip-flop 355 is connected to the access request signal m0_ram_req of the first host. The output terminal is connected to the second input terminal of the tenth AND gate 353 through the sixth inverter 357. The output terminal of the tenth AND gate 353 is connected to the first input terminal of the second NOR gate 356. The second input terminal of the ninth AND gate 352 is connected to the output terminal of the eighth D flip-flop 354. The output terminal is connected to the second input terminal of the second NOR gate 356. The output terminal of the second NOR gate 356 outputs the second asynchronous reset signal async_rst_n_m0. The eighth D flip-flop 354 is used to acquire the rising edge information m0_ram_req_r_r of the request signal m0_ram_req_r, and the ninth D flip-flop 355 is used to acquire the rising edge information neg_m0_ram_req of the access request signal m0_ram_req. The ninth AND gate 352, the tenth AND gate 353, and the second NOR gate 356 process these two rising edge information to obtain the second asynchronous reset signal async_rst_n_m0, which is provided to the sixth D flip-flop 422 and the seventh D flip-flop 423 respectively. This ensures the accuracy of the timing of the first sub-synchronous circuit when it performs an asynchronous reset when async_rst_n_m0 = 1.

[0080] In the above memory access circuit, the clock switching circuit can seamlessly switch clocks according to a preset scenario clock, providing the switched operating clock to the arbitration circuit. This allows the arbitration circuit to use a stable and effective operating clock to control the orderly access of memory by each host, improving memory access efficiency and performance. Furthermore, the above memory access circuit eliminates the asynchronous FIFO for cached data, reducing the circuit area. Since the memory is accessed using the clock of the corresponding host, the operating clock of the arbitration circuit can be switched at any time. This means that even when the operating clock of the arbitration circuit is switched, the corresponding host can still access the memory normally, improving the flexibility of memory access by each host.

[0081] This application also provides a method for accessing memory in a second aspect, comprising:

[0082] The clock is switched according to the preset scene clock, and the working clock used to control the host to access the memory is switched to the target clock.

[0083] It receives access requests from multiple hosts and uses the target clock to control the orderly access of each host to the memory.

[0084] The above-described method for accessing memory can be used in memory access circuits. Specifically, a clock switching circuit switches the clock according to a preset scenario clock and provides the switched working clock (target clock) to the arbitration circuit. The arbitration circuit receives access requests from multiple hosts and uses the working clock provided by the clock switching circuit to control each host to access the memory in an orderly manner, thereby improving the efficiency of each host accessing the memory.

[0085] For a detailed description of the method for accessing memory provided in this application, please refer to the corresponding description of the circuit for accessing memory in the foregoing embodiments. The method for accessing memory described above has all the beneficial effects of the circuit for accessing memory described above, and will not be repeated here.

[0086] In a third aspect, this application also provides a System-on-a-Chip (SoC) chip, including a memory, multiple hosts, and circuitry for accessing the memory as described in any of the above embodiments. The efficiency and effectiveness of each host accessing the memory in this SoC chip are optimized, the area is reduced, and the chip performance is simultaneously improved.

[0087] In one embodiment, the structure of the above-mentioned SOC chip can be referred to Figure 10As shown in the figure, this diagram illustrates the connection characteristics and signal interaction characteristics between the first host MASTER1 and the nth host MASTERn and other circuits in the SOC chip. Taking MASTER1 as an example, MASTER1's read / write bus connects to various synchronization circuits (such as Request synchronization and Mem ready synchronization in the figure) and arbitration circuits via a protocol conversion circuit. When memory access is required, MASTER1 sends an access request (Request) to Request synchronization via the protocol conversion circuit. Request synchronization processes this access request and then sends MASTER1's access request (Request_sync) to the arbitration circuit. The arbitration circuit determines the target host for the next memory access based on the currently received access request. If the target host is MASTER1, it synchronously feeds back the access preparation signal Ready to Memready. Memready then synchronously processes the Ready signal and feeds back the Ready_sync signal to MASTER1, preparing MASTER1 to access the memory and providing its own host read / write clock MASTER_1_clk to the arbitration circuit. The arbitration circuit also switches the memory's read / write clock to MASTER1's host read / write clock MASTER_1_clk. Figure 10 In the `MASTER_x_clk`, x = 1, enable memory access to provide read and write permissions to `MASTER1`. Figure 10 The MASTER_x mem read / write bus (x=1) is shown to achieve Mem clock switching, enabling MASTER1 to access memory using its own host read / write clock MASTER_1_clk. The clock switching circuit can seamlessly switch between different scene clocks according to preset scene clocks, providing the switched working clock Arbit_clk to the arbitration circuit, allowing the arbitration circuit to control the orderly access of memory by each host using a stable and effective working clock.

[0088] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0089] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0090] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0091] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A circuit for accessing a memory, characterized by The clock switching circuit and the arbitration circuit are included; The clock switching circuit is configured to perform clock switching according to a preset scene clock, and provide a working clock after switching to the arbitration circuit; The arbitration circuit is configured to receive access requests of a plurality of hosts, and control the hosts to orderly access a memory by using the working clock; The arbitration circuit is further configured to control a current host to access the memory by using the working clock, and determine a target host for next time to access the memory, and switch the host to access the memory to the target host when the target host is inconsistent with the current host; The scene clock includes a first clock and a second clock, the first clock is a clock before switching, and the second clock is a clock after switching; the clock switching circuit is configured to turn off a first selection signal corresponding to the first clock at a preset clock switching time, turn off a first clock domain signal corresponding to the first selection signal, turn on a second selection signal corresponding to the second clock, turn on a second clock domain signal corresponding to the second selection signal, and provide the second clock to the arbitration circuit as a clock after switching.

2. The circuit for accessing a memory according to claim 1, characterized in that, The first clock domain signal is turned off at a falling edge of the first clock; and / or, the second clock domain signal is turned on at a falling edge of the second clock.

3. The circuit for accessing a memory according to claim 1, wherein, The clock switching circuit includes a first OR gate and a clock switching unit corresponding to each scene clock; an output end of each clock switching unit is connected to one input end of the first OR gate, and an output end of the first OR gate is an output end of the clock switching circuit; Each clock switching unit is configured to access a corresponding scene clock and a selection signal.

4. The circuit for accessing a memory according to claim 3, characterized in that, When the corresponding clock domain signal is turned on, each clock switching unit is further configured to set other clock switching units to an asynchronous reset state.

5. The circuit for accessing memory of claim 3, wherein, The clock switching unit includes a first D flip-flop, a second D flip-flop, and a first AND gate; A first input end of the first D flip-flop accesses corresponding selection information, a second input end accesses a corresponding scene clock, and an output end is connected to a first input end of the second D flip-flop; a second input end of the second D flip-flop accesses the corresponding scene clock, and an output end is connected to a first input end of the first AND gate; a second input end of the first AND gate accesses the corresponding scene clock, and an output end is connected to one input end of the first OR gate.

6. The circuit for accessing a memory according to claim 5, characterized in that, The clock switching unit further includes a first NOR gate; each input end of the first NOR gate is connected to an output end of a second D flip-flop in one other clock switching unit, and an output end is connected to asynchronous reset ends of the first D flip-flop and the second D flip-flop.

7. The circuit for accessing memory of claim 1, wherein, The arbitration circuit is further configured to prestore access sequences corresponding to each host, and when an access request of a first host is received, determine whether the first host is a host to access the memory next time according to the access sequences, and if yes, determine the first host as the target host.

8. The circuit for accessing memory of claim 1, wherein, The arbitration circuit is further configured to prestore access priorities corresponding to each host, and when an access request of a first host is received, determine whether the first host has access authority according to the access priorities and the currently received access request, and if yes, determine the first host as the target host.

9. The circuit for accessing memory of claim 1, wherein, The arbitration circuit is further configured to, after determining the target host, feed back an access preparation signal to the target host, switch a read-write clock of the memory to a host read-write clock of the target host, and feed back an access occupation signal to each of the other hosts.

10. The circuit for accessing a memory according to claim 9, characterized in that, The arbitration circuit comprises an access state determination unit, a signal feedback unit, and a clock configuration unit. The access state determination unit is configured to determine an access state of each of the hosts and the target host. The signal feedback unit is configured to feed back an access preparation signal to the target host and an access occupation signal to each of the other hosts. The clock configuration unit is configured to switch the read-write clock of the memory to the host read-write clock of the target host.

11. The circuit for accessing memory of claim 1, wherein, Each host is further provided with a protocol conversion circuit, which is configured to convert a data read-write interface of the corresponding host to an interface matched with the memory. Each host is further provided with a synchronization circuit, which is configured to synchronize information between the corresponding host and the arbitration circuit.

12. A method of accessing a memory, characterized by, The method for accessing the memory is implemented by using the circuit for accessing the memory according to any one of claims 1 to 11, and comprises the following steps. Switching a working clock for controlling the hosts to access the memory to a target clock according to a preset scene clock; Receiving access requests of the hosts, and controlling the hosts to access the memory in an orderly manner by using the target clock.

13. A SOC chip, comprising: The system comprises a memory, a plurality of hosts, and the circuit for accessing the memory according to any one of claims 1 to 11.

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