Gate driver and display device including the same

Abstract

Disclosed are a gate driver and a display device including the gate driver. The gate driver includes: a plurality of signal transmission units connected in cascade via a carry line to which a carry signal from a preceding signal transmission unit is applied, the nth signal transmission unit including: a first circuit unit including a first Q logic generator receiving a carry signal from the preceding signal transmission unit to charge a first control node and a second Q logic generator discharging the first control node; a second circuit unit charging or discharging the second control node according to a voltage of the first control node; and an output unit outputting a carry signal and a gate signal based on potentials of the first and second control nodes, the output unit including: a 2-1st transistor having a first electrode, a gate, a back gate, and a second electrode; and a 2-2nd transistor having a first electrode, a gate, a back gate, and a second electrode, wherein n is a positive integer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0127134, filed on September 27, 2021, and Korean Patent Application No. 10-2021-0181988, filed on December 17, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a gate driver and a display device including the gate driver. Background Art

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field luminescent display (FED) devices, plasma display panels (PDPs), and the like.

[0005] Electroluminescent displays are categorized into inorganic and organic light-emitting displays (OLEDs), depending on the material used in their light-emitting layers. Active-matrix OLEDs use self-luminous elements, such as organic light-emitting diodes (OLEDs), to reproduce input images. OLEDs offer advantages such as fast response times, high luminous efficiency, high brightness, and a wide viewing angle.

[0006] Some display devices, such as liquid crystal display devices or organic light-emitting display devices, include: a display panel including a plurality of sub-pixels; a driver that outputs drive signals for driving the display panel; a power supply that generates power to be supplied to the display panel or the driver; etc. The driver includes a gate driver that provides scan signals or gate signals to the display panel, and a data driver that provides data signals to the display panel.

[0007] In such a display device, when driving signals such as scan signals, EM signals, and data signals are supplied to a plurality of sub-pixels formed in a display panel, selected sub-pixels transmit light or directly emit light, thereby displaying an image.

[0008] In this case, a transistor for improving discharge characteristics is added to the gate driver. However, since the addition of the transistor may increase the frame, and the added transistor operates at Vgs=0V in the off section, which generates leakage current, power consumption may increase, and the output of the gate signal may be degraded. Summary of the Invention

[0009] The present invention is intended to meet all of the above needs and / or solve the above problems.

[0010] The present invention is directed to providing a gate driver capable of reducing leakage current while reducing the number of transistors, and a display device including the gate driver.

[0011] It should be noted that the objects of the present invention are not limited to the above objects, and other objects of the present invention will be clear to those skilled in the art based on the following description.

[0012] A gate driver according to an embodiment of the present invention includes: a plurality of signal transmission units, the signal transmission units being cascade-connected via carry lines to which carry signals from preceding signal transmission units are applied, wherein an nth signal transmission unit includes: a first circuit unit including a first Q logic generator configured to receive the carry signal from the preceding signal transmission unit to charge a first control node and a second Q logic generator configured to discharge the first control node; a second circuit unit configured to discharge a second control node according to a voltage of the first control node; and an output unit configured to output a voltage based on the first control node. The carry signal and the gate signal are outputted from the potential of the node and the second control node, wherein the second Q logic generator includes: a 2-1 transistor, the 2-1 transistor having a first electrode connected to the first control node, a gate connected to the second control node, a back gate receiving the carry signal from the subsequent signal transmission unit, and a second electrode connected to the buffer node; and a 2-2 transistor, the 2-2 transistor having a first electrode connected to the buffer node, a gate connected to the second control node, a back gate receiving the carry signal from the subsequent signal transmission unit, and a second electrode connected to the low potential voltage line, wherein n is a positive integer.

[0013] A gate driver according to an embodiment of the present invention includes: a plurality of signal transmission units, the signal transmission units being cascade-connected via carry lines to which carry signals from preceding signal transmission units are applied, wherein an nth signal transmission unit includes: a circuit unit configured to receive the carry signal from the preceding signal transmission unit to charge or discharge voltages of a first control node and a second control node; and an output unit configured to output a gate signal and the carry signal based on potentials of the first control node and the second control node, wherein the output unit includes: a first pull-up transistor having a first electrode connected to a first high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a first output node a first pull-down transistor having a first electrode connected to the first output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a first low-potential voltage line; a second pull-up transistor having a first electrode connected to a second high-potential voltage line, a gate connected to the first control node, and a second electrode connected to the second output node; and a second pull-down transistor having a first electrode connected to the second output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a second low-potential voltage line, wherein n is a positive integer.

[0014] A display device according to an embodiment of the present invention includes: a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power supply lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver configured to provide data voltages of pixel data to the data lines; and a gate driver configured to provide gate signals to the gate lines, wherein the gate driver includes a plurality of signal transmission units cascade-connected via carry lines to which carry signals from preceding signal transmission units are applied, wherein the nth signal transmission unit includes: a first circuit unit including a first Q logic generator configured to receive the carry signal from the preceding signal transmission unit to charge a first control node, and a second Q logic generator configured to discharge the first control node a second circuit unit configured to discharge a second control node according to a voltage of the first control node; and an output unit configured to output the carry signal and the gate signal based on the potentials of the first control node and the second control node, wherein the second Q logic generator includes: a 2-1 transistor having a first electrode connected to the first control node, a gate connected to the second control node, a back gate receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a buffer node; and a 2-2 transistor having a first electrode connected to the buffer node, a gate connected to the second control node, a back gate receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a low potential voltage line, wherein n is a positive integer.

[0015] According to an embodiment of the present invention, a display device includes: a display panel, on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver, the data driver being configured to provide a data voltage of pixel data to the data driver; and a gate driver, the gate driver being configured to provide a gate signal to the gate line, wherein the gate driver includes a plurality of signal transmission units, the signal transmission units being cascade-connected via a carry line to which a carry signal from a previous signal transmission unit is applied, wherein the nth signal transmission unit includes: a circuit unit, the circuit unit being configured to receive the carry signal from the previous signal transmission unit to charge or discharge the voltages of a first control node and a second control node; and an output unit, the output unit being configured to output a gate signal and the carry signal based on the potentials of the first control node and the second control node, wherein the output unit The element includes: a first pull-up transistor, the first pull-up transistor having a first electrode connected to a first high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a first output node; a first pull-down transistor, the first pull-down transistor having a first electrode connected to the first output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a first low-potential voltage line; a second pull-up transistor, the second pull-up transistor having a first electrode connected to a second high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a second output node; and a second pull-down transistor, the second pull-down transistor having a first electrode connected to the second output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a second low-potential voltage line, wherein n is a positive integer.

[0016] In the present invention, since the transistor for controlling discharge of the gate driver is configured in a dual-gate structure and a negative bias is applied to the back gate when the transistor of the dual-gate structure is turned off, leakage current can be reduced while reducing the number of transistors.

[0017] In the present invention, power consumption and output characteristics can be improved by reducing leakage current.

[0018] In the present invention, since a separate transistor for improving discharge characteristics is not necessary, not only can a path where leakage current may be generated be reduced, but also a frame size can be reduced.

[0019] The effects of the present invention are not limited to the above-mentioned effects, and those skilled in the art will clearly understand other effects not mentioned above based on the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art through detailed description of exemplary embodiments with reference to the accompanying drawings.

[0021] Figure 1 is a view schematically illustrating a shift register of a gate driver according to a first embodiment of the present invention;

[0022] Figure 2 is a view illustrating a gate driver according to a first embodiment of the present invention;

[0023] Figure 3 It is a diagram Figure 2 The voltage waveform of the control node and the input / output signal of the gate driver shown;

[0024] Figures 4A to 4C is a diagram illustrating a leakage current reduction principle of a second Q logic generator by comparison;

[0025] Figure 5 is a view illustrating a gate driver according to a second embodiment of the present invention;

[0026] Figure 6 is a view schematically illustrating a shift register of a gate driver according to a third embodiment of the present invention;

[0027] Figure 7 is a circuit diagram illustrating in detail a gate driver according to a third embodiment of the present invention;

[0028] Figure 8 It is a diagram Figure 7 The voltage of the control node of the gate driver and the waveform of the input / output signal are shown;

[0029] Figures 9A to 9C This is a diagram illustrating the principle of reducing leakage current of an output unit by comparison.

[0030] Figure 10 It is used for graphic purposes Figure 7 A view of the simulation results (display picture) obtained for the EM driver shown;

[0031] Figure 11 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0032] Figure 12 It is a diagram Figure 11A cross-sectional view of the display panel is shown;

[0033] Figure 13 Is a diagram applied to Figure 11 A circuit diagram of a pixel circuit of a display panel shown;

[0034] Figure 14 It is a diagram Figure 13 2 is a waveform diagram of the driving method of the pixel circuit shown. DETAILED DESCRIPTION

[0035] The advantages and features of the present invention and their implementation methods will be more clearly understood through the following embodiments described with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and can be implemented in various forms. The embodiments of the present invention will complete the disclosure of the present invention and enable those skilled in the art to fully understand the scope of the present invention. The present invention is limited only by the scope of the appended claims.

[0036] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for the purpose of describing the embodiments of the present invention are merely examples and the present invention is not limited thereto. Like reference numerals generally denote like elements throughout the specification. Furthermore, in describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0037] As used herein, terms such as "including," "comprising," and "having" are generally intended to allow for the addition of additional components unless these terms are used with the term "only."

[0038] Even if not explicitly described, the components are construed as including the usual error range.

[0039] When terms such as “on,” “over,” “below,” and “after” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used with the terms “immediately” or “directly.”

[0040] Terms such as “first” and “second” may be used to distinguish components from each other, but the functions or structures of the components are not limited by the sequence numbers or names preceding these components.

[0041] The same reference numerals may substantially refer to the same elements throughout the specification.

[0042] The following embodiments may be combined or combined with each other in part or in whole and may be technically related and operated in various ways. These embodiments may be implemented independently of each other or in association with each other.

[0043] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a view schematically illustrating a shift register of a gate driver according to a first embodiment of the present invention.

[0045] Reference Figure 1 , the gate driver according to the first embodiment includes a shift register that sequentially outputs output pulses of gate signals (hereinafter, referred to as “gate pulses”) SCOUT(n−2) to SCOUT(n+2) in synchronization with a shift clock CLK. Figure 1 SET in the figure represents the set terminal, and RESET represents the reset terminal.

[0046] The shift register includes a plurality of signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) that are cascade-connected via a carry line for transmitting a carry signal.

[0047] The timing controller may adjust the width and multi-output of the output signal SCOUT of the gate driver using the start pulse VST input to the gate driver.

[0048] The start signal VST is usually input to the first signal transmission unit. Figure 2 , the n-2 th signal transmission unit ST(n-2) may be the first signal transmission unit to receive the start signal VST.

[0049] The signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) receive the start pulse or carry signal Cout(n-2), Cout(n-1), Cout(n), Cout(n+1), and Cout(n+2) output from the previous signal transmission unit, respectively, and receive the shift clock CLK. The first signal transmission unit ST(n-2) starts driving according to the start pulse VST, and the other signal transmission units ST(n-1), ST(n), ST(n+1), and ST(n+2) receive the carry signal Cout(n-2), Cout(n-1), Cout(n), and Cout(n+1) from the previous signal transmission unit and start driving. The shift clock CLK can be an N-phase clock (N is a positive integer greater than or equal to 2). For example, the shift clock CLK can be a four-phase clock CLK1, CLK2, CLK3, and CLK4. The phase difference between the four-phase clocks CLK1 , CLK2 , CLK3 , and CLK4 may be 90 degrees.

[0050] The signal transmission units ST(n-2) to ST(n+2) may output the carry signal Cout through the second output node while outputting the scan pulses SCOUT(n-2) to SCOUT(n+2) through the first output node, respectively.

[0051] Figure 2 is a view illustrating a gate driver according to a first embodiment of the present invention; Figure 3 It is a diagram Figure 2 Here, an example in which the gate driver is implemented as a scan driver will be described.

[0052] Reference Figure 2 According to an embodiment, the scan driver may include: a first control node (hereinafter referred to as a "Q node") for pulling up the output voltage; a second control node (hereinafter referred to as a "Qb node") for pulling down the output voltage; a first circuit unit 61; a second circuit unit 62; and an output unit 63.

[0053] The first circuit unit 61 may include a first Q logic generator 61a and a second Q logic generator 61b. The first Q logic generator 61a charges the Q node Q, and the second Q logic generator 61b discharges the first control node.

[0054] The first Q logic generator 61 a includes a 1-1th transistor T1 , a 1-2th transistor T1A, and a 1-3rd transistor T3 q .

[0055] The 1-1 transistor T1 is turned on by the N-2 th carry signal C(n-2) from the previous signal transmission unit and provides the voltage of the N-2 th carry signal C(n-2) to the buffer node Qh. The 1-1 transistor T1 includes a first electrode and a gate that receive the N-2 th carry signal from the previous signal transmission unit, and a second electrode connected to the buffer node.

[0056] The 1-2 transistor T1A is turned on by the N-2 th carry signal C(n-2) and charges the Q node Q based on the N-2 th carry signal. The 1-2 transistor T1A includes a first electrode connected to the second electrode of the 1-1 transistor T1 or the buffer node Qh, a gate connected to the N-2 th carry signal C(n-2), and a second electrode connected to the Q node Q.

[0057] The 1-3 transistor T3q is turned on through the Q node Q and transmits the high potential voltage of the high potential voltage line GVDD to the buffer node Qh. The 1-3 transistor T3q includes a first electrode connected to the high potential voltage line GVDD, a gate connected to the Q node Q, and a second electrode connected to the buffer node Qh.

[0058] The second Q logic generator 61 b ​​includes a 2-1st transistor T3 , a 2-2nd transistor T3A, a 2-3rd transistor T3 nB, and a 2-4th transistor T3 nC.

[0059] The 2-1st transistor T3 is turned on via the Qb node Qb, and discharges the Q node Q to the third low potential voltage of the third low potential voltage line GVSS2 together with the 2-2nd transistor T3A.

[0060] When the 2-1st transistor T3 is turned off via the Qb node Qb, a negative bias voltage is applied to the back gate electrode via the N+2th carry signal C(n+2) from the next signal transmission unit. Consequently, the threshold voltage Vth of the 2-1st transistor T3 can be increased, thereby reducing leakage current. The 2-1st transistor T3 includes a first electrode connected to the first control node Q, a gate connected to the second control node Qb, a back gate to which the N+2th carry signal C(n+2) is applied, and a second electrode connected to the first electrode of the 2-2nd transistor T3A.

[0061] The 2-2 th transistor T3A is turned on through the second control node Qb, and discharges the first control node Qb to the third low potential voltage of the third low potential voltage line GVSS2 together with the 2-1 th transistor T3 .

[0062] When the 2-2 transistor T3A is turned off via the Qb node Qb, a negative bias voltage is applied to the back gate via the N+2 carry signal C(n+2) from the subsequent signal transmission unit. Consequently, the threshold voltage Vth of the 2-2 transistor T3A can be increased, thereby reducing leakage current. The 2-2 transistor T3A includes a first electrode connected to the second electrode of the 2-1 transistor T3, a gate connected to the Qb node Qb, a back gate to which the N+2 carry signal C(n+2) is applied, and a second electrode connected to the third low potential voltage line GVSS2.

[0063] The 2nd-3rd transistor T3nB is turned on by the start pulse VST and discharges the Q node Q to the third low potential voltage of the third low potential voltage line GVSS2 together with the 2nd-4th transistor T3nC. The 2nd-3rd transistor T3nB includes a first electrode connected to the Q node Q, a gate to which the start pulse VST is applied, and a second electrode connected to the first electrode of the 2nd-4th transistor T3nC.

[0064] The 2nd-4th transistor T3nC is turned on by the start pulse VST and discharges the first control node Q to the third low potential voltage of the third low potential voltage line GVSS2 together with the 2nd-3rd transistor T3nB. The 2nd-4th transistor T3nC includes a first electrode connected to the second electrode of the 2nd-3rd transistor T3nB, a gate to which the start pulse VST is applied, and a second electrode connected to the third low potential voltage line GVSS2.

[0065] The second circuit unit 62 includes a 3-1st transistor T4, a 3-2nd transistor T41, a 3-3rd transistor T4q, a 3-4th transistor T5q, and a 3-5th transistor T5.

[0066] The 3-1st transistor T4 is turned on by the voltage of the first node n1 and supplies a high potential voltage to the Qb node Qb. The 3-1st transistor T4 includes a first electrode connected to a high potential voltage line to which a high potential voltage is applied, a gate connected to the first node n1, and a second electrode connected to the second control node. A first capacitor C1 is connected between the gate and the second electrode of the fourth transistor T4.

[0067] The 3-2 th transistor T41 is turned on by the high potential voltage and supplies the high potential voltage to the first node n1. The 3-2 th transistor T41 includes a first electrode and a gate connected to the high potential voltage line, and a second electrode connected to the first node n1.

[0068] The 3-3 transistor T4q is turned on by the voltage of the Q node Q and discharges the first node n1 to the second low potential voltage. The 3-3 transistor T4q includes a first electrode connected to the first node n1, a gate connected to the Q node, and a second electrode connected to the second low potential voltage line GVSS1.

[0069] The 3rd-4th transistor T5q is turned on by the voltage of the Q node Q and discharges the Qb node Qb to the third low potential voltage. The 3rd-4th transistor T5q includes a first electrode connected to the Qb node Qb, a gate connected to the Q node Q, and a second electrode connected to the third low potential voltage line GVSS2.

[0070] The 3-5th transistor T5 is turned on by the voltage of the carry signal C(n-2) from the previous signal transmission unit and discharges the Qb node Qb to the third low potential voltage. The 3-5th transistor T5 includes a first electrode connected to the Qb node Qb, a gate to which the carry signal C(n-2) from the previous signal transmission unit is applied, and a second electrode connected to the third low potential voltage line GVSS2.

[0071] The output unit 63 can output a scan signal SCOUT(n) to a first output node based on the potentials of the Q node Q and the Qb node Qb, and output a carry signal COUT(n) to a second output node. The output unit 63 can include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

[0072] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q and the Qb node Qb to output the scan signal SCOUT(n). The first pull-up transistor T6 includes a gate connected to the Q node Q, a first electrode to which the clock signal SCCLK(n) is applied, and a second electrode connected to the first output node. The second capacitor C2 is connected between the gate and the second electrode of the first pull-up transistor T6. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node therebetween. The first pull-down transistor T7 includes a gate connected to the Qb node Qb, a first electrode connected to the first output node, and a second electrode connected to the first low potential voltage line GVSS0.

[0073] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltage of the Q node Q and the Qb node Qb to output the scan signal COUT(n). The second pull-up transistor T6cr includes a gate connected to the Q node Q, a first electrode to which the clock signal SC_CRCLK(n) is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node therebetween. The second pull-down transistor T7cr includes a gate connected to the Qb node Qb, a first electrode connected to the second output node, and a second electrode connected to the third low potential voltage line GVSS2.

[0074] A description will be given of a structural advantage of the second Q logic generator applied to the scan driver according to the embodiment.

[0075] Figures 4A to 4C is a view describing the leakage current reduction principle of the second Q logic generator by comparison.

[0076] Reference Figure 4A The 2-1 transistor T3 and the 2-2 transistor T3A of the second Q logic generator according to the embodiment are implemented using a dual-gate structure with an LS metal layer, which is a light-blocking layer of a coplanar element, as a back gate. While the Qb node Qb is turned off when it is discharged, the back gate receives a negative bias voltage, that is, a carry signal C(n+2) of a gate low voltage, from a subsequent signal transmission unit. Due to the negative bias voltage, the threshold voltage Vth increases, and thus the leakage current is reduced.

[0077] like Figure 4B As shown, the circuit for comparison with the second Q logic generator of the embodiment is additionally configured with a 2-1b transistor T3n and a 2-2b transistor T3nA in addition to the 2-1 transistor T3 and the 2-2 transistor T3A to improve discharge characteristics. Therefore, even if the 2-1 transistor T3, the 2-1b transistor T3n, the 2-2 transistor T3A, and the 2-2b transistor T3nA are turned off when the Qb node Qb is discharged, since the gate-source voltage Vgs of each of the 2-2 transistor T3A and the 2-2b transistor T3nA becomes less than 0 when the threshold voltage Vth shifts to the negative polarity and thus Vth is less than 0, leakage current is generated in the low potential voltage line GVSS2, and thus power consumption increases.

[0078] In this case, in the circuit of the comparative example, leakage current is generated to the same degree as the threshold voltage, namely Vth(Δ), but in the circuit of the embodiment, leakage current is generated to the degree corresponding to Vth×0.42, thereby reducing leakage current. The leakage current generated in the circuit of the embodiment is reduced by the effect of the dual-gate structure and is reduced in proportion to the capacitance ratio of the upper gate and the lower gate (0.42). The capacitance ratio of the upper gate and the lower gate can be changed according to various design parameters of each of the upper gate and the lower gate, such as length, thickness, width, etc.

[0079] In this case, the leakage current decreases in proportion to the capacitance ratio of the upper gate and the lower gate, and thus can be effective only when the capacitance of the upper gate is smaller than that of the lower gate.

[0080] In the embodiment, by applying the signal applied to the 2-1b-th transistor T3n and the 2-2b-th transistor T3nA of the comparative example to the back gates of the 2-1 transistor T3 and the 2-2 transistor T3A, the 2-1 transistor T3 and the 2-2 transistor T3A are configured to also function as the 2-1b-th transistor T3n and the 2-2b-th transistor T3nA.

[0081] exist Figure 4A In the circuit of the embodiment, due to the Figure 4B In the circuit of the comparative example, transistors T3n and T3nA are removed, reducing the leakage current generation path and reducing the frame size accordingly. In this case, the circuit of the embodiment requires increasing the transistor size to maintain the same falling characteristics as the circuit of the comparative example, but the amount of leakage current is reduced, thus offering advantages in terms of improved power consumption and improved output.

[0082] like Figure 4CAs shown, when Vth is -2 V, a leakage current is generated in the low-potential voltage line GVSS2, so a difference occurs between the target voltage and the actual voltage of the low-potential voltage line in the circuit of the comparative example. On the other hand, there is no difference between the target voltage and the actual voltage of the low-potential voltage line in the circuit of the embodiment.

[0083] That is, it can be seen that in the circuit of the embodiment, power consumption is improved and the output is stabilized.

[0084] Figure 5 is a view illustrating a gate driver according to a second embodiment of the present invention.

[0085] Reference Figure 5 The gate driver according to the second embodiment may include a first control node (hereinafter referred to as “Q node”), a second control node (hereinafter referred to as “Qb node”), a circuit unit 70 and an output unit 73.

[0086] The circuit unit 70 may receive a carry signal from a previous signal transmission unit to charge or discharge the voltages of the first control node and the second control node.

[0087] The output unit 73 may output the emission control signal EMOUT to the first output node and the carry signal COUT(n) to the second output node based on the potentials of the Q node Q and the Qb node Qb. The output unit 73 may include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

[0088] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q and the Qb node Qb to output the light emission control signal EMOUT. The first pull-up transistor T6 includes a gate connected to the Q node Q, a first electrode connected to the first high-potential voltage line GVDD0 to which a first high-potential voltage is applied, and a second electrode connected to the first output node. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node therebetween. The first pull-down transistor T7 includes a gate connected to the second control node Qb, a first electrode connected to the first output node, and a second electrode connected to the first low-potential voltage line GVSS0 to which a first low-potential voltage is applied.

[0089] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q and the Qb node Qb to output a carry signal COUT(n). The second pull-up transistor T6cr includes a gate connected to the Q node Q, a first electrode connected to the second high potential voltage line GVDD1 to which a second high potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node therebetween. The second pull-down transistor T7cr includes a gate connected to the Qb node Qb, a first electrode connected to the second output node, and a second electrode connected to the second low potential voltage line GVSS1 to which a second low potential voltage is applied.

[0090] Figure 6 is a view schematically illustrating a shift register of a gate driver according to a third embodiment of the present invention.

[0091] Reference Figure 6 , a gate driver according to an embodiment includes a shift register that sequentially outputs output pulses (hereinafter, referred to as “EM pulses”) EMOUT(n−2) to EMOUT(n+2) of a gate signal in synchronization with a shift clock CLK. Figure 6 QbSET in represents a terminal receiving a voltage from the Qb node Qb(n-1) of the previous stage.

[0092] The shift register includes a plurality of signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) connected in cascade via a carry line to which a carry signal is applied.

[0093] Timing controller 130 (see Figure 11 ) The width and number of outputs of the output signal EMOUT of the gate driver 120 can be adjusted using the start pulse VST input to the gate driver 120.

[0094] The start signal VST is usually input to the first signal transmission unit. Figure 6 , the n-2 th signal transmission unit ST(n-2) may be the first signal transmission unit to receive the start signal VST.

[0095] The signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) receive the start pulse or carry signal Cout(n-2), Cout(n-1), Cout(n), Cout(n+1), and Cout(n+2) output from the preceding signal transmission unit, respectively, and receive the shift clock CLK. The first signal transmission unit ST(n-2) begins driving based on the start pulse VST, while the other signal transmission units ST(n-1), ST(n), ST(n+1), and ST(n+2) receive the carry signal Cout(n-2), Cout(n-1), Cout(n), and Cout(n+1) from the preceding signal transmission unit and begin driving. The shift clock CLK can be an N-phase clock (N is a positive integer greater than or equal to 2). For example, the shift clock CLK can be a two-phase clock CLK1 and CLK2. The two-phase clocks CLK1 and CLK2 have opposite phases.

[0096] The signal transmission units ST(n-2) to ST(n+2) may respectively output the carry signal Cout through the second output node while outputting the EM pulses EMOUT(n-2) to EMOUT(n+2) through the first output node.

[0097] Figure 7 is a circuit diagram illustrating in detail a gate driver according to a third embodiment of the present invention. Figure 7 The circuit shown is the circuit of the nth (n is a positive integer) signal transmission unit ST(n). Other signal transmission units can be implemented using circuits substantially the same as the nth signal transmission unit ST(n). Figure 8 It is a diagram Figure 7 Here, an example in which the gate driver is implemented as an EM driver will be described.

[0098] Reference Figure 7 and Figure 8 , the EM driver according to an embodiment may include: a first control node (hereinafter referred to as “Q node”); a second control node (hereinafter referred to as “Qb node”); a first circuit unit 71; a second circuit unit 72; and an output unit 73.

[0099] The first circuit unit 71 is used to control the charging and discharging of the Q node Q and the Qb node Qb(n). When the shift clock EMCLK has a voltage greater than or equal to the gate-on voltage VGH, the first circuit unit 71 provides the voltage of the n-1th carry signal C(n-1) from the n-1th signal transmission unit ST(n-1), which is the previous signal transmission unit, to the first control node Q to charge the first control node Q. This first circuit unit 71 includes first to third transistors T1, T1A, and T3q.

[0100] When the shift clock EMCLK is at the gate-on voltage VGH, the first transistor T1 is turned on to provide the voltage of the carry signal C(n-1) to the buffer node Qh. The first transistor T1 includes a first electrode connected to the (n-1)th carry signal C(n-1) line, a gate to which the shift clock EMCLK is applied, and a second electrode connected to the buffer node Qh.

[0101] When the shift clock EMCLK is the gate-on voltage VGH, the second transistor T1A is turned on to provide the voltage of the buffer node Qh to the first control node Q, thereby charging the first control node Q. The second transistor T1A includes a first electrode connected to the buffer node Qh, a gate to which the shift clock EMCLK is applied, and a second electrode connected to the first control node Q.

[0102] The first transistor T1 and the second transistor T1A are connected in series. The first transistor T1 and the second transistor T1A are connected in series between the (n-1)th carry signal C(n-1) line and the buffer node Qh.

[0103] When the first control node Q is charged, the third transistor T3q is turned on to supply a second high potential voltage to the buffer node Qh via the second high potential voltage line GVDD1. The second high potential voltage is supplied to the buffer node Qh via the second high potential voltage line GVDD1. The third transistor T3q includes a first electrode connected to the second high potential voltage line GVDD1, a gate connected to the first control node Q, and a second electrode connected to the buffer node Qh.

[0104] The second circuit unit 72 includes an inverter circuit that inverts the voltage of the first control node Q and applies the inverted voltage to the second control node Qb(n). The inverter circuit of the second circuit unit 72 includes a first Qb logic generator and a second Qb logic generator.

[0105] The first Qb logic generator includes a plurality of transistors T4 and T41. The second Qb logic generator includes a plurality of transistors T4q and T5q, and the plurality of transistors T4q and T5q are connected in series.

[0106] The first Qb logic generator switches a current path between the second high potential voltage line GVDD1 and the second control node Qb(n) according to the voltage of the Qb node Qb(n-1) from the n-1th signal transmission unit ST(n-1).

[0107] When the voltage at the first node n1 is the gate-on voltage VGH, the fourth transistor T4 is turned on to charge the Qb node Qb(n) to the gate-on voltage VGH by connecting the second high potential voltage line GVDD1 to the Qb node Qb(n). The fourth transistor T4 includes a first electrode connected to the second high potential voltage line GVDD1, a gate connected to the first node n1, and a second electrode connected to the Qb node Qb(n). The first capacitor C1 is connected between the gate and the second electrode of the fourth transistor T4. When the fourth transistor T4 is turned on by the first capacitor C1, the voltage at the first node n1 can be boosted.

[0108] When the voltage of the Qb node Qb(n-1) of the n-1th signal transmission unit ST(n-1) is the gate-on voltage VGH, the 4-1th transistor T41 is turned on to charge the first node n1 to the gate-on voltage VGH by supplying the second high potential voltage to the first node n1. The 4-1th transistor T41 includes a first electrode connected to the second high potential voltage line GVDD1, a gate connected to the Qb node Qb(n-1) of the n-1th signal transmission unit ST(n-1), and a second electrode connected to the first node n1.

[0109] When the voltage of the previous carry signal C(n-1) input from the n-1th signal transmission unit ST(n-1) and the voltage of the Q node Q are the gate-on voltage VGH, the second Qb logic generator is turned on to discharge the Qb node Qb(n).

[0110] When the voltage of the buffer node Qh is the gate-on voltage VGH, the 4-q-th transistor T4q is turned on to connect the first node n1 to the Qb node Qb(n). The 4-q-th transistor T4q includes a first electrode connected to the first node n1, a gate connected to the buffer node Qh, and a second electrode connected to the Qb node Qb(n).

[0111] When the voltage of the buffer node Qh is the gate-on voltage VGH, the 5-q-th transistor T5q is turned on to discharge the voltage of the Qb node Qb(n) to the second low potential voltage by connecting the Qb node Qb(n) to the second low potential voltage line GVSS1. The 5-q-th transistor T5q includes a first electrode connected to the Qb node Qb(n), a gate connected to the buffer node Qh, and a second electrode connected to the second low potential voltage line GVSS1.

[0112] The output unit 73 can output the emission control signal EMOUT to the first output node and the carry signal COUT(n) to the second output node based on the potentials of the Q node Q and the Qb node Qb(n). The output unit 73 can include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

[0113] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltage of the Q node Q and the Qb node Qb(n) to output the light emission control signal EMOUT. The first pull-up transistor T6 includes a gate connected to the first control node Q, a first electrode connected to the first high potential voltage line GVDD to which a first high potential voltage is applied, and a second electrode connected to the first output node. The second capacitor C2 is connected between the gate and the second electrode of the first pull-up transistor T6. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node therebetween. The first pull-down transistor T7 includes a gate connected to the second control node Qb(n), a first electrode connected to the first output node, a back gate that receives a carry signal from the previous signal transmission unit, and a second electrode connected to the first low potential voltage line GVSS0 to which a first low potential voltage is applied.

[0114] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q and the Qb node Qb(n) to output a carry signal COUT(n). The second pull-up transistor T6cr includes a gate connected to the Q node Q, a first electrode connected to the second high potential voltage line GVDD1 to which a second high potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node therebetween. The second pull-down transistor T7cr includes a gate connected to the Qb node Qb(n), a first electrode connected to the second output node, a back gate that receives a carry signal from a previous signal transmission unit, and a second electrode connected to the second low potential voltage line GVSS1 to which a second low potential voltage is applied.

[0115] Structural advantages applied to the output unit of the EM driver according to the embodiment will be described.

[0116] Figures 9A to 9C It is a view describing the leakage current reduction principle of the output unit by comparison.

[0117] Reference Figure 9AAccording to the embodiment, the first pull-down transistor T7 and the second pull-down transistor T7cr of the output unit are implemented using a dual-gate structure with an LS metal layer as a light-blocking layer of a coplanar element as a back gate, so as to receive a negative bias voltage, that is, a carry signal C(n-2) of a gate low voltage, from the scan driver to the back gate while being turned off when the Qb node Qb(n) is discharged. The threshold voltage Vth of each of the first pull-down transistor T7 and the second pull-down transistor T7cr is increased due to the negative bias voltage, and thus the leakage current is reduced.

[0118] like Figure 9B As shown, in the circuit compared with the output unit of the embodiment, a 2-1st pull-down transistor T8cr is added to the second pull-down transistor T7cr, whereby even if the second pull-down transistor T7cr is turned off when the second control node is discharged and the carry signal SC_C(n-2) of the low voltage level is applied to the 2-1st pull-down transistor T8cr, since the threshold voltage is shifted to the negative polarity and the carry signal SC_C(n-2) of the low voltage level leaks by an amount corresponding to the threshold voltage Δ, a leakage current of an amount corresponding to the threshold voltage Δ may be generated from the gate-source voltage Vgs of the 2-1st pull-down transistor T8cr, thereby increasing power consumption.

[0119] In this case, in the circuit of the comparative example, leakage current is generated to a level corresponding to the threshold voltage, namely Vth(Δ), but in the circuit of the embodiment, leakage current is generated to a level corresponding to Vth×0.42, thereby reducing leakage current. The leakage current generated in the circuit of the embodiment is reduced by the effect of the dual-gate structure and is reduced in proportion to the capacitance ratio of the upper gate and the lower gate (0.42). The capacitance ratio of the upper gate and the lower gate can be changed according to various design parameters of each of the upper gate and the lower gate, such as length, thickness, width, etc.

[0120] In this case, the leakage current decreases in proportion to the capacitance ratio of the upper gate and the lower gate, and thus can be effective only when the capacitance of the upper gate is smaller than that of the lower gate.

[0121] In an embodiment, by applying a signal applied to the 1-1 pull-down transistor T8 and the 2-1 pull-down transistor T8cr of the comparative example to the back gates of the first pull-down transistor T7 and the second pull-down transistor T7cr, the first pull-down transistor T7 and the second pull-down transistor T7cr are configured to also function as the 1-1 pull-down transistor T8 and the 2-1 pull-down transistor T8cr.

[0122] exist Figure 9A In the circuit of the embodiment, due to the Figure 9BIn the circuit of the comparative example, transistors T8 and T8cr are removed, reducing the leakage current generation path and reducing the frame size accordingly. In this case, the circuit of the embodiment requires increasing the transistor size to maintain the same voltage-dropping characteristics as the circuit of the comparative example, but the amount of leakage current is reduced, thus offering advantages in terms of improved power consumption and improved output.

[0123] like Figure 9C As shown, since leakage current is generated toward the output node outputting the carry signal COUT(n), a difference occurs between the target voltage and the actual voltage of the output node in the circuit of the comparative example. On the other hand, there is no difference between the target voltage and the actual voltage of the output node in the circuit of the embodiment.

[0124] Figure 10 It is used for graphic purposes Figure 7 A view of the simulation results (display picture) of the EM driver is shown.

[0125] Reference Figure 10 , shows simulation results using an EM driver according to an embodiment. It can be seen that the leakage current in the low-potential voltage line is significantly reduced in the circuit according to the embodiment compared to the circuit according to the comparative example. Furthermore, it can be seen that the leakage current at the output node outputting the carry signal is significantly reduced in the circuit according to the embodiment compared to the circuit according to the comparative example.

[0126] Figure 11 is a block diagram illustrating a display device according to an embodiment of the present invention; Figure 12 It is a diagram Figure 11 A view of the cross-sectional structure of the display panel is shown.

[0127] Reference Figure 11 and 12 , a display device according to an embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0128] The display panel 100 may be a rectangular display panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and a plurality of pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may include a power line to which a pixel drive voltage ELVDD is applied, a power line to which an initialization voltage Vinit is applied, a power line to which a reference voltage Vref is applied, and a power line to which a low potential power supply voltage ELVSS is applied. These power lines are commonly connected to the pixels.

[0129] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0130] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device that displays an image on a screen while allowing the actual background to be seen.

[0131] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on a rear panel of the plastic OLED panel, and the pixel array AA and the light-emitting element may be formed on the organic film.

[0132] To achieve color, each pixel 101 can be divided into a red sub-pixel (hereinafter referred to as an R sub-pixel), a green sub-pixel (hereinafter referred to as a G sub-pixel), and a blue sub-pixel (hereinafter referred to as a B sub-pixel). Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit. The pixel circuit is connected to a data line, a gate line, and a power line.

[0133] Pixels can be arranged as actual color pixels and pentile pixels. Pentile pixels can achieve higher resolution than actual color pixels by driving two sub-pixels with different colors into one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can use the color of light emitted from adjacent pixels to compensate for insufficient color representation in each pixel.

[0134] A touch sensor may be provided on the display panel 100. Touch input may be sensed using a separate touch sensor or may be sensed via pixels. The touch sensor may be provided as an on-cell type or an add-on type on the screen of the display panel, or implemented as an integrated type touch sensor built into the pixel array AA.

[0135] like Figure 12 As shown, when viewed from a cross-sectional structure, the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0136] The circuit layer 12 may include: pixel circuits connected to wirings such as data lines, gate lines, and power lines; gate drivers (GIPs) connected to the gate lines; etc. The wirings and circuit elements of the circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer including a semiconductor material.

[0137] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0138] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure with alternating organic and inorganic films. The inorganic films block the penetration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the path for moisture or oxygen to migrate becomes longer than with a single layer, effectively preventing the penetration of moisture and oxygen that could affect light-emitting element layer 14.

[0139] The touch sensor layer may be provided on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include an insulating layer and a metal wiring pattern that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be provided on the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase delay film are bonded, or as a circular polarizing plate. A cover glass may be bonded to the polarizing plate.

[0140] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer may replace the polarizing plate and improve color purity by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 having a higher light transmittance than the polarizing plate to the display panel, the light transmittance of the display panel 100 can be improved, and the thickness and flexibility of the display panel 100 can be improved. A glass cover may be adhered to the color filter layer.

[0141] The power supply 140 generates the DC power required to drive the pixel array AA and display panel driver of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, and the like. The power supply 140 regulates the DC input voltage from a host system (not shown) to generate DC voltages such as the gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, pixel driving voltage ELVDD, pixel low-potential power supply voltage ELVSS, reference voltage Vref, initialization voltage Vinit, and anode voltage Vano. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel driving voltage ELVDD, pixel low-potential power supply voltage ELVSS, reference voltage Vref, initialization voltage Vinit, and anode voltage Vano are commonly provided to the pixels.

[0142] The display panel driver writes pixel data (digital data) of an input image to pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0143] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0144] The demultiplexer array 112 sequentially supplies data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUXs). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0145] The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is configured to: Figure 1 The touch sensor driver may be integrated into a driver integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, the touch sensor driver, etc. may be integrated into a driver integrated circuit (IC).

[0146] The display panel driver may operate in a low-speed drive mode under the control of a timing controller (TCON) 130. The low-speed drive mode may be set to reduce the power consumption of the display device when an input image is analyzed and the input image has not changed within a preset number of frames. In the low-speed drive mode, the power consumption of the display panel driver and the display panel 100 may be reduced by reducing the refresh rate of the pixels when a still image is input for a predetermined time or longer. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in a standby mode or when no user command or input image is input to the display panel driver for a predetermined time or longer, the display panel driver may operate in a low-speed drive mode.

[0147] The data driver 110 generates data voltages Vdata by converting pixel data of an input image received from the timing controller 130 using a digital-to-analog converter (DAC) with a gamma compensation voltage during each frame period. A gamma reference voltage VGMA is divided for each grayscale level via a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is supplied to the DAC of the data driver 110. The data voltages Vdata are output via an output buffer AMP in each channel of the data driver 110.

[0148] The gate driver 120 may be implemented as a GIP (gate in panel) circuit directly formed on the circuit layer 12 of the display panel 100 together with the TFT array of the pixel array AA. The gate in panel (GIP) circuit may be provided on the bezel area BZ, which is a non-display area of ​​the display panel 100, or may be dispersed in the pixel array on which the input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals may include a scan pulse, a light emitting control pulse (hereinafter referred to as an "EM pulse"), an initialization pulse, and a sensing pulse.

[0149] The shift register of the gate driver 120 outputs a pulse of a gate signal in response to a start pulse and a shift clock from the timing controller 130 , and shifts the pulse according to the shift clock timing.

[0150] In this case, the gate driver 120 may be implemented as Figure 1 、 3 , 6, and 8 are gate drivers capable of reducing leakage current while reducing the number of transistors. In the present invention, all transistors in a display panel including a data driver, a gate driver, and a plurality of sub-pixels can be implemented using oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

[0151] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized therewith from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, and the like. Since the vertical and horizontal periods can be obtained by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0152] The host system may be any of a television (TV) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a vehicle system. The host system may scale the image signal from the video source according to the resolution of the display panel 100 and transmit the image signal along with the timing signal to the timing controller 130.

[0153] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driver at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) format and 50 Hz in the PAL (Phase Alternation Line) format. The timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz, thereby reducing the refresh rate of the pixels in the low-speed drive mode.

[0154] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110, control signals for controlling the operation timing of the demultiplexer array 112, and gate timing control signals for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver, thereby synchronizing the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0155] The voltage levels of the gate timing control signals output from the timing controller 130 may be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL via a level shifter (not shown), and then provided to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signals into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signals into the gate-on voltages VGH and VEH. The gate timing control signals include a start pulse and a shift clock.

[0156] Due to device characteristic deviations and process variations in the manufacturing process of the display panel 100, the electrical characteristics of the driving element may vary between pixels, and this difference may increase as the pixel driving time elapses. To compensate for the deviations in the electrical characteristics of the driving element between pixels, internal compensation technology or external compensation technology may be applied to the organic light emitting diode display. Internal compensation technology uses an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element of each sub-pixel to compensate the gate-source voltage Vgs of the driving element by the threshold voltage. External compensation technology uses an external compensation circuit to sense the current or voltage of the driving element in real time, which varies based on the electrical characteristics of the driving element. External compensation technology compensates for the deviations (or changes) in the electrical characteristics of the driving element of each pixel in real time by modulating the pixel data (digital data) of the input image by the deviation (or change) in the electrical characteristics of the driving element sensed for each pixel. The display panel driver can use external compensation technology and / or internal compensation technology to drive pixels. The pixel circuit of the present invention can be implemented as a pixel circuit using an internal compensation circuit.

[0157] Figure 13 Is a diagram applied to Figure 11 A circuit diagram of a pixel circuit of a display panel shown; Figure 14 It is a diagram Figure 13 2 is a waveform diagram of the driving method of the pixel circuit shown.

[0158] Reference Figure 13 and 14 The pixel circuit may include a light emitting element EL, a driving element DT driving the light emitting element EL, a plurality of switching elements (M01, M02, M03, and M04), and a capacitor Cst.

[0159] This pixel circuit is connected to a first power line PL1 to which a pixel driving voltage EVDD is applied, a second power line PL2 to which a low-potential power supply voltage EVSS is applied, a third power line PL3 to which an initialization voltage Vinit is applied, a fourth power line PL4 to which a reference voltage Vref is applied, a data line DL to which a data voltage Vdata is applied, and gate lines to which gate signals (INIT(n), SENSE(n), SCAN(n), and EM(n)) are applied. The gate signals INIT(n), SENSE(n), SCAN(n), and EM(n) may be generated by a gate driver according to an embodiment and applied to the pixel circuit via the gate lines.

[0160] The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. The anode of the light-emitting element EL is connected to the third node n3, and the cathode is connected to the second power line PL2 to which the low potential power supply voltage EVSS is applied. When a voltage is applied to the anode and cathode of the light-emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML), thereby generating excitons, thereby causing visible light to be emitted from the light-emitting layer (EML).

[0161] An organic light emitting diode (OLED) used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. An organic light emitting diode having a tandem structure may improve the brightness and lifespan of a pixel.

[0162] The driving element DT generates a current for driving the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a first electrode connected to a first node n1, a gate connected to a second node n2, and a second electrode connected to a third node n3.

[0163] The first switching element M01 is turned on by the gate-on voltage VGH of the scan pulse SCAN(n) to apply the data voltage to the second node n2. The first switching element M01 includes a first electrode connected to the data line DL to which the data voltage is applied, a gate to which the scan pulse SCAN(n) is applied, and a second electrode connected to the second node n2.

[0164] The second switching element M02 is turned on according to the gate-on voltage VGH of the initialization pulse INIT(n) to apply the initialization voltage to the second node n2. The second switching element M02 includes a first electrode connected to the third power line PL3 to which the initialization voltage is applied, a gate to which the initialization pulse INIT(n) is applied, and a second electrode connected to the second node n2.

[0165] The third switching element M03 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n) to apply the reference voltage to the third node n3. The third switching element M03 includes a first electrode connected to the third node n3, a gate to which the sensing pulse is applied, and a second electrode connected to the fourth power line PL4 to which the reference voltage is applied.

[0166] The fourth switching element M04 is turned on by the gate-on voltage VGH of the light emitting control pulse EM(n) to apply the pixel driving voltage to the first node n1. The fourth switching element M04 includes a first electrode connected to the first power line to which the pixel driving voltage is applied, a gate to which the light emitting control pulse is applied, and a second electrode connected to the first node n1.

[0167] The capacitor Cst is connected between the second node n2 and the third node n3. In the present invention, the first high potential voltage line and the second high potential voltage line are collectively referred to as high potential voltage lines, and the first low potential voltage line, the second low potential voltage line and the third low potential voltage line are collectively referred to as low potential voltage lines.

[0168] like Figure 14 As shown, the pixel circuit can be driven in the order of an initialization operation Ti, a sensing operation Ts, a data writing operation Tw, and a light emitting operation Tem. In the sensing operation Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the capacitor Cst. In the data writing operation Tw, the data voltage Vdata of the pixel data is applied to the second node n2. In the light emitting operation Tem, the light emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data.

[0169] Although the embodiments of the present invention are described in more detail with reference to the accompanying drawings, the present invention is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided for illustrative purposes only, and these embodiments are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present invention.

Claims

1. A gate driver comprising a plurality of signal transmission units, the signal transmission units being cascade-connected via a carry line to which a carry signal from a preceding signal transmission unit is applied, The nth signal transmission unit includes: a first circuit unit including a first Q logic generator configured to receive the carry signal from a previous signal transmission unit to charge a first control node and a second Q logic generator configured to discharge the first control node; a second circuit unit configured to discharge a second control node according to the voltage of the first control node; as well as an output unit configured to output a carry signal and a gate signal based on the potentials of the first control node and the second control node, The second Q logic generator comprises: a 2-1st transistor having a first electrode connected to the first control node, a gate connected to the second control node, a back gate for receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a buffer node; and a 2-2 transistor having a first electrode connected to the buffer node, a gate connected to the second control node, a back gate receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a low potential voltage line, Where n is a positive integer, and wherein the 2-1 transistor and the 2-2 transistor are configured to receive a carry signal of a gate low voltage from the subsequent signal transmission unit to the subsequent gate while being turned off when the second control node is discharged, The second circuit unit includes an inverter circuit configured to invert the voltage of the first control node and apply the inverted voltage to the second control node. wherein the inverter circuit comprises a first Qb logic generator and a second Qb logic generator, wherein the first Qb logic generator includes: a fourth transistor having a first electrode connected to a high potential voltage line, a gate connected to a first node, and a second electrode connected to the second control node; and a 4-1 transistor having a first electrode connected to the high potential voltage line, a gate connected to the second control node of the preceding signal transmission unit, and a second electrode connected to the first node, The second Qb logic generator includes: a 4-q transistor having a first electrode connected to the first node, a gate connected to the buffer node, and a second electrode connected to the second control node; and a 5-q transistor having a first electrode connected to the second control node, a gate connected to the buffer node, and a second electrode connected to the low potential voltage line. 2 . The gate driver according to claim 1 , wherein the 2-1 transistor and the 2-2 transistor are configured to be turned on by the charge voltage of the second control node to discharge the first control node to a low potential voltage.

3. The gate driver according to claim 1 , wherein the second Q logic generator further comprises: a 2-3rd transistor having a first electrode connected to the first control node, a gate for receiving a start signal, and a second electrode connected to the buffer node; as well as A 2-4th transistor includes a first electrode connected to the buffer node, a gate for receiving the start signal, and a second electrode connected to the low-potential voltage line.

4. The gate driver according to claim 3 , wherein the first Q logic generator comprises: a 1-1th transistor having a first electrode and a gate for receiving a carry signal from a previous signal transmission unit, and a second electrode connected to the buffer node; a 1-2 transistor having a first electrode connected to the buffer node, a gate for receiving a carry signal from a previous signal transmission unit, and a second electrode connected to the first control node; as well as A 1-3 transistor includes a first electrode connected to a high-potential voltage line to which a high-potential voltage is applied, a gate connected to the first control node, and a second electrode connected to the buffer node.

5. The gate driver according to claim 1 , wherein the output unit comprises: a first pull-up transistor having a first electrode to which a first clock signal is applied, a gate connected to the first control node, and a second electrode connected to a first output node; a first pull-down transistor having a first electrode connected to the first output node, a gate connected to the second control node, and a second electrode to which a first low potential voltage is applied; a second pull-up transistor having a first electrode to which a second clock signal is applied, a gate connected to the first control node, and a second electrode connected to a second output node; as well as A second pull-down transistor has a first electrode connected to the second output node, a gate connected to the second control node, and a second electrode to which a second low potential voltage is applied. 6 . The gate driver of claim 1 , wherein the first Qb logic generator further comprises a capacitor connected between the gate and the second electrode of the fourth transistor.

7. A gate driver comprising a plurality of signal transmission units, the signal transmission units being cascade-connected via a carry line to which a carry signal from a preceding signal transmission unit is applied, The nth signal transmission unit includes: a circuit unit configured to receive the carry signal from the previous signal transmission unit to charge or discharge the voltages of the first control node and the second control node; as well as an output unit configured to output a gate signal and a carry signal based on the potentials of the first control node and the second control node, The output unit includes: a first pull-up transistor having a first electrode connected to a first high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a first output node; a first pull-down transistor having a first electrode connected to the first output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a first low-potential voltage line; a second pull-up transistor having a first electrode connected to a second high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a second output node; and a second pull-down transistor having a first electrode connected to the second output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a second low potential voltage line; Where n is a positive integer, and wherein the first pull-down transistor and the second pull-down transistor are configured to receive a carry signal of a gate low voltage from the previous signal transmission unit to a corresponding back gate while being turned off when the second control node is discharged, The circuit unit includes a second circuit unit configured to discharge the second control node according to the voltage of the first control node. The second circuit unit includes: a fourth transistor having a first electrode connected to the second high-potential voltage line, a gate connected to the first node, and a second electrode connected to the second control node; a fifth transistor having a first electrode connected to the second high-potential voltage line, a gate to which a voltage from the second control node of the preceding signal transmission unit is applied, and a second electrode connected to the first node; a sixth transistor having a first electrode connected to the first node, a gate connected to a buffer node, and a second electrode connected to the second control node; and a seventh transistor having a first electrode connected to the second control node, a gate connected to the buffer node, and a second electrode connected to a second low potential voltage line to which a second low potential voltage is applied. 8 . The gate driver according to claim 7 , wherein the first pull-down transistor and the second pull-down transistor are configured to be turned on by the charge voltage of the second control node to discharge the first output node to a low potential voltage.

9. The gate driver according to claim 7 , wherein the circuit unit comprises a first circuit unit configured to receive the carry signal from a previous signal transmission unit to charge the first control node, The first circuit unit includes: a first transistor having a first electrode for receiving a carry signal from a previous signal transmission unit, a gate for being applied with a clock signal, and a second electrode connected to the buffer node; a second transistor having a first electrode connected to the buffer node, a gate to which the clock signal is applied, and a second electrode connected to the first control node; as well as a third transistor having a first electrode connected to a second high potential voltage line to which a second high potential voltage is applied, a gate connected to the first control node, and a second electrode connected to the buffer node.

10. A display device comprising: a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power supply lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver configured to provide a data voltage of pixel data to the data line; as well as a gate driver configured to provide a gate signal to the gate line, wherein the gate driver includes a plurality of signal transmission units connected in cascade via a carry line to which a carry signal from a preceding signal transmission unit is applied, The nth signal transmission unit includes: a first circuit unit including a first Q logic generator configured to receive the carry signal from a previous signal transmission unit to charge a first control node and a second Q logic generator configured to discharge the first control node; a second circuit unit configured to discharge a second control node according to the voltage of the first control node; and an output unit configured to output a carry signal and a gate signal based on the potentials of the first control node and the second control node, The second Q logic generator comprises: a 2-1st transistor having a first electrode connected to the first control node, a gate connected to the second control node, a back gate for receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a buffer node; and a 2-2 transistor having a first electrode connected to the buffer node, a gate connected to the second control node, a back gate receiving a carry signal from a subsequent signal transmission unit, and a second electrode connected to a low potential voltage line; Where n is a positive integer, and wherein the 2-1 transistor and the 2-2 transistor are configured to receive a carry signal of a gate low voltage from the subsequent signal transmission unit to the corresponding subsequent gate while being turned off when the second control node is discharged, The second circuit unit includes an inverter circuit configured to invert the voltage of the first control node and apply the inverted voltage to the second control node. wherein the inverter circuit comprises a first Qb logic generator and a second Qb logic generator, wherein the first Qb logic generator includes: a fourth transistor having a first electrode connected to a high potential voltage line, a gate connected to a first node, and a second electrode connected to the second control node; and a 4-1 transistor having a first electrode connected to the high potential voltage line, a gate connected to the second control node of the preceding signal transmission unit, and a second electrode connected to the first node, The second Qb logic generator includes: a 4-q transistor having a first electrode connected to the first node, a gate connected to the buffer node, and a second electrode connected to the second control node; and a 5-q transistor having a first electrode connected to the second control node, a gate connected to the buffer node, and a second electrode connected to the low potential voltage line. 11 . The display device according to claim 10 , wherein the 2-1 transistor and the 2-2 transistor are configured to be turned on by the charge voltage of the second control node to discharge the first control node to a low potential voltage.

12. The display device according to claim 10, wherein the second Q logic generator further comprises: a 2-3rd transistor having a first electrode connected to the first control node, a gate for receiving a start signal, and a second electrode connected to the buffer node; as well as A 2-4th transistor includes a first electrode connected to the buffer node, a gate for receiving the start signal, and a second electrode connected to the low-potential voltage line.

13. The display device according to claim 12, wherein the first Q logic generator comprises: a 1-1th transistor having a first electrode and a gate for receiving a carry signal from a previous signal transmission unit, and a second electrode connected to the buffer node; a 1-2 transistor having a first electrode connected to the buffer node, a gate for receiving a carry signal from a previous signal transmission unit, and a second electrode connected to the first control node; as well as A 1-3 transistor includes a first electrode connected to a high-potential voltage line to which a high-potential voltage is applied, a gate connected to the first control node, and a second electrode connected to the buffer node. 14 . The display device of claim 10 , wherein the first Qb logic generator further comprises a capacitor connected between the gate and the second electrode of the fourth transistor.

15. A display device comprising: a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power supply lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver configured to provide a data voltage of pixel data to the data line; as well as a gate driver configured to provide a gate signal to the gate line, wherein the gate driver includes a plurality of signal transmission units connected in cascade via a carry line to which a carry signal from a preceding signal transmission unit is applied, The nth signal transmission unit includes: a circuit unit configured to receive the carry signal from a previous signal transmission unit to charge or discharge voltages of the first control node and the second control node; and an output unit configured to output a gate signal and a carry signal based on the potentials of the first control node and the second control node, The output unit includes: a first pull-up transistor having a first electrode connected to a first high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a first output node; a first pull-down transistor having a first electrode connected to the first output node, a gate connected to the second control node, a back gate for receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a first low-potential voltage line; a second pull-up transistor having a first electrode connected to a second high-potential voltage line, a gate connected to the first control node, and a second electrode connected to a second output node; and a second pull-down transistor having a first electrode connected to the second output node, a gate connected to the second control node, a back gate receiving a carry signal from a previous signal transmission unit, and a second electrode connected to a second low potential voltage line; Where n is a positive integer, and wherein the first pull-down transistor and the second pull-down transistor are configured to receive a carry signal of a gate low voltage from the previous signal transmission unit to a corresponding back gate while being turned off when the second control node is discharged, The circuit unit includes a second circuit unit configured to discharge the second control node according to the voltage of the first control node. The second circuit unit includes: a fourth transistor having a first electrode connected to the second high-potential voltage line, a gate connected to the first node, and a second electrode connected to the second control node; a fifth transistor having a first electrode connected to the second high-potential voltage line, a gate to which a voltage from the second control node of the preceding signal transmission unit is applied, and a second electrode connected to the first node; a sixth transistor having a first electrode connected to the first node, a gate connected to a buffer node, and a second electrode connected to the second control node; and a seventh transistor having a first electrode connected to the second control node, a gate connected to the buffer node, and a second electrode connected to a second low potential voltage line to which a second low potential voltage is applied. 16 . The display device according to claim 15 , wherein the first pull-down transistor and the second pull-down transistor are configured to be turned on by the charge voltage of the second control node to discharge the first output node to a low potential voltage. 17 . The display device according to claim 13 , wherein all transistors in the display panel including the data driver, the gate driver, and a plurality of sub-pixels are implemented using oxide thin film transistors including an n-channel oxide semiconductor.

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