Shift register, gate drive circuit and display device

Abstract

The present disclosure provides a shift register, a gate drive circuit, and a display device. The shift register includes: an input subcircuit configured to write an input signal to a pull-up node; a first output subcircuit configured to output a first clock signal from a clock signal terminal to a gate signal output terminal under the potential control of the pull-up node; an overvoltage processing subcircuit configured to process the overvoltage of the first clock signal at a level transition point and output a second clock signal obtained after processing to the first node; a second output subcircuit configured to output the second clock signal to a cascade signal output terminal under the potential control of the pull-up node; and a first reset subcircuit configured to reset the pull-up node through the potential of a first power signal terminal under the signal control of a first reset terminal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technology, and more particularly to a shift register, a gate driving circuit, and a display device. Background Art

[0002] Currently, medium and large-sized display products are rapidly developing towards high-end products. Design and production of products such as 65-inch 8K120Hz and 65-inch 4K240Hz have begun. These products have high requirements for charge rate. Conventional double-thick copper designs can no longer meet the Tr (Rise Time) and Tf (Fall Time) requirements of the gate drive signal (Gout). Therefore, how to meet the Tr and Tf requirements of Gout while ensuring normal image display is particularly important for the development of display products. Summary of the Invention

[0003] Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising:

[0005] an input subcircuit, connected to the input terminal and the pull-up node, and configured to write an input signal into the pull-up node;

[0006] a first output sub-circuit connected to the clock signal terminal and the gate signal output terminal, and configured to output the first clock signal of the clock signal terminal to the gate signal output terminal under the potential control of the pull-up node;

[0007] an overvoltage processing subcircuit, connected to the clock signal terminal, configured to process an overvoltage of the first clock signal at a level transition point, and output a second clock signal obtained after processing to the first node;

[0008] a second output sub-circuit connected to the first node and the cascade signal output terminal, and configured to output the second clock signal to the cascade signal output terminal under the potential control of the pull-up node;

[0009] The first reset subcircuit is connected to the pull-up node, the first power signal terminal and the first reset terminal, and is configured to reset the pull-up node through the potential of the first power signal terminal under the control of the signal of the first reset terminal.

[0010] Furthermore, the overvoltage processing subcircuit includes: a first transistor, a gate and a first electrode of the first transistor are connected to the clock signal terminal, and a second electrode is connected to the first node.

[0011] Furthermore, the second output sub-circuit includes a second transistor, a first electrode of the second transistor is connected to the first node, a gate is connected to the pull-up node, and a second electrode is connected to the cascade signal output terminal.

[0012] Furthermore, the shift register further includes: a first control subcircuit connected to the second power signal terminal and the first pull-down node, and configured to transmit the second power signal to the first pull-down node under the control of the second power signal at the second power signal terminal;

[0013] a first pull-down sub-circuit connected to the pull-up node and the first power signal terminal, and configured to pull down the first pull-down node through the potential of the first power signal terminal under the potential control of the pull-up node; and

[0014] The first noise reduction sub-circuit is electrically connected to the pull-up node, the first power signal terminal and the first pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the first pull-down node.

[0015] Furthermore, the shift register further includes: a second control subcircuit connected to the third power signal terminal and the second pull-down node, and configured to transmit the third power signal to the second pull-down node under the control of a third power signal at the third power signal terminal;

[0016] a second pull-down sub-circuit connected to the pull-up node and the first power signal terminal, and configured to pull down the second pull-down node through the potential of the first power signal terminal under the potential control of the pull-up node; and

[0017] The second noise reduction sub-circuit is connected to the pull-up node, the first power signal terminal and the second pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the second pull-down node.

[0018] Furthermore, the shift register further includes: a third noise reduction sub-circuit connected to the gate signal output terminal, the first pull-down node, the second pull-down node, and the first power signal terminal, and configured to pull down the gate signal output terminal through the potential of the first power signal terminal under the control of the first pull-down node or the second pull-down node;

[0019] A fourth noise reduction sub-circuit is connected to the cascade signal output terminal, the first pull-down node, the second pull-down node and the first power signal terminal, and is configured to pull down the cascade signal output terminal through the potential of the first power signal terminal under the control of the first pull-down node or the second pull-down node.

[0020] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, comprising a cascaded N-stage shift register, wherein the shift register is the shift register described in the first aspect above, wherein N is an integer greater than 2;

[0021] The input terminal of the first stage shift register is connected to the frame input signal line;

[0022] The input end of the i-th stage shift register is connected to the output end of the i-1-th stage shift register, and the output end of the i-th stage shift register is connected to the first reset end of the i-1-th stage shift register, wherein 1 <i≤N;

[0023] The first reset terminal of the N-th stage shift register is connected to the frame reset signal line.

[0024] Furthermore, the gate drive circuit further includes: a level conversion sub-circuit and an inductor device, wherein the inductor device is connected between the level conversion sub-circuit and the clock signal terminal of the shift register.

[0025] The inductor device is configured to apply an overvoltage at a level transition of the initial clock signal output by the level conversion sub-circuit, to obtain the first clock signal and output it to the clock signal terminal of the shift register.

[0026] Furthermore, the difference between the maximum value of the overvoltage and the set level of the initial clock signal is greater than 10V.

[0027] In a third aspect, an embodiment of the present disclosure provides a display device, comprising: the gate driving circuit provided in the second aspect above.

[0028] The technical solutions provided in the embodiments of the present disclosure have at least the following technical effects or advantages:

[0029] The shift register provided in the embodiment of the present disclosure processes the overvoltage of the first clock signal at the level jump by setting an overvoltage processing subcircuit between the clock signal end and the second output subcircuit, thereby reducing the degree of characteristic drift of the transistor in the second output subcircuit. This is beneficial to ensuring the stability and effectiveness of the cascade relationship of the shift register and improving the screen display abnormality caused by the large degree of characteristic drift of the second output subcircuit in the reliability experiment.

[0030] The above description is only an overview of the technical solution of the embodiment of the present disclosure. In order to more clearly understand the technical means of the embodiment of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present disclosure more obvious and easy to understand, the specific implementation methods of the embodiment of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the embodiments of the present disclosure. The same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0032] Figure 1 is a schematic structural diagram of an exemplary display panel;

[0033] Figure 2 Schematic diagram of the waveforms of CLK0 and CLK1;

[0034] Figure 3 The waveform diagram of Gout before and after adding the inductor device;

[0035] Figure 4 This is a curve diagram of Vgh Margin value changing with time under different Vgh conditions;

[0036] Figure 5 is a structural block diagram of a first exemplary shift register in an embodiment of the present disclosure;

[0037] Figure 6 is a structural block diagram of a second exemplary shift register in an embodiment of the present disclosure;

[0038] Figure 7 is a circuit structure diagram of an exemplary shift register according to an embodiment of the present disclosure;

[0039] Figure 8 for Figure 7 The timing diagram of the shift register shown;

[0040] Figure 9 The waveform comparison of OUT_C ​​of the comparative example and the sample example in the reliability experiment;

[0041] Figure 10 The working status diagram of M1 and M2 in time periods T1 and T3;

[0042] Figure 11 This is the working status diagram of M1 and M2 in time period T2;

[0043] Figure 12 This is the working status diagram of M1 and M2 in time period T4;

[0044] Figure 13 This is the working status diagram of M1 and M2 in the T5 period;

[0045] Figure 14 Schematic diagram of the structure of a gate drive circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In medium and large-sized display products, the clock signal provided to the display panel needs to be transmitted through a relatively long clock signal line. The line resistance R of each clock signal line itself is relatively large (such as 200Ω), and each clock signal line and its adjacent metal, dielectric, color filter substrate, etc. will form a certain capacitance C (nF level). The existence of R and C will cause signal attenuation, delay, and deformation, making the GOA signal have a certain rise and fall time, which will lead to poor image quality such as mischarging. To solve the mischarging phenomenon, it is often necessary to set a relatively long GOE (Gate output enable) time, which sacrifices the charging time of the pixel unit and reduces the charging rate.

[0047] Therefore, for some display products with higher charging rate requirements, such as products with display parameters of 65-inch 8K120Hz or 65-inch 4K 240Hz, some means need to be adopted to improve their charging rate. One of them is to add an inductor device 104 to the X-PCB board 103 of the display panel 100, such as Figure 1 As shown, it is connected between the clock signal output terminal of the level conversion sub-circuit 102 and the clock signal terminal of each stage of the shift register 101, thereby reducing Tr and Tf of the gate drive signal Gout output by the shift register 101 to improve the charging rate.

[0048] The specific principle is that an overvoltage is applied to the rising and falling positions of the clock signal output by the level conversion sub-circuit 102 through the inductor device 104, such as Figure 2 As shown, increasing the voltage difference between the source and drain of the output transistor can effectively reduce the impact of the RC delay on the clock signal line on the gate drive signal output by the shift register, thereby increasing the debugging range of the product's GOE. For ease of distinction, this article refers to the clock signal output by the level shifter chip as the initial clock signal.

[0049] In the gate drive circuit, the level conversion subcircuit can convert the logic level into the initial clock signal according to the preset timing. Before the inductor device 104 is set, the initial clock signal has a certain rising edge time and falling edge time during the transmission process on the clock signal line due to the influence of RCDelay, such as Figure 2 By adding an inductor device, the clock signal transmitted to the clock signal terminal of the shift register 101 can be adjusted to the first clock signal CLK1 (whose waveform is shown in FIG. Figure 2). The first clock signal CLK1 has an overvoltage (spike) at the level transition. In some examples, the voltage difference ΔU between the maximum value Vmax of the overvoltage and the set voltage of the initial clock signal is greater than 10V. For example, the high-level set voltage is represented by Vgh, and the low-level set voltage is represented by Vgl. The voltage difference between the peak value of the overvoltage at the rising edge of CLK1 and Vgh is greater than 10V, and the voltage difference between the peak value of the overvoltage at the falling edge and Vgl is also greater than 10V, thereby making Tf of the first clock signal CLK1 smaller than Tf of CLK0, and Tr of the first clock signal CLK1 smaller than Tr of CLK0.

[0050] Furthermore, by transmitting the first clock signal CLK1 with smaller Tr and Tf to the clock signal terminal of the shift register 101, the gate drive signal Gout output by the shift register 101 can also have smaller Tr and Tf than before the inductor 104 is added. Figure 3 As shown, the transistors and other devices in the pixel circuit can be turned on and off in time, improving poor image quality such as mischarging caused by signal attenuation, delay, and deformation, achieving a shorter GOE time, which is conducive to extending the charging time and improving the charging rate of the pixel unit.

[0051] However, during reliability testing, the inventors discovered that the product's high-level voltage threshold (Vgh Margin) was too high after installing the aforementioned inductor, leading to display anomalies at low temperatures. This is because overvoltage on the first clock signal CLK1 can cause the characteristics of the output transistors in the shift register to drift significantly, resulting in lower on-state currents and weakening the output transistors' output capability. This, in turn, affects the stability and effectiveness of the shift register cascade, leading to display anomalies.

[0052] In this regard, the inventors also studied the change of Vgh Margin value over time under different Vgh conditions. Figure 4 The curves of the Vgh Margin value changing with time when Vgh is 34V and the curves of the Vgh Margin value changing with time when Vgh is 38V are shown. The horizontal axis represents time in hours, and the vertical axis represents the voltage value. It should be noted that the Vgh Margin value is the critical value at which horizontal stripes appear on the screen when the Vgh value is lowered. It can characterize the output capability of the shift register for the input signal of the next cascade unit. If the output capability is insufficient, the required Vgh value is higher. In the reliability experiment with different Vgh values, the 1000-hour reliability Vgh Margin result with Vgh of 34V is 27.14V, and the 1000-hour reliability Vgh Margin result with Vgh of 38V is 29.66V. The Vgh Margin value corresponding to 38V is about 2.5V higher, indicating that the output capability of the output transistor is weak and the degree of characteristic drift is large during the reliability process.

[0053] The degree of transistor characteristic drift is related to voltage and time, mainly to the voltage difference Vgs between the gate and the source and the voltage difference Vds between the source and the drain. The higher the Vgh, the higher the corresponding Vgs and Vds, and the easier it is to deviate during the reliability process.

[0054] Based on this, the embodiment of the present disclosure provides a shift register that can reduce the characteristic drift of the transistors in the second output sub-circuit to ensure the stability and effectiveness of the cascade relationship. Figure 5 As shown, the shift register 10 includes: an input sub-circuit 111 , a first output sub-circuit 112 , an overvoltage processing sub-circuit 113 , a second output sub-circuit 114 and a first reset sub-circuit 115 .

[0055] The input subcircuit 111 is connected to the input terminal INPUT and the pull-up node PU, and is configured to write the input signal to the pull-up node PU. The first output subcircuit 112 is connected to the clock signal terminal CLK and the gate signal output terminal OUT_G, and is configured to output the first clock signal CLK1 of the clock signal terminal CLK to the gate signal output terminal OUT_G under the potential control of the pull-up node PU. The overvoltage processing subcircuit 113 is connected to the clock signal terminal CLK, and is configured to process the overvoltage of the first clock signal CLK1 at the level transition point, and output the second clock signal CLK2 obtained after processing to the first node B. The second output subcircuit 114 is connected to the first node B and the cascade signal output terminal OUT_C, and is configured to output the second clock signal CLK2 to the cascade signal output terminal OUT_C ​​under the potential control of the pull-up node PU. The first reset sub-circuit 115 is connected to the pull-up node PU, the first power signal terminal VSS and the first reset terminal Reset_PU, and is configured to reset the pull-up node through the potential of the first power signal terminal VSS under the signal control of the first reset terminal Reset_PU, so as to reset the signals output by the gate signal output terminal OUT_G and the cascade signal output terminal OUT_C.

[0056] The gate signal output terminal OUT_G connected to the first output sub-circuit 112 is used to provide a gate drive signal to the corresponding gate line of the pixel circuit (pixel row) to drive the pixel unit connected to the gate line to turn on or off. The cascade signal output terminal OUT_C ​​connected to the second output sub-circuit 114 is used to provide a cascade signal to the first reset terminal Reset_PU of the previous level (except the first level shift register) and the input terminal INPUT of the next level (except the last level shift register) shift register. By separating the gate signal output terminal OUT_G and the cascade signal output terminal OUT_C, it is beneficial to reduce the power consumption of the gate drive circuit.

[0057] For example, the waveform of the first clock signal CLK1 received by the clock signal terminal CLK is as follows: Figure 2 As shown, the first clock signal CLK1 is applied with overvoltage when the low level jumps to the high level and when the high level jumps to the low level, so that the waveform appears as follows at the rising edge and the falling edge. Figure 2 In some examples, this overvoltage is generated by providing an inductor between the level shifter subcircuit and the clock signal terminal. For example, the difference between this overvoltage and the set voltage of the initial clock signal output by the level shifter subcircuit can reach 10V or more. While this overvoltage helps reduce Tr and Tf of the gate drive signal output by the first output subcircuit 112, it also increases the characteristic drift of the transistors in the second output subcircuit 114, thereby affecting the cascade signal outputted therefrom and hindering the stability and effectiveness of the shift register cascade relationship.

[0058] The embodiment of the present disclosure adds an overvoltage processing subcircuit 113 between the clock signal terminal CLK of the shift register 10 and the second output subcircuit 114. For example, the voltage processing subcircuit can use a semiconductor device such as a transistor that can eliminate overvoltage, and the embodiment of the present disclosure does not limit its specific implementation method. After passing through the overvoltage processing subcircuit 113, the overvoltage (spike) at the rising and falling edges of the first clock signal CLK1 will be greatly weakened or even disappear, that is, converted into the second clock signal CLK2, and then input into the second output subcircuit 114. In this way, it will not affect the gate drive signal output by the first output subcircuit 112, ensuring that the gate drive signal has smaller Tr and Tf, and can avoid the influence of overvoltage on the drift of the transistor characteristics in the second output subcircuit 114, ensuring the stability and effectiveness of the cascade relationship of the shift register, which is conducive to ensuring the normal display of the product screen in the reliability experiment on the basis of improving the charging rate.

[0059] Figure 6 FIG. 2 shows a structural block diagram of another exemplary shift register provided by an embodiment of the present disclosure. Figure 6 As shown, in addition to the input sub-circuit 111, the first output sub-circuit 112, the overvoltage processing sub-circuit 113, the second output sub-circuit 114 and the first reset sub-circuit 115, in some examples, the shift register 20 provided in the embodiment of the present disclosure may also include: a first control sub-circuit 121, a first pull-down sub-circuit 122 and a first noise reduction sub-circuit 123.

[0060] The first control sub-circuit 121 is connected to the second power signal terminal VDD1 and the first pull-down node PD1, and is configured to transmit the second power signal to the first pull-down node PD1 under the control of the second power signal of the second power signal terminal VDD1. The first pull-down sub-circuit 122 is connected to the pull-up node PU and the first power signal terminal VSS, and is configured to pull down the first pull-down node PD1 through the potential of the first power signal terminal VSS under the control of the potential of the pull-up node PU. The first noise reduction sub-circuit 123 is electrically connected to the pull-up node PU, the first power signal terminal VSS, and the first pull-down node PD1, and is configured to pull down the pull-up node PU through the potential of the first power signal terminal VSS under the control of the first pull-down node PD1 to reduce noise on the pull-up node PU.

[0061] In some examples, the shift register 20 provided by the embodiments of the present disclosure may further include: a second control sub-circuit 131 , a second pull-down sub-circuit 132 , and a second noise reduction sub-circuit 133 .

[0062] The second control sub-circuit 131 is connected to the third power signal terminal VDD2 and the second pull-down node PD2, and is configured to transmit the third power signal to the second pull-down node PD2 under the control of the third power signal at the third power signal terminal VDD2. The second pull-down sub-circuit 132 is connected to the pull-up node PU and the first power signal terminal VSS, and is configured to pull down the second pull-down node PD2 via the potential of the first power signal terminal VSS under the control of the potential of the pull-up node PU. The second noise reduction sub-circuit 133 is connected to the pull-up node PU, the first power signal terminal VSS, and the second pull-down node PD2, and is configured to pull down the pull-up node PU via the potential of the first power signal terminal VSS under the control of the second pull-down node PD2 to reduce noise on the pull-up node PU.

[0063] At this time, the second power signal terminal VDD1 and the third power signal terminal VDD2 respectively receive alternating DC high-level signals and DC low-level signals, and the received DC signals are mutually inverted. For example, in one cycle, the second power signal terminal VDD1 receives a DC high-level signal, the third power signal terminal VDD2 receives a DC low-level signal, the first pull-down node PD1 is at an active level, and the first noise reduction sub-circuit 123 operates to reduce noise on the pull-up node PU. In the next cycle, the second power signal terminal VDD1 receives a DC low-level signal, the third power signal terminal VDD2 receives a DC high-level signal, the second pull-down node PD2 is at an active level, and the second noise reduction sub-circuit 133 operates to reduce noise on the pull-up node PU. Thus, providing two sets of control sub-circuits, pull-down sub-circuits, and noise reduction sub-circuits for the pull-up node PU, and alternating between the two sets, helps prevent performance drift caused by long-term conduction of transistors in the shift register.

[0064] In some examples, the shift register 20 provided by the embodiments of the present disclosure may further include a third noise reduction sub-circuit 141. The third noise reduction sub-circuit 141 is connected to the gate signal output terminal OUT_G, the first pull-down node PD1, the second pull-down node PD2, and the first power signal terminal VSS, and is configured to pull down the gate signal output terminal OUT_G through the potential of the first power signal terminal VSS under the control of the first pull-down node PD1 or the second pull-down node PD2 to reduce noise on the gate signal output terminal OUT_G.

[0065] In some examples, the shift register 20 provided by the embodiments of the present disclosure may further include a fourth noise reduction sub-circuit 142. The fourth noise reduction sub-circuit 142 is connected to the cascade signal output terminal OUT_C, the first pull-down node PD1, the second pull-down node PD2, and the first power signal terminal VSS, and is configured to pull down the cascade signal output terminal OUT_C ​​through the potential of the first power signal terminal VSS under the control of the first pull-down node PD1 or the second pull-down node PD2 to reduce noise on the cascade signal output terminal OUT_C.

[0066] In some examples, the shift register 20 provided by the embodiments of the present disclosure may further include a second reset subcircuit 150. The second reset subcircuit 150 is connected to the second reset terminal Reset_T, the first power signal terminal VSS, and the pull-up node PU. The second reset subcircuit 150 is configured to reset the pull-up node PU by the potential of the first power signal terminal VSS under the control of the signal of the second reset terminal Reset_T. The signal of the second reset terminal Reset_T is a frame reset signal, i.e., a reset signal generated after a frame scan is completed. The second reset subcircuit 150 is configured to reset the pull-up node PU of each level of the shift register after a frame scan is completed.

[0067] Figure 7 for Figure 6 The circuit diagram of a specific implementation example of the shift register 20 shown in FIG. It should be noted that in the following description, each transistor is an N-type transistor as an example, but this does not constitute a limitation to the embodiment of the present disclosure. In other examples, one or more transistors in the shift register may also be P-type transistors. It should also be noted that Figure 7 The specific circuit structure shown is only an example, and other applicable circuit structures may also be used, and the embodiments of the present disclosure are not limited to this.

[0068] like Figure 7As shown, the overvoltage processing subcircuit 113 may include a first transistor M1. The gate and first electrode of the first transistor M1 are both connected to the clock signal terminal CLK, and the second electrode is connected to the first node B. After passing through the first transistor M1, the overvoltage at the level transition of the first clock signal CLK1 can be significantly reduced or even eliminated. This can effectively alleviate the problem of increased characteristic drift of the second transistor M2 due to the overvoltage, help ensure the output capacity of the second transistor M2, thereby ensuring the effective reset of the previous stage shift register and ensuring the stability and effectiveness of the cascade relationship.

[0069] The second output sub-circuit 114 may include: a second transistor M2, a first electrode of the second transistor is connected to the first node B, a gate is connected to the pull-up node PU, and a second electrode is connected to the cascade signal output terminal OUT_C.

[0070] The first output sub-circuit 112 may include: a third transistor M3 and a capacitor C1, the gate of the third transistor and one end of the capacitor are connected to the pull-up node PU, the first electrode of the third transistor M3 is connected to the clock signal terminal CLK, and the second electrode of the third transistor M3 and the other end of the capacitor C1 are connected to the gate signal output terminal OUT_G.

[0071] The input sub-circuit 111 may include: a fourth transistor M4 , wherein a gate and a first electrode of the fourth transistor M4 are both connected to the input terminal INPUT, and a second electrode of the fourth transistor M4 is connected to the pull-up node PU.

[0072] The first reset sub-circuit 115 may include a fifth transistor M5, wherein the gate of the fifth transistor M5 is connected to the first reset terminal Reset_PU, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first power signal terminal VSS. For example, when the signal processing active level at the first reset terminal Reset_PU is high, the fifth transistor M5 is turned on, and the level of the first power signal terminal VSS, such as low, is written to the pull-up node PU, thereby resetting the pull-up node PU.

[0073] The first control sub-circuit 121 may include a sixth transistor M6 and a seventh transistor M7. The first pull-down sub-circuit 122 may include an eighth transistor M8 and a ninth transistor M9. The first noise reduction sub-circuit 123 may include a tenth transistor M10.

[0074] The gate and first electrode of the sixth transistor M6 are connected to the second power signal terminal VDD1, and the second electrode is connected to the first electrode of the eighth transistor M8. The first electrode of the seventh transistor M7 is connected to the second power signal terminal VDD1, the gate is connected to the second electrode of the sixth transistor M6, and the second electrode is connected to the first pull-down node PD1. The gate of the eighth transistor M8 is connected to the pull-up node PU, and the second electrode is connected to the first power signal terminal VSS. The first electrode of the ninth transistor M9 is connected to the first pull-down node PD1, the gate is connected to the pull-up node PU, and the second electrode is connected to the first power signal terminal VSS. The first electrode of the tenth transistor M10 is connected to the pull-up node PU, the gate is connected to the first pull-down node PD1, and the second electrode is connected to the first power signal terminal VSS.

[0075] The second control sub-circuit 131 may include an eleventh transistor M11 and a twelfth transistor M12 , the second pull-down sub-circuit 132 may include a thirteenth transistor M13 and a fourteenth transistor M14 , and the second noise reduction sub-circuit 133 may include a fifteenth transistor M15 .

[0076] The gate and first electrode of the eleventh transistor M11 are connected to the third power signal terminal VDD2, and the second electrode is connected to the first electrode of the thirteenth transistor M13. The first electrode of the twelfth transistor M12 is connected to the third power signal terminal VDD2, the gate is connected to the second electrode of the eleventh transistor M11, and the second electrode is connected to the second pull-down node PD2. The gate of the thirteenth transistor M13 is connected to the pull-up node PU, and the second electrode is connected to the first power signal terminal VSS. The first electrode of the fourteenth transistor M14 is connected to the second pull-down node PD2, the gate is connected to the pull-up node PU, and the second electrode is connected to the first power signal terminal VSS. The first electrode of the fifteenth transistor M15 is connected to the pull-up node PU, the gate is connected to the second pull-down node PD2, and the second electrode is connected to the first power signal terminal VSS.

[0077] The third noise reduction sub-circuit 141 may include a sixteenth transistor M16 and a seventeenth transistor M17. The sixteenth transistor M16 has a first electrode connected to the gate signal output terminal OUT_G, a gate connected to the first pull-down node PD1, and a second electrode connected to the first power signal terminal VSS. The seventeenth transistor M17 has a first electrode connected to the gate signal output terminal OUT_G, a gate connected to the second pull-down node PD2, and a second electrode connected to the first power signal terminal VSS. For example, when the first pull-down node PD1 or the second pull-down node PD is at a high level, the sixteenth transistor M16 or the seventeenth transistor M17 is turned on, and the level of the first power signal terminal VSS, such as a low level, is written to the gate signal output terminal OUT_G, thereby reducing noise on the gate drive signal outputted therefrom.

[0078] The fourth noise reduction sub-circuit 142 may include an eighteenth transistor M18 and a nineteenth transistor M19. The eighteenth transistor M18 has a first electrode connected to the cascade signal output terminal OUT_C, a gate connected to the first pull-down node PD1, and a second electrode connected to the first power signal terminal VSS. The nineteenth transistor M19 has a first electrode connected to the cascade signal output terminal OUT_C, a gate connected to the second pull-down node PD2, and a second electrode connected to the first power signal terminal VSS. For example, when the first pull-down node PD1 or the second pull-down node PD is at a high level, the eighteenth transistor M18 or the nineteenth transistor M19 is turned on, and the level of the first power signal terminal VSS, such as a low level, is written to the cascade signal output terminal OUT_C, thereby performing noise reduction on the cascade signal outputted therefrom.

[0079] The second reset sub-circuit 150 may include a twentieth transistor M20, wherein a first electrode of the twentieth transistor M20 is connected to the pull-up node PU, a gate of the twentieth transistor M20 is connected to the second reset terminal Reset_T, and a second electrode of the twentieth transistor M20 is connected to the first power signal terminal VSS. For example, when the second reset terminal Reset_T is at an active level, such as a high level, the twentieth transistor M20 is turned on, and the level of the first power signal terminal VSS, such as a low level, is written to the pull-up node PU, thereby resetting the pull-up node PU.

[0080] Figure 8 Shown Figure 7 An exemplary timing diagram of Figure 7 The waveforms of the first clock signal CLK1 received by the clock signal terminal CLK, the second node A, the first node B, the input terminal INPUT, the pull-up node PU, the cascade signal output terminal OUT_C ​​and the gate signal output terminal OUT_G. Figure 8 As shown, in the T1 time period, the input signal of the input terminal INPUT is at a high level, the first clock signal CLK1 of the clock signal terminal is at a low level, the fourth transistor M1 is turned on, and the high level signal of the input terminal INPUT is input to the pull-up node PU, the pull-up node PU is charged, and it is pulled up to a high level, for example, equal to the high level voltage of the input signal, so that the second transistor M2 and the third transistor M3 are pre-turned on, and the capacitor C1 is charged.

[0081] During time period T2, the input signal is at a low level, the first clock signal CLK1 is at a high level, the first transistor M1 is turned on, and the first clock signal CLK1 is output to the first node B through the second node A and the first transistor M1. The overvoltage at the level transition disappears, and the second clock signal CLK2 is obtained. In addition, the voltage at the pull-up node PU is further pulled up by the bootstrap effect of capacitor C1. The second transistor M2 is turned on, writing the second clock signal CLK2 of the first node B to the cascade signal output terminal OUT_C, causing the cascade signal output terminal OUT_C ​​to output a high level. The third transistor M3 is turned on, writing the first clock signal CLK1 to the gate signal output terminal OUT_G, causing the gate signal output terminal OUT_G to output a high level.

[0082] exist Figure 7 In the illustrated 20T1C design, an input signal is transmitted to the input terminal INPUT of the next-stage shift register through the second transistor M2, and a reset signal is input to the first reset terminal Reset_PU of the previous-stage shift register. Therefore, the second transistor M2 is a key TFT device that affects the Vgh Margin value of the gate drive circuit. By adding the first transistor M1, characteristic drift of the second transistor M2 during reliability testing can be effectively reduced.

[0083] For example, the Figure 7 The display product of the circuit shown is used as a sample example, and the display product before the first transistor M1 is set is used as a comparative example. The same reliability experiment is performed on the sample example and the comparative example. Figure 9 Figure (a) shows the waveform of the cascade signal output from the cascade signal output terminal OUT_C ​​when the comparative example starts working in an experimental environment (working time is 0 hours), the waveform of the cascade signal output from the cascade signal output terminal OUT_C ​​after working for 1000 hours, and a waveform comparison diagram of the two. Figure 9 Figure (b) shows the waveform of the cascade signal output from the cascade signal output terminal OUT_C ​​at the start of operation of the sample under the same experimental environment, the waveform of the cascade signal output from the cascade signal output terminal OUT_C ​​after 1000 hours of operation, and a waveform comparison of the two. For easy distinction, the dotted line in the waveform comparison diagram represents the waveform after 1000 hours of operation.

[0084] from Figure 9As can be seen from Figures (a) and (b) in the figure, for the cascade signal output by the comparative example, Tr and Tf are small at the beginning, but after working for 1000 hours, the characteristic drift is large, Tr and Tf increase significantly, and the difference before and after is large; for the cascade signal output by the sample example, Tr and Tf are relatively large at the beginning, but after working for 1000 hours, the characteristic drift is small, although Tr and Tf also increase slightly, the difference before and after is small, the output capacity of the second transistor T2 is guaranteed, and the stability and effectiveness of the cascade relationship can be guaranteed.

[0085] in addition, Figure 10-13 FIG. 1 shows the working states of the first transistor M1 and the second transistor M2 in different time periods. Figure 10 As shown, in Figure 8 In the T1 time period and the T3 time period, the clock signal terminal CLK is at a low level (Vgl), the pull-up node PU is pulled up to a high level (Vgh), M1 and M2 are turned off, the gate, the first pole and the second pole connected to the first node B of M1 are all at a low level (Vgl), the first pole connected to the first node B of M2 is at a low level, and the cascade signal output terminal OUT_C ​​has no output.

[0086] like Figure 11 As shown, in Figure 8 In the T2 time period, the clock signal terminal CLK is at a high level (Vgh), the pull-up node PU is pulled up to a level greater than the high level (Vgh) for the second time, M1 and M2 are turned on, the gate, the first pole and the second pole connected to the first node B of M1 are all at a high level (Vgh), the first pole connected to the first node B of M2 is at a high level (Vgh), and the cascade signal output terminal OUT_C ​​is output normally.

[0087] like Figure 12 As shown, in Figure 8 In the T4 time period, the clock signal terminal CLK is at a low level (Vgl), the pull-up node PU is at a low level (Vgl), M1 and M2 are turned off, the gate, the first pole and the second pole connected to the first node B of M1 are all at a low level (Vgl), the first pole connected to the first node B of M2 is at a low level, and the cascade signal output terminal OUT_C ​​has no output.

[0088] like Figure 13 As shown, in Figure 8 In the T5 time period, the clock signal terminal CLK is at a high level (Vgl), the pull-up node PU is at a low level (Vgl), M1 is turned on, M2 is turned off, the gate, the first pole and the second pole connected to the first node B of M1 are all at a high level (Vgh), the first pole connected to the first node B of M2 is at a high level (Vgh), and the cascade signal output terminal OUT_C ​​has no output.

[0089] It can be seen from this that since the gate of the first transistor M1 is connected to the first electrode, the signals of the gate, the first electrode and the second electrode are always consistent during actual operation, that is, Vgs=Vds=0. During operation, it is almost unaffected by the electrical bias and is not prone to characteristic drift.

[0090] Therefore, adding the first transistor M1 can reduce the abnormal characteristic drift of the second transistor M2 after the product operates for a long time in a high temperature environment such as 60 degrees Celsius. This helps ensure the stability and effectiveness of the shift register cascade relationship and improves display anomalies caused by abnormal characteristic drift of the second transistor M2. In addition, adding the first transistor M1 does not require additional masking (masking) and only requires changing the design of the clock signal lines around the shift register, which has no impact on production capacity.

[0091] It should be noted that the "high level" and "low level" herein refer to two logical states represented by a potential height range at a certain location. For example, a high level can specifically refer to a potential higher than the common terminal voltage, and a low level can specifically refer to a potential lower than the common terminal voltage. At the same time, the "high level" potential at different locations may be different, and the "low level" potential at different locations may also be different. It is understandable that the specific potential height range can be set as needed in a specific application scenario, and this embodiment does not limit this.

[0092] The effective level of each port herein refers to the working level, which can be a high level or a low level. The effective levels of different ports can be the same or different, depending on the specific circuit implementation method, and the embodiments of the present disclosure do not limit this.

[0093] In the description of the embodiments of the present disclosure, the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the first node B, and the second node A do not represent actual components but represent junction points of related electrical connections in the circuit diagram.

[0094] It should also be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate (i.e., the source and drain), one of the poles is described as the first pole and the other pole is described as the second pole.

[0095] like Figure 14 As shown, the embodiment of the present disclosure further provides a gate drive circuit 30, comprising a cascaded N-stage shift register (such as Figure 14The shift registers shown as G1 to GN), where N is an integer greater than 2. Among them, the shift register adopts the shift register provided by the embodiment of the present disclosure. The input end of the shift register of the first stage is connected to the frame input signal line STV; the input end INPUT of the shift register of the i-th stage is connected to the cascaded signal output end OUT_C of the shift register of the (i-1)-th stage, and the cascaded signal output end OUT_C of the shift register of the i-th stage is connected to the first reset end Reset_PU of the shift register of the (i-1)-th stage, where 1 < i ≤ N; the first reset end Reset_PU of the shift register of the N-th stage is connected to the frame reset signal line.

[0096] Since the shift register included in the gate driving circuit 30 introduced in the embodiment of the present disclosure has been described above, based on the shift register introduced in the embodiment of the present disclosure, those skilled in the art can understand the specific structure and effect principle of the gate driving circuit 30, so it will not be repeated here. Any gate driving circuit 30 including the shift register of the embodiment of the present disclosure falls within the scope of protection of the present disclosure.

[0097] In some examples, the gate driving circuit 30 further includes: a level conversion sub-circuit and an inductor device. The inductor device is connected between the level conversion sub-circuit and the clock signal terminal of the shift register. The inductor device is configured to apply an overvoltage at the level transition of the initial clock signal output by the level conversion sub-circuit to obtain a first clock signal and output it to the clock signal terminal of the shift register.

[0098] In some examples, the difference between the overvoltage of the first clock signal and the set level of the initial clock signal is greater than 10V.

[0099] The embodiment of the present disclosure also provides a display device, including the gate driving circuit 30 provided in the above embodiment. For example, the display device may be a display device with a high requirement for the charging rate, such as a size greater than or equal to 65 inches, and / or, a resolution greater than or equal to 8K, and / or, a refresh rate greater than or equal to 120Hz.

[0100] For example, the display device may be a display panel, such as a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, etc., or, it may also be a product or component with a display function such as a TV, a monitor, an electronic paper display device, etc. The embodiment of the present disclosure does not limit this. The technical effects of the display device can refer to the corresponding description of the shift register in the above embodiment, and will not be repeated here.

[0101] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0102] Similarly, it should be understood that in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of a single embodiment disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present disclosure.

[0103] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0104] In addition, those skilled in the art will appreciate that the combination of features of different embodiments is within the scope of the present disclosure and forms different embodiments. The above embodiments are intended to illustrate rather than limit the present disclosure, and those skilled in the art may design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A shift register, characterized in that: include: an input subcircuit, connected to the input terminal and the pull-up node, and configured to write an input signal into the pull-up node; a first output sub-circuit connected to the clock signal terminal and the gate signal output terminal, and configured to output the first clock signal of the clock signal terminal to the gate signal output terminal under the potential control of the pull-up node; an overvoltage processing subcircuit, connected to the clock signal terminal, configured to process an overvoltage of the first clock signal at a level transition point, and output a second clock signal obtained after processing to the first node; a second output sub-circuit connected to the first node and the cascade signal output terminal, and configured to output the second clock signal to the cascade signal output terminal under the potential control of the pull-up node; a first reset sub-circuit connected to the pull-up node, a first power signal terminal, and a first reset terminal, and configured to reset the pull-up node by the potential of the first power signal terminal under the control of a signal from the first reset terminal; The overvoltage processing subcircuit includes a first transistor, a gate and a first electrode of the first transistor are connected to the clock signal terminal, and a second electrode is connected to the first node.

2. The shift register according to claim 1, wherein: The second output sub-circuit includes a second transistor, wherein a first electrode of the second transistor is connected to the first node, a gate is connected to the pull-up node, and a second electrode is connected to the cascade signal output terminal.

3. The shift register according to claim 1, wherein: Also includes: a first control subcircuit connected to the second power signal terminal and the first pull-down node, and configured to transmit the second power signal to the first pull-down node under the control of the second power signal of the second power signal terminal; a first pull-down sub-circuit, connected to the pull-up node and the first power signal terminal, and configured to pull down the first pull-down node through the potential of the first power signal terminal under the potential control of the pull-up node; as well as The first noise reduction sub-circuit is electrically connected to the pull-up node, the first power signal terminal and the first pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the first pull-down node.

4. The shift register according to claim 3, wherein: Also includes: a second control subcircuit connected to the third power signal terminal and the second pull-down node, and configured to transmit the third power signal to the second pull-down node under the control of a third power signal at the third power signal terminal; a second pull-down sub-circuit, connected to the pull-up node and the first power signal terminal, and configured to pull down the second pull-down node through the potential of the first power signal terminal under the potential control of the pull-up node; as well as The second noise reduction sub-circuit is connected to the pull-up node, the first power signal terminal and the second pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the second pull-down node.

5. The shift register according to claim 4, wherein: Also includes: a third noise reduction sub-circuit, connected to the gate signal output terminal, the first pull-down node, the second pull-down node, and the first power signal terminal, and configured to pull down the gate signal output terminal through the potential of the first power signal terminal under the control of the first pull-down node or the second pull-down node; A fourth noise reduction sub-circuit is connected to the cascade signal output terminal, the first pull-down node, the second pull-down node and the first power signal terminal, and is configured to pull down the cascade signal output terminal through the potential of the first power signal terminal under the control of the first pull-down node or the second pull-down node.

6. A gate drive circuit, characterized in that: A cascaded N-stage shift register, wherein the shift register is the shift register according to any one of claims 1 to 5, wherein N is an integer greater than 2; The input terminal of the first stage shift register is connected to the frame input signal line; The input end of the i-th stage shift register is connected to the output end of the i-1-th stage shift register, and the output end of the i-th stage shift register is connected to the first reset end of the i-1-th stage shift register, wherein 1 <i≤N; The first reset terminal of the N-th stage shift register is connected to the frame reset signal line.

7. The gate driving circuit according to claim 6, wherein: Also includes: a level conversion sub-circuit and an inductor device, wherein the inductor device is connected between the level conversion sub-circuit and the clock signal terminal of the shift register, The inductor device is configured to apply an overvoltage at a level transition of the initial clock signal output by the level conversion sub-circuit, to obtain the first clock signal and output it to the clock signal terminal of the shift register.

8. The gate driving circuit according to claim 7, wherein: The difference between the maximum value of the overvoltage and the set level of the initial clock signal is greater than 10V.

9. A display device, characterized in that: include: The gate drive circuit according to any one of claims 6 to 8.

Images