Startup control circuit, its control method, and display control circuit

Abstract

A startup control circuit, its control method, and a display control circuit are provided. The startup control circuit includes: a first timing management circuit configured to provide a first set of startup control signals; a second timing management circuit configured to provide a second set of startup control signals; a selection circuit connected to the first timing management circuit and the second timing management circuit, the selection circuit being configured to receive the first set of startup control signals and the second set of startup control signals, and select a set of startup control signals from the first set of startup control signals and the second set of startup control signals for output.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a startup control circuit and a control method thereof, and a display control circuit. Background Art

[0002] For a whole machine system that is distributed in different places, has a large quantity, and needs to be remotely controlled, it includes a local timing management circuit and a remote control timing management circuit, so that while realizing functions such as remote data processing and transmission, and remote monitoring, system management functions such as energy saving, remote system upgrade, and remote restart can be realized. However, in some cases, the whole machine system will have failures in startup control. Summary of the Invention

[0003] Embodiments of the present disclosure provide a startup control circuit, including:

[0004] A first timing management circuit configured to provide a first set of startup control signals;

[0005] A second timing management circuit configured to provide a second set of startup control signals;

[0006] A selection circuit connected to the first timing management circuit and the second timing management circuit, the selection circuit being configured to receive the first set of startup control signals and the second set of startup control signals, and select a set of startup control signals from the first set of startup control signals and the second set of startup control signals for output.

[0007] For example, the first timing management circuit is further configured to provide a first status signal, the second timing management circuit is further configured to provide a second status signal, the selection circuit is configured to receive the first status signal and the first set of startup control signals from the first timing management circuit, receive the second status signal and the second set of startup control signals from the second timing management circuit, and select a set of startup control signals from the first set of startup control signals and the second set of startup control signals for output according to the first status signal and the second status signal.

[0008] For example, the selection circuit includes:

[0009] A state selection sub-circuit, a first input end of the state selection sub-circuit is connected to the first timing management circuit to receive the first state signal, a second input end of the state selection sub-circuit is connected to the second timing management circuit to receive the second state signal, and the state selection sub-circuit is configured to output a first switch control signal at a first output end of the state selection sub-circuit and output a second switch control signal at a second output end of the state selection sub-circuit according to the first state signal and the second state signal;

[0010] A first switch sub-circuit, a control end of the first switch sub-circuit is connected to the first output end of the state selection sub-circuit, an input end of the first switch sub-circuit is connected to the first timing management sub-circuit to receive the first set of start control signals, and the first switch sub-circuit is configured to provide the first set of start control signals received at the input end of the first switch sub-circuit to an output end of the first switch sub-circuit under the control of a first switch control signal received at the control end of the first switch sub-circuit;

[0011] A second switch sub-circuit, a control end of the second switch sub-circuit is connected to the second output end of the state selection sub-circuit, an input end of the second switch sub-circuit is connected to the second timing management sub-circuit to receive the second set of start control signals, and the second switch sub-circuit is configured to provide the second set of start control signals received at the input end of the second switch sub-circuit to an output end of the second switch sub-circuit under the control of a second switch control signal received at the control end of the second switch sub-circuit.

[0012] For example, the state selection sub-circuit includes:

[0013] A first inverter, an input end of the first inverter is connected to the second input end of the state selection sub-circuit;

[0014] A first AND gate, a first input end of the first AND gate is connected to the first input end of the state selection sub-circuit, a second input end of the first AND gate is connected to an output end of the first inverter, and an output end of the first AND gate is connected to the first output end of the state selection sub-circuit;

[0015] A second inverter, an input end of the second inverter is connected to the first input end of the state selection sub-circuit;

[0016] A second AND gate, a first input end of the second AND gate is connected to the second input end of the state selection sub-circuit, a second input end of the second AND gate is connected to an output end of the second inverter, and an output end of the second AND gate is connected to the second output end of the state selection sub-circuit.

[0017] For example, the first set of startup control signals includes a first enable signal and a first reset signal, and the first switch sub - circuit includes:

[0018] A first transistor, the gate of the first transistor is connected to the control end of the first switch sub - circuit, the first pole of the first transistor serves as the first input end of the first switch sub - circuit and is connected to receive the first enable signal, and the second pole of the first transistor is connected to the first output end of the first switch sub - circuit;

[0019] A second transistor, the gate of the second transistor is connected to the control end of the first switch sub - circuit, the first pole of the second transistor serves as the second input end of the first switch sub - circuit and is connected to receive the first reset signal, and the second pole of the second transistor is connected to the second output end of the first switch sub - circuit.

[0020] For example, the second set of startup control signals includes a second enable signal and a second reset signal, and the second switch sub - circuit includes:

[0021] A third transistor, the gate of the third transistor is connected to the control end of the second switch sub - circuit, the first pole of the third transistor serves as the first input end of the second switch sub - circuit and is connected to receive the second enable signal, and the second pole of the third transistor is connected to the first output end of the second switch sub - circuit;

[0022] A fourth transistor, the gate of the fourth transistor is connected to the control end of the second switch sub - circuit, the first pole of the fourth transistor serves as the second input end of the second switch sub - circuit and is connected to receive the second reset signal, and the second pole of the fourth transistor is connected to the second output end of the second switch sub - circuit.

[0023] For example, the first output end of the first switch sub - circuit and the first output end of the second switch sub - circuit are connected as the first output end of the selection circuit, and the second output end of the first switch sub - circuit and the second output end of the second switch sub - circuit are connected as the second output end of the selection circuit.

[0024] For example, the first timing management circuit is configured to generate a valid first set of startup control signals in response to a first startup event and send a first blocking signal to the second timing management circuit through a communication interface, and generate an invalid first set of startup control signals in response to a second blocking signal from the second timing management circuit;

[0025] The second timing management circuit is configured to generate a valid second set of start control signals in response to a second start event and send a second blocking signal to the first timing management circuit through the communication interface, and generate an invalid second set of start control signals in response to a first blocking signal from the first timing management circuit;

[0026] The selection circuit is configured to select a valid set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0027] For example, the first set of start control signals includes a first enable signal and a first reset signal, the second set of start control signals includes a second enable signal and a second reset signal, and the selection circuit includes:

[0028] An exclusive-OR gate, a first input terminal of the exclusive-OR gate is connected to the first timing management circuit to receive the first enable signal, a second input terminal of the exclusive-OR gate is connected to the second timing management circuit to receive the second enable signal, and an output terminal of the exclusive-OR gate serves as a first output terminal of the selection circuit;

[0029] An exclusive-NOR gate, a first input terminal of the exclusive-NOR gate is connected to the first timing management circuit to receive the first reset signal, a second input terminal of the exclusive-NOR gate is connected to the second timing management circuit to receive the second reset signal, and an output terminal of the exclusive-NOR gate serves as a second output terminal of the selection circuit.

[0030] For example, the communication interface is an inter-integrated circuit I 2 C interface.

[0031] Embodiments of the present disclosure further provide a display control circuit, including:

[0032] The start control circuit as described above;

[0033] A main controller, connected to the start control circuit, and configured to perform start control according to a set of start control signals output by the start control circuit.

[0034] For example, the display control circuit further includes:

[0035] A first power management circuit, connected to the first timing management circuit and the second timing management circuit in the start control circuit, and configured to provide a first power signal;

[0036] A second power management circuit, connected to the first timing management circuit in the start control circuit and the main controller, and configured to provide a second power signal;

[0037] A generation circuit, the main controller is connected to a selection circuit in the start control circuit through the generation circuit, the generation circuit is also connected to the first power management circuit and the second power management circuit, and the generation circuit is configured to generate a system start control signal based on the first power signal, the second power signal, and a set of start control signals output by the selection circuit in the start control circuit;

[0038] Wherein the main controller is configured to perform start control based on the system start control signal generated by the generation circuit.

[0039] An embodiment of the present disclosure further provides a control method for the start control circuit as described above, including:

[0040] The first timing management circuit provides a first set of start control signals, and the second timing management circuit provides a second set of start control signals;

[0041] The selection circuit receives the first set of start control signals and the second set of start control signals, and selects a set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0042] For example, in the first mode, the first timing management circuit provides a valid first status signal and the first set of start control signals, the second timing management circuit provides an invalid second status signal and the second set of start control signals, and the selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals for output according to the first status signal and the second status signal;

[0043] In the second mode, the first timing management circuit provides an invalid first status signal and the first set of start control signals, the second timing management circuit provides a valid second status signal and the second set of start control signals, and the selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals for output according to the first status signal and the second status signal.

[0044] For example, the first timing management circuit generates a valid first set of start control signals in response to a first start event and sends a first blocking signal to the second timing management circuit through a communication interface, the second timing management circuit generates an invalid second set of start control signals in response to the first blocking signal from the first timing management circuit, and the selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals for output;

[0045] The second timing management circuit generates a valid second set of start control signals in response to a second start event and sends a second blocking signal to the first timing management circuit through the communication interface. The first timing management circuit generates an invalid first set of start control signals in response to the second blocking signal from the second timing management circuit. The selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals for output. Description of the Drawings

[0046] Figure 1 It is a schematic block diagram of a start control circuit according to some embodiments;

[0047] Figure 2 It is a schematic block diagram of another start control circuit according to some embodiments;

[0048] Figure 3 It is an equivalent circuit diagram of a selection circuit according to some embodiments;

[0049] Figure 4 It is a schematic block diagram of yet another start control circuit according to some embodiments;

[0050] Figure 5 It is a flowchart of the steps of a control method for a start control circuit according to some embodiments;

[0051] Figure 6 It is a flowchart of the steps of a control method for another start control circuit according to some embodiments;

[0052] Figure 7 It is a flowchart of the steps of a control method for yet another start control circuit according to some embodiments;

[0053] Figure 8 It is a schematic block diagram of a display control circuit according to some embodiments;

[0054] Figure 9 It is a circuit diagram of a generation circuit according to some embodiments;

[0055] Figure 10 It is a schematic block diagram of another display control circuit according to some embodiments. Detailed Description of the Embodiments

[0056] Although the present disclosure will be fully described with reference to the drawings containing the preferred embodiments of the present disclosure, it should be understood before this description that those of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it must be understood that the above description is a broad disclosure to those of ordinary skill in the art, and its content is not intended to limit the exemplary embodiments described in the present disclosure.

[0057] In addition, in the following detailed description, for the sake of explanation, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details. In other instances, well-known structures and devices are illustrated in a schematic manner to simplify the drawings.

[0058] The entire machine system can include both a local timing management circuit and a remotely controllable timing management circuit (referred to simply as a remote control timing management circuit). During the operation of the entire machine system, both jointly control the timing and state of the entire machine system. For example, the remote control timing management circuit can remotely control software to turn on and off the device, and can also remotely control the device to switch between states such as sleep, wake-up, and standby. This can not only turn off high-power-consuming devices during idle time to save energy, but also effectively extend the life of the entire machine. In addition, remote control can also effectively reduce the frequency of on-site operations by personnel. For example, when the remote control center detects a problem with the system, it can restart the system through remote control to eliminate some minor defects, without having to arrange operators at the on-site distribution of each entire machine at all times.

[0059] However, since the entire machine system is controlled by both the local timing management circuit and the remote control timing management circuit, it is possible for the control signals sent by the two to conflict with each other, resulting in the entire machine system malfunctioning or even losing its functions. For example, during the startup phase of the entire machine system, or during the wake-up phase after sleep, after the local timing management circuit controls the entire machine system to power on and reset, the entire machine system starts to boot. If the remote control timing management circuit issues another power-on reset control signal during the system startup process, it may cause the data in the memory boot area of the entire machine system to be damaged during the loading process, thereby causing the entire machine system to malfunction or even lose its functions and be unable to operate.

[0060] Figure 1 It is a schematic block diagram of a startup control circuit according to some embodiments of the present disclosure.

[0061] See Figure 1 , the startup control circuit 00 includes a first timing management circuit 10, a second timing management circuit 20, and a selection circuit 30. The first timing management circuit 10 can provide a first set of startup control signals SC1. The second timing management circuit 20 can provide a second set of startup control signals SC2. The selection circuit 30 is connected to the first timing management circuit 10 and the second timing management circuit 20. The selection circuit 30 can receive the first set of startup control signals SC1 and the second set of startup control signals SC2, and select a set of startup control signals from the first set of startup control signals SC1 and the second set of startup control signals SC2 for output.

[0062] In this way, even if start control signals are sent by both the first timing management circuit and the second timing management circuit during a certain period, the start control circuit can select one set of start control signals from the two sets of start control signals for subsequent start control operations, thereby avoiding the situation of system start-up failure caused by the conflict of start control signals from the two timing management circuits.

[0063] In some embodiments, the first timing management circuit 10 can be used as a local timing management circuit, and the second timing management circuit 20 can be used as a remote timing management circuit. The local timing management circuit can be used to implement local timing management functions. For example, in the case where the whole machine system has no remote connection (such as connecting to a remote device through a Wi-Fi wireless network), the start of the whole machine system can be controlled by the first timing management circuit 10. The remote timing management circuit can receive instructions transmitted by a remote device (such as a remote server) and can be used to implement part of the local timing management functions and remote communication functions. For example, in the cases of abnormal state restart of the digital display system of the whole machine system, system hibernation, and wake-up from the hibernation state, etc., the start of the system can be controlled by the remote timing management circuit. For example, the remote server can send instructions to the remote timing management circuit to achieve remote control of the entire system.

[0064] In this case, when the local timing management circuit is abnormal, the start can be controlled by the remote timing management circuit, thereby reducing the number of on-site operations of personnel; moreover, the system hibernation and wake-up processes can be controlled by the remote timing management circuit, reducing the priority of the local timing management circuit, so that a complete timing management logic can be formed in the whole machine system, reducing the risk of abnormal hibernation and wake-up.

[0065] Figure 2 It is a schematic block diagram of another start control circuit according to some embodiments.

[0066] See Figure 2 , the start control circuit 01 includes a first timing management circuit 10, a second timing management circuit 20, and a selection circuit 30. In addition to being able to provide a first set of start control signals SC1, the first timing management circuit 10 can also provide a first status signal STAS1. In addition to being able to provide a second set of start control signals SC2, the second timing management circuit 20 can also provide a second status signal STAS2. The selection circuit 30 can receive the first status signal STAS1 and the first set of start control signals SC1 from the first timing management circuit 10, receive the second status signal STAS2 and the second set of start control signals SC2 from the second timing management circuit 20, and select one set of start control signals from the first set of start control signals SC1 and the second set of start control signals SC2 according to the first status signal STAS1 and the second status signal STAS2 for output.

[0067] In this way, based on the status signals of the first timing management circuit and the second timing management circuit, the startup control circuit can accurately determine which startup control signal output from the first timing management circuit and the second timing management circuit should be used to perform startup control, thereby avoiding the mutual conflict of startup control signals from different timing management circuits, and further avoiding startup failures caused by such conflicts.

[0068] Figure 3 FIG. is a circuit diagram of a selection circuit according to some embodiments. The selection circuit can be the selection circuit in any of the above embodiments, for example Figure 2 the control circuit in the startup control circuit of. The description of the selection circuit in the above text also applies to this embodiment.

[0069] See Figure 3 , the selection circuit includes a status selection sub-circuit 301, a first switch sub-circuit 302, and a second switch sub-circuit 303.

[0070] The status selection sub-circuit 301 can have a first input terminal IN1, a second input terminal IN2, a first output terminal O1, and a second output terminal O2. The first input terminal IN1 of the status selection sub-circuit 301 is connected to the first timing management circuit 10 to receive the first status signal STAS1. The second input terminal IN2 of the status selection sub-circuit 301 is connected to the second timing management circuit 20 to receive the second status signal STAS2. The status selection sub-circuit 301 can output a first switch control signal at the first output terminal O1 of the status selection sub-circuit 301 and output a second switch control signal at the second output terminal O2 of the status selection sub-circuit 301 according to the first status signal STAS1 received at the first input terminal IN1 and the second status signal STAS2 received at the second input terminal IN2.

[0071] The control terminal C1 of the first switch sub-circuit 302 is connected to the first output terminal O1 of the status selection sub-circuit 301 to receive the first switch control signal. The input terminal of the first switch sub-circuit 302 is connected to the above-mentioned first timing management sub-circuit to receive the above-mentioned first set of startup control signals. In some embodiments, the first set of startup signals can include a first enable signal En1 and a first reset signal Rst1, and the input terminal of the first switch sub-circuit 302 can include a first input terminal I for receiving the first enable signal En1 A and a second input terminal I for receiving the first reset signal Rst1 B. The first switch sub - circuit 302 can provide a first set of start - up control signals received at the input end of the first switch sub - circuit 302 to the output end of the first switch sub - circuit 302 under the control of a first switch control signal received at the control end C1 of the first switch sub - circuit 302. In some embodiments, the output end of the first switch sub - circuit 302 may include a first output end O for outputting a first enable signal En1 A and a second output end O for receiving a first reset signal Rst1 B .

[0072] . The control end C2 of the second switch sub - circuit 303 is connected to the second output end O2 of the state selection sub - circuit 301 to receive a second switch control signal. The input end of the second switch sub - circuit 303 is connected to the second timing management sub - circuit described above to receive the second set of start - up control signals. In some embodiments, the second set of start - up signals may include a second enable signal En2 and a first reset signal Rst2. The input end of the second switch sub - circuit 303 may include a first input end I for receiving the second enable signal En2 C and a second input end I for receiving the second reset signal Rst2 D . The second switch sub - circuit 303 can provide the second set of start - up control signals received at the input end of the second switch sub - circuit 303 to the output end of the second switch sub - circuit 303 under the control of a second switch control signal received at the control end C2 of the second switch sub - circuit 303. In some embodiments, the output end of the second switch sub - circuit 303 may include a first output end O for outputting a second enable signal En2 C and a second output end O for receiving the second reset signal Rst2 D .

[0073] In some embodiments, referring to Figure 3 , the state selection sub - circuit 301 may include a first inverter 3011, a first AND gate 3013, a second inverter 3012, and a second AND gate 3014. The first input end of the first AND gate 3013 is connected to the first input end IN1 of the state selection sub - circuit 301. The second input end of the first AND gate 3013 is connected to the output end of the first inverter 3011. The output end of the first AND gate 3013 is connected to the first output end O1 of the state selection sub - circuit 301. The input end of the second inverter 3012 is connected to the first input end IN1 of the state selection sub - circuit 301. The first input end of the second AND gate 3014 is connected to the second input end IN2 of the state selection sub - circuit 301. The second input end of the second AND gate 3014 is connected to the output end of the second inverter 3012. The output end of the second AND gate 3014 is connected to the second output end O2 of the state selection sub - circuit.

[0074] In some embodiments, referring to Figure 3 , the first set of startup control signals SC1 includes a first enable signal En1 and a first reset signal Rst1. The first switch sub - circuit 302 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is connected to the control terminal C1 of the first switch sub - circuit 302. The first pole of the first transistor M1 serves as the first input terminal I of the first switch sub - circuit 302 A and is connected to receive the first enable signal En1. The second pole of the first transistor M1 is connected to the first output terminal O of the first switch sub - circuit 302 A . The gate of the second transistor M2 is connected to the control terminal C1 of the first switch sub - circuit 302. The first pole of the second transistor M2 serves as the second input terminal I of the first switch sub - circuit 302 B and is connected to receive the first reset signal Rst1. The second pole of the second transistor M2 is connected to the second output terminal O of the first switch sub - circuit 303 B .

[0075] In some embodiments, referring to Figure 3 , the second set of startup control signals SC2 includes a second enable signal En2 and a second reset signal Rst2. The second switch sub - circuit 303 includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the control terminal C2 of the second switch sub - circuit 303. The first pole of the third transistor M3 serves as the first input terminal I of the second switch sub - circuit 303 C and is connected to receive the second enable signal En2. The second pole of the third transistor M3 is connected to the first output terminal O of the second switch sub - circuit 303 C . The gate of the fourth transistor M4 is connected to the control terminal C2 of the second switch sub - circuit 303. The first pole of the fourth transistor M4 serves as the second input terminal I of the second switch sub - circuit 303 D and is connected to receive the second reset signal Rst2. The second pole of the fourth transistor is connected to the second output terminal O of the second switch sub - circuit 303 D . In some embodiments, referring to Figure 3 , the first output terminal O of the first switch sub - circuit 302 A is connected to the first output terminal O of the second switch sub - circuit 303 C to form the first output terminal OUT1 of the selection circuit 30. The second output terminal O of the first switch sub - circuit 302 B is connected to the second output terminal O of the second switch sub - circuit 303 Dis connected to the second output terminal OUT2 of the selection circuit 30.

[0076] The operation of the selection circuit will be described below with reference to Table 1 and Table 2. Table 1 is the truth table of the signal states of the first AND gate 3013, and Table 2 is the truth table of the signal states of the second AND gate 3014. Figure 3 The operation of the selection circuit will be described below with reference to Table 1 and Table 2. Table 1 is the truth table of the signal states of the first AND gate 3013, and Table 2 is the truth table of the signal states of the second AND gate 3014.

[0077] Table 1

[0078]

[0079] Table 2

[0080]

[0081] Below, taking the state of the first state signal STAS1 as 0 and the state of the second state signal STAS2 as 1 as an example, an exemplary description of the operation performed by the state selection sub-circuit 301 will be given.

[0082] The first state signal STAS1 with a state of 0 is provided to the first input terminal of the first AND gate 3013, such that the state of the first input terminal of the first AND gate 3013 is 0. The second state signal STAS2 with a state of 1 becomes a signal with a state of 0 after passing through the first inverter 3011, such that the state of the second input terminal of the first AND gate 3013 is 0. In this case, the states of the first input terminal and the second input terminal of the first AND gate 3013 are 0, such that the state of the first switch control signal output at the output terminal of the first AND gate 3013 is 0.

[0083] Similarly, the first state signal STAS1 with a state of 0 is transmitted to the second input terminal of the second AND gate 3014 after passing through the second inverter 3012, such that the state of the second input terminal of the second AND gate 3014 is 1; the second state signal STAS2 with a state of 1 is provided to the first input terminal of the second AND gate 3014, such that the state of the first input terminal of the second AND gate 3014 is 1. In this case, the states of the first input terminal and the second input terminal of the second AND gate 3014 are both 1, such that the state of the second switch control signal output at the output terminal of the second AND gate 3014 is 1.

[0084] For other combinations of the states of the first state signal STAS1 and the second state signal STAS2, the state selection sub-circuit 301 works in a similar manner according to the above truth table, which will not be elaborated here one by one.

[0085] As can be seen from Table 1 and Table 2 above, when one of the first state signal STAS1 and the second state signal STAS2 is in the state of 1 and the other is in the state of 0, the state selection sub - circuit 301 outputs a switch control signal with a state of 1 at one of the first output terminal O1 and the second output terminal O2, and outputs a switch control signal with a state of 0 at the other of the first output terminal O1 and the second output terminal O2. For example, when the state of the first state signal STAS1 is 1 and the state of the second state signal STAS2 is 0, the state selection sub - circuit 301 outputs a first switch control signal with a state of 1 at the first output terminal O1, and outputs a second switch control signal with a state of 0 at the second output terminal O2. When the state of the first state signal STAS1 is 0 and the state of the second state signal STAS2 is 1, the state selection sub - circuit 301 outputs a first switch control signal with a state of 0 at the first output terminal O1, and outputs a second switch control signal with a state of 1 at the second output terminal O2.

[0086] Similarly, taking the case where the state of the first state signal STAS1 is 0 and the state of the second state signal STAS1 is 0 as an example, since the state of the first switch control signal output by the state selection sub - circuit 301 at the first output terminal O1 is 0, the first transistor M1 and the second transistor M2 are turned off, and no output signal is generated at the first output terminal O A and the second output terminal O B of the first switch sub - circuit 302; since the state of the second switch control signal output by the state selection sub - circuit 301 at the second output terminal O2 is 1, the third transistor M3 and the fourth transistor M4 are turned on, and the second switch sub - circuit 303 outputs a second enable signal En2 at the first output terminal O C and outputs a second reset signal Rst2 at the second output terminal O D

[0087] Similarly, when the state of the first state signal STAS1 is 1 and the state of the second state signal STAS1 is 0, the state of the first switch control signal output by the state selection sub - circuit 301 at the first output terminal O1 is 1, and the first transistor M1 and the second transistor M2 are turned on, so that the first switch sub - circuit 302 outputs a first enable signal En1 and a first reset signal RST1 at the first output terminal O A and the second output terminal O B respectively; the third transistor M3 and the fourth transistor M4 are turned off, so that no output signal is generated at the first output terminal O C and the second output terminal O D of the second switch sub - circuit 303.

[0088] In this way, the selection circuit can output the first set of start control signals En1 and Rst1 when the first state signal is 1 and the second state signal is 0; and output the second set of start control signals En2 and Rst2 when the first state signal is 0 and the second state signal is 1, so that it is possible to select one set of control signals from the two sets for output, reducing start-up failures caused by conflicts between the two sets of start control signals.

[0089] Figure 4 It is a schematic block diagram of another start control circuit according to some embodiments.

[0090] See Figure 4 , the start control circuit 02 includes a first timing management circuit 10', a second timing management circuit 20' and a selection circuit 30'.

[0091] The first timing management circuit 10' can generate valid first set of start control signals in response to a first start event and send a first blocking signal to the second timing management circuit 20' through the communication interface P. The first timing management circuit 10' can also generate invalid first set of start control signals in response to a second blocking signal from the second timing management circuit 20'. As Figure 4 shown, the first set of start control signals can include a first enable signal En1 and a first reset signal Rst1. Exemplarily, the above first start event includes but is not limited to a power-on event.

[0092] The second timing management circuit 20' can generate valid second set of start control signals in response to a second start event and send a second blocking signal to the first timing management circuit 10' through the communication interface P. The second timing management circuit 20' can also generate invalid second set of start control signals in response to a first blocking signal from the first timing management circuit 10'. As Figure 4 shown, the second set of start control signals can include a second enable signal En2 and a first reset signal Rst2. Exemplarily, the above second start event includes but is not limited to a restart event, a sleep event, a wake-up event, etc.

[0093] The selection circuit 30' can select a valid set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0094] In some embodiments, the communication interface P includes but is not limited to an Inter-Integrated Circuit (I 2 C) interface or a Universal Asynchronous Receiver / Transmitter (Uart) serial port.

[0095] During operation, the first timing management circuit 10' and the second timing management circuit 20' can transmit blocking signals through the communication interface P, and coordinate the output of the start control signals by sending blocking signals to each other when needed. The selection circuit 30' can select a valid set of start control signals from the two sets of start control signals for output.

[0096] In some embodiments, referring to Figure 4 , the first set of start control signals may include a first enable signal En1 and a first reset signal Rst1, and the second set of start control signals may include a second enable signal En2 and a second reset signal Rst2. The selection circuit 30' includes an exclusive OR gate 306 and an exclusive NOR gate 307.

[0097] The first input terminal of the exclusive OR gate 306 is connected to the first timing management circuit 10' to receive the first enable signal En1. The second input terminal of the exclusive OR gate 306 is connected to the second timing management circuit 20' to receive the second enable signal En2. The output terminal of the exclusive OR gate 306 serves as the first output terminal OUT1 of the selection circuit 30'.

[0098] The first input terminal of the exclusive NOR gate 307 is connected to the first timing management circuit 10' to receive the first reset signal Rst1. The second input terminal of the exclusive NOR gate 307 is connected to the second timing management circuit 20' to receive the second reset signal Rst2. The output terminal of the exclusive NOR gate 307 serves as the second output terminal OUT2 of the selection circuit 30'.

[0099] By setting the exclusive OR gate 306, selective output of the first enable signal En1 and the second enable signal En2 can be achieved. By setting the exclusive NOR gate 307, selective output of the first reset signal Rst1 and the second reset signal Rst2 can be achieved. Both the exclusive OR gate 306 and the exclusive NOR gate 307 are unidirectional logic circuits, which can avoid mutual interference between the two sets of start control signals.

[0100] The operation of the selection circuit 30' will be described below with reference to Table 3 and Table 4.

[0101] Table 3 is the truth table of the signal states of the exclusive OR gate 306, and Table 4 is the truth table of the signal states of the exclusive NOR gate 307.

[0102] Table 3

[0103] First enable signal En1 Second enable signal En2 EN 0 0 0 0 1 1 1 0 1 1 1 0

[0104] Table 4

[0105] First reset signal Rst1 Second reset signal Rst2 RST 0 0 1 0 1 0 1 0 0 1 1 1

[0106] In this embodiment, an example is given where the active levels of the first enable signal En1 and the second enable signal En2 are low levels (i.e., 0 state), and the active levels of the first reset signal Rst1 and the second reset signal Rst2 are high levels (i.e., 1 state). Those skilled in the art should understand that the embodiments of the present disclosure are not limited thereto, and the active levels of the enable signal and the reset signal can be set to high level or low level as needed.

[0107] When En1 = 0, the first enable signal En1 is an invalid signal. The exclusive - OR gate 306 operates according to the truth table in Table 3. If the state of the second enable signal En2 is 0, it outputs 0; if the state of the second enable signal En2 is 1, it outputs 1. It can be seen that when the first enable signal En1 is an invalid signal, the output signal of the exclusive - OR gate 306 is the same as the second enable signal En2.

[0108] When Rst1 = 1, the first reset signal Rst1 is an invalid signal. The equivalence gate 307 operates according to the truth table in Table 4. If the state of the second reset signal Rst2 is 0, it outputs 0; if the state of the second reset signal Rst2 is 1, it outputs 1. It can be seen that when the first reset signal Rst1 is an invalid signal, the output signal of the equivalence gate 307 is the same as the second reset signal Rst2.

[0109] In this way, when the first set of start - up control signals En1 and Rst1 are invalid, that is, when En1 = 0 and Rst1 = 1, the signals output from the first output terminal OUT1 and the second output terminal OUT2 of the selection circuit 30' are the same as the second set of start - up control signals En2 and Rst2 respectively.

[0110] In a similar way, referring to Table 3 and Table 4, when the second set of start - up control signals En2 and Rst2 are invalid, that is, when En2 = 0 and Rst2 = 1, the signals output from the first output terminal OUT1 and the second output terminal OUT2 of the selection circuit 30' are the same as the first set of start - up control signals En1 and Rst1 respectively.

[0111] In other words, the exclusive - OR gate 306 can output an enable signal in an invalid state (i.e., state 0) when the first enable signal En1 and the second enable signal En2 are in the same state; and output an enable signal in an effective state (i.e., state 1) when one of the first enable signal En1 and the second enable signal En2 is in an effective state and the other is in an invalid state. Thus, it realizes selecting an effective one from the first enable signal En1 and the second enable signal En2 for output and there is no conflict between the two.

[0112] Similarly, the XNOR gate 307 can output a reset signal in an invalid state (i.e., state 1) when the first reset signal Rst1 and the second reset signal Rst2 are in the same state; and can output a reset signal in a valid state (i.e., state 0) when one of the first reset signal Rst1 and the second reset signal Rst2 is in a valid state and the other is in an invalid state. Thus, it is realized to select a valid one from the first reset signal Rst1 and the second reset signal Rst2 for output and the two do not conflict.

[0113] Through the above method, it is realized to select a valid set of start control signals from two sets of start control signals for output, thus avoiding conflicts between the two sets of start control signals.

[0114] Figure 5 It is a step flowchart of a control method for a start control circuit according to some embodiments. This method is applicable to the start control circuit of any of the above embodiments.

[0115] See Figure 5 , this method includes the following operations S10 and S20.

[0116] In operation S10, the first timing management circuit provides a first set of start control signals, and the second timing management circuit provides a second set of start control signals.

[0117] In operation S20, the selection circuit receives the first set of start control signals and the second set of start control signals, and selects a set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0118] Figure 6 It is a step flowchart of a control method for a start control circuit according to some embodiments. This method is applicable to the start control circuit of any of the above embodiments, such as the above start control circuit 01. See Figure 6 , the above control method may include the following operations S101 and S102.

[0119] In operation S101, in the first mode, the first timing management circuit provides a valid first state signal and a first set of start control signals, the second timing management circuit provides an invalid second state signal and a second set of start control signals, and the selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals for output according to the first state signal and the second state signal.

[0120] In operation S102, in the second mode, the first timing management circuit provides an invalid first status signal and a first set of start control signals, the second timing management circuit provides a valid second status signal and a second set of start control signals, and the selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals according to the first status signal and the second status signal for output.

[0121] Figure 7 It is a flowchart of steps of a control method for a start control circuit according to some embodiments. This method is applicable to the start control circuit of any of the above embodiments, such as the above start control circuit 02. Refer to Figure 7 , the above method may include the following operations S201 and S202.

[0122] In operation S201, the first timing management circuit generates a valid first set of start control signals in response to a first start event and sends a first blocking signal to the second timing management circuit through a communication interface. The second timing management circuit generates an invalid second set of start control signals in response to the first blocking signal from the first timing management circuit. The selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0123] In operation S202, the second timing management circuit generates a valid second set of start control signals in response to a second start event and sends a second blocking signal to the first timing management circuit through a communication interface. The first timing management circuit generates an invalid first set of start control signals in response to the second blocking signal from the second timing management circuit. The selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals for output.

[0124] Figure 8 It is a schematic block diagram of a display control circuit 001 according to some embodiments.

[0125] Refer to Figure 8 , the display control circuit 001 includes the above start control circuit and a main controller 05.

[0126] The start control circuit can be the start control circuit of any of the above embodiments, such as the above start control circuit 01.

[0127] The main controller 05 is connected to the startup control circuit 01. The main controller 05 can perform startup control according to a set of startup control signals output by the startup control circuit 01. The set of startup control signals includes, for example, an enable signal EN output at the first output terminal OUT1 of the selection circuit 30 in the startup control circuit 01 and a reset signal RST output at the second output terminal OUT2 of the selection circuit 30. The main controller 05 is the core processor of the software and hardware of the entire machine system and is the center for implementing various functions of the system. It can cooperate with the above-mentioned startup control circuit and power management circuit to achieve startup control.

[0128] In some embodiments, the display control circuit 001 may further include a first power management circuit 06, a second power management circuit 07, and a generation circuit 08.

[0129] The first power management circuit 06 is connected to the first timing management circuit 10 and the second timing management circuit 20 in the startup control circuit 01. The first power management circuit 06 provides a first power signal PW1, such as a 3.3V power signal.

[0130] The second power management circuit 07 is connected to the first timing management circuit 10 in the startup control circuit 01 and the main controller 05. The second power management circuit 07 can provide a second power signal PW2, such as a 5V power signal. In Figure 8 this case, there are two second power management circuits 07. One is used to provide the system power supply voltage, and the other is used to provide the interface power supply voltage for interfaces such as USB interfaces, M.2 interfaces, and HDMI interfaces. The first power management circuit 06 and the second power management circuit form a power supply system, which completes the power-on / power-off process according to the power-on / power-off timing requirements and performs switch control on the enable and control signals of the main controller.

[0131] The main controller 05 can be connected to the selection circuit 30 in the startup control circuit through the generation circuit 08. The generation circuit 08 is also connected to the first power management circuit 06 and the second power management circuit 07. The generation circuit 08 can generate system startup control signals ENs and RSTs based on the first power signal PW1, the second power signal PW2, and a set of startup control signals EN and RST output by the selection circuit 30 in the startup control circuit 01. The main controller 05 can perform startup control based on the system startup control signals ENs and RSTs generated by the generation circuit 08.

[0132] In the above embodiments, each of the first power management circuit 06 and the second power management circuit 07 can be implemented as a power management chip. Each of the first timing management circuit 10 and the second timing management circuit 20 can also be implemented as a timing management chip.

[0133] In some embodiments, the display control circuit may further include a physical button PB. For example, in Figure 8 the display control circuit includes two reset buttons PB. The reset button PB is used to force the power-on of the display device and force it to enter the protection mode (factory mode). Generally, the physical button has a higher priority than any other signal to ensure that the display device can receive the button instruction and implement the required function.

[0134] Figure 9 Fig. shows a partial equivalent circuit diagram of a generating circuit according to some embodiments. The generating circuit is applicable to the display control circuit of the above embodiments, such as Figure 8 the display control circuit.

[0135] As Figure 9 shown, the generating circuit includes a first generating sub-circuit and a second generating sub-circuit. The first generating sub-circuit includes transistors M5 and M6, and the second generating sub-circuit includes transistors M7 and M8.

[0136] The gate of transistor M5 is electrically connected to the selection circuit 30 to receive the enable signal EN output from the first output terminal OUT1 of the selection circuit 30. The first pole of transistor M5 is connected to receive the second power signal PW2 from the second power management circuit 07. The second pole of transistor M5 is grounded to GND. The gate of transistor M6 is connected to receive the second power signal PW2. The first pole of transistor M6 is connected to receive the second power voltage PW2 from the second power management circuit 07 and is connected to output the enable signal ENs in the system start control signal. The second pole of transistor M6 is grounded to GND.

[0137] Similarly, the gate of transistor M7 is connected to the first output terminal OUT1 of the selection circuit 30 to receive the enable signal EN. The first pole of transistor M7 is connected to receive the second power signal PW2 from the second power management circuit 07. The second pole of transistor M7 is grounded to GND. The gate of transistor M8 is connected to receive the second power signal PW2. The first pole of transistor M8 is connected to receive the second power voltage PW2 from the second power management circuit 07 and is connected to output the reset signal RSTs in the system start control signal. The second pole of transistor M8 is grounded to GND.

[0138] The display control circuit described above is applicable to various display devices, including but not limited to display devices used in large commercial supermarkets, vending machines, freezer cabinets in gas stations, etc. for product introduction and advertising of freezer cabinets, refrigerators, etc.

[0139] Next, Figure 8An exemplary introduction is made to the startup control process executed by the display control circuit shown. The startup control process may include a power-on control process, a restart control process, a remote sleep control process, a remote wake-up control process, etc.

[0140] In the following described example, the first timing management circuit 10 is a local timing management circuit, the second timing management circuit 20 is a remote timing management circuit, the first power management circuit 06 is a 3.3V power management chip for providing a 3.3V power supply voltage, and the second power management circuit 07 is a 3.3V power management chip for a 5V power supply voltage.

[0141] See Figure 8 , the power-on control process of the display control circuit includes the following steps A11 - A19.

[0142] Step A11: A 12V power supply is input to the display device where the display control circuit is located, and the first power management circuit 06 starts to work and provides a 3.3V first power signal PW1 and a power normal signal Power_Good to the first timing management circuit 10 and the second timing management circuit 20.

[0143] Step A12: After the first timing management circuit 10 is powered on, it confirms the current state. The power-on state flag bit Flag = 1 can be set in the program. The initial state of the state flag bit Flag is 0 and is set to 1 after power-on is completed. After the first timing management circuit 10 is powered off, the flag bit Flag returns from 1 to the initial state 0. When the first timing management circuit 10 reads that the current state flag bit is 0, it determines that the display device is in the power-on process. The first timing management circuit 10 outputs a system power-on signal System_Power_On and a power-on signal Power_On_2 for the second power management circuit 07 to the second power management circuit 07, and outputs STAS1 = 1, En1 = 1, and Rst1 = 1 to the selection circuit 30.

[0144] Step A13: After the second timing management circuit 20 is powered on, it can confirm whether remote control of the display device is required by connecting to the remote server through Wifi. Generally, when the remote server does not receive an abnormal reporting signal, it will not issue a system control command. In this case, the second timing management circuit 20 outputs STAS1 = 0, En2 = 0, and Rst1 = 1 to the selection circuit 30.

[0145] Step A14: The second power management circuit 07 for powering the system receives the signal System_Power_On, starts to output a 5V first power signal PW1 to power the system, and at the same time provides an enabling level for the second power management circuit 07 for powering the interface, and enables the second power management circuit 07 for powering the interface together with the signal Power_On_2.

[0146] Step A15: After the above signal is output in Step A12, after an interval of the first time T1, output En1 = 1 and Rst1 = 0, and maintain for the second time T2.

[0147] Step A16: The selection circuit 30 receives STAS1 = 1 and STAS2 = 0, and performs the corresponding operations described above, so as to output the En1 and Rst1 signals provided by the first timing management circuit 10 as the enable signal EN and the reset signal RST to the generation circuit 08.

[0148] Step A17: The generation circuit 08 generates the system enable signal EN S and the system reset signal RST S and outputs them to the main controller 05.

[0149] Step A18: After the main controller 05 receives the system enable signal EN S and the reset signal RST S it starts to control the display device to enter the power-on process and enables the HDMI interface, so as to output a video signal.

[0150] Step A19: After an interval of the third time T3, the status flag bit of the first timing management circuit 10 changes from 0 to 1. At this time, it is marked that the power-on ends, and the display device enters the idle state.

[0151] See Figure 8 The restart control process of the display control circuit includes the following steps A21 - A24.

[0152] Step A21: When an abnormality occurs during the power-on process of the display device, an abnormality occurs during the operation process, or the display device needs to be restarted according to the requirements of the remote server, the second timing management circuit 20 will set STAS2 = 1, En2 = 1, and Rst2 = 1 according to the instructions of the remote server. After the fourth time T4, Rst2 = 0 and lasts for the third time T3. At the same time, the second timing management circuit 20 will output the forced reset signal Force_RST to the first timing management circuit 10 to reset the first timing management circuit 10. After the first timing management circuit 10 completes the reset, STAS1 = 0, En1 = 0, and Rst1 = 1.

[0153] Step A22: The selection circuit 30 receives STAS1 = 0 and STAS2 = 1, and performs the corresponding operations described above, so as to output En2 and Rst2 provided by the second timing management circuit 20 as the enable signal EN and the reset signal RST to the generation circuit 08.

[0154] Step A23: Based on the PW1 and PW2 signals provided by the first power management circuit 06, the second power management circuit 07 and the first power management circuit 06, as well as the enable signal EN and the reset signal RST output by the selection circuit 30, the generation circuit 08 generates a system enable signal EN S and a system reset signal RST S and outputs them to the main controller 05.

[0155] Step A24: After receiving the system enable signal EN S and the reset signal RST S by the main controller 05, it starts to control the display device to enter the restart process, and enables the HDMI interface after restart, and starts to output video signals.

[0156] See Figure 8 , the remote sleep control process executed by the display control circuit includes the following steps S31 to S37.

[0157] Step A31: The second timing management circuit 20 receives the information transmitted by the remote server through the Wifi connection, and confirms whether the display device needs to be put to sleep according to this information.

[0158] Step A32: In response to receiving a signal indicating that sleep is required from the remote server, the second timing management circuit 20 sets the wake-up signal Wake_Up_2 to 0 (the default state of the Wake Up2 signal is 1) and sends it to the first timing management circuit 10 to notify the first timing management circuit 10 to perform the sleep program processing. The second timing management circuit 20 also outputs STAS2 = 1, En2 = 0, and Rst2 = 1 to the selection circuit 30, where En2 = 0 indicates sleep, and Rst2 = 1 indicates no reset.

[0159] Step A33: After receiving Wake_Up_2 = 0, the first timing management circuit 10 turns off the second power management circuit 07, and outputs STAS1 = 0, En1 = 1 (notifying the system to sleep), and Rst1 = 1 signals to the selection circuit 30.

[0160] Step A34: The state selection sub - circuit 301 in the selection circuit 30 obtains STAS1 = 0 and STAS2 = 1 according to Step A32 and Step A33, and performs the corresponding operations described above, so as to output the En2 signal and Rst2 signal provided by the second timing management circuit 20 as the enable signal EN and the reset signal RST to the generation circuit 08.

[0161] Step A35: The generation circuit 08 generates the system enable signal EN S and the system reset signal RST S based on the PW1 and PW2 signals provided by the first power management circuit 06, the second power management circuit 07 and the first power management circuit 06, as well as the enable signal EN and the reset signal RST output by the selection circuit 30, and outputs them to the main controller 05.

[0162] Step A36: When the main controller 05 receives that the system enable signal EN S is 0 (system in sleep mode) and the system reset signal RST S is 1 (no reset), it enters the sleep mode, and at the same time outputs the sleep mode signal Mode_Sleep = 0, turns off the HDMI interface output, and notifies the second timing management circuit 20 that the display device has entered the sleep mode through the sleep mode signal Mode_Sleep. The main controller 05 also outputs the forced shutdown signal Force_Off = 0 to the first timing management circuit 10 to notify the first timing management circuit 10 that the system sleep operation is completed, and the first timing management circuit 10 can enter the sleep mode. The main controller 05 also outputs the wake - up signal Wake_Up_1 = 0 to the second timing management circuit 20 to notify the second timing management circuit 20 to enter the sleep mode.

[0163] Step A37: In response to receiving the sleep mode signal Mode_Sleep = 0 and the wake - up signal Wake_Up_1 = 0, the second timing management circuit 20 keeps the remote communication wake - up functional unit in the second timing management circuit 20 working and shuts down the remaining circuits. In response to receiving Force_Off = 0, the first timing management circuit 10 keeps the standby functional unit in the first timing management circuit 10 working and shuts down the remaining circuits. After completing the above steps, the control module of the display device where the display control circuit is located enters the sleep state. After the HDMI interface has no output, the entire display device then enters the sleep state, thus realizing the sleep of the display device.

[0164] See Figure 8 The remote wake - up process of the display device controlled by the display control circuit includes the following steps A41 - A47.

[0165] Step A41: The second timing management circuit 20 receives the information transmitted by the Wifi connection and confirms whether the display device needs to be woken up according to this information.

[0166] Step A42: When the second timing management circuit 20 receives the wake-up signal, the second timing management circuit 20 sets the wake-up signal Wake_Up_2 to 1 to notify the first timing management circuit 10 to perform the wake-up program processing. The second timing management circuit 20 also outputs STAS2 = 1, En2 = 1 (notifying the system to wake up) and Rst2 = 1 (not performing reset) to the selection circuit 30.

[0167] Step A43: In response to receiving the wake-up signal Wake_Up_2 = 1, the first timing management circuit 10 turns on the second power management circuit 07 and outputs STAS1 = 0, En1 = 1 (system wake-up) and Rst1 = 1 (not performing reset) to the selection circuit 30.

[0168] Step A44: The selection circuit 30 receives STAS1 = 0 and STAS2 = 1 and performs the corresponding operations described above, so as to output the En2 signal and Rst2 signal output by the second timing management circuit 20 as the enable signal EN and the reset signal RST to the generation circuit 08

[0169] Step A45: The generation circuit 08 generates the system enable signal EN S and the system reset signal RST S based on the PW1 and PW2 signals provided by the first power management circuit 06, the second power management circuit 07 and the first power management circuit 06, as well as the enable signal EN and the reset signal RST output by the selection circuit 30, and outputs them to the main controller 05.

[0170] Step A46: When the main controller 05 receives the system enable signal EN S is 1 (system wake-up), and the system reset signal RST S is 1 (not performing reset), it starts to wake up each functional unit of the display device, and at the same time outputs the sleep mode signal Mode_Sleep = 1, turns on the HDMI interface output, and notifies the second timing management circuit 20 that the system has been woken up through this Mode_Sleep = 1. The main controller 05 also outputs the forced shutdown signal Force_Off = 1 to the first timing management circuit 10 to notify the first timing management circuit 10 that the system wake-up operation is completed, and the first timing management circuit 10 can enter the normal working mode. The main controller 05 also outputs the output wake-up signal Wake_Up_1 = 1 to the second timing management circuit 20 to notify the second timing management circuit 20 to enter the normal working mode.

[0171] Step A47: The second timing management circuit 20 wakes up all the functional circuits of the second timing management circuit 20 in response to receiving the sleep mode signal Mode_Sleep = 1 and the wake-up signal Wake_Up_1 = 1; when the first timing management circuit 10 receives the Force_Off signal as 1, it wakes up all the functional circuits. After completing the above steps, the control module of the display device enters the normal working state. After the HDMI interface resumes output, the entire display device then also enters the normal working state, thus realizing the wake-up of the display device.

[0172] Figure 10 It is a schematic block diagram of another display control circuit according to some embodiments. Figure 10 The display control circuit 002 of Figure 8 is similar to the display control circuit 001 of Figure 10 The start control circuit in the display control circuit 002 of

[0173] The display control circuit 002 includes a start control circuit 02 and a main controller 05. The display control circuit 002 may also include a first power management circuit 06, a second power management circuit 07, and a generation circuit 08. The above descriptions of the first power management circuit 06, the second power management circuit 07, and the generation circuit 08 also apply to this embodiment.

[0174] The selection circuit 30 of the display control circuit 002 provides an enable signal EN at the first output terminal OUT1 and a reset signal RST at the second output terminal OUT2. The generation circuit 08 generates a system start control signal ENs and RSTs based on the enable signal EN and the reset signal RST and provides them to the main controller 05. The main controller 05 performs start control based on the system start control signal ENs and RSTs.

[0175] Next, Figure 10 An exemplary introduction will be made to the start control process executed by the display control circuit shown in

[0176] Refer to Figure 10 The power-on control process executed by the display control circuit includes the following steps B11 to B16.

[0177] Step B11: The 12V power supply inputs to the display device where the display control circuit is located, and the first power management circuit 06 starts to work and provides a first power signal PW1 of 3.3V and a power good signal Power_Good to the first timing management circuit 10' and the second timing management circuit 20'.

[0178] Step B12: After the first timing management circuit 10’ is powered on, confirm the current state. The power-on status flag bit Flag can be set to 1 in the program. The initial state is 0 and it is set to 1 after the power-on is completed. After power-off, the flag bit Flag returns to the initial state. When the first timing management circuit 10’ reads that the current state flag bit is flag = 0, it determines that the display device is in the power-on process, outputs the system power-on signal System_Power_On and the power-on signal Power_On_2 for the second power management circuit 07 to the second power management circuit 07, and outputs the first blocking signal to the second timing management circuit 20’ through the communication interface P (such as an I 2 C interface) to notify the second timing management circuit 20’ to output an invalid start control signal, that is, En2 = 0 and Rst2 = 1.

[0179] Step B13: The second power management circuit 07 for powering the system receives the System_Power_On signal, starts to output the second power signal PW2 of 5V to power the system, and at the same time provides an enabling level to the second power management circuit 07 for powering the interface. The enabling level and the signal Power_On_2 jointly enable the second power management circuit 07.

[0180] Step B14: In response to receiving the first blocking signal through the I 2 C interface, the second timing management circuit 20’ outputs En1 = 0 and Rst1 = 1. The exclusive-OR gate 306 and the equivalence gate 307 operate in the above manner to output the start control signals EN and RST, so as to ensure that the start control signals output by the second timing management circuit 20’ do not conflict with the start control signals output by the first timing management circuit 10’. This state will continue until the blocking end signal is received.

[0181] Step B15: After receiving the start control signals EN and RST, the main controller 05 enters the power-on process, enables the HDMI interface, and starts to output video signals.

[0182] Step B16: After the first timing management circuit 10’ times the preset time, it notifies the second timing management circuit 20’ to end the blocking state through the I 2 C interface, outputs En1 = 0, Rst1 = 1, and sets the power-on status flag bit Flag to 1, thereby completing the power-on control of the display device.

[0183] See Figure 10 , the remote reset control process executed by the display control circuit includes the following steps B21 to B25.

[0184] Step B21: When the second timing management circuit 20' is not in the blocked state, it can respond to the control of the remote server to perform operations such as restarting and hibernating the system. The second timing management circuit 20' receives the Wifi information, judges the information content, and performs specific operations according to the information.

[0185] Step B22: In response to the signal indicating reset received by the second timing management circuit 20', it outputs a blocking signal to notify the first timing management circuit 10', and outputs En2 = 1 and Rst2 = 0 to forcibly reset the display device.

[0186] Step B23: In response to the received blocking signal, the first timing management circuit 10' continuously outputs En1 = 0 and Rst1 = 1, and does not change its state during the blocking period. The exclusive-OR gate 306 and the equivalence gate 307 operate in the above manner to output the start control signals EN = 1 and RST = 0, so as to ensure that the start control signals output by the second timing management circuit 20' do not conflict with those output by the first timing management circuit 10'.

[0187] Step B24: In response to the received start control signals EN and RST, the main controller 05 forcibly resets the operating system and interface circuit of the display device.

[0188] See Figure 10 , the remote hibernation control process executed by the display control circuit includes the following steps B31 - B35.

[0189] Step B31: The second timing management circuit 20' receives the Wifi information, judges the information content, and confirms that the hibernation operation needs to be performed according to the information.

[0190] Step B32: When the second timing management circuit 20' receives the signal indicating hibernation, it sets the wake-up signal Wake_Up_2 to 0 to notify the first timing management circuit 10' to process the hibernation program. The second timing management circuit 20' also outputs En2 = 0 (notifying the system to hibernate) and Rst2 = 1 (not performing reset) to the main controller 05.

[0191] Step B33: When the first timing management circuit 10' receives the hibernation signal, it turns off the second power management circuit 07 for powering the interface, and outputs En1 = 0 (notifying the system to hibernate) and Rst1 = 1 (not performing reset). The exclusive-OR gate 306 receives En1 = 0 and EN2 = 0, and the equivalence gate 307 receives Rst1 = 1 and Rst2 = 1. According to the above truth table, the selection circuit including the exclusive-OR gate 306 and the equivalence gate 307 outputs EN = 0 and RST = 1.

[0192] Step B34: In response to receiving En1 = 0 (system in sleep mode) and Rst1 signal = 1 (no reset), the main controller 05 enters the sleep mode, outputs the sleep mode signal Mode_Sleep = 0, turns off the HDMI output, and notifies the second timing management circuit 20' that the system has entered the sleep mode through this signal. The main controller 05 also outputs a forced shutdown signal Force_off = 0 to the first timing management circuit 10' to notify the first timing management circuit 10' that the system sleep operation is completed, and the first timing management circuit 10' can enter the sleep mode. The main controller 05 also outputs a wake-up signal Wake_up_1 = 0 to the second timing management circuit 20' to notify the second timing management circuit 20' to enter the sleep mode.

[0193] Step B35: In response to receiving Mode_Sleep = 0 and Wake_up_1 = 0, the second timing management circuit 20' keeps the remote communication wake-up function unit of the second timing management circuit 20' working and turns off the remaining circuits; in response to receiving Force_off = 0, the first timing management circuit 10' keeps the standby function unit of the first timing management circuit 10' working and turns off the remaining circuits. After completing the above steps, the control module of the display device enters the sleep state. After the HDMI has no output, the entire display device then enters the sleep state, thus achieving the sleep of the entire machine.

[0194] See Figure 10 , the remote wake-up control process executed by the display control circuit includes the following steps B41 to B45.

[0195] Step B41: The second timing management circuit 20' receives the Wifi information, judges the information content, and confirms the need for a wake-up operation based on the information.

[0196] Step B42: When the second timing management circuit 20' receives the wake-up signal, it sets the wake-up signal Wake_up_2 to 1 and notifies the first timing management circuit 10' to perform the sleep program processing. The second timing management circuit 20' also sends En2 = 1 (notify the system to wake up) and Rst2 = 1 (no reset) to the main controller 05.

[0197] Step B43: When the first timing management circuit 10' receives the sleep signal, it turns off the second power management circuit 07 for powering the interface and outputs En1 = 0 (notify the system to wake up) and Rst1 = 1 (no reset). The exclusive-OR gate 306 receives En1 = 0 and En2 = 1 and outputs EN = 1; the equivalence gate 307 receives Rst1 = 1 and Rst2 = 1 and outputs EN = 1.

[0198] Step B44: In response to receiving En1 signal = 1 (system wake-up) and Rst1 signal = 1 (no reset), the main controller 05 starts to wake up each functional unit, and at the same time outputs Mode sleep = 1 to turn on the HDMI output, and notifies the second timing management circuit 20' that the system has been woken up through this signal. The main controller 05 also outputs Force_off = 1 to the first timing management circuit 10' to notify the first timing management circuit 10' that the system wake-up operation is completed, and the first timing management circuit 10' can enter the normal working mode. The main controller 05 also outputs Wake_Up_1 = 1 to notify the remote timing management circuit 20' to enter the normal working mode.

[0199] Step B45: In response to receiving Mode_Sleep = 1 and Wake Up_1 = 1, the second timing management circuit 20' wakes up all functional circuits of the second timing management circuit 20'. In response to receiving Force_off = 1, the first timing management circuit 10' wakes up all functional circuits of the first timing management circuit 10'. After completing the above steps, the control module of the display device enters the normal working state. After the HDMI restores the output, the entire display device then enters the normal working state, thus realizing the wake-up of the entire machine.

[0200] Those skilled in the art can understand that the above-described embodiments are all exemplary, and those skilled in the art can make improvements to them. The structures described in various embodiments can be freely combined without conflicts in structure or principle.

[0201] After detailing the preferred embodiments of the present disclosure, those skilled in the art can clearly understand that various changes and alterations can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation manners of the exemplary embodiments described in the specification.

Claims

1. A startup control circuit, comprising: A first timing management circuit configured to provide a first set of startup control signals; A second timing management circuit configured to provide a second set of startup control signals; A selection circuit connected to the first timing management circuit and the second timing management circuit, the selection circuit being configured to receive the first set of startup control signals and the second set of startup control signals, and select a set of startup control signals from the first set of startup control signals and the second set of startup control signals for output; The selection circuit includes: A first switch sub-circuit, an input end of the first switch sub-circuit is connected to the first timing management circuit to receive the first set of startup control signals; A second switch sub-circuit, an input end of the second switch sub-circuit is connected to the second timing management circuit to receive the second set of startup control signals; Wherein, the selection circuit is configured to select a valid set of startup control signals from the first set of startup control signals and the second set of startup control signals, and output them to the input end of the first switch sub-circuit or the input end of the second switch sub-circuit.

2. The startup control circuit according to claim 1, wherein, The first timing management circuit is further configured to provide a first status signal, the second timing management circuit is further configured to provide a second status signal, the selection circuit is configured to receive the first status signal and the first set of startup control signals from the first timing management circuit, receive the second status signal and the second set of startup control signals from the second timing management circuit, and select a set of startup control signals from the first set of startup control signals and the second set of startup control signals for output according to the first status signal and the second status signal.

3. The startup control circuit according to claim 1, wherein, The selection circuit includes: A status selection sub-circuit, a first input end of the status selection sub-circuit is connected to the first timing management circuit to receive the first status signal, a second input end of the status selection sub-circuit is connected to the second timing management circuit to receive the second status signal, the status selection sub-circuit is configured to output a first switch control signal at a first output end of the status selection sub-circuit and output a second switch control signal at a second output end of the status selection sub-circuit according to the first status signal and the second status signal; A first switch sub-circuit, a control end of the first switch sub-circuit is connected to the first output end of the status selection sub-circuit, the first switch sub-circuit is configured to provide the first set of startup control signals received at the input end of the first switch sub-circuit to the output end of the first switch sub-circuit under the control of the first switch control signal received at the control end of the first switch sub-circuit; A second switch sub-circuit, a control end of the second switch sub-circuit is connected to the second output end of the status selection sub-circuit, the second switch sub-circuit is configured to provide the second set of startup control signals received at the input end of the second switch sub-circuit to the output end of the second switch sub-circuit under the control of the second switch control signal received at the control end of the second switch sub-circuit.

4. The startup control circuit according to claim 3, wherein The status selection sub-circuit includes: A first inverter, wherein an input end of the first inverter is connected to a second input end of the state selection sub-circuit; A first AND gate, wherein a first input end of the first AND gate is connected to a first input end of the state selection sub-circuit, a second input end of the first AND gate is connected to an output end of the first inverter, and an output end of the first AND gate is connected to a first output end of the state selection sub-circuit; A second inverter, wherein an input end of the second inverter is connected to the first input end of the state selection sub-circuit; A second AND gate, wherein a first input end of the second AND gate is connected to the second input end of the state selection sub-circuit, a second input end of the second AND gate is connected to an output end of the second inverter, and an output end of the second AND gate is connected to a second output end of the state selection sub-circuit.

5. The startup control circuit according to claim 3, wherein, The first set of start control signals includes a first enable signal and a first reset signal, and the first switch sub-circuit includes: A first transistor, wherein a gate of the first transistor is connected to a control end of the first switch sub-circuit, a first pole of the first transistor serves as a first input end of the first switch sub-circuit and is connected to receive the first enable signal, and a second pole of the first transistor is connected to a first output end of the first switch sub-circuit; A second transistor, wherein a gate of the second transistor is connected to the control end of the first switch sub-circuit, a first pole of the second transistor serves as a second input end of the first switch sub-circuit and is connected to receive the first reset signal, and a second pole of the second transistor is connected to a second output end of the first switch sub-circuit.

6. The start control circuit according to any one of claims 3 to 5, wherein, The second set of start control signals includes a second enable signal and a second reset signal, and the second switch sub-circuit includes: A third transistor, wherein a gate of the third transistor is connected to a control end of the second switch sub-circuit, a first pole of the third transistor serves as a first input end of the second switch sub-circuit and is connected to receive the second enable signal, and a second pole of the third transistor is connected to a first output end of the second switch sub-circuit; A fourth transistor, wherein a gate of the fourth transistor is connected to the control end of the second switch sub-circuit, a first pole of the fourth transistor serves as a second input end of the second switch sub-circuit and is connected to receive the second reset signal, and a second pole of the fourth transistor is connected to a second output end of the second switch sub-circuit.

7. The start control circuit according to claim 6, wherein the first output end of the first switch sub-circuit and the first output end of the second switch sub-circuit are connected to be a first output end of the selection circuit, and the second output end of the first switch sub-circuit and the second output end of the second switch sub-circuit are connected to be a second output end of the selection circuit.

8. The start control circuit according to claim 1, wherein, The first timing management circuit is configured to generate a valid first set of start control signals in response to a first start event and send a first blocking signal to the second timing management circuit through a communication interface, and generate an invalid first set of start control signals in response to a second blocking signal from the second timing management circuit; The second timing management circuit is configured to generate a valid second set of start control signals in response to a second start event and send a second blocking signal to the first timing management circuit through the communication interface, and generate an invalid second set of start control signals in response to a first blocking signal from the first timing management circuit.

9. The startup control circuit according to claim 8, wherein The first set of start control signals includes a first enable signal and a first reset signal, the second set of start control signals includes a second enable signal and a second reset signal, and the selection circuit includes: An exclusive-OR gate, a first input terminal of the exclusive-OR gate is connected to the first timing management circuit to receive the first enable signal, a second input terminal of the exclusive-OR gate is connected to the second timing management circuit to receive the second enable signal, and an output terminal of the exclusive-OR gate serves as a first output terminal of the selection circuit; An exclusive-NOR gate, a first input terminal of the exclusive-NOR gate is connected to the first timing management circuit to receive the first reset signal, a second input terminal of the exclusive-NOR gate is connected to the second timing management circuit to receive the second reset signal, and an output terminal of the exclusive-NOR gate serves as a second output terminal of the selection circuit.

10. The startup control circuit according to claim 8 or 9, wherein, The communication interface is an Inter-Integrated Circuit (I 2 C) interface.

11. A display control circuit, comprising: The start control circuit according to any one of claims 1 to 10; A main controller, connected to the start control circuit and configured to perform start control according to a set of start control signals output by the start control circuit.

12. The display control circuit according to claim 11, further comprising: A first power management circuit, connected to the first timing management circuit and the second timing management circuit in the start control circuit and configured to provide a first power signal; A second power management circuit, connected to the first timing management circuit in the start control circuit and the main controller and configured to provide a second power signal; A generation circuit, the main controller is connected to the selection circuit in the start control circuit through the generation circuit, the generation circuit is further connected to the first power management circuit and the second power management circuit, and the generation circuit is configured to generate a system start control signal based on the first power signal, the second power signal, and a set of start control signals output by the selection circuit in the start control circuit; Wherein the main controller is configured to perform start control based on the system start control signal generated by the generation circuit.

13. A control method for a start control circuit according to any one of claims 1 to 10, comprising: The first timing management circuit provides a first set of start control signals, and the second timing management circuit provides a second set of start control signals; The selection circuit receives the first set of start control signals and the second set of start control signals, and selects a set of start control signals from the first set of start control signals and the second set of start control signals to output; The method further comprises: a first switch sub-circuit receives the first set of start control signals, and a second switch sub-circuit receives the second set of start control signals; The selection circuit selects a valid set of start control signals from the first set of start control signals and the second set of start control signals, and outputs them to the input end of the first switch sub-circuit or the input end of the second switch sub-circuit.

14. The method according to claim 13, wherein In the first mode, the first timing management circuit provides a valid first status signal and the first set of start control signals, the second timing management circuit provides an invalid second status signal and the second set of start control signals, and the selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals according to the first status signal and the second status signal for output; In the second mode, the first timing management circuit provides an invalid first status signal and the first set of start control signals, the second timing management circuit provides a valid second status signal and the second set of start control signals, and the selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals according to the first status signal and the second status signal for output.

15. The method according to claim 13, wherein The first timing management circuit generates a valid first set of start control signals in response to a first start event and sends a first blocking signal to the second timing management circuit through a communication interface. The second timing management circuit generates an invalid second set of start control signals in response to the first blocking signal from the first timing management circuit. The selection circuit selects the first set of start control signals from the first set of start control signals and the second set of start control signals for output; The second timing management circuit generates a valid second set of start control signals in response to a second start event and sends a second blocking signal to the first timing management circuit through the communication interface. The first timing management circuit generates an invalid first set of start control signals in response to the second blocking signal from the second timing management circuit. The selection circuit selects the second set of start control signals from the first set of start control signals and the second set of start control signals for output.

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